10974d292Smrg/* 20974d292Smrg * Copyright 2005 Eric Anholt 30974d292Smrg * Copyright 2005 Benjamin Herrenschmidt 40974d292Smrg * Copyright 2008 Advanced Micro Devices, Inc. 50974d292Smrg * All Rights Reserved. 60974d292Smrg * 70974d292Smrg * Permission is hereby granted, free of charge, to any person obtaining a 80974d292Smrg * copy of this software and associated documentation files (the "Software"), 90974d292Smrg * to deal in the Software without restriction, including without limitation 100974d292Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 110974d292Smrg * and/or sell copies of the Software, and to permit persons to whom the 120974d292Smrg * Software is furnished to do so, subject to the following conditions: 130974d292Smrg * 140974d292Smrg * The above copyright notice and this permission notice (including the next 150974d292Smrg * paragraph) shall be included in all copies or substantial portions of the 160974d292Smrg * Software. 170974d292Smrg * 180974d292Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 190974d292Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 200974d292Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 210974d292Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 220974d292Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 230974d292Smrg * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 240974d292Smrg * SOFTWARE. 250974d292Smrg * 260974d292Smrg * Authors: 270974d292Smrg * Eric Anholt <anholt@FreeBSD.org> 280974d292Smrg * Zack Rusin <zrusin@trolltech.com> 290974d292Smrg * Benjamin Herrenschmidt <benh@kernel.crashing.org> 300974d292Smrg * Alex Deucher <alexander.deucher@amd.com> 310974d292Smrg * Matthias Hopf <mhopf@suse.de> 320974d292Smrg */ 330974d292Smrg#ifndef RADEON_EXA_SHARED_H 340974d292Smrg 350974d292Smrg#define RADEON_EXA_SHARED_H 360974d292Smrg 370974d292Smrgextern PixmapPtr RADEONGetDrawablePixmap(DrawablePtr pDrawable); 380974d292Smrg 390974d292Smrgextern void RADEONVlineHelperClear(ScrnInfoPtr pScrn); 400974d292Smrgextern void RADEONVlineHelperSet(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2); 410974d292Smrgextern Bool RADEONValidPM(uint32_t pm, int bpp); 420974d292Smrgextern Bool RADEONCheckBPP(int bpp); 4368105dcbSveegoextern PixmapPtr RADEONSolidPixmap(ScreenPtr pScreen, uint32_t solid); 440974d292Smrg 450974d292Smrg#define RADEON_TRACE_FALL 0 460974d292Smrg#define RADEON_TRACE_DRAW 0 470974d292Smrg 480974d292Smrg#if RADEON_TRACE_FALL 490974d292Smrg#define RADEON_FALLBACK(x) \ 500974d292Smrgdo { \ 510974d292Smrg ErrorF("%s: ", __FUNCTION__); \ 520974d292Smrg ErrorF x; \ 530974d292Smrg return FALSE; \ 540974d292Smrg} while (0) 550974d292Smrg#else 560974d292Smrg#define RADEON_FALLBACK(x) return FALSE 570974d292Smrg#endif 580974d292Smrg 590974d292Smrg#if RADEON_TRACE_DRAW 600974d292Smrg#define TRACE do { ErrorF("TRACE: %s\n", __FUNCTION__); } while(0) 610974d292Smrg#else 620974d292Smrg#define TRACE 630974d292Smrg#endif 640974d292Smrg 6543df4709Smrg#ifdef XF86DRM_MODE 660974d292Smrgstatic inline void radeon_add_pixmap(struct radeon_cs *cs, PixmapPtr pPix, int read_domains, int write_domain) 670974d292Smrg{ 680974d292Smrg struct radeon_exa_pixmap_priv *driver_priv = exaGetPixmapDriverPrivate(pPix); 690974d292Smrg 700974d292Smrg radeon_cs_space_add_persistent_bo(cs, driver_priv->bo, read_domains, write_domain); 710974d292Smrg} 720974d292Smrg 730974d292Smrgextern void radeon_ib_discard(ScrnInfoPtr pScrn); 7443df4709Smrg#endif /* XF86DRM_MODE */ 750974d292Smrg 760974d292Smrgextern int radeon_cp_start(ScrnInfoPtr pScrn); 77921a55d8Smrgextern void radeon_vb_no_space(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo, int vert_size); 780974d292Smrgextern void radeon_vbo_done_composite(PixmapPtr pDst); 790974d292Smrg 800974d292Smrg#endif 81