theatre200.c revision 209ff23f
1/************************************************************************************* 2 * 3 * Copyright (C) 2005 Bogdan D. bogdand@users.sourceforge.net 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a copy of this 6 * software and associated documentation files (the "Software"), to deal in the Software 7 * without restriction, including without limitation the rights to use, copy, modify, 8 * merge, publish, distribute, sublicense, and/or sell copies of the Software, 9 * and to permit persons to whom the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in all copies or 12 * substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 15 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE 16 * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * Except as contained in this notice, the name of the author shall not be used in advertising or 21 * otherwise to promote the sale, use or other dealings in this Software without prior written 22 * authorization from the author. 23 * 24 * $Log: theatre200.c,v $ 25 * Revision 1.1.1.1 2008/08/02 05:10:35 mrg 26 * initial import of xf86-video-ati-6.9.0 27 * 28 * Revision 1.6 2006/03/22 22:30:14 krh 29 * 2006-03-22 Kristian Høgsberg <krh@redhat.com> 30 * 31 * * src/theatre200.c: Convert use of xf86fopen() and other xf86 32 * wrapped libc symbols to use libc symbols directly. The xf86* 33 * versions aren't supposed to be used directly. 34 * 35 * * src/ *.c: Drop libc wrapper; don't include xf86_ansic.h and add 36 * includes now missing. 37 * 38 * Revision 1.4 2005/08/28 18:00:23 bogdand 39 * Modified the licens type from GPL to a X/MIT one 40 * 41 * Revision 1.3 2005/07/11 02:29:45 ajax 42 * Prep for modular builds by adding guarded #include "config.h" everywhere. 43 * 44 * Revision 1.2 2005/07/01 22:43:11 daniels 45 * Change all misc.h and os.h references to <X11/foo.h>. 46 * 47 * 48 ************************************************************************************/ 49 50#ifdef HAVE_CONFIG_H 51#include "config.h" 52#endif 53 54#include <stdio.h> 55#include <string.h> 56 57#include "xf86.h" 58#include "generic_bus.h" 59#include "radeon_reg.h" 60#include "radeon.h" 61#include "theatre_reg.h" 62#include "theatre200.h" 63#include "radeon_macros.h" 64 65#undef read 66#undef write 67#undef ioctl 68 69void DumpRageTheatreRegsByName(TheatrePtr t); 70 71static int DownloadMicrocode(TheatrePtr t); 72static int microc_load (char* micro_path, char* micro_type, struct rt200_microc_data* microc_datap, int screen); 73static void microc_clean(struct rt200_microc_data* microc_datap, int screen); 74static int dsp_init(TheatrePtr t, struct rt200_microc_data* microc_datap); 75static int dsp_load(TheatrePtr t, struct rt200_microc_data* microc_datap); 76 77static uint32_t dsp_send_command(TheatrePtr t, uint32_t fb_scratch1, uint32_t fb_scratch0); 78static uint32_t dsp_set_video_input_connector(TheatrePtr t, uint32_t connector); 79//static uint32_t dsp_reset(TheatrePtr t); 80static uint32_t dsp_set_lowpowerstate(TheatrePtr t, uint32_t pstate); 81static uint32_t dsp_set_video_standard(TheatrePtr t, uint32_t standard); 82static uint32_t dsp_set_videostreamformat(TheatrePtr t, uint32_t format); 83static uint32_t dsp_video_standard_detection(TheatrePtr t); 84//static uint32_t dsp_get_signallockstatus(TheatrePtr t); 85//static uint32_t dsp_get_signallinenumber(TheatrePtr t); 86 87static uint32_t dsp_set_brightness(TheatrePtr t, uint8_t brightness); 88static uint32_t dsp_set_contrast(TheatrePtr t, uint8_t contrast); 89//static uint32_t dsp_set_sharpness(TheatrePtr t, int sharpness); 90static uint32_t dsp_set_tint(TheatrePtr t, uint8_t tint); 91static uint32_t dsp_set_saturation(TheatrePtr t, uint8_t saturation); 92static uint32_t dsp_set_video_scaler_horizontal(TheatrePtr t, uint16_t output_width, uint16_t horz_start, uint16_t horz_end); 93static uint32_t dsp_set_video_scaler_vertical(TheatrePtr t, uint16_t output_height, uint16_t vert_start, uint16_t vert_end); 94static uint32_t dsp_audio_mute(TheatrePtr t, uint8_t left, uint8_t right); 95static uint32_t dsp_set_audio_volume(TheatrePtr t, uint8_t left, uint8_t right, uint8_t auto_mute); 96//static uint32_t dsp_audio_detection(TheatrePtr t, uint8_t option); 97static uint32_t dsp_configure_i2s_port(TheatrePtr t, uint8_t tx_mode, uint8_t rx_mode, uint8_t clk_mode); 98static uint32_t dsp_configure_spdif_port(TheatrePtr t, uint8_t state); 99 100static Bool theatre_read(TheatrePtr t,uint32_t reg, uint32_t *data) 101{ 102 if(t->theatre_num<0)return FALSE; 103 return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (uint8_t *) data); 104} 105 106static Bool theatre_write(TheatrePtr t,uint32_t reg, uint32_t data) 107{ 108 if(t->theatre_num<0)return FALSE; 109 return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (uint8_t *) &data); 110} 111 112static Bool theatre_fifo_read(TheatrePtr t,uint32_t fifo, uint8_t *data) 113{ 114 if(t->theatre_num<0)return FALSE; 115 return t->VIP->fifo_read(t->VIP, ((t->theatre_num & 0x3)<<14) | fifo,1, (uint8_t *) data); 116} 117 118static Bool theatre_fifo_write(TheatrePtr t,uint32_t fifo, uint32_t count, uint8_t* buffer) 119{ 120 if(t->theatre_num<0)return FALSE; 121 return t->VIP->fifo_write(t->VIP,((t->theatre_num & 0x03)<<14) | fifo,count, (uint8_t *)buffer); 122} 123 124#define RT_regr(reg,data) theatre_read(t,(reg),(data)) 125#define RT_regw(reg,data) theatre_write(t,(reg),(data)) 126#define RT_fifor(fifo,data) theatre_fifo_read(t,(fifo),(data)) 127#define RT_fifow(fifo,count,data) theatre_fifo_write(t,(fifo),(count),(data)) 128#define VIP_TYPE "ATI VIP BUS" 129 130static int microc_load (char* micro_path, char* micro_type, struct rt200_microc_data* microc_datap, int screen) 131{ 132 FILE* file; 133 struct rt200_microc_head* microc_headp = µc_datap->microc_head; 134 struct rt200_microc_seg* seg_list = NULL; 135 struct rt200_microc_seg* curr_seg = NULL; 136 struct rt200_microc_seg* prev_seg = NULL; 137 int i; 138 139 if (micro_path == NULL) 140 return -1; 141 142 if (micro_type == NULL) 143 return -1; 144 145 file = fopen(micro_path, "r"); 146 if (file == NULL) { 147 ERROR_0("Cannot open microcode file\n"); 148 return -1; 149 } 150 151 if (!strcmp(micro_type, "BINARY")) 152 { 153 if (fread(microc_headp, sizeof(struct rt200_microc_head), 1, file) != 1) 154 { 155 ERROR("Cannot read header from file: %s\n", micro_path); 156 goto fail_exit; 157 } 158 159 DEBUG("Microcode: num_seg: %x\n", microc_headp->num_seg); 160 161 if (microc_headp->num_seg == 0) 162 goto fail_exit; 163 164 for (i = 0; i < microc_headp->num_seg; i++) 165 { 166 int ret; 167 168 curr_seg = (struct rt200_microc_seg*)Xalloc(sizeof(struct rt200_microc_seg)); 169 if (curr_seg == NULL) 170 { 171 ERROR_0("Cannot allocate memory\n"); 172 goto fail_exit; 173 } 174 175 ret = fread(&curr_seg->num_bytes, 4, 1, file); 176 ret += fread(&curr_seg->download_dst, 4, 1, file); 177 ret += fread(&curr_seg->crc_val, 4, 1, file); 178 if (ret != 3) 179 { 180 ERROR("Cannot read segment from microcode file: %s\n", micro_path); 181 goto fail_exit; 182 } 183 184 curr_seg->data = (unsigned char*)Xalloc(curr_seg->num_bytes); 185 if (curr_seg->data == NULL) 186 { 187 ERROR_0("cannot allocate memory\n"); 188 goto fail_exit; 189 } 190 191 DEBUG("Microcode: segment number: %x\n", i); 192 DEBUG("Microcode: curr_seg->num_bytes: %x\n", curr_seg->num_bytes); 193 DEBUG("Microcode: curr_seg->download_dst: %x\n", curr_seg->download_dst); 194 DEBUG("Microcode: curr_seg->crc_val: %x\n", curr_seg->crc_val); 195 196 if (seg_list) 197 { 198 prev_seg->next = curr_seg; 199 curr_seg->next = NULL; 200 prev_seg = curr_seg; 201 } 202 else 203 seg_list = prev_seg = curr_seg; 204 205 } 206 207 curr_seg = seg_list; 208 while (curr_seg) 209 { 210 if (fread(curr_seg->data, curr_seg->num_bytes, 1, file) != 1) 211 { 212 ERROR_0("Cannot read segment data\n"); 213 goto fail_exit; 214 } 215 216 curr_seg = curr_seg->next; 217 } 218 } 219 else if (!strcmp(micro_type, "ASCII")) 220 { 221 char tmp1[12], tmp2[12], tmp3[12], tmp4[12]; 222 unsigned int ltmp; 223 224 if ((fgets(tmp1, 12, file) != NULL) && 225 (fgets(tmp2, 12, file) != NULL) && 226 (fgets(tmp3, 12, file) != NULL) && 227 fgets(tmp4, 12, file) != NULL) 228 { 229 microc_headp->device_id = strtoul(tmp1, NULL, 16); 230 microc_headp->vendor_id = strtoul(tmp2, NULL, 16); 231 microc_headp->revision_id = strtoul(tmp3, NULL, 16); 232 microc_headp->num_seg = strtoul(tmp4, NULL, 16); 233 } 234 else 235 { 236 ERROR("Cannot read header from file: %s\n", micro_path); 237 goto fail_exit; 238 } 239 240 DEBUG("Microcode: num_seg: %x\n", microc_headp->num_seg); 241 242 if (microc_headp->num_seg == 0) 243 goto fail_exit; 244 245 for (i = 0; i < microc_headp->num_seg; i++) 246 { 247 curr_seg = (struct rt200_microc_seg*)Xalloc(sizeof(struct rt200_microc_seg)); 248 if (curr_seg == NULL) 249 { 250 ERROR_0("Cannot allocate memory\n"); 251 goto fail_exit; 252 } 253 254 if (fgets(tmp1, 12, file) != NULL && 255 fgets(tmp2, 12, file) != NULL && 256 fgets(tmp3, 12, file) != NULL) 257 { 258 curr_seg->num_bytes = strtoul(tmp1, NULL, 16); 259 curr_seg->download_dst = strtoul(tmp2, NULL, 16); 260 curr_seg->crc_val = strtoul(tmp3, NULL, 16); 261 } 262 else 263 { 264 ERROR("Cannot read segment from microcode file: %s\n", micro_path); 265 goto fail_exit; 266 } 267 268 curr_seg->data = (unsigned char*)Xalloc(curr_seg->num_bytes); 269 if (curr_seg->data == NULL) 270 { 271 ERROR_0("cannot allocate memory\n"); 272 goto fail_exit; 273 } 274 275 DEBUG("Microcode: segment number: %x\n", i); 276 DEBUG("Microcode: curr_seg->num_bytes: %x\n", curr_seg->num_bytes); 277 DEBUG("Microcode: curr_seg->download_dst: %x\n", curr_seg->download_dst); 278 DEBUG("Microcode: curr_seg->crc_val: %x\n", curr_seg->crc_val); 279 280 if (seg_list) 281 { 282 curr_seg->next = NULL; 283 prev_seg->next = curr_seg; 284 prev_seg = curr_seg; 285 } 286 else 287 seg_list = prev_seg = curr_seg; 288 } 289 290 curr_seg = seg_list; 291 while (curr_seg) 292 { 293 for ( i = 0; i < curr_seg->num_bytes; i+=4) 294 { 295 296 if (fgets(tmp1, 12, file) == NULL) 297 { 298 ERROR_0("Cannot read from file\n"); 299 goto fail_exit; 300 } 301 ltmp = strtoul(tmp1, NULL, 16); 302 303 *(unsigned int*)(curr_seg->data + i) = ltmp; 304 } 305 306 curr_seg = curr_seg->next; 307 } 308 309 } 310 else 311 { 312 ERROR("File type %s unknown\n", micro_type); 313 } 314 315 microc_datap->microc_seg_list = seg_list; 316 317 fclose(file); 318 return 0; 319 320fail_exit: 321 curr_seg = seg_list; 322 while(curr_seg) 323 { 324 Xfree(curr_seg->data); 325 prev_seg = curr_seg; 326 curr_seg = curr_seg->next; 327 Xfree(prev_seg); 328 } 329 fclose(file); 330 331 return -1; 332} 333 334static void microc_clean(struct rt200_microc_data* microc_datap, int screen) 335{ 336 struct rt200_microc_seg* seg_list = microc_datap->microc_seg_list; 337 struct rt200_microc_seg* prev_seg; 338 339 while(seg_list) 340 { 341 Xfree(seg_list->data); 342 prev_seg = seg_list; 343 seg_list = seg_list->next; 344 Xfree(prev_seg); 345 } 346} 347 348static int dsp_init(TheatrePtr t, struct rt200_microc_data* microc_datap) 349{ 350 uint32_t data; 351 int i = 0; 352 int screen = t->VIP->scrnIndex; 353 354 /* Map FIFOD to DSP Port I/O port */ 355 RT_regr(VIP_HOSTINTF_PORT_CNTL, &data); 356 RT_regw(VIP_HOSTINTF_PORT_CNTL, data & (~VIP_HOSTINTF_PORT_CNTL__FIFO_RW_MODE)); 357 358 /* The default endianess is LE. It matches the ost one for x86 */ 359 RT_regr(VIP_HOSTINTF_PORT_CNTL, &data); 360 RT_regw(VIP_HOSTINTF_PORT_CNTL, data & (~VIP_HOSTINTF_PORT_CNTL__FIFOD_ENDIAN_SWAP)); 361 362 /* Wait until Shuttle bus channel 14 is available */ 363 RT_regr(VIP_TC_STATUS, &data); 364 while(((data & VIP_TC_STATUS__TC_CHAN_BUSY) & 0x00004000) && (i++ < 10000)) 365 RT_regr(VIP_TC_STATUS, &data); 366 367 DEBUG_0("Microcode: dsp_init: channel 14 available\n"); 368 369 return 0; 370} 371 372static int dsp_load(TheatrePtr t, struct rt200_microc_data* microc_datap) 373{ 374 struct rt200_microc_seg* seg_list = microc_datap->microc_seg_list; 375 uint8_t data8; 376 uint32_t data, fb_scratch0, fb_scratch1; 377 uint32_t i; 378 uint32_t tries = 0; 379 uint32_t result = 0; 380 uint32_t seg_id = 0; 381 int screen = t->VIP->scrnIndex; 382 383 DEBUG("Microcode: before everything: %x\n", data8); 384 385 if (RT_fifor(0x000, &data8)) 386 DEBUG("Microcode: FIFO status0: %x\n", data8); 387 else 388 { 389 ERROR_0("Microcode: error reading FIFO status0\n"); 390 return -1; 391 } 392 393 394 if (RT_fifor(0x100, &data8)) 395 DEBUG("Microcode: FIFO status1: %x\n", data8); 396 else 397 { 398 ERROR_0("Microcode: error reading FIFO status1\n"); 399 return -1; 400 } 401 402 /* 403 * Download the Boot Code and CRC Checking Code (first segment) 404 */ 405 seg_id = 1; 406 while(result != DSP_OK && tries < 10) 407 { 408 /* Put DSP in reset before download (0x02) */ 409 RT_regr(VIP_TC_DOWNLOAD, &data); 410 RT_regw(VIP_TC_DOWNLOAD, (data & ~VIP_TC_DOWNLOAD__TC_RESET_MODE) | (0x02 << 17)); 411 412 /* 413 * Configure shuttle bus for tranfer between DSP I/O "Program Interface" 414 * and Program Memory at address 0 415 */ 416 417 RT_regw(VIP_TC_SOURCE, 0x90000000); 418 RT_regw(VIP_TC_DESTINATION, 0x00000000); 419 RT_regw(VIP_TC_COMMAND, 0xe0000044 | ((seg_list->num_bytes - 1) << 7)); 420 421 /* Load first segment */ 422 DEBUG_0("Microcode: Loading first segment\n"); 423 424 if (!RT_fifow(0x700, seg_list->num_bytes, seg_list->data)) 425 { 426 ERROR_0("Microcode: write to FIFOD failed\n"); 427 return -1; 428 } 429 430 /* Wait until Shuttle bus channel 14 is available */ 431 i = data = 0; 432 RT_regr(VIP_TC_STATUS, &data); 433 while(((data & VIP_TC_STATUS__TC_CHAN_BUSY) & 0x00004000) && (i++ < 10000)) 434 RT_regr(VIP_TC_STATUS, &data); 435 436 if (i >= 10000) 437 { 438 ERROR_0("Microcode: channel 14 timeout\n"); 439 return -1; 440 } 441 442 DEBUG_0("Microcode: dsp_load: checkpoint 1\n"); 443 DEBUG("Microcode: TC_STATUS: %x\n", data); 444 445 /* transfer the code from program memory to data memory */ 446 RT_regw(VIP_TC_SOURCE, 0x00000000); 447 RT_regw(VIP_TC_DESTINATION, 0x10000000); 448 RT_regw(VIP_TC_COMMAND, 0xe0000006 | ((seg_list->num_bytes - 1) << 7)); 449 450 /* Wait until Shuttle bus channel 14 is available */ 451 i = data = 0; 452 RT_regr(VIP_TC_STATUS, &data); 453 while(((data & VIP_TC_STATUS__TC_CHAN_BUSY) & 0x00004000) && (i++ < 10000)) 454 RT_regr(VIP_TC_STATUS, &data); 455 456 if (i >= 10000) 457 { 458 ERROR_0("Microcode: channel 14 timeout\n"); 459 return -1; 460 } 461 DEBUG_0("Microcode: dsp_load: checkpoint 2\n"); 462 DEBUG("Microcode: TC_STATUS: %x\n", data); 463 464 /* Take DSP out from reset (0x0) */ 465 data = 0; 466 RT_regr(VIP_TC_DOWNLOAD, &data); 467 RT_regw(VIP_TC_DOWNLOAD, data & ~VIP_TC_DOWNLOAD__TC_RESET_MODE); 468 469 RT_regr(VIP_TC_STATUS, &data); 470 DEBUG_0("Microcode: dsp_load: checkpoint 3\n"); 471 DEBUG("Microcode: TC_STATUS: %x\n", data); 472 473 /* send dsp_download_check_CRC */ 474 fb_scratch0 = ((seg_list->num_bytes << 16) & 0xffff0000) | ((seg_id << 8) & 0xff00) | (0xff & 193); 475 fb_scratch1 = (unsigned int)seg_list->crc_val; 476 477 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 478 479 DEBUG_0("Microcode: dsp_load: checkpoint 4\n"); 480 } 481 482 if (tries >= 10) 483 { 484 ERROR_0("Microcode: Download of boot degment failed\n"); 485 return -1; 486 } 487 488 DEBUG_0("Microcode: Download of boot code succeeded\n"); 489 490 while((seg_list = seg_list->next) != NULL) 491 { 492 seg_id++; 493 result = tries = 0; 494 while(result != DSP_OK && tries < 10) 495 { 496 /* 497 * Configure shuttle bus for tranfer between DSP I/O "Program Interface" 498 * and Data Memory at address 0 499 */ 500 501 RT_regw(VIP_TC_SOURCE, 0x90000000); 502 RT_regw(VIP_TC_DESTINATION, 0x10000000); 503 RT_regw(VIP_TC_COMMAND, 0xe0000044 | ((seg_list->num_bytes - 1) << 7)); 504 505 if (!RT_fifow(0x700, seg_list->num_bytes, seg_list->data)) 506 { 507 ERROR_0("Microcode: write to FIFOD failed\n"); 508 return -1; 509 } 510 511 i = data = 0; 512 RT_regr(VIP_TC_STATUS, &data); 513 while(((data & VIP_TC_STATUS__TC_CHAN_BUSY) & 0x00004000) && (i++ < 10000)) 514 RT_regr(VIP_TC_STATUS, &data); 515 516 /* send dsp_download_check_CRC */ 517 fb_scratch0 = ((seg_list->num_bytes << 16) & 0xffff0000) | ((seg_id << 8) & 0xff00) | (0xff & 193); 518 fb_scratch1 = (unsigned int)seg_list->crc_val; 519 520 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 521 } 522 523 if (i >=10) 524 { 525 ERROR("Microcode: DSP failed to move seg: %x from data to code memory\n", seg_id); 526 return -1; 527 } 528 529 DEBUG("Microcode: segment: %x loaded\n", seg_id); 530 531 /* 532 * The segment is downloaded correctly to data memory. Now move it to code memory 533 * by using dsp_download_code_transfer command. 534 */ 535 536 fb_scratch0 = ((seg_list->num_bytes << 16) & 0xffff0000) | ((seg_id << 8) & 0xff00) | (0xff & 194); 537 fb_scratch1 = (unsigned int)seg_list->download_dst; 538 539 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 540 541 if (result != DSP_OK) 542 { 543 ERROR("Microcode: DSP failed to move seg: %x from data to code memory\n", seg_id); 544 return -1; 545 } 546 } 547 548 DEBUG_0("Microcode: download complete\n"); 549 550 /* 551 * The last step is sending dsp_download_check_CRC with "download complete" 552 */ 553 554 fb_scratch0 = ((165 << 8) & 0xff00) | (0xff & 193); 555 fb_scratch1 = (unsigned int)0x11111; 556 557 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 558 559 if (result == DSP_OK) 560 DEBUG_0("Microcode: DSP microcode successfully loaded\n"); 561 else 562 { 563 ERROR_0("Microcode: DSP microcode UNsuccessfully loaded\n"); 564 return -1; 565 } 566 567 return 0; 568} 569 570static uint32_t dsp_send_command(TheatrePtr t, uint32_t fb_scratch1, uint32_t fb_scratch0) 571{ 572 uint32_t data; 573 int i; 574 575 /* 576 * Clear the FB_INT0 bit in INT_CNTL 577 */ 578 RT_regr(VIP_INT_CNTL, &data); 579 RT_regw(VIP_INT_CNTL, data | VIP_INT_CNTL__FB_INT0_CLR); 580 581 /* 582 * Write FB_SCRATCHx registers. If FB_SCRATCH1==0 then we have a DWORD command. 583 */ 584 RT_regw(VIP_FB_SCRATCH0, fb_scratch0); 585 if (fb_scratch1 != 0) 586 RT_regw(VIP_FB_SCRATCH1, fb_scratch1); 587 588 /* 589 * Attention DSP. We are talking to you. 590 */ 591 RT_regr(VIP_FB_INT, &data); 592 RT_regw(VIP_FB_INT, data | VIP_FB_INT__INT_7); 593 594 /* 595 * Wait (by polling) for the DSP to process the command. 596 */ 597 i = 0; 598 RT_regr(VIP_INT_CNTL, &data); 599 while((!(data & VIP_INT_CNTL__FB_INT0)) /*&& (i++ < 10000)*/) 600 RT_regr(VIP_INT_CNTL, &data); 601 602 /* 603 * The return code is in FB_SCRATCH0 604 */ 605 RT_regr(VIP_FB_SCRATCH0, &fb_scratch0); 606 607 /* 608 * If we are here it means we got an answer. Clear the FB_INT0 bit. 609 */ 610 RT_regr(VIP_INT_CNTL, &data); 611 RT_regw(VIP_INT_CNTL, data | VIP_INT_CNTL__FB_INT0_CLR); 612 613 614 return fb_scratch0; 615} 616 617static uint32_t dsp_set_video_input_connector(TheatrePtr t, uint32_t connector) 618{ 619 uint32_t fb_scratch0 = 0; 620 uint32_t result; 621 int screen = t->VIP->scrnIndex; 622 623 fb_scratch0 = ((connector << 8) & 0xff00) | (55 & 0xff); 624 625 result = dsp_send_command(t, 0, fb_scratch0); 626 627 DEBUG_2("dsp_set_video_input_connector: %x, result: %x\n", connector, result); 628 629 return result; 630} 631 632#if 0 633static uint32_t dsp_reset(TheatrePtr t) 634{ 635 uint32_t fb_scratch0 = 0; 636 uint32_t result; 637 int screen = t->VIP->scrnIndex; 638 639 fb_scratch0 = ((2 << 8) & 0xff00) | (8 & 0xff); 640 641 result = dsp_send_command(t, 0, fb_scratch0); 642 643 DEBUG("dsp_reset: %x\n", result); 644 645 return result; 646} 647#endif 648 649static uint32_t dsp_set_lowpowerstate(TheatrePtr t, uint32_t pstate) 650{ 651 uint32_t fb_scratch0 = 0; 652 uint32_t result; 653 int screen = t->VIP->scrnIndex; 654 655 fb_scratch0 = ((pstate << 8) & 0xff00) | (82 & 0xff); 656 657 result = dsp_send_command(t, 0, fb_scratch0); 658 659 DEBUG("dsp_set_lowpowerstate: %x\n", result); 660 661 return result; 662} 663static uint32_t dsp_set_video_standard(TheatrePtr t, uint32_t standard) 664{ 665 uint32_t fb_scratch0 = 0; 666 uint32_t result; 667 int screen = t->VIP->scrnIndex; 668 669 fb_scratch0 = ((standard << 8) & 0xff00) | (52 & 0xff); 670 671 result = dsp_send_command(t, 0, fb_scratch0); 672 673 DEBUG("dsp_set_video_standard: %x\n", result); 674 675 return result; 676} 677 678static uint32_t dsp_set_videostreamformat(TheatrePtr t, uint32_t format) 679{ 680 uint32_t fb_scratch0 = 0; 681 uint32_t result; 682 int screen = t->VIP->scrnIndex; 683 684 fb_scratch0 = ((format << 8) & 0xff00) | (65 & 0xff); 685 686 result = dsp_send_command(t, 0, fb_scratch0); 687 688 DEBUG("dsp_set_videostreamformat: %x\n", result); 689 690 return result; 691} 692 693static uint32_t dsp_video_standard_detection(TheatrePtr t) 694{ 695 uint32_t fb_scratch0 = 0; 696 uint32_t result; 697 int screen = t->VIP->scrnIndex; 698 699 fb_scratch0 = 0 | (54 & 0xff); 700 701 result = dsp_send_command(t, 0, fb_scratch0); 702 703 DEBUG("dsp_video_standard_detection: %x\n", result); 704 705 return result; 706} 707 708#if 0 709static uint32_t dsp_get_signallockstatus(TheatrePtr t) 710{ 711 uint32_t fb_scratch1 = 0; 712 uint32_t fb_scratch0 = 0; 713 uint32_t result; 714 int screen = t->VIP->scrnIndex; 715 716 fb_scratch0 = 0 | (77 & 0xff); 717 718 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 719 720 DEBUG_3("dsp_get_signallockstatus: %x, h_pll: %x, v_pll: %x\n", \ 721 result, (result >> 8) & 0xff, (result >> 16) & 0xff); 722 723 return result; 724} 725 726static uint32_t dsp_get_signallinenumber(TheatrePtr t) 727{ 728 uint32_t fb_scratch1 = 0; 729 uint32_t fb_scratch0 = 0; 730 uint32_t result; 731 int screen = t->VIP->scrnIndex; 732 733 fb_scratch0 = 0 | (78 & 0xff); 734 735 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 736 737 DEBUG_2("dsp_get_signallinenumber: %x, linenum: %x\n", \ 738 result, (result >> 8) & 0xffff); 739 740 return result; 741} 742#endif 743 744static uint32_t dsp_set_brightness(TheatrePtr t, uint8_t brightness) 745{ 746 uint32_t fb_scratch1 = 0; 747 uint32_t fb_scratch0 = 0; 748 uint32_t result; 749 int screen = t->VIP->scrnIndex; 750 751 fb_scratch0 = ((brightness << 8) & 0xff00) | (67 & 0xff); 752 753 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 754 755 DEBUG("dsp_set_brightness: %x\n", result); 756 757 return result; 758} 759 760static uint32_t dsp_set_contrast(TheatrePtr t, uint8_t contrast) 761{ 762 uint32_t fb_scratch1 = 0; 763 uint32_t fb_scratch0 = 0; 764 uint32_t result; 765 int screen = t->VIP->scrnIndex; 766 767 fb_scratch0 = ((contrast << 8) & 0xff00) | (71 & 0xff); 768 769 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 770 771 DEBUG("dsp_set_contrast: %x\n", result); 772 773 return result; 774} 775 776#if 0 777static uint32_t dsp_set_sharpness(TheatrePtr t, int sharpness) 778{ 779 uint32_t fb_scratch1 = 0; 780 uint32_t fb_scratch0 = 0; 781 uint32_t result; 782 int screen = t->VIP->scrnIndex; 783 784 fb_scratch0 = 0 | (73 & 0xff); 785 786 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 787 788 DEBUG("dsp_set_sharpness: %x\n", result); 789 790 return result; 791} 792#endif 793 794static uint32_t dsp_set_tint(TheatrePtr t, uint8_t tint) 795{ 796 uint32_t fb_scratch1 = 0; 797 uint32_t fb_scratch0 = 0; 798 uint32_t result; 799 int screen = t->VIP->scrnIndex; 800 801 fb_scratch0 = ((tint << 8) & 0xff00) | (75 & 0xff); 802 803 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 804 805 DEBUG("dsp_set_tint: %x\n", result); 806 807 return result; 808} 809 810static uint32_t dsp_set_saturation(TheatrePtr t, uint8_t saturation) 811{ 812 uint32_t fb_scratch1 = 0; 813 uint32_t fb_scratch0 = 0; 814 uint32_t result; 815 int screen = t->VIP->scrnIndex; 816 817 fb_scratch0 = ((saturation << 8) & 0xff00) | (69 & 0xff); 818 819 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 820 821 DEBUG("dsp_set_saturation: %x\n", result); 822 823 return result; 824} 825 826static uint32_t dsp_set_video_scaler_horizontal(TheatrePtr t, uint16_t output_width, uint16_t horz_start, uint16_t horz_end) 827{ 828 uint32_t fb_scratch1 = 0; 829 uint32_t fb_scratch0 = 0; 830 uint32_t result; 831 int screen = t->VIP->scrnIndex; 832 833 fb_scratch0 = ((output_width << 8) & 0x00ffff00) | (195 & 0xff); 834 fb_scratch1 = ((horz_end << 16) & 0xffff0000) | (horz_start & 0xffff); 835 836 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 837 838 DEBUG("dsp_set_video_scaler_horizontal: %x\n", result); 839 840 return result; 841} 842 843static uint32_t dsp_set_video_scaler_vertical(TheatrePtr t, uint16_t output_height, uint16_t vert_start, uint16_t vert_end) 844{ 845 uint32_t fb_scratch1 = 0; 846 uint32_t fb_scratch0 = 0; 847 uint32_t result; 848 int screen = t->VIP->scrnIndex; 849 850 fb_scratch0 = ((output_height << 8) & 0x00ffff00) | (196 & 0xff); 851 fb_scratch1 = ((vert_end << 16) & 0xffff0000) | (vert_start & 0xffff); 852 853 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 854 855 DEBUG("dsp_set_video_scaler_vertical: %x\n", result); 856 857 return result; 858} 859 860static uint32_t dsp_audio_mute(TheatrePtr t, uint8_t left, uint8_t right) 861{ 862 uint32_t fb_scratch1 = 0; 863 uint32_t fb_scratch0 = 0; 864 uint32_t result; 865 int screen = t->VIP->scrnIndex; 866 867 fb_scratch0 = ((right << 16) & 0xff0000) | ((left << 8) & 0xff00) | (21 & 0xff); 868 869 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 870 871 DEBUG("dsp_audio_mute: %x\n", result); 872 873 return result; 874} 875 876static uint32_t dsp_set_audio_volume(TheatrePtr t, uint8_t left, uint8_t right, uint8_t auto_mute) 877{ 878 uint32_t fb_scratch1 = 0; 879 uint32_t fb_scratch0 = 0; 880 uint32_t result; 881 int screen = t->VIP->scrnIndex; 882 883 fb_scratch0 = ((auto_mute << 24) & 0xff000000) | ((right << 16) & 0xff0000) | ((left << 8) & 0xff00) | (22 & 0xff); 884 885 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 886 887 DEBUG("dsp_set_audio_volume: %x\n", result); 888 889 return result; 890} 891 892#if 0 893static uint32_t dsp_audio_detection(TheatrePtr t, uint8_t option) 894{ 895 uint32_t fb_scratch1 = 0; 896 uint32_t fb_scratch0 = 0; 897 uint32_t result; 898 int screen = t->VIP->scrnIndex; 899 900 fb_scratch0 = ((option << 8) & 0xff00) | (16 & 0xff); 901 902 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 903 904 DEBUG("dsp_audio_detection: %x\n", result); 905 906 return result; 907} 908#endif 909 910static uint32_t dsp_configure_i2s_port(TheatrePtr t, uint8_t tx_mode, uint8_t rx_mode, uint8_t clk_mode) 911{ 912 uint32_t fb_scratch1 = 0; 913 uint32_t fb_scratch0 = 0; 914 uint32_t result; 915 int screen = t->VIP->scrnIndex; 916 917 fb_scratch0 = ((clk_mode << 24) & 0xff000000) | ((rx_mode << 16) & 0xff0000) | ((tx_mode << 8) & 0xff00) | (40 & 0xff); 918 919 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 920 921 DEBUG("dsp_configure_i2s_port: %x\n", result); 922 923 return result; 924} 925 926static uint32_t dsp_configure_spdif_port(TheatrePtr t, uint8_t state) 927{ 928 uint32_t fb_scratch1 = 0; 929 uint32_t fb_scratch0 = 0; 930 uint32_t result; 931 int screen = t->VIP->scrnIndex; 932 933 fb_scratch0 = ((state << 8) & 0xff00) | (41 & 0xff); 934 935 result = dsp_send_command(t, fb_scratch1, fb_scratch0); 936 937 DEBUG("dsp_configure_spdif_port: %x\n", result); 938 939 return result; 940} 941 942enum 943{ 944fld_tmpReg1=0, 945fld_tmpReg2, 946fld_tmpReg3, 947fld_LP_CONTRAST, 948fld_LP_BRIGHTNESS, 949fld_CP_HUE_CNTL, 950fld_LUMA_FILTER, 951fld_H_SCALE_RATIO, 952fld_H_SHARPNESS, 953fld_V_SCALE_RATIO, 954fld_V_DEINTERLACE_ON, 955fld_V_BYPSS, 956fld_V_DITHER_ON, 957fld_EVENF_OFFSET, 958fld_ODDF_OFFSET, 959fld_INTERLACE_DETECTED, 960fld_VS_LINE_COUNT, 961fld_VS_DETECTED_LINES, 962fld_VS_ITU656_VB, 963fld_VBI_CC_DATA, 964fld_VBI_CC_WT, 965fld_VBI_CC_WT_ACK, 966fld_VBI_CC_HOLD, 967fld_VBI_DECODE_EN, 968fld_VBI_CC_DTO_P, 969fld_VBI_20BIT_DTO_P, 970fld_VBI_CC_LEVEL, 971fld_VBI_20BIT_LEVEL, 972fld_VBI_CLK_RUNIN_GAIN, 973fld_H_VBI_WIND_START, 974fld_H_VBI_WIND_END, 975fld_V_VBI_WIND_START, 976fld_V_VBI_WIND_END, 977fld_VBI_20BIT_DATA0, 978fld_VBI_20BIT_DATA1, 979fld_VBI_20BIT_WT, 980fld_VBI_20BIT_WT_ACK, 981fld_VBI_20BIT_HOLD, 982fld_VBI_CAPTURE_ENABLE, 983fld_VBI_EDS_DATA, 984fld_VBI_EDS_WT, 985fld_VBI_EDS_WT_ACK, 986fld_VBI_EDS_HOLD, 987fld_VBI_SCALING_RATIO, 988fld_VBI_ALIGNER_ENABLE, 989fld_H_ACTIVE_START, 990fld_H_ACTIVE_END, 991fld_V_ACTIVE_START, 992fld_V_ACTIVE_END, 993fld_CH_HEIGHT, 994fld_CH_KILL_LEVEL, 995fld_CH_AGC_ERROR_LIM, 996fld_CH_AGC_FILTER_EN, 997fld_CH_AGC_LOOP_SPEED, 998fld_HUE_ADJ, 999fld_STANDARD_SEL, 1000fld_STANDARD_YC, 1001fld_ADC_PDWN, 1002fld_INPUT_SELECT, 1003fld_ADC_PREFLO, 1004fld_H_SYNC_PULSE_WIDTH, 1005fld_HS_GENLOCKED, 1006fld_HS_SYNC_IN_WIN, 1007fld_VIN_ASYNC_RST, 1008fld_DVS_ASYNC_RST, 1009fld_VIP_VENDOR_ID, 1010fld_VIP_DEVICE_ID, 1011fld_VIP_REVISION_ID, 1012fld_BLACK_INT_START, 1013fld_BLACK_INT_LENGTH, 1014fld_UV_INT_START, 1015fld_U_INT_LENGTH, 1016fld_V_INT_LENGTH, 1017fld_CRDR_ACTIVE_GAIN, 1018fld_CBDB_ACTIVE_GAIN, 1019fld_DVS_DIRECTION, 1020fld_DVS_VBI_UINT8_SWAP, 1021fld_DVS_CLK_SELECT, 1022fld_CONTINUOUS_STREAM, 1023fld_DVSOUT_CLK_DRV, 1024fld_DVSOUT_DATA_DRV, 1025fld_COMB_CNTL0, 1026fld_COMB_CNTL1, 1027fld_COMB_CNTL2, 1028fld_COMB_LENGTH, 1029fld_SYNCTIP_REF0, 1030fld_SYNCTIP_REF1, 1031fld_CLAMP_REF, 1032fld_AGC_PEAKWHITE, 1033fld_VBI_PEAKWHITE, 1034fld_WPA_THRESHOLD, 1035fld_WPA_TRIGGER_LO, 1036fld_WPA_TRIGGER_HIGH, 1037fld_LOCKOUT_START, 1038fld_LOCKOUT_END, 1039fld_CH_DTO_INC, 1040fld_PLL_SGAIN, 1041fld_PLL_FGAIN, 1042fld_CR_BURST_GAIN, 1043fld_CB_BURST_GAIN, 1044fld_VERT_LOCKOUT_START, 1045fld_VERT_LOCKOUT_END, 1046fld_H_IN_WIND_START, 1047fld_V_IN_WIND_START, 1048fld_H_OUT_WIND_WIDTH, 1049fld_V_OUT_WIND_WIDTH, 1050fld_HS_LINE_TOTAL, 1051fld_MIN_PULSE_WIDTH, 1052fld_MAX_PULSE_WIDTH, 1053fld_WIN_CLOSE_LIMIT, 1054fld_WIN_OPEN_LIMIT, 1055fld_VSYNC_INT_TRIGGER, 1056fld_VSYNC_INT_HOLD, 1057fld_VIN_M0, 1058fld_VIN_N0, 1059fld_MNFLIP_EN, 1060fld_VIN_P, 1061fld_REG_CLK_SEL, 1062fld_VIN_M1, 1063fld_VIN_N1, 1064fld_VIN_DRIVER_SEL, 1065fld_VIN_MNFLIP_REQ, 1066fld_VIN_MNFLIP_DONE, 1067fld_TV_LOCK_TO_VIN, 1068fld_TV_P_FOR_WINCLK, 1069fld_VINRST, 1070fld_VIN_CLK_SEL, 1071fld_VS_FIELD_BLANK_START, 1072fld_VS_FIELD_BLANK_END, 1073fld_VS_FIELD_IDLOCATION, 1074fld_VS_FRAME_TOTAL, 1075fld_SYNC_TIP_START, 1076fld_SYNC_TIP_LENGTH, 1077fld_GAIN_FORCE_DATA, 1078fld_GAIN_FORCE_EN, 1079fld_I_CLAMP_SEL, 1080fld_I_AGC_SEL, 1081fld_EXT_CLAMP_CAP, 1082fld_EXT_AGC_CAP, 1083fld_DECI_DITHER_EN, 1084fld_ADC_PREFHI, 1085fld_ADC_CH_GAIN_SEL, 1086fld_HS_PLL_SGAIN, 1087fld_NREn, 1088fld_NRGainCntl, 1089fld_NRBWTresh, 1090fld_NRGCTresh, 1091fld_NRCoefDespeclMode, 1092fld_GPIO_5_OE, 1093fld_GPIO_6_OE, 1094fld_GPIO_5_OUT, 1095fld_GPIO_6_OUT, 1096 1097regRT_MAX_REGS 1098} a; 1099 1100 1101typedef struct { 1102 uint8_t size; 1103 uint32_t fld_id; 1104 uint32_t dwRegAddrLSBs; 1105 uint32_t dwFldOffsetLSBs; 1106 uint32_t dwMaskLSBs; 1107 uint32_t addr2; 1108 uint32_t offs2; 1109 uint32_t mask2; 1110 uint32_t dwCurrValue; 1111 uint32_t rw; 1112 } RTREGMAP; 1113 1114#define READONLY 1 1115#define WRITEONLY 2 1116#define READWRITE 3 1117 1118/* Rage Theatre's Register Mappings, including the default values: */ 1119RTREGMAP RT_RegMap[regRT_MAX_REGS]={ 1120/* 1121{size, fidname, AddrOfst, Ofst, Mask, Addr, Ofst, Mask, Cur, R/W 1122*/ 1123{32 , fld_tmpReg1 ,0x151 , 0, 0x0, 0, 0,0, 0,READWRITE }, 1124{1 , fld_tmpReg2 ,VIP_VIP_SUB_VENDOR_DEVICE_ID , 3, 0xFFFFFFFF, 0, 0,0, 0,READWRITE }, 1125{1 , fld_tmpReg3 ,VIP_VIP_COMMAND_STATUS , 3, 0xFFFFFFFF, 0, 0,0, 0,READWRITE }, 1126{8 , fld_LP_CONTRAST ,VIP_LP_CONTRAST , 0, 0xFFFFFF00, 0, 0,0, fld_LP_CONTRAST_def ,READWRITE }, 1127{14 , fld_LP_BRIGHTNESS ,VIP_LP_BRIGHTNESS , 0, 0xFFFFC000, 0, 0,0, fld_LP_BRIGHTNESS_def ,READWRITE }, 1128{8 , fld_CP_HUE_CNTL ,VIP_CP_HUE_CNTL , 0, 0xFFFFFF00, 0, 0,0, fld_CP_HUE_CNTL_def ,READWRITE }, 1129{1 , fld_LUMA_FILTER ,VIP_LP_BRIGHTNESS , 15, 0xFFFF7FFF, 0, 0,0, fld_LUMA_FILTER_def ,READWRITE }, 1130{21 , fld_H_SCALE_RATIO ,VIP_H_SCALER_CONTROL , 0, 0xFFE00000, 0, 0,0, fld_H_SCALE_RATIO_def ,READWRITE }, 1131{4 , fld_H_SHARPNESS ,VIP_H_SCALER_CONTROL , 25, 0xE1FFFFFF, 0, 0,0, fld_H_SHARPNESS_def ,READWRITE }, 1132{12 , fld_V_SCALE_RATIO ,VIP_V_SCALER_CONTROL , 0, 0xFFFFF000, 0, 0,0, fld_V_SCALE_RATIO_def ,READWRITE }, 1133{1 , fld_V_DEINTERLACE_ON,VIP_V_SCALER_CONTROL , 12, 0xFFFFEFFF, 0, 0,0, fld_V_DEINTERLACE_ON_def ,READWRITE }, 1134{1 , fld_V_BYPSS ,VIP_V_SCALER_CONTROL , 14, 0xFFFFBFFF, 0, 0,0, fld_V_BYPSS_def ,READWRITE }, 1135{1 , fld_V_DITHER_ON ,VIP_V_SCALER_CONTROL , 15, 0xFFFF7FFF, 0, 0,0, fld_V_DITHER_ON_def ,READWRITE }, 1136{11 , fld_EVENF_OFFSET ,VIP_V_DEINTERLACE_CONTROL , 0, 0xFFFFF800, 0, 0,0, fld_EVENF_OFFSET_def ,READWRITE }, 1137{11 , fld_ODDF_OFFSET ,VIP_V_DEINTERLACE_CONTROL , 11, 0xFFC007FF, 0, 0,0, fld_ODDF_OFFSET_def ,READWRITE }, 1138{1 , fld_INTERLACE_DETECTED ,VIP_VS_LINE_COUNT , 15, 0xFFFF7FFF, 0, 0,0, fld_INTERLACE_DETECTED_def,READONLY }, 1139{10 , fld_VS_LINE_COUNT ,VIP_VS_LINE_COUNT , 0, 0xFFFFFC00, 0, 0,0, fld_VS_LINE_COUNT_def ,READONLY }, 1140{10 , fld_VS_DETECTED_LINES ,VIP_VS_LINE_COUNT , 16, 0xFC00FFFF, 0, 0,0, fld_VS_DETECTED_LINES_def ,READONLY }, 1141{1 , fld_VS_ITU656_VB ,VIP_VS_LINE_COUNT , 13, 0xFFFFDFFF, 0, 0,0, fld_VS_ITU656_VB_def ,READONLY }, 1142{16 , fld_VBI_CC_DATA ,VIP_VBI_CC_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_CC_DATA_def ,READWRITE }, 1143{1 , fld_VBI_CC_WT ,VIP_VBI_CC_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VBI_CC_WT_def ,READWRITE }, 1144{1 , fld_VBI_CC_WT_ACK ,VIP_VBI_CC_CNTL , 25, 0xFDFFFFFF, 0, 0,0, fld_VBI_CC_WT_ACK_def ,READONLY }, 1145{1 , fld_VBI_CC_HOLD ,VIP_VBI_CC_CNTL , 26, 0xFBFFFFFF, 0, 0,0, fld_VBI_CC_HOLD_def ,READWRITE }, 1146{1 , fld_VBI_DECODE_EN ,VIP_VBI_CC_CNTL , 31, 0x7FFFFFFF, 0, 0,0, fld_VBI_DECODE_EN_def ,READWRITE }, 1147{16 , fld_VBI_CC_DTO_P ,VIP_VBI_DTO_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_CC_DTO_P_def ,READWRITE }, 1148{16 ,fld_VBI_20BIT_DTO_P,VIP_VBI_DTO_CNTL , 16, 0x0000FFFF, 0, 0,0, fld_VBI_20BIT_DTO_P_def ,READWRITE }, 1149{7 ,fld_VBI_CC_LEVEL ,VIP_VBI_LEVEL_CNTL , 0, 0xFFFFFF80, 0, 0,0, fld_VBI_CC_LEVEL_def ,READWRITE }, 1150{7 ,fld_VBI_20BIT_LEVEL,VIP_VBI_LEVEL_CNTL , 8, 0xFFFF80FF, 0, 0,0, fld_VBI_20BIT_LEVEL_def ,READWRITE }, 1151{9 ,fld_VBI_CLK_RUNIN_GAIN,VIP_VBI_LEVEL_CNTL , 16, 0xFE00FFFF, 0, 0,0, fld_VBI_CLK_RUNIN_GAIN_def,READWRITE }, 1152{11 ,fld_H_VBI_WIND_START,VIP_H_VBI_WINDOW , 0, 0xFFFFF800, 0, 0,0, fld_H_VBI_WIND_START_def ,READWRITE }, 1153{11 ,fld_H_VBI_WIND_END,VIP_H_VBI_WINDOW , 16, 0xF800FFFF, 0, 0,0, fld_H_VBI_WIND_END_def ,READWRITE }, 1154{10 ,fld_V_VBI_WIND_START,VIP_V_VBI_WINDOW , 0, 0xFFFFFC00, 0, 0,0, fld_V_VBI_WIND_START_def ,READWRITE }, 1155{10 ,fld_V_VBI_WIND_END,VIP_V_VBI_WINDOW , 16, 0xFC00FFFF, 0, 0,0, fld_V_VBI_WIND_END_def ,READWRITE }, /* CHK */ 1156{16 ,fld_VBI_20BIT_DATA0,VIP_VBI_20BIT_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_20BIT_DATA0_def ,READWRITE }, 1157{4 ,fld_VBI_20BIT_DATA1,VIP_VBI_20BIT_CNTL , 16, 0xFFF0FFFF, 0, 0,0, fld_VBI_20BIT_DATA1_def ,READWRITE }, 1158{1 ,fld_VBI_20BIT_WT ,VIP_VBI_20BIT_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VBI_20BIT_WT_def ,READWRITE }, 1159{1 ,fld_VBI_20BIT_WT_ACK ,VIP_VBI_20BIT_CNTL , 25, 0xFDFFFFFF, 0, 0,0, fld_VBI_20BIT_WT_ACK_def ,READONLY }, 1160{1 ,fld_VBI_20BIT_HOLD ,VIP_VBI_20BIT_CNTL , 26, 0xFBFFFFFF, 0, 0,0, fld_VBI_20BIT_HOLD_def ,READWRITE }, 1161{2 ,fld_VBI_CAPTURE_ENABLE ,VIP_VBI_CONTROL , 0, 0xFFFFFFFC, 0, 0,0, fld_VBI_CAPTURE_ENABLE_def,READWRITE }, 1162{16 ,fld_VBI_EDS_DATA ,VIP_VBI_EDS_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_EDS_DATA_def ,READWRITE }, 1163{1 ,fld_VBI_EDS_WT ,VIP_VBI_EDS_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VBI_EDS_WT_def ,READWRITE }, 1164{1 ,fld_VBI_EDS_WT_ACK ,VIP_VBI_EDS_CNTL , 25, 0xFDFFFFFF, 0, 0,0, fld_VBI_EDS_WT_ACK_def ,READONLY }, 1165{1 ,fld_VBI_EDS_HOLD ,VIP_VBI_EDS_CNTL , 26, 0xFBFFFFFF, 0, 0,0, fld_VBI_EDS_HOLD_def ,READWRITE }, 1166{17 ,fld_VBI_SCALING_RATIO ,VIP_VBI_SCALER_CONTROL , 0, 0xFFFE0000, 0, 0,0, fld_VBI_SCALING_RATIO_def ,READWRITE }, 1167{1 ,fld_VBI_ALIGNER_ENABLE ,VIP_VBI_SCALER_CONTROL , 17, 0xFFFDFFFF, 0, 0,0, fld_VBI_ALIGNER_ENABLE_def,READWRITE }, 1168{11 ,fld_H_ACTIVE_START ,VIP_H_ACTIVE_WINDOW , 0, 0xFFFFF800, 0, 0,0, fld_H_ACTIVE_START_def ,READWRITE }, 1169{11 ,fld_H_ACTIVE_END ,VIP_H_ACTIVE_WINDOW , 16, 0xF800FFFF, 0, 0,0, fld_H_ACTIVE_END_def ,READWRITE }, 1170{10 ,fld_V_ACTIVE_START ,VIP_V_ACTIVE_WINDOW , 0, 0xFFFFFC00, 0, 0,0, fld_V_ACTIVE_START_def ,READWRITE }, 1171{10 ,fld_V_ACTIVE_END ,VIP_V_ACTIVE_WINDOW , 16, 0xFC00FFFF, 0, 0,0, fld_V_ACTIVE_END_def ,READWRITE }, 1172{8 ,fld_CH_HEIGHT ,VIP_CP_AGC_CNTL , 0, 0xFFFFFF00, 0, 0,0, fld_CH_HEIGHT_def ,READWRITE }, 1173{8 ,fld_CH_KILL_LEVEL ,VIP_CP_AGC_CNTL , 8, 0xFFFF00FF, 0, 0,0, fld_CH_KILL_LEVEL_def ,READWRITE }, 1174{2 ,fld_CH_AGC_ERROR_LIM ,VIP_CP_AGC_CNTL , 16, 0xFFFCFFFF, 0, 0,0, fld_CH_AGC_ERROR_LIM_def ,READWRITE }, 1175{1 ,fld_CH_AGC_FILTER_EN ,VIP_CP_AGC_CNTL , 18, 0xFFFBFFFF, 0, 0,0, fld_CH_AGC_FILTER_EN_def ,READWRITE }, 1176{1 ,fld_CH_AGC_LOOP_SPEED ,VIP_CP_AGC_CNTL , 19, 0xFFF7FFFF, 0, 0,0, fld_CH_AGC_LOOP_SPEED_def ,READWRITE }, 1177{8 ,fld_HUE_ADJ ,VIP_CP_HUE_CNTL , 0, 0xFFFFFF00, 0, 0,0, fld_HUE_ADJ_def ,READWRITE }, 1178{2 ,fld_STANDARD_SEL ,VIP_STANDARD_SELECT , 0, 0xFFFFFFFC, 0, 0,0, fld_STANDARD_SEL_def ,READWRITE }, 1179{1 ,fld_STANDARD_YC ,VIP_STANDARD_SELECT , 2, 0xFFFFFFFB, 0, 0,0, fld_STANDARD_YC_def ,READWRITE }, 1180{1 ,fld_ADC_PDWN ,VIP_ADC_CNTL , 7, 0xFFFFFF7F, 0, 0,0, fld_ADC_PDWN_def ,READWRITE }, 1181{3 ,fld_INPUT_SELECT ,VIP_ADC_CNTL , 0, 0xFFFFFFF8, 0, 0,0, fld_INPUT_SELECT_def ,READWRITE }, 1182{2 ,fld_ADC_PREFLO ,VIP_ADC_CNTL , 24, 0xFCFFFFFF, 0, 0,0, fld_ADC_PREFLO_def ,READWRITE }, 1183{8 ,fld_H_SYNC_PULSE_WIDTH ,VIP_HS_PULSE_WIDTH , 0, 0xFFFFFF00, 0, 0,0, fld_H_SYNC_PULSE_WIDTH_def,READONLY }, 1184{1 ,fld_HS_GENLOCKED ,VIP_HS_PULSE_WIDTH , 8, 0xFFFFFEFF, 0, 0,0, fld_HS_GENLOCKED_def ,READONLY }, 1185{1 ,fld_HS_SYNC_IN_WIN ,VIP_HS_PULSE_WIDTH , 9, 0xFFFFFDFF, 0, 0,0, fld_HS_SYNC_IN_WIN_def ,READONLY }, 1186{1 ,fld_VIN_ASYNC_RST ,VIP_MASTER_CNTL , 5, 0xFFFFFFDF, 0, 0,0, fld_VIN_ASYNC_RST_def ,READWRITE }, 1187{1 ,fld_DVS_ASYNC_RST ,VIP_MASTER_CNTL , 7, 0xFFFFFF7F, 0, 0,0, fld_DVS_ASYNC_RST_def ,READWRITE }, 1188{16 ,fld_VIP_VENDOR_ID ,VIP_VIP_VENDOR_DEVICE_ID, 0, 0xFFFF0000, 0, 0,0, fld_VIP_VENDOR_ID_def ,READONLY }, 1189{16 ,fld_VIP_DEVICE_ID ,VIP_VIP_VENDOR_DEVICE_ID,16, 0x0000FFFF, 0, 0,0, fld_VIP_DEVICE_ID_def ,READONLY }, 1190{16 ,fld_VIP_REVISION_ID ,VIP_VIP_REVISION_ID , 0, 0xFFFF0000, 0, 0,0, fld_VIP_REVISION_ID_def ,READONLY }, 1191{8 ,fld_BLACK_INT_START ,VIP_SG_BLACK_GATE , 0, 0xFFFFFF00, 0, 0,0, fld_BLACK_INT_START_def ,READWRITE }, 1192{4 ,fld_BLACK_INT_LENGTH ,VIP_SG_BLACK_GATE , 8, 0xFFFFF0FF, 0, 0,0, fld_BLACK_INT_LENGTH_def ,READWRITE }, 1193{8 ,fld_UV_INT_START ,VIP_SG_UVGATE_GATE , 0, 0xFFFFFF00, 0, 0,0, fld_UV_INT_START_def ,READWRITE }, 1194{4 ,fld_U_INT_LENGTH ,VIP_SG_UVGATE_GATE , 8, 0xFFFFF0FF, 0, 0,0, fld_U_INT_LENGTH_def ,READWRITE }, 1195{4 ,fld_V_INT_LENGTH ,VIP_SG_UVGATE_GATE , 12, 0xFFFF0FFF, 0, 0,0, fld_V_INT_LENGTH_def ,READWRITE }, 1196{10 ,fld_CRDR_ACTIVE_GAIN ,VIP_CP_ACTIVE_GAIN , 0, 0xFFFFFC00, 0, 0,0, fld_CRDR_ACTIVE_GAIN_def ,READWRITE }, 1197{10 ,fld_CBDB_ACTIVE_GAIN ,VIP_CP_ACTIVE_GAIN , 16, 0xFC00FFFF, 0, 0,0, fld_CBDB_ACTIVE_GAIN_def ,READWRITE }, 1198{1 ,fld_DVS_DIRECTION ,VIP_DVS_PORT_CTRL , 0, 0xFFFFFFFE, 0, 0,0, fld_DVS_DIRECTION_def ,READWRITE }, 1199{1 ,fld_DVS_VBI_UINT8_SWAP ,VIP_DVS_PORT_CTRL , 1, 0xFFFFFFFD, 0, 0,0, fld_DVS_VBI_UINT8_SWAP_def ,READWRITE }, 1200{1 ,fld_DVS_CLK_SELECT ,VIP_DVS_PORT_CTRL , 2, 0xFFFFFFFB, 0, 0,0, fld_DVS_CLK_SELECT_def ,READWRITE }, 1201{1 ,fld_CONTINUOUS_STREAM ,VIP_DVS_PORT_CTRL , 3, 0xFFFFFFF7, 0, 0,0, fld_CONTINUOUS_STREAM_def ,READWRITE }, 1202{1 ,fld_DVSOUT_CLK_DRV ,VIP_DVS_PORT_CTRL , 4, 0xFFFFFFEF, 0, 0,0, fld_DVSOUT_CLK_DRV_def ,READWRITE }, 1203{1 ,fld_DVSOUT_DATA_DRV ,VIP_DVS_PORT_CTRL , 5, 0xFFFFFFDF, 0, 0,0, fld_DVSOUT_DATA_DRV_def ,READWRITE }, 1204{32 ,fld_COMB_CNTL0 ,VIP_COMB_CNTL0 , 0, 0x00000000, 0, 0,0, fld_COMB_CNTL0_def ,READWRITE }, 1205{32 ,fld_COMB_CNTL1 ,VIP_COMB_CNTL1 , 0, 0x00000000, 0, 0,0, fld_COMB_CNTL1_def ,READWRITE }, 1206{32 ,fld_COMB_CNTL2 ,VIP_COMB_CNTL2 , 0, 0x00000000, 0, 0,0, fld_COMB_CNTL2_def ,READWRITE }, 1207{32 ,fld_COMB_LENGTH ,VIP_COMB_LINE_LENGTH , 0, 0x00000000, 0, 0,0, fld_COMB_LENGTH_def ,READWRITE }, 1208{8 ,fld_SYNCTIP_REF0 ,VIP_LP_AGC_CLAMP_CNTL0 , 0, 0xFFFFFF00, 0, 0,0, fld_SYNCTIP_REF0_def ,READWRITE }, 1209{8 ,fld_SYNCTIP_REF1 ,VIP_LP_AGC_CLAMP_CNTL0 , 8, 0xFFFF00FF, 0, 0,0, fld_SYNCTIP_REF1_def ,READWRITE }, 1210{8 ,fld_CLAMP_REF ,VIP_LP_AGC_CLAMP_CNTL0 , 16, 0xFF00FFFF, 0, 0,0, fld_CLAMP_REF_def ,READWRITE }, 1211{8 ,fld_AGC_PEAKWHITE ,VIP_LP_AGC_CLAMP_CNTL0 , 24, 0x00FFFFFF, 0, 0,0, fld_AGC_PEAKWHITE_def ,READWRITE }, 1212{8 ,fld_VBI_PEAKWHITE ,VIP_LP_AGC_CLAMP_CNTL1 , 0, 0xFFFFFF00, 0, 0,0, fld_VBI_PEAKWHITE_def ,READWRITE }, 1213{11 ,fld_WPA_THRESHOLD ,VIP_LP_WPA_CNTL0 , 0, 0xFFFFF800, 0, 0,0, fld_WPA_THRESHOLD_def ,READWRITE }, 1214{10 ,fld_WPA_TRIGGER_LO ,VIP_LP_WPA_CNTL1 , 0, 0xFFFFFC00, 0, 0,0, fld_WPA_TRIGGER_LO_def ,READWRITE }, 1215{10 ,fld_WPA_TRIGGER_HIGH ,VIP_LP_WPA_CNTL1 , 16, 0xFC00FFFF, 0, 0,0, fld_WPA_TRIGGER_HIGH_def ,READWRITE }, 1216{10 ,fld_LOCKOUT_START ,VIP_LP_VERT_LOCKOUT , 0, 0xFFFFFC00, 0, 0,0, fld_LOCKOUT_START_def ,READWRITE }, 1217{10 ,fld_LOCKOUT_END ,VIP_LP_VERT_LOCKOUT , 16, 0xFC00FFFF, 0, 0,0, fld_LOCKOUT_END_def ,READWRITE }, 1218{24 ,fld_CH_DTO_INC ,VIP_CP_PLL_CNTL0 , 0, 0xFF000000, 0, 0,0, fld_CH_DTO_INC_def ,READWRITE }, 1219{4 ,fld_PLL_SGAIN ,VIP_CP_PLL_CNTL0 , 24, 0xF0FFFFFF, 0, 0,0, fld_PLL_SGAIN_def ,READWRITE }, 1220{4 ,fld_PLL_FGAIN ,VIP_CP_PLL_CNTL0 , 28, 0x0FFFFFFF, 0, 0,0, fld_PLL_FGAIN_def ,READWRITE }, 1221{9 ,fld_CR_BURST_GAIN ,VIP_CP_BURST_GAIN , 0, 0xFFFFFE00, 0, 0,0, fld_CR_BURST_GAIN_def ,READWRITE }, 1222{9 ,fld_CB_BURST_GAIN ,VIP_CP_BURST_GAIN , 16, 0xFE00FFFF, 0, 0,0, fld_CB_BURST_GAIN_def ,READWRITE }, 1223{10 ,fld_VERT_LOCKOUT_START ,VIP_CP_VERT_LOCKOUT , 0, 0xFFFFFC00, 0, 0,0, fld_VERT_LOCKOUT_START_def,READWRITE }, 1224{10 ,fld_VERT_LOCKOUT_END ,VIP_CP_VERT_LOCKOUT , 16, 0xFC00FFFF, 0, 0,0, fld_VERT_LOCKOUT_END_def ,READWRITE }, 1225{11 ,fld_H_IN_WIND_START ,VIP_SCALER_IN_WINDOW , 0, 0xFFFFF800, 0, 0,0, fld_H_IN_WIND_START_def ,READWRITE }, 1226{10 ,fld_V_IN_WIND_START ,VIP_SCALER_IN_WINDOW , 16, 0xFC00FFFF, 0, 0,0, fld_V_IN_WIND_START_def ,READWRITE }, 1227{10 ,fld_H_OUT_WIND_WIDTH ,VIP_SCALER_OUT_WINDOW , 0, 0xFFFFFC00, 0, 0,0, fld_H_OUT_WIND_WIDTH_def ,READWRITE }, 1228{9 ,fld_V_OUT_WIND_WIDTH ,VIP_SCALER_OUT_WINDOW , 16, 0xFE00FFFF, 0, 0,0, fld_V_OUT_WIND_WIDTH_def ,READWRITE }, 1229{11 ,fld_HS_LINE_TOTAL ,VIP_HS_PLINE , 0, 0xFFFFF800, 0, 0,0, fld_HS_LINE_TOTAL_def ,READWRITE }, 1230{8 ,fld_MIN_PULSE_WIDTH ,VIP_HS_MINMAXWIDTH , 0, 0xFFFFFF00, 0, 0,0, fld_MIN_PULSE_WIDTH_def ,READWRITE }, 1231{8 ,fld_MAX_PULSE_WIDTH ,VIP_HS_MINMAXWIDTH , 8, 0xFFFF00FF, 0, 0,0, fld_MAX_PULSE_WIDTH_def ,READWRITE }, 1232{11 ,fld_WIN_CLOSE_LIMIT ,VIP_HS_WINDOW_LIMIT , 0, 0xFFFFF800, 0, 0,0, fld_WIN_CLOSE_LIMIT_def ,READWRITE }, 1233{11 ,fld_WIN_OPEN_LIMIT ,VIP_HS_WINDOW_LIMIT , 16, 0xF800FFFF, 0, 0,0, fld_WIN_OPEN_LIMIT_def ,READWRITE }, 1234{11 ,fld_VSYNC_INT_TRIGGER ,VIP_VS_DETECTOR_CNTL , 0, 0xFFFFF800, 0, 0,0, fld_VSYNC_INT_TRIGGER_def ,READWRITE }, 1235{11 ,fld_VSYNC_INT_HOLD ,VIP_VS_DETECTOR_CNTL , 16, 0xF800FFFF, 0, 0,0, fld_VSYNC_INT_HOLD_def ,READWRITE }, 1236{11 ,fld_VIN_M0 ,VIP_VIN_PLL_CNTL , 0, 0xFFFFF800, 0, 0,0, fld_VIN_M0_def ,READWRITE }, 1237{11 ,fld_VIN_N0 ,VIP_VIN_PLL_CNTL , 11, 0xFFC007FF, 0, 0,0, fld_VIN_N0_def ,READWRITE }, 1238{1 ,fld_MNFLIP_EN ,VIP_VIN_PLL_CNTL , 22, 0xFFBFFFFF, 0, 0,0, fld_MNFLIP_EN_def ,READWRITE }, 1239{4 ,fld_VIN_P ,VIP_VIN_PLL_CNTL , 24, 0xF0FFFFFF, 0, 0,0, fld_VIN_P_def ,READWRITE }, 1240{2 ,fld_REG_CLK_SEL ,VIP_VIN_PLL_CNTL , 30, 0x3FFFFFFF, 0, 0,0, fld_REG_CLK_SEL_def ,READWRITE }, 1241{11 ,fld_VIN_M1 ,VIP_VIN_PLL_FINE_CNTL , 0, 0xFFFFF800, 0, 0,0, fld_VIN_M1_def ,READWRITE }, 1242{11 ,fld_VIN_N1 ,VIP_VIN_PLL_FINE_CNTL , 11, 0xFFC007FF, 0, 0,0, fld_VIN_N1_def ,READWRITE }, 1243{1 ,fld_VIN_DRIVER_SEL ,VIP_VIN_PLL_FINE_CNTL , 22, 0xFFBFFFFF, 0, 0,0, fld_VIN_DRIVER_SEL_def ,READWRITE }, 1244{1 ,fld_VIN_MNFLIP_REQ ,VIP_VIN_PLL_FINE_CNTL , 23, 0xFF7FFFFF, 0, 0,0, fld_VIN_MNFLIP_REQ_def ,READWRITE }, 1245{1 ,fld_VIN_MNFLIP_DONE ,VIP_VIN_PLL_FINE_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VIN_MNFLIP_DONE_def ,READONLY }, 1246{1 ,fld_TV_LOCK_TO_VIN ,VIP_VIN_PLL_FINE_CNTL , 27, 0xF7FFFFFF, 0, 0,0, fld_TV_LOCK_TO_VIN_def ,READWRITE }, 1247{4 ,fld_TV_P_FOR_WINCLK ,VIP_VIN_PLL_FINE_CNTL , 28, 0x0FFFFFFF, 0, 0,0, fld_TV_P_FOR_WINCLK_def ,READWRITE }, 1248{1 ,fld_VINRST ,VIP_PLL_CNTL1 , 1, 0xFFFFFFFD, 0, 0,0, fld_VINRST_def ,READWRITE }, 1249{1 ,fld_VIN_CLK_SEL ,VIP_CLOCK_SEL_CNTL , 7, 0xFFFFFF7F, 0, 0,0, fld_VIN_CLK_SEL_def ,READWRITE }, 1250{10 ,fld_VS_FIELD_BLANK_START,VIP_VS_BLANKING_CNTL , 0, 0xFFFFFC00, 0, 0,0, fld_VS_FIELD_BLANK_START_def ,READWRITE }, 1251{10 ,fld_VS_FIELD_BLANK_END,VIP_VS_BLANKING_CNTL , 16, 0xFC00FFFF, 0, 0,0, fld_VS_FIELD_BLANK_END_def ,READWRITE }, 1252{9 ,fld_VS_FIELD_IDLOCATION,VIP_VS_FIELD_ID_CNTL , 0, 0xFFFFFE00, 0, 0,0, fld_VS_FIELD_IDLOCATION_def ,READWRITE }, 1253{10 ,fld_VS_FRAME_TOTAL ,VIP_VS_FRAME_TOTAL , 0, 0xFFFFFC00, 0, 0,0, fld_VS_FRAME_TOTAL_def ,READWRITE }, 1254{11 ,fld_SYNC_TIP_START ,VIP_SG_SYNCTIP_GATE , 0, 0xFFFFF800, 0, 0,0, fld_SYNC_TIP_START_def ,READWRITE }, 1255{4 ,fld_SYNC_TIP_LENGTH ,VIP_SG_SYNCTIP_GATE , 12, 0xFFFF0FFF, 0, 0,0, fld_SYNC_TIP_LENGTH_def ,READWRITE }, 1256{12 ,fld_GAIN_FORCE_DATA ,VIP_CP_DEBUG_FORCE , 0, 0xFFFFF000, 0, 0,0, fld_GAIN_FORCE_DATA_def ,READWRITE }, 1257{1 ,fld_GAIN_FORCE_EN ,VIP_CP_DEBUG_FORCE , 12, 0xFFFFEFFF, 0, 0,0, fld_GAIN_FORCE_EN_def ,READWRITE }, 1258{2 ,fld_I_CLAMP_SEL ,VIP_ADC_CNTL , 3, 0xFFFFFFE7, 0, 0,0, fld_I_CLAMP_SEL_def ,READWRITE }, 1259{2 ,fld_I_AGC_SEL ,VIP_ADC_CNTL , 5, 0xFFFFFF9F, 0, 0,0, fld_I_AGC_SEL_def ,READWRITE }, 1260{1 ,fld_EXT_CLAMP_CAP ,VIP_ADC_CNTL , 8, 0xFFFFFEFF, 0, 0,0, fld_EXT_CLAMP_CAP_def ,READWRITE }, 1261{1 ,fld_EXT_AGC_CAP ,VIP_ADC_CNTL , 9, 0xFFFFFDFF, 0, 0,0, fld_EXT_AGC_CAP_def ,READWRITE }, 1262{1 ,fld_DECI_DITHER_EN ,VIP_ADC_CNTL , 12, 0xFFFFEFFF, 0, 0,0, fld_DECI_DITHER_EN_def ,READWRITE }, 1263{2 ,fld_ADC_PREFHI ,VIP_ADC_CNTL , 22, 0xFF3FFFFF, 0, 0,0, fld_ADC_PREFHI_def ,READWRITE }, 1264{2 ,fld_ADC_CH_GAIN_SEL ,VIP_ADC_CNTL , 16, 0xFFFCFFFF, 0, 0,0, fld_ADC_CH_GAIN_SEL_def ,READWRITE }, 1265{4 ,fld_HS_PLL_SGAIN ,VIP_HS_PLLGAIN , 0, 0xFFFFFFF0, 0, 0,0, fld_HS_PLL_SGAIN_def ,READWRITE }, 1266{1 ,fld_NREn ,VIP_NOISE_CNTL0 , 0, 0xFFFFFFFE, 0, 0,0, fld_NREn_def ,READWRITE }, 1267{3 ,fld_NRGainCntl ,VIP_NOISE_CNTL0 , 1, 0xFFFFFFF1, 0, 0,0, fld_NRGainCntl_def ,READWRITE }, 1268{6 ,fld_NRBWTresh ,VIP_NOISE_CNTL0 , 4, 0xFFFFFC0F, 0, 0,0, fld_NRBWTresh_def ,READWRITE }, 1269{5 ,fld_NRGCTresh ,VIP_NOISE_CNTL0 , 10, 0xFFFF83FF, 0, 0,0, fld_NRGCTresh_def ,READWRITE }, 1270{1 ,fld_NRCoefDespeclMode ,VIP_NOISE_CNTL0 , 15, 0xFFFF7FFF, 0, 0,0, fld_NRCoefDespeclMode_def ,READWRITE }, 1271{1 ,fld_GPIO_5_OE ,VIP_GPIO_CNTL , 5, 0xFFFFFFDF, 0, 0,0, fld_GPIO_5_OE_def ,READWRITE }, 1272{1 ,fld_GPIO_6_OE ,VIP_GPIO_CNTL , 6, 0xFFFFFFBF, 0, 0,0, fld_GPIO_6_OE_def ,READWRITE }, 1273{1 ,fld_GPIO_5_OUT ,VIP_GPIO_INOUT , 5, 0xFFFFFFDF, 0, 0,0, fld_GPIO_5_OUT_def ,READWRITE }, 1274{1 ,fld_GPIO_6_OUT ,VIP_GPIO_INOUT , 6, 0xFFFFFFBF, 0, 0,0, fld_GPIO_6_OUT_def ,READWRITE }, 1275}; 1276 1277/* Rage Theatre's register fields default values: */ 1278uint32_t RT_RegDef[regRT_MAX_REGS]= 1279{ 1280fld_tmpReg1_def, 1281fld_tmpReg2_def, 1282fld_tmpReg3_def, 1283fld_LP_CONTRAST_def, 1284fld_LP_BRIGHTNESS_def, 1285fld_CP_HUE_CNTL_def, 1286fld_LUMA_FILTER_def, 1287fld_H_SCALE_RATIO_def, 1288fld_H_SHARPNESS_def, 1289fld_V_SCALE_RATIO_def, 1290fld_V_DEINTERLACE_ON_def, 1291fld_V_BYPSS_def, 1292fld_V_DITHER_ON_def, 1293fld_EVENF_OFFSET_def, 1294fld_ODDF_OFFSET_def, 1295fld_INTERLACE_DETECTED_def, 1296fld_VS_LINE_COUNT_def, 1297fld_VS_DETECTED_LINES_def, 1298fld_VS_ITU656_VB_def, 1299fld_VBI_CC_DATA_def, 1300fld_VBI_CC_WT_def, 1301fld_VBI_CC_WT_ACK_def, 1302fld_VBI_CC_HOLD_def, 1303fld_VBI_DECODE_EN_def, 1304fld_VBI_CC_DTO_P_def, 1305fld_VBI_20BIT_DTO_P_def, 1306fld_VBI_CC_LEVEL_def, 1307fld_VBI_20BIT_LEVEL_def, 1308fld_VBI_CLK_RUNIN_GAIN_def, 1309fld_H_VBI_WIND_START_def, 1310fld_H_VBI_WIND_END_def, 1311fld_V_VBI_WIND_START_def, 1312fld_V_VBI_WIND_END_def, 1313fld_VBI_20BIT_DATA0_def, 1314fld_VBI_20BIT_DATA1_def, 1315fld_VBI_20BIT_WT_def, 1316fld_VBI_20BIT_WT_ACK_def, 1317fld_VBI_20BIT_HOLD_def, 1318fld_VBI_CAPTURE_ENABLE_def, 1319fld_VBI_EDS_DATA_def, 1320fld_VBI_EDS_WT_def, 1321fld_VBI_EDS_WT_ACK_def, 1322fld_VBI_EDS_HOLD_def, 1323fld_VBI_SCALING_RATIO_def, 1324fld_VBI_ALIGNER_ENABLE_def, 1325fld_H_ACTIVE_START_def, 1326fld_H_ACTIVE_END_def, 1327fld_V_ACTIVE_START_def, 1328fld_V_ACTIVE_END_def, 1329fld_CH_HEIGHT_def, 1330fld_CH_KILL_LEVEL_def, 1331fld_CH_AGC_ERROR_LIM_def, 1332fld_CH_AGC_FILTER_EN_def, 1333fld_CH_AGC_LOOP_SPEED_def, 1334fld_HUE_ADJ_def, 1335fld_STANDARD_SEL_def, 1336fld_STANDARD_YC_def, 1337fld_ADC_PDWN_def, 1338fld_INPUT_SELECT_def, 1339fld_ADC_PREFLO_def, 1340fld_H_SYNC_PULSE_WIDTH_def, 1341fld_HS_GENLOCKED_def, 1342fld_HS_SYNC_IN_WIN_def, 1343fld_VIN_ASYNC_RST_def, 1344fld_DVS_ASYNC_RST_def, 1345fld_VIP_VENDOR_ID_def, 1346fld_VIP_DEVICE_ID_def, 1347fld_VIP_REVISION_ID_def, 1348fld_BLACK_INT_START_def, 1349fld_BLACK_INT_LENGTH_def, 1350fld_UV_INT_START_def, 1351fld_U_INT_LENGTH_def, 1352fld_V_INT_LENGTH_def, 1353fld_CRDR_ACTIVE_GAIN_def, 1354fld_CBDB_ACTIVE_GAIN_def, 1355fld_DVS_DIRECTION_def, 1356fld_DVS_VBI_UINT8_SWAP_def, 1357fld_DVS_CLK_SELECT_def, 1358fld_CONTINUOUS_STREAM_def, 1359fld_DVSOUT_CLK_DRV_def, 1360fld_DVSOUT_DATA_DRV_def, 1361fld_COMB_CNTL0_def, 1362fld_COMB_CNTL1_def, 1363fld_COMB_CNTL2_def, 1364fld_COMB_LENGTH_def, 1365fld_SYNCTIP_REF0_def, 1366fld_SYNCTIP_REF1_def, 1367fld_CLAMP_REF_def, 1368fld_AGC_PEAKWHITE_def, 1369fld_VBI_PEAKWHITE_def, 1370fld_WPA_THRESHOLD_def, 1371fld_WPA_TRIGGER_LO_def, 1372fld_WPA_TRIGGER_HIGH_def, 1373fld_LOCKOUT_START_def, 1374fld_LOCKOUT_END_def, 1375fld_CH_DTO_INC_def, 1376fld_PLL_SGAIN_def, 1377fld_PLL_FGAIN_def, 1378fld_CR_BURST_GAIN_def, 1379fld_CB_BURST_GAIN_def, 1380fld_VERT_LOCKOUT_START_def, 1381fld_VERT_LOCKOUT_END_def, 1382fld_H_IN_WIND_START_def, 1383fld_V_IN_WIND_START_def, 1384fld_H_OUT_WIND_WIDTH_def, 1385fld_V_OUT_WIND_WIDTH_def, 1386fld_HS_LINE_TOTAL_def, 1387fld_MIN_PULSE_WIDTH_def, 1388fld_MAX_PULSE_WIDTH_def, 1389fld_WIN_CLOSE_LIMIT_def, 1390fld_WIN_OPEN_LIMIT_def, 1391fld_VSYNC_INT_TRIGGER_def, 1392fld_VSYNC_INT_HOLD_def, 1393fld_VIN_M0_def, 1394fld_VIN_N0_def, 1395fld_MNFLIP_EN_def, 1396fld_VIN_P_def, 1397fld_REG_CLK_SEL_def, 1398fld_VIN_M1_def, 1399fld_VIN_N1_def, 1400fld_VIN_DRIVER_SEL_def, 1401fld_VIN_MNFLIP_REQ_def, 1402fld_VIN_MNFLIP_DONE_def, 1403fld_TV_LOCK_TO_VIN_def, 1404fld_TV_P_FOR_WINCLK_def, 1405fld_VINRST_def, 1406fld_VIN_CLK_SEL_def, 1407fld_VS_FIELD_BLANK_START_def, 1408fld_VS_FIELD_BLANK_END_def, 1409fld_VS_FIELD_IDLOCATION_def, 1410fld_VS_FRAME_TOTAL_def, 1411fld_SYNC_TIP_START_def, 1412fld_SYNC_TIP_LENGTH_def, 1413fld_GAIN_FORCE_DATA_def, 1414fld_GAIN_FORCE_EN_def, 1415fld_I_CLAMP_SEL_def, 1416fld_I_AGC_SEL_def, 1417fld_EXT_CLAMP_CAP_def, 1418fld_EXT_AGC_CAP_def, 1419fld_DECI_DITHER_EN_def, 1420fld_ADC_PREFHI_def, 1421fld_ADC_CH_GAIN_SEL_def, 1422fld_HS_PLL_SGAIN_def, 1423fld_NREn_def, 1424fld_NRGainCntl_def, 1425fld_NRBWTresh_def, 1426fld_NRGCTresh_def, 1427fld_NRCoefDespeclMode_def, 1428fld_GPIO_5_OE_def, 1429fld_GPIO_6_OE_def, 1430fld_GPIO_5_OUT_def, 1431fld_GPIO_6_OUT_def, 1432}; 1433 1434/**************************************************************************** 1435 * WriteRT_fld (uint32_t dwReg, uint32_t dwData) * 1436 * Function: Writes a register field within Rage Theatre * 1437 * Inputs: uint32_t dwReg = register field to be written * 1438 * uint32_t dwData = data that will be written to the reg field * 1439 * Outputs: NONE * 1440 ****************************************************************************/ 1441static void WriteRT_fld1 (TheatrePtr t, uint32_t dwReg, uint32_t dwData) 1442{ 1443 uint32_t dwResult=0; 1444 uint32_t dwValue=0; 1445 1446 if (RT_regr (RT_RegMap[dwReg].dwRegAddrLSBs, &dwResult) == TRUE) 1447 { 1448 dwValue = (dwResult & RT_RegMap[dwReg].dwMaskLSBs) | 1449 (dwData << RT_RegMap[dwReg].dwFldOffsetLSBs); 1450 1451 if (RT_regw (RT_RegMap[dwReg].dwRegAddrLSBs, dwValue) == TRUE) 1452 { 1453 /* update the memory mapped registers */ 1454 RT_RegMap[dwReg].dwCurrValue = dwData; 1455 } 1456 } 1457 1458 return; 1459 1460} /* WriteRT_fld ()... */ 1461 1462#if 0 1463/**************************************************************************** 1464 * ReadRT_fld (uint32_t dwReg) * 1465 * Function: Reads a register field within Rage Theatre * 1466 * Inputs: uint32_t dwReg = register field to be read * 1467 * Outputs: uint32_t - value read from register field * 1468 ****************************************************************************/ 1469static uint32_t ReadRT_fld1 (TheatrePtr t,uint32_t dwReg) 1470{ 1471 uint32_t dwResult=0; 1472 1473 if (RT_regr (RT_RegMap[dwReg].dwRegAddrLSBs, &dwResult) == TRUE) 1474 { 1475 RT_RegMap[dwReg].dwCurrValue = ((dwResult & ~RT_RegMap[dwReg].dwMaskLSBs) >> 1476 RT_RegMap[dwReg].dwFldOffsetLSBs); 1477 return (RT_RegMap[dwReg].dwCurrValue); 1478 } 1479 else 1480 { 1481 return (0xFFFFFFFF); 1482 } 1483 1484} /* ReadRT_fld ()... */ 1485 1486#define ReadRT_fld(a) ReadRT_fld1(t,(a)) 1487#endif 1488 1489#define WriteRT_fld(a,b) WriteRT_fld1(t, (a), (b)) 1490 1491 1492/**************************************************************************** 1493 * RT_SetTint (int hue) * 1494 * Function: sets the tint (hue) for the Rage Theatre video in * 1495 * Inputs: int hue - the hue value to be set. * 1496 * Outputs: NONE * 1497 ****************************************************************************/ 1498_X_EXPORT void RT_SetTint (TheatrePtr t, int hue) 1499{ 1500 /* Validate Hue level */ 1501 if (hue < -1000) 1502 { 1503 hue = -1000; 1504 } 1505 else if (hue > 1000) 1506 { 1507 hue = 1000; 1508 } 1509 1510 t->iHue=hue; 1511 1512 dsp_set_tint(t, (uint8_t)((hue*255)/2000 + 128)); 1513 1514} /* RT_SetTint ()... */ 1515 1516 1517/**************************************************************************** 1518 * RT_SetSaturation (int Saturation) * 1519 * Function: sets the saturation level for the Rage Theatre video in * 1520 * Inputs: int Saturation - the saturation value to be set. * 1521 * Outputs: NONE * 1522 ****************************************************************************/ 1523_X_EXPORT void RT_SetSaturation (TheatrePtr t, int Saturation) 1524{ 1525 /* VALIDATE SATURATION LEVEL */ 1526 if (Saturation < -1000L) 1527 { 1528 Saturation = -1000; 1529 } 1530 else if (Saturation > 1000L) 1531 { 1532 Saturation = 1000; 1533 } 1534 1535 t->iSaturation = Saturation; 1536 1537 /* RT200 has saturation in range 0 to 255 with nominal value 128 */ 1538 dsp_set_saturation(t, (uint8_t)((Saturation*255)/2000 + 128)); 1539 1540 return; 1541} /* RT_SetSaturation ()...*/ 1542 1543/**************************************************************************** 1544 * RT_SetBrightness (int Brightness) * 1545 * Function: sets the brightness level for the Rage Theatre video in * 1546 * Inputs: int Brightness - the brightness value to be set. * 1547 * Outputs: NONE * 1548 ****************************************************************************/ 1549_X_EXPORT void RT_SetBrightness (TheatrePtr t, int Brightness) 1550{ 1551 /* VALIDATE BRIGHTNESS LEVEL */ 1552 if (Brightness < -1000) 1553 { 1554 Brightness = -1000; 1555 } 1556 else if (Brightness > 1000) 1557 { 1558 Brightness = 1000; 1559 } 1560 1561 /* Save value */ 1562 t->iBrightness = Brightness; 1563 t->dbBrightnessRatio = (double) (Brightness+1000.0) / 10.0; 1564 1565 /* RT200 is having brightness level from 0 to 255 with 128 nominal value */ 1566 dsp_set_brightness(t, (uint8_t)((Brightness*255)/2000 + 128)); 1567 1568 return; 1569} /* RT_SetBrightness ()... */ 1570 1571 1572/**************************************************************************** 1573 * RT_SetSharpness (uint16_t wSharpness) * 1574 * Function: sets the sharpness level for the Rage Theatre video in * 1575 * Inputs: uint16_t wSharpness - the sharpness value to be set. * 1576 * Outputs: NONE * 1577 ****************************************************************************/ 1578_X_EXPORT void RT_SetSharpness (TheatrePtr t, uint16_t wSharpness) 1579{ 1580 switch (wSharpness) 1581 { 1582 case DEC_SMOOTH : 1583 WriteRT_fld (fld_H_SHARPNESS, RT_NORM_SHARPNESS); 1584 t->wSharpness = RT_NORM_SHARPNESS; 1585 break; 1586 case DEC_SHARP : 1587 WriteRT_fld (fld_H_SHARPNESS, RT_HIGH_SHARPNESS); 1588 t->wSharpness = RT_HIGH_SHARPNESS; 1589 break; 1590 default: 1591 break; 1592 } 1593 return; 1594 1595} /* RT_SetSharpness ()... */ 1596 1597 1598/**************************************************************************** 1599 * RT_SetContrast (int Contrast) * 1600 * Function: sets the contrast level for the Rage Theatre video in * 1601 * Inputs: int Contrast - the contrast value to be set. * 1602 * Outputs: NONE * 1603 ****************************************************************************/ 1604_X_EXPORT void RT_SetContrast (TheatrePtr t, int Contrast) 1605{ 1606 /* VALIDATE CONTRAST LEVEL */ 1607 if (Contrast < -1000) 1608 { 1609 Contrast = -1000; 1610 } 1611 else if (Contrast > 1000) 1612 { 1613 Contrast = 1000; 1614 } 1615 1616 /* Save contrast value */ 1617 t->iContrast = Contrast; 1618 t->dbContrast = (double) (Contrast+1000.0) / 1000.0; 1619 1620 /* RT200 has contrast values between 0 to 255 with nominal value at 128 */ 1621 dsp_set_contrast(t, (uint8_t)((Contrast*255)/2000 + 128)); 1622 return; 1623 1624} /* RT_SetContrast ()... */ 1625 1626/**************************************************************************** 1627 * RT_SetInterlace (uint8_t bInterlace) * 1628 * Function: to set the interlacing pattern for the Rage Theatre video in * 1629 * Inputs: uint8_t bInterlace * 1630 * Outputs: NONE * 1631 ****************************************************************************/ 1632_X_EXPORT void RT_SetInterlace (TheatrePtr t, uint8_t bInterlace) 1633{ 1634 switch(bInterlace) 1635 { 1636 case (TRUE): /*DEC_INTERLACE */ 1637 WriteRT_fld (fld_V_DEINTERLACE_ON, 0x1); 1638 t->wInterlaced = (uint16_t) RT_DECINTERLACED; 1639 break; 1640 case (FALSE): /*DEC_NONINTERLACE */ 1641 WriteRT_fld (fld_V_DEINTERLACE_ON, RT_DECNONINTERLACED); 1642 t->wInterlaced = (uint16_t) RT_DECNONINTERLACED; 1643 break; 1644 default: 1645 break; 1646 } 1647 1648 return; 1649 1650} /* RT_SetInterlace ()... */ 1651 1652 1653/**************************************************************************** 1654 * RT_SetStandard (uint16_t wStandard) * 1655 * Function: to set the input standard for the Rage Theatre video in * 1656 * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * 1657 * Outputs: NONE * 1658 ****************************************************************************/ 1659_X_EXPORT void RT_SetStandard (TheatrePtr t, uint16_t wStandard) 1660{ 1661 xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"Rage Theatre setting standard 0x%04x\n", 1662 wStandard); 1663 1664 t->wStandard = wStandard; 1665 1666 /* Program the new standards: */ 1667 switch (wStandard & 0x00FF) 1668 { 1669 case (DEC_NTSC): /*NTSC GROUP - 480 lines */ 1670 switch (wStandard & 0xFF00) 1671 { 1672 case (extNONE): 1673 case (extNTSC): 1674 dsp_set_video_standard(t, 2); 1675 break; 1676 case (extNTSC_J): 1677 dsp_set_video_standard(t, RT200_NTSC_J); 1678 break; 1679 case (extNTSC_443): 1680 dsp_set_video_standard(t, RT200_NTSC_433); 1681 break; 1682 default: 1683 dsp_video_standard_detection(t); 1684 break; 1685 } 1686 break; 1687 case (DEC_PAL): /*PAL GROUP - 625 lines */ 1688 switch (wStandard & 0xFF00) 1689 { 1690 case (extNONE): 1691 case (extPAL): 1692 case (extPAL_B): 1693 case (extPAL_BGHI): 1694 dsp_set_video_standard(t, RT200_PAL_B); 1695 break; 1696 case (extPAL_D): 1697 dsp_set_video_standard(t, RT200_PAL_D); 1698 break; 1699 case (extPAL_G): 1700 dsp_set_video_standard(t, RT200_PAL_G); 1701 break; 1702 case (extPAL_H): 1703 dsp_set_video_standard(t, RT200_PAL_H); 1704 break; 1705 case (extPAL_I): 1706 dsp_set_video_standard(t, RT200_PAL_D); 1707 break; 1708 case (extPAL_N): 1709 dsp_set_video_standard(t, RT200_PAL_N); 1710 break; 1711 case (extPAL_NCOMB): 1712 dsp_set_video_standard(t, RT200_PAL_Ncomb); 1713 break; 1714 case (extPAL_M): 1715 dsp_set_video_standard(t, RT200_PAL_M); 1716 break; 1717 case (extPAL_60): 1718 dsp_set_video_standard(t, RT200_PAL_60); 1719 break; 1720 default: 1721 dsp_video_standard_detection(t); 1722 break; 1723 } 1724 break; 1725 case (DEC_SECAM): /*SECAM GROUP*/ 1726 switch (wStandard & 0xFF00) 1727 { 1728 case (extNONE): 1729 case (extSECAM): 1730 dsp_set_video_standard(t, RT200_SECAM); 1731 break; 1732 case (extSECAM_B): 1733 dsp_set_video_standard(t, RT200_SECAM_B); 1734 break; 1735 case (extSECAM_D): 1736 dsp_set_video_standard(t, RT200_SECAM_D); 1737 break; 1738 case (extSECAM_G): 1739 dsp_set_video_standard(t, RT200_SECAM_G); 1740 break; 1741 case (extSECAM_H): 1742 dsp_set_video_standard(t, RT200_SECAM_H); 1743 break; 1744 case (extSECAM_K): 1745 dsp_set_video_standard(t, RT200_SECAM_K); 1746 break; 1747 case (extSECAM_K1): 1748 dsp_set_video_standard(t, RT200_SECAM_K1); 1749 break; 1750 case (extSECAM_L): 1751 dsp_set_video_standard(t, RT200_SECAM_L); 1752 break; 1753 case (extSECAM_L1): 1754 dsp_set_video_standard(t, RT200_SECAM_L1); 1755 break; 1756 default: 1757 dsp_video_standard_detection(t); 1758 break; 1759 } 1760 break; 1761 default: 1762 dsp_video_standard_detection(t); 1763 } 1764 1765} /* RT_SetStandard ()... */ 1766 1767 1768/**************************************************************************** 1769 * RT_SetOutputVideoSize (uint16_t wHorzSize, uint16_t wVertSize, * 1770 * uint8_t fCC_On, uint8_t fVBICap_On) * 1771 * Function: sets the output video size for the Rage Theatre video in * 1772 * Inputs: uint16_t wHorzSize - width of output in pixels * 1773 * uint16_t wVertSize - height of output in pixels (lines) * 1774 * uint8_t fCC_On - enable CC output * 1775 * uint8_t fVBI_Cap_On - enable VBI capture * 1776 * Outputs: NONE * 1777 ****************************************************************************/ 1778_X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, uint16_t wHorzSize, uint16_t wVertSize, uint8_t fCC_On, uint8_t fVBICap_On) 1779{ 1780 /* VBI is ignored now */ 1781 1782 /* 1783 * If I pass the (wHorzSize, 0, 0) (wVertSize, 0, 0) the image does not synchronize 1784 */ 1785 dsp_set_video_scaler_horizontal(t, 0, 0, 0); 1786 dsp_set_video_scaler_vertical(t, 0, 0, 0); 1787 1788} /* RT_SetOutputVideoSize ()...*/ 1789 1790 1791/**************************************************************************** 1792 * RT_SetConnector (uint16_t wStandard, int tunerFlag) * 1793 * Function: 1794 * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * 1795 * int tunerFlag 1796 * Outputs: NONE * 1797 ****************************************************************************/ 1798_X_EXPORT void RT_SetConnector (TheatrePtr t, uint16_t wConnector, int tunerFlag) 1799{ 1800 uint32_t data; 1801 1802 t->wConnector = wConnector; 1803 1804 theatre_read(t, VIP_GPIO_CNTL, &data); 1805 xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"VIP_GPIO_CNTL: %x\n", 1806 (unsigned)data); 1807 1808 theatre_read(t, VIP_GPIO_INOUT, &data); 1809 xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"VIP_GPIO_INOUT: %x\n", 1810 (unsigned)data); 1811 1812 switch (wConnector) 1813 { 1814 case (DEC_TUNER): /* Tuner*/ 1815 /* RT200 does not have any input connector 0 */ 1816 dsp_set_video_input_connector(t, t->wTunerConnector + 1); 1817 1818 /* this is to set the analog mux used for sond */ 1819 theatre_read(t, VIP_GPIO_CNTL, &data); 1820 data &= ~0x10; 1821 theatre_write(t, VIP_GPIO_CNTL, data); 1822 1823 theatre_read(t, VIP_GPIO_INOUT, &data); 1824 data &= ~0x10; 1825 theatre_write(t, VIP_GPIO_INOUT, data); 1826 1827 break; 1828 case (DEC_COMPOSITE): /* Comp*/ 1829 dsp_set_video_input_connector(t, t->wComp0Connector); 1830 1831 /* this is to set the analog mux used for sond */ 1832 theatre_read(t, VIP_GPIO_CNTL, &data); 1833 data |= 0x10; 1834 theatre_write(t, VIP_GPIO_CNTL, data); 1835 1836 theatre_read(t, VIP_GPIO_INOUT, &data); 1837 data |= 0x10; 1838 theatre_write(t, VIP_GPIO_INOUT, data); 1839 1840 break; 1841 case (DEC_SVIDEO): /* Svideo*/ 1842 dsp_set_video_input_connector(t, t->wSVideo0Connector); 1843 1844 /* this is to set the analog mux used for sond */ 1845 theatre_read(t, VIP_GPIO_CNTL, &data); 1846 data |= 0x10; 1847 theatre_write(t, VIP_GPIO_CNTL, data); 1848 1849 theatre_read(t, VIP_GPIO_INOUT, &data); 1850 data |= 0x10; 1851 theatre_write(t, VIP_GPIO_INOUT, data); 1852 1853 break; 1854 default: 1855 dsp_set_video_input_connector(t, t->wComp0Connector); 1856 } 1857 1858 theatre_read(t, VIP_GPIO_CNTL, &data); 1859 xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"VIP_GPIO_CNTL: %x\n", 1860 (unsigned)data); 1861 1862 theatre_read(t, VIP_GPIO_INOUT, &data); 1863 xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"VIP_GPIO_INOUT: %x\n", 1864 (unsigned)data); 1865 1866 1867 dsp_configure_i2s_port(t, 0, 0, 0); 1868 dsp_configure_spdif_port(t, 0); 1869 1870 /*dsp_audio_detection(t, 0);*/ 1871 dsp_audio_mute(t, 1, 1); 1872 dsp_set_audio_volume(t, 128, 128, 0); 1873 1874} /* RT_SetConnector ()...*/ 1875 1876 1877_X_EXPORT void InitTheatre(TheatrePtr t) 1878{ 1879 uint32_t data; 1880 uint32_t M, N, P; 1881 1882 /* this will give 108Mhz at 27Mhz reference */ 1883 M = 28; 1884 N = 224; 1885 P = 1; 1886 1887 ShutdownTheatre(t); 1888 usleep(100000); 1889 t->mode=MODE_INITIALIZATION_IN_PROGRESS; 1890 1891 1892 data = M | (N << 11) | (P <<24); 1893 RT_regw(VIP_DSP_PLL_CNTL, data); 1894 1895 RT_regr(VIP_PLL_CNTL0, &data); 1896 data |= 0x2000; 1897 RT_regw(VIP_PLL_CNTL0, data); 1898 1899 /* RT_regw(VIP_I2C_SLVCNTL, 0x249); */ 1900 RT_regr(VIP_PLL_CNTL1, &data); 1901 data |= 0x00030003; 1902 RT_regw(VIP_PLL_CNTL1, data); 1903 1904 RT_regr(VIP_PLL_CNTL0, &data); 1905 data &= 0xfffffffc; 1906 RT_regw(VIP_PLL_CNTL0, data); 1907 usleep(15000); 1908 1909 RT_regr(VIP_CLOCK_SEL_CNTL, &data); 1910 data |= 0x1b; 1911 RT_regw(VIP_CLOCK_SEL_CNTL, data); 1912 1913 RT_regr(VIP_MASTER_CNTL, &data); 1914 data &= 0xffffff07; 1915 RT_regw(VIP_MASTER_CNTL, data); 1916 data &= 0xffffff03; 1917 RT_regw(VIP_MASTER_CNTL, data); 1918 usleep(1000); 1919 1920 if (t->microc_path == NULL) 1921 { 1922 t->microc_path = DEFAULT_MICROC_PATH; 1923 xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "Microcode: Use default microcode path: %s\n", DEFAULT_MICROC_PATH); 1924 } 1925 else 1926 xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "Microcode: Use microcode path: %s\n", t->microc_path); 1927 1928 1929 if (t->microc_type == NULL) 1930 { 1931 t->microc_type = DEFAULT_MICROC_TYPE; 1932 xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "Microcode: Use default microcode type: %s\n", DEFAULT_MICROC_TYPE); 1933 } 1934 else 1935 xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "Microcode: Use microcode type: %s\n", t->microc_type); 1936 1937 if (DownloadMicrocode(t) < 0) 1938 { 1939 ShutdownTheatre(t); 1940 return; 1941 } 1942 1943 dsp_set_lowpowerstate(t, 1); 1944 dsp_set_videostreamformat(t, 1); 1945 1946 t->mode=MODE_INITIALIZED_FOR_TV_IN; 1947} 1948 1949static int DownloadMicrocode(TheatrePtr t) 1950{ 1951 struct rt200_microc_data microc_data; 1952 microc_data.microc_seg_list = NULL; 1953 1954 if (microc_load(t->microc_path, t->microc_type, µc_data, t->VIP->scrnIndex) < 0) 1955 { 1956 xf86DrvMsg(t->VIP->scrnIndex, X_ERROR, "Microcode: cannot load microcode\n"); 1957 goto err_exit; 1958 } 1959 else 1960 { 1961 xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "Microcode: device_id: %x\n", microc_data.microc_head.device_id); 1962 xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "Microcode: vendor_id: %x\n", microc_data.microc_head.vendor_id); 1963 xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "Microcode: rev_id: %x\n", microc_data.microc_head.revision_id); 1964 xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "Microcode: num_seg: %x\n", microc_data.microc_head.num_seg); 1965 } 1966 1967 if (dsp_init(t, µc_data) < 0) 1968 { 1969 xf86DrvMsg(t->VIP->scrnIndex, X_ERROR, "Microcode: dsp_init failed\n"); 1970 goto err_exit; 1971 } 1972 else 1973 { 1974 xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "Microcode: dsp_init OK\n"); 1975 } 1976 1977 if (dsp_load(t, µc_data) < 0) 1978 { 1979 xf86DrvMsg(t->VIP->scrnIndex, X_ERROR, "Microcode: dsp_download failed\n"); 1980 goto err_exit; 1981 } 1982 else 1983 { 1984 xf86DrvMsg(t->VIP->scrnIndex, X_INFO, "Microcode: dsp_download OK\n"); 1985 } 1986 1987 microc_clean(µc_data, t->VIP->scrnIndex); 1988 return 0; 1989 1990err_exit: 1991 1992 microc_clean(µc_data, t->VIP->scrnIndex); 1993 return -1; 1994 1995} 1996 1997 1998_X_EXPORT void ShutdownTheatre(TheatrePtr t) 1999{ 2000#if 0 2001 WriteRT_fld (fld_VIN_ASYNC_RST, RT_ASYNC_DISABLE); 2002 WriteRT_fld (fld_VINRST , RT_VINRST_RESET); 2003 WriteRT_fld (fld_ADC_PDWN , RT_ADC_DISABLE); 2004 WriteRT_fld (fld_DVS_DIRECTION, RT_DVSDIR_IN); 2005#endif 2006 t->mode=MODE_UNINITIALIZED; 2007} 2008 2009_X_EXPORT void DumpRageTheatreRegs(TheatrePtr t) 2010{ 2011 int i; 2012 uint32_t data; 2013 2014 for(i=0;i<0x900;i+=4) 2015 { 2016 RT_regr(i, &data); 2017 xf86DrvMsg(t->VIP->scrnIndex, X_INFO, 2018 "register 0x%04x is equal to 0x%08x\n", i, (unsigned)data); 2019 } 2020 2021} 2022 2023void DumpRageTheatreRegsByName(TheatrePtr t) 2024{ 2025 int i; 2026 uint32_t data; 2027 struct { char *name; long addr; } rt_reg_list[]={ 2028 { "ADC_CNTL ", 0x0400 }, 2029 { "ADC_DEBUG ", 0x0404 }, 2030 { "AUD_CLK_DIVIDERS ", 0x00e8 }, 2031 { "AUD_DTO_INCREMENTS ", 0x00ec }, 2032 { "AUD_PLL_CNTL ", 0x00e0 }, 2033 { "AUD_PLL_FINE_CNTL ", 0x00e4 }, 2034 { "CLKOUT_CNTL ", 0x004c }, 2035 { "CLKOUT_GPIO_CNTL ", 0x0038 }, 2036 { "CLOCK_SEL_CNTL ", 0x00d0 }, 2037 { "COMB_CNTL0 ", 0x0440 }, 2038 { "COMB_CNTL1 ", 0x0444 }, 2039 { "COMB_CNTL2 ", 0x0448 }, 2040 { "COMB_LINE_LENGTH ", 0x044c }, 2041 { "CP_ACTIVE_GAIN ", 0x0594 }, 2042 { "CP_AGC_CNTL ", 0x0590 }, 2043 { "CP_BURST_GAIN ", 0x058c }, 2044 { "CP_DEBUG_FORCE ", 0x05b8 }, 2045 { "CP_HUE_CNTL ", 0x0588 }, 2046 { "CP_PLL_CNTL0 ", 0x0580 }, 2047 { "CP_PLL_CNTL1 ", 0x0584 }, 2048 { "CP_PLL_STATUS0 ", 0x0598 }, 2049 { "CP_PLL_STATUS1 ", 0x059c }, 2050 { "CP_PLL_STATUS2 ", 0x05a0 }, 2051 { "CP_PLL_STATUS3 ", 0x05a4 }, 2052 { "CP_PLL_STATUS4 ", 0x05a8 }, 2053 { "CP_PLL_STATUS5 ", 0x05ac }, 2054 { "CP_PLL_STATUS6 ", 0x05b0 }, 2055 { "CP_PLL_STATUS7 ", 0x05b4 }, 2056 { "CP_VERT_LOCKOUT ", 0x05bc }, 2057 { "CRC_CNTL ", 0x02c0 }, 2058 { "CRT_DTO_INCREMENTS ", 0x0394 }, 2059 { "CRT_PLL_CNTL ", 0x00c4 }, 2060 { "CRT_PLL_FINE_CNTL ", 0x00bc }, 2061 { "DECODER_DEBUG_CNTL ", 0x05d4 }, 2062 { "DELAY_ONE_MAP_A ", 0x0114 }, 2063 { "DELAY_ONE_MAP_B ", 0x0118 }, 2064 { "DELAY_ZERO_MAP_A ", 0x011c }, 2065 { "DELAY_ZERO_MAP_B ", 0x0120 }, 2066 { "DFCOUNT ", 0x00a4 }, 2067 { "DFRESTART ", 0x00a8 }, 2068 { "DHRESTART ", 0x00ac }, 2069 { "DVRESTART ", 0x00b0 }, 2070 { "DVS_PORT_CTRL ", 0x0610 }, 2071 { "DVS_PORT_READBACK ", 0x0614 }, 2072 { "FIFOA_CONFIG ", 0x0800 }, 2073 { "FIFOB_CONFIG ", 0x0804 }, 2074 { "FIFOC_CONFIG ", 0x0808 }, 2075 { "FRAME_LOCK_CNTL ", 0x0100 }, 2076 { "GAIN_LIMIT_SETTINGS ", 0x01e4 }, 2077 { "GPIO_CNTL ", 0x0034 }, 2078 { "GPIO_INOUT ", 0x0030 }, 2079 { "HCOUNT ", 0x0090 }, 2080 { "HDISP ", 0x0084 }, 2081 { "HOST_RD_WT_CNTL ", 0x0188 }, 2082 { "HOST_READ_DATA ", 0x0180 }, 2083 { "HOST_WRITE_DATA ", 0x0184 }, 2084 { "HSIZE ", 0x0088 }, 2085 { "HSTART ", 0x008c }, 2086 { "HS_DTOINC ", 0x0484 }, 2087 { "HS_GENLOCKDELAY ", 0x0490 }, 2088 { "HS_MINMAXWIDTH ", 0x048c }, 2089 { "HS_PLINE ", 0x0480 }, 2090 { "HS_PLLGAIN ", 0x0488 }, 2091 { "HS_PLL_ERROR ", 0x04a0 }, 2092 { "HS_PLL_FS_PATH ", 0x04a4 }, 2093 { "HS_PULSE_WIDTH ", 0x049c }, 2094 { "HS_WINDOW_LIMIT ", 0x0494 }, 2095 { "HS_WINDOW_OC_SPEED ", 0x0498 }, 2096 { "HTOTAL ", 0x0080 }, 2097 { "HW_DEBUG ", 0x0010 }, 2098 { "H_ACTIVE_WINDOW ", 0x05c0 }, 2099 { "H_SCALER_CONTROL ", 0x0600 }, 2100 { "H_VBI_WINDOW ", 0x05c8 }, 2101 { "I2C_CNTL ", 0x0054 }, 2102 { "I2C_CNTL_0 ", 0x0020 }, 2103 { "I2C_CNTL_1 ", 0x0024 }, 2104 { "I2C_DATA ", 0x0028 }, 2105 { "I2S_RECEIVE_CNTL ", 0x081c }, 2106 { "I2S_TRANSMIT_CNTL ", 0x0818 }, 2107 { "IIS_TX_CNT_REG ", 0x0824 }, 2108 { "INT_CNTL ", 0x002c }, 2109 { "L54_DTO_INCREMENTS ", 0x00f8 }, 2110 { "L54_PLL_CNTL ", 0x00f0 }, 2111 { "L54_PLL_FINE_CNTL ", 0x00f4 }, 2112 { "LINEAR_GAIN_SETTINGS ", 0x01e8 }, 2113 { "LP_AGC_CLAMP_CNTL0 ", 0x0500 }, 2114 { "LP_AGC_CLAMP_CNTL1 ", 0x0504 }, 2115 { "LP_BLACK_LEVEL ", 0x051c }, 2116 { "LP_BRIGHTNESS ", 0x0508 }, 2117 { "LP_CONTRAST ", 0x050c }, 2118 { "LP_SLICE_LEVEL ", 0x0520 }, 2119 { "LP_SLICE_LIMIT ", 0x0510 }, 2120 { "LP_SYNCTIP_LEVEL ", 0x0524 }, 2121 { "LP_VERT_LOCKOUT ", 0x0528 }, 2122 { "LP_WPA_CNTL0 ", 0x0514 }, 2123 { "LP_WPA_CNTL1 ", 0x0518 }, 2124 { "MASTER_CNTL ", 0x0040 }, 2125 { "MODULATOR_CNTL1 ", 0x0200 }, 2126 { "MODULATOR_CNTL2 ", 0x0204 }, 2127 { "MV_LEVEL_CNTL1 ", 0x0210 }, 2128 { "MV_LEVEL_CNTL2 ", 0x0214 }, 2129 { "MV_MODE_CNTL ", 0x0208 }, 2130 { "MV_STATUS ", 0x0330 }, 2131 { "MV_STRIPE_CNTL ", 0x020c }, 2132 { "NOISE_CNTL0 ", 0x0450 }, 2133 { "PLL_CNTL0 ", 0x00c8 }, 2134 { "PLL_CNTL1 ", 0x00fc }, 2135 { "PLL_TEST_CNTL ", 0x00cc }, 2136 { "PRE_DAC_MUX_CNTL ", 0x0240 }, 2137 { "RGB_CNTL ", 0x0048 }, 2138 { "RIPINTF_PORT_CNTL ", 0x003c }, 2139 { "SCALER_IN_WINDOW ", 0x0618 }, 2140 { "SCALER_OUT_WINDOW ", 0x061c }, 2141 { "SG_BLACK_GATE ", 0x04c0 }, 2142 { "SG_SYNCTIP_GATE ", 0x04c4 }, 2143 { "SG_UVGATE_GATE ", 0x04c8 }, 2144 { "SINGLE_STEP_DATA ", 0x05d8 }, 2145 { "SPDIF_AC3_PREAMBLE ", 0x0814 }, 2146 { "SPDIF_CHANNEL_STAT ", 0x0810 }, 2147 { "SPDIF_PORT_CNTL ", 0x080c }, 2148 { "SPDIF_TX_CNT_REG ", 0x0820 }, 2149 { "STANDARD_SELECT ", 0x0408 }, 2150 { "SW_SCRATCH ", 0x0014 }, 2151 { "SYNC_CNTL ", 0x0050 }, 2152 { "SYNC_LOCK_CNTL ", 0x0104 }, 2153 { "SYNC_SIZE ", 0x00b4 }, 2154 { "THERMO2BIN_STATUS ", 0x040c }, 2155 { "TIMING_CNTL ", 0x01c4 }, 2156 { "TVO_DATA_DELAY_A ", 0x0140 }, 2157 { "TVO_DATA_DELAY_B ", 0x0144 }, 2158 { "TVO_SYNC_PAT_ACCUM ", 0x0108 }, 2159 { "TVO_SYNC_PAT_EXPECT ", 0x0110 }, 2160 { "TVO_SYNC_THRESHOLD ", 0x010c }, 2161 { "TV_DAC_CNTL ", 0x0280 }, 2162 { "TV_DTO_INCREMENTS ", 0x0390 }, 2163 { "TV_PLL_CNTL ", 0x00c0 }, 2164 { "TV_PLL_FINE_CNTL ", 0x00b8 }, 2165 { "UPSAMP_AND_GAIN_CNTL ", 0x01e0 }, 2166 { "UPSAMP_COEFF0_0 ", 0x0340 }, 2167 { "UPSAMP_COEFF0_1 ", 0x0344 }, 2168 { "UPSAMP_COEFF0_2 ", 0x0348 }, 2169 { "UPSAMP_COEFF1_0 ", 0x034c }, 2170 { "UPSAMP_COEFF1_1 ", 0x0350 }, 2171 { "UPSAMP_COEFF1_2 ", 0x0354 }, 2172 { "UPSAMP_COEFF2_0 ", 0x0358 }, 2173 { "UPSAMP_COEFF2_1 ", 0x035c }, 2174 { "UPSAMP_COEFF2_2 ", 0x0360 }, 2175 { "UPSAMP_COEFF3_0 ", 0x0364 }, 2176 { "UPSAMP_COEFF3_1 ", 0x0368 }, 2177 { "UPSAMP_COEFF3_2 ", 0x036c }, 2178 { "UPSAMP_COEFF4_0 ", 0x0370 }, 2179 { "UPSAMP_COEFF4_1 ", 0x0374 }, 2180 { "UPSAMP_COEFF4_2 ", 0x0378 }, 2181 { "UV_ADR ", 0x0300 }, 2182 { "VBI_20BIT_CNTL ", 0x02d0 }, 2183 { "VBI_CC_CNTL ", 0x02c8 }, 2184 { "VBI_CONTROL ", 0x05d0 }, 2185 { "VBI_DTO_CNTL ", 0x02d4 }, 2186 { "VBI_EDS_CNTL ", 0x02cc }, 2187 { "VBI_LEVEL_CNTL ", 0x02d8 }, 2188 { "VBI_SCALER_CONTROL ", 0x060c }, 2189 { "VCOUNT ", 0x009c }, 2190 { "VDISP ", 0x0098 }, 2191 { "VFTOTAL ", 0x00a0 }, 2192 { "VIDEO_PORT_SIG ", 0x02c4 }, 2193 { "VIN_PLL_CNTL ", 0x00d4 }, 2194 { "VIN_PLL_FINE_CNTL ", 0x00d8 }, 2195 { "VIP_COMMAND_STATUS ", 0x0008 }, 2196 { "VIP_REVISION_ID ", 0x000c }, 2197 { "VIP_SUB_VENDOR_DEVICE_ID", 0x0004 }, 2198 { "VIP_VENDOR_DEVICE_ID ", 0x0000 }, 2199 { "VSCALER_CNTL1 ", 0x01c0 }, 2200 { "VSCALER_CNTL2 ", 0x01c8 }, 2201 { "VSYNC_DIFF_CNTL ", 0x03a0 }, 2202 { "VSYNC_DIFF_LIMITS ", 0x03a4 }, 2203 { "VSYNC_DIFF_RD_DATA ", 0x03a8 }, 2204 { "VS_BLANKING_CNTL ", 0x0544 }, 2205 { "VS_COUNTER_CNTL ", 0x054c }, 2206 { "VS_DETECTOR_CNTL ", 0x0540 }, 2207 { "VS_FIELD_ID_CNTL ", 0x0548 }, 2208 { "VS_FRAME_TOTAL ", 0x0550 }, 2209 { "VS_LINE_COUNT ", 0x0554 }, 2210 { "VTOTAL ", 0x0094 }, 2211 { "V_ACTIVE_WINDOW ", 0x05c4 }, 2212 { "V_DEINTERLACE_CONTROL ", 0x0608 }, 2213 { "V_SCALER_CONTROL ", 0x0604 }, 2214 { "V_VBI_WINDOW ", 0x05cc }, 2215 { "Y_FALL_CNTL ", 0x01cc }, 2216 { "Y_RISE_CNTL ", 0x01d0 }, 2217 { "Y_SAW_TOOTH_CNTL ", 0x01d4 }, 2218 {NULL, 0} 2219 }; 2220 2221 for(i=0; rt_reg_list[i].name!=NULL;i++){ 2222 RT_regr(rt_reg_list[i].addr, &data); 2223 xf86DrvMsg(t->VIP->scrnIndex, X_INFO, 2224 "register (0x%04lx) %s is equal to 0x%08x\n", 2225 rt_reg_list[i].addr, rt_reg_list[i].name, (unsigned)data); 2226 } 2227 2228} 2229 2230_X_EXPORT void ResetTheatreRegsForNoTVout(TheatrePtr t) 2231{ 2232 RT_regw(VIP_CLKOUT_CNTL, 0x0); 2233 RT_regw(VIP_HCOUNT, 0x0); 2234 RT_regw(VIP_VCOUNT, 0x0); 2235 RT_regw(VIP_DFCOUNT, 0x0); 2236 #if 0 2237 RT_regw(VIP_CLOCK_SEL_CNTL, 0x2b7); /* versus 0x237 <-> 0x2b7 */ 2238 RT_regw(VIP_VIN_PLL_CNTL, 0x60a6039); 2239 #endif 2240 RT_regw(VIP_FRAME_LOCK_CNTL, 0x0); 2241} 2242 2243 2244_X_EXPORT void ResetTheatreRegsForTVout(TheatrePtr t) 2245{ 2246/* RT_regw(VIP_HW_DEBUG, 0x200); */ 2247/* RT_regw(VIP_INT_CNTL, 0x0); 2248 RT_regw(VIP_GPIO_INOUT, 0x10090000); 2249 RT_regw(VIP_GPIO_INOUT, 0x340b0000); */ 2250/* RT_regw(VIP_MASTER_CNTL, 0x6e8); */ 2251 RT_regw(VIP_CLKOUT_CNTL, 0x29); 2252#if 1 2253 RT_regw(VIP_HCOUNT, 0x1d1); 2254 RT_regw(VIP_VCOUNT, 0x1e3); 2255#else 2256 RT_regw(VIP_HCOUNT, 0x322); 2257 RT_regw(VIP_VCOUNT, 0x151); 2258#endif 2259 RT_regw(VIP_DFCOUNT, 0x01); 2260/* RT_regw(VIP_CLOCK_SEL_CNTL, 0xb7); versus 0x237 <-> 0x2b7 */ 2261 RT_regw(VIP_CLOCK_SEL_CNTL, 0x2b7); /* versus 0x237 <-> 0x2b7 */ 2262 RT_regw(VIP_VIN_PLL_CNTL, 0x60a6039); 2263/* RT_regw(VIP_PLL_CNTL1, 0xacacac74); */ 2264 RT_regw(VIP_FRAME_LOCK_CNTL, 0x0f); 2265/* RT_regw(VIP_ADC_CNTL, 0x02a420a8); 2266 RT_regw(VIP_COMB_CNTL_0, 0x0d438083); 2267 RT_regw(VIP_COMB_CNTL_2, 0x06080102); 2268 RT_regw(VIP_HS_MINMAXWIDTH, 0x462f); 2269 ... 2270 */ 2271/* 2272 RT_regw(VIP_HS_PULSE_WIDTH, 0x359); 2273 RT_regw(VIP_HS_PLL_ERROR, 0xab6); 2274 RT_regw(VIP_HS_PLL_FS_PATH, 0x7fff08f8); 2275 RT_regw(VIP_VS_LINE_COUNT, 0x49b5e005); 2276 */ 2277} 2278 2279