ct_BlitMM.h revision c06b6b69
1c06b6b69Smrg/* $XConsortium: ct_BlitMM.h /main/2 1996/10/25 10:28:31 kaleb $ */ 2c06b6b69Smrg 3c06b6b69Smrg 4c06b6b69Smrg 5c06b6b69Smrg 6c06b6b69Smrg 7c06b6b69Smrg/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/chips/ct_BlitMM.h,v 1.3 1998/08/20 08:55:56 dawes Exp $ */ 8c06b6b69Smrg 9c06b6b69Smrg/* Definitions for the Chips and Technology BitBLT engine communication. */ 10c06b6b69Smrg/* These are done using Memory Mapped IO, of the registers */ 11c06b6b69Smrg/* BitBLT modes for register 93D0. */ 12c06b6b69Smrg 13c06b6b69Smrg#define ctPATCOPY 0xF0 14c06b6b69Smrg#define ctTOP2BOTTOM 0x100 15c06b6b69Smrg#define ctBOTTOM2TOP 0x000 16c06b6b69Smrg#define ctLEFT2RIGHT 0x200 17c06b6b69Smrg#define ctRIGHT2LEFT 0x000 18c06b6b69Smrg#define ctSRCFG 0x400 19c06b6b69Smrg#define ctSRCMONO 0x800 20c06b6b69Smrg#define ctPATMONO 0x1000 21c06b6b69Smrg#define ctBGTRANSPARENT 0x2000 22c06b6b69Smrg#define ctSRCSYSTEM 0x4000 23c06b6b69Smrg#define ctPATSOLID 0x80000L 24c06b6b69Smrg#define ctPATSTART0 0x00000L 25c06b6b69Smrg#define ctPATSTART1 0x10000L 26c06b6b69Smrg#define ctPATSTART2 0x20000L 27c06b6b69Smrg#define ctPATSTART3 0x30000L 28c06b6b69Smrg#define ctPATSTART4 0x40000L 29c06b6b69Smrg#define ctPATSTART5 0x50000L 30c06b6b69Smrg#define ctPATSTART6 0x60000L 31c06b6b69Smrg#define ctPATSTART7 0x70000L 32c06b6b69Smrg 33c06b6b69Smrg/* Macros to do useful things with the C&T BitBLT engine */ 34c06b6b69Smrg#define ctBLTWAIT \ 35c06b6b69Smrg {HW_DEBUG(0x4); \ 36c06b6b69Smrg while(MMIO_IN32(cPtr->MMIOBase, MR(0x4)) & 0x00100000){};} 37c06b6b69Smrg 38c06b6b69Smrg#define ctSETROP(op) \ 39c06b6b69Smrg {HW_DEBUG(0x4); MMIO_OUT32(cPtr->MMIOBase, MR(0x4), op);} 40c06b6b69Smrg 41c06b6b69Smrg#define ctSETSRCADDR(srcAddr) \ 42c06b6b69Smrg {HW_DEBUG(0x5); \ 43c06b6b69Smrg MMIO_OUT32(cPtr->MMIOBase, MR(0x5),(srcAddr)&0x7FFFFFL);} 44c06b6b69Smrg 45c06b6b69Smrg#define ctSETDSTADDR(dstAddr) \ 46c06b6b69Smrg{HW_DEBUG(0x6); \ 47c06b6b69Smrg MMIO_OUT32(cPtr->MMIOBase, MR(0x6), (dstAddr)&0x7FFFFFL);} 48c06b6b69Smrg 49c06b6b69Smrg#define ctSETPITCH(srcPitch,dstPitch) \ 50c06b6b69Smrg{HW_DEBUG(0x0); \ 51c06b6b69Smrg MMIO_OUT32(cPtr->MMIOBase, MR(0x0),(((dstPitch)&0xFFFF)<<16)| \ 52c06b6b69Smrg ((srcPitch)&0xFFFF));} 53c06b6b69Smrg 54c06b6b69Smrg#define ctSETHEIGHTWIDTHGO(Height,Width)\ 55c06b6b69Smrg{HW_DEBUG(0x7); \ 56c06b6b69Smrg MMIO_OUT32(cPtr->MMIOBase, MR(0x7), (((Height)&0xFFFF)<<16)| \ 57c06b6b69Smrg ((Width)&0xFFFF));} 58c06b6b69Smrg 59c06b6b69Smrg#define ctSETPATSRCADDR(srcAddr)\ 60c06b6b69Smrg{HW_DEBUG(0x1); \ 61c06b6b69Smrg MMIO_OUT32(cPtr->MMIOBase, MR(0x1),(srcAddr)&0x1FFFFFL);} 62c06b6b69Smrg 63c06b6b69Smrg#define ctSETBGCOLOR8(c) {\ 64c06b6b69Smrg HW_DEBUG(0x2); \ 65c06b6b69Smrg if ((cAcl->bgColor != (c)) || (cAcl->bgColor == -1)) { \ 66c06b6b69Smrg cAcl->bgColor = (c); \ 67c06b6b69Smrg MMIO_OUT32(cPtr->MMIOBase, MR(0x2),\ 68c06b6b69Smrg ((((((c)&0xFF)<<8)|((c)&0xFF))<<16) | \ 69c06b6b69Smrg ((((c)&0xFF)<<8)|((c)&0xFF)))); \ 70c06b6b69Smrg } \ 71c06b6b69Smrg} 72c06b6b69Smrg 73c06b6b69Smrg#define ctSETBGCOLOR16(c) {\ 74c06b6b69Smrg HW_DEBUG(0x2); \ 75c06b6b69Smrg if ((cAcl->bgColor != (c)) || (cAcl->bgColor == -1)) { \ 76c06b6b69Smrg cAcl->bgColor = (c); \ 77c06b6b69Smrg MMIO_OUT32(cPtr->MMIOBase, MR(0x2), \ 78c06b6b69Smrg ((((c)&0xFFFF)<<16)|((c)&0xFFFF))); \ 79c06b6b69Smrg } \ 80c06b6b69Smrg} 81c06b6b69Smrg 82c06b6b69Smrg/* As the 6554x doesn't support 24bpp colour expansion this doesn't work, 83c06b6b69Smrg * It is here only for later use with the 65550 */ 84c06b6b69Smrg#define ctSETBGCOLOR24(c) {\ 85c06b6b69Smrg HW_DEBUG(0x2); \ 86c06b6b69Smrg if ((cAcl->bgColor != (c)) || (cAcl->bgColor == -1)) { \ 87c06b6b69Smrg cAcl->bgColor = (c); \ 88c06b6b69Smrg MMIO_OUT32(cPtr->MMIOBase, MR(0x2),((c)&0xFFFFFF)); \ 89c06b6b69Smrg } \ 90c06b6b69Smrg} 91c06b6b69Smrg 92c06b6b69Smrg#define ctSETFGCOLOR8(c) {\ 93c06b6b69Smrg HW_DEBUG(0x3); \ 94c06b6b69Smrg if ((cAcl->fgColor != (c)) || (cAcl->fgColor == -1)) { \ 95c06b6b69Smrg cAcl->fgColor = (c); \ 96c06b6b69Smrg MMIO_OUT32(cPtr->MMIOBase, MR(0x3), \ 97c06b6b69Smrg ((((((c)&0xFF)<<8)|((c)&0xFF))<<16) | \ 98c06b6b69Smrg ((((c)&0xFF)<<8)|((c)&0xFF)))); \ 99c06b6b69Smrg } \ 100c06b6b69Smrg} 101c06b6b69Smrg 102c06b6b69Smrg#define ctSETFGCOLOR16(c) {\ 103c06b6b69Smrg HW_DEBUG(0x3); \ 104c06b6b69Smrg if ((cAcl->fgColor != (c)) || (cAcl->fgColor == -1)) { \ 105c06b6b69Smrg cAcl->fgColor = (c); \ 106c06b6b69Smrg MMIO_OUT32(cPtr->MMIOBase, MR(0x3), \ 107c06b6b69Smrg ((((c)&0xFFFF)<<16)|((c)&0xFFFF))); \ 108c06b6b69Smrg } \ 109c06b6b69Smrg} 110c06b6b69Smrg 111c06b6b69Smrg/* As the 6554x doesn't support 24bpp colour expansion this doesn't work, 112c06b6b69Smrg * It is here only for later use with the 65550 */ 113c06b6b69Smrg#define ctSETFGCOLOR24(c) {\ 114c06b6b69Smrg HW_DEBUG(0x3); \ 115c06b6b69Smrg if ((cAcl->fgColor != (c)) || (cAcl->fgColor == -1)) { \ 116c06b6b69Smrg cAcl->fgColor = (c); \ 117c06b6b69Smrg MMIO_OUT32(cPtr->MMIOBase, MR(0x3),((c)&0xFFFFFF)); \ 118c06b6b69Smrg } \ 119c06b6b69Smrg} 120c06b6b69Smrg 121c06b6b69Smrg/* Define a Macro to replicate a planemask 64 times and write to address 122c06b6b69Smrg * allocated for planemask pattern */ 123c06b6b69Smrg#define ctWRITEPLANEMASK8(mask,addr) { \ 124c06b6b69Smrg if (cAcl->planemask != (mask&0xFF)) { \ 125c06b6b69Smrg cAcl->planemask = (mask&0xFF); \ 126c06b6b69Smrg memset((unsigned char *)cPtr->FbBase + addr, (mask&0xFF), 64); \ 127c06b6b69Smrg } \ 128c06b6b69Smrg} 129c06b6b69Smrg 130c06b6b69Smrg#define ctWRITEPLANEMASK16(mask,addr) { \ 131c06b6b69Smrg if (cAcl->planemask != (mask&0xFFFF)) { \ 132c06b6b69Smrg cAcl->planemask = (mask&0xFFFF); \ 133c06b6b69Smrg { int i; \ 134c06b6b69Smrg for (i = 0; i < 64; i++) { \ 135c06b6b69Smrg memcpy((unsigned char *)cPtr->FbBase + addr \ 136c06b6b69Smrg + i * 2, &mask, 2); \ 137c06b6b69Smrg } \ 138c06b6b69Smrg } \ 139c06b6b69Smrg } \ 140c06b6b69Smrg} 141