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7/* Definitions for the Chips and Technology BitBLT engine communication. */
8/* These are done using Memory Mapped IO, of the registers */
9/* BitBLT modes for register 93D0. */
10
11#define ctPATCOPY               0xF0
12#define ctLEFT2RIGHT            0x000
13#define ctRIGHT2LEFT            0x100
14#define ctTOP2BOTTOM            0x000
15#define ctBOTTOM2TOP            0x200
16#define ctSRCSYSTEM             0x400
17#define ctDSTSYSTEM             0x800
18#define ctSRCMONO               0x1000
19#define ctBGTRANSPARENT         0x22000
20#define ctCOLORTRANSENABLE      0x4000
21#define ctCOLORTRANSDISABLE     0x0
22#define ctCOLORTRANSDST         0x8000
23#define ctCOLORTRANSROP         0x0
24#define ctCOLORTRANSEQUAL       0x10000L
25#define ctCOLORTRANSNEQUAL      0x0
26#define ctPATMONO               0x40000L
27#define ctPATSOLID              0x80000L
28#define ctPATSTART0             0x000000L
29#define ctPATSTART1             0x100000L
30#define ctPATSTART2             0x200000L
31#define ctPATSTART3             0x300000L
32#define ctPATSTART4             0x400000L
33#define ctPATSTART5             0x500000L
34#define ctPATSTART6             0x600000L
35#define ctPATSTART7             0x700000L
36#define ctSRCFG                 0x000000L	/* Where is this for the 65550?? */
37
38/* The Monochrome expansion register setup */
39#define ctCLIPLEFT(clip)        ((clip)&0x3F)
40#define ctCLIPRIGHT(clip)       (((clip)&0x3F) << 8)
41#define ctSRCDISCARD(clip)      (((clip)&0x3F) << 16)
42#define ctBITALIGN              0x1000000L
43#define ctBYTEALIGN             0x2000000L
44#define ctWORDALIGN             0x3000000L
45#define ctDWORDALIGN            0x4000000L
46#define ctQWORDALIGN            0x5000000L
47/* This shouldn't be used because not all chip rev's
48 * have BR09 and BR0A, and I haven't even defined
49 * macros to write to these registers
50 */
51#define ctEXPCOLSEL             0x8000000L
52
53/* Macros to do useful things with the C&T BitBLT engine */
54
55/* For some odd reason the blitter busy bit occasionly "locks up" when
56 * it gets polled to fast. However I have observed this behavior only
57 * when doing ScreenToScreenColorExpandFill on a 65550. This operation
58 * was broken anyway (the source offset register is not observed) therefore
59 * no action was taken.
60 *
61 * This function uses indirect access to XR20 to test whether the blitter
62 * is busy. If the cost of doing this is too high then other options will
63 * need to be considered.
64 *
65 * Note that BR04[31] can't be used as some C&T chipsets lockup when reading
66 * the BRxx registers.
67 */
68
69#if 0
70#define ctBLTWAIT \
71                     {int timeout; \
72                     timeout = 0; \
73		     for (;;) { \
74                         if (cPtr->Chipset >= CHIPS_CT69000 ) { \
75                            if (!(MMIO_IN32(cPtr->MMIOBase,BR(0x4))&(1<<31)))\
76                                    break; \
77                         } else { \
78                            if (!(cPtr->readXR(cPtr,0x20) & 0x1)) break; \
79                         } \
80                         timeout++; \
81                         if ((cPtr->Chipset < CHIPS_CT69000 && \
82			     (timeout > 100000)) || timeout > 300000) { \
83			    unsigned char tmp; \
84                            ErrorF("%s: timeout %d (%d, %d, %d x %d) -> %d, %d \n", __func__, last_op, lx, ly, lw, lh, dx, dy); \
85                            ErrorF("dir %d %d, pitch %d %d\n", xdir, ydir, lsp, ldp); \
86			    tmp = cPtr->readXR(cPtr, 0x20); \
87			    cPtr->writeXR(cPtr, 0x20, ((tmp & 0xFD) | 0x2)); \
88                            usleep(10000); \
89                            cPtr->writeXR(cPtr, 0x20, (tmp & 0xFD)); \
90			    break; \
91                         } \
92		      } \
93		    }
94#endif
95
96/*
97 * XXX
98 * we only care about C&T 6555x which can safely use BR04
99 */
100
101#ifdef DEBUG
102#define ctBLTWAIT \
103                     {int timeout; \
104                     timeout = 0; \
105		     for (;;) { \
106		         if (!(MMIO_IN32(cPtr->MMIOBase,BR(0x4))&(1<<31)))\
107                             break; \
108                         timeout++; \
109                         if (timeout > 300000) { \
110			    unsigned char tmp; \
111                            ErrorF("%s: timeout %d (%d, %d, %d x %d) -> %d, %d \n", __func__, last_op, lx, ly, lw, lh, dx, dy); \
112                            ErrorF("dir %d %d, pitch %d %d\n", xdir, ydir, lsp, ldp); \
113			    tmp = cPtr->readXR(cPtr, 0x20); \
114			    cPtr->writeXR(cPtr, 0x20, ((tmp & 0xFD) | 0x2)); \
115                            usleep(10000); \
116                            cPtr->writeXR(cPtr, 0x20, (tmp & 0xFD)); \
117			    break; \
118                         } \
119		      } \
120		    }
121
122#else
123#define ctBLTWAIT \
124                     {int timeout; \
125                     timeout = 0; \
126		     for (;;) { \
127		         if (!(MMIO_IN32(cPtr->MMIOBase,BR(0x4))&(1<<31)))\
128                             break; \
129                         timeout++; \
130                         if (timeout > 300000) { \
131			    unsigned char tmp; \
132                            ErrorF("%s: timeout\n", __func__); \
133			    tmp = cPtr->readXR(cPtr, 0x20); \
134			    cPtr->writeXR(cPtr, 0x20, ((tmp & 0xFD) | 0x2)); \
135                            usleep(10000); \
136                            cPtr->writeXR(cPtr, 0x20, (tmp & 0xFD)); \
137			    break; \
138                         } \
139		      } \
140		    }
141
142#endif
143
144#if X_BYTE_ORDER == X_BIG_ENDIAN
145# define TWEAK_24_BE(c) \
146    c = ((c & 0xFF0000) >> 16) | (c & 0xFF00) | (( c & 0xFF) << 16)
147#else
148# define TWEAK_24_BE(c)
149#endif
150
151#define ctSETROP(op) \
152  MMIO_OUT32(cPtr->MMIOBase, BR(0x4), op)
153
154#define ctSETMONOCTL(op) \
155  MMIO_OUT32(cPtr->MMIOBase, BR(0x3), op)
156
157#define ctSETSRCADDR(srcAddr) \
158  MMIO_OUT32(cPtr->MMIOBase, BR(0x6), (srcAddr)&0x7FFFFFL)
159
160#define ctSETDSTADDR(dstAddr) \
161  MMIO_OUT32(cPtr->MMIOBase, BR(0x7), (dstAddr)&0x7FFFFFL)
162
163#define ctSETPITCH(srcPitch,dstPitch) \
164  MMIO_OUT32(cPtr->MMIOBase, BR(0x0), (((dstPitch)&0xFFFF)<<16)| \
165      ((srcPitch)&0xFFFF))
166
167#define ctSETHEIGHTWIDTHGO(Height,Width)\
168  MMIO_OUT32(cPtr->MMIOBase, BR(0x8), (((Height)&0xFFFF)<<16)| \
169      ((Width)&0xFFFF))
170
171#define ctSETPATSRCADDR(srcAddr)\
172  MMIO_OUT32(cPtr->MMIOBase, BR(0x5), (srcAddr)&0x7FFFFFL)
173
174#define ctSETBGCOLOR8(c) {\
175    if ((cAcl->bgColor != (c)) || (cAcl->bgColor == -1)) { \
176	cAcl->bgColor = (c); \
177        MMIO_OUT32(cPtr->MMIOBase, BR(0x1), ((c)&0xFF)); \
178    } \
179}
180
181#define ctSETBGCOLOR16(c) {\
182    if ((cAcl->bgColor != (c)) || (cAcl->bgColor == -1)) { \
183	cAcl->bgColor = (c); \
184        MMIO_OUT32(cPtr->MMIOBase, BR(0x1), ((c)&0xFFFF)); \
185    } \
186}
187
188#define ctSETBGCOLOR24(c) {\
189    TWEAK_24_BE(c); \
190    if ((cAcl->bgColor != (c)) || (cAcl->bgColor == -1)) { \
191	cAcl->bgColor = (c); \
192        MMIO_OUT32(cPtr->MMIOBase, BR(0x1), ((c)&0xFFFFFF)); \
193    } \
194}
195
196#define ctSETFGCOLOR8(c) {\
197    if ((cAcl->fgColor != (c)) || (cAcl->fgColor == -1)) { \
198	cAcl->fgColor = (c); \
199        MMIO_OUT32(cPtr->MMIOBase, BR(0x2), ((c)&0xFF)); \
200    } \
201}
202
203#define ctSETFGCOLOR16(c) {\
204    if ((cAcl->fgColor != (c)) || (cAcl->fgColor == -1)) { \
205	cAcl->fgColor = (c); \
206        MMIO_OUT32(cPtr->MMIOBase, BR(0x2), ((c)&0xFFFF)); \
207    } \
208}
209
210#define ctSETFGCOLOR24(c) {\
211    TWEAK_24_BE(c); \
212    if ((cAcl->fgColor != (c)) || (cAcl->fgColor == -1)) { \
213	cAcl->fgColor = (c); \
214        MMIO_OUT32(cPtr->MMIOBase, BR(0x2), ((c)&0xFFFFFF)); \
215    } \
216}
217
218/* Define a Macro to replicate a planemask 64 times and write to address
219 * allocated for planemask pattern */
220#define ctWRITEPLANEMASK8(mask,addr) { \
221    if (cAcl->planemask != (mask&0xFF)) { \
222	cAcl->planemask = (mask&0xFF); \
223	memset((unsigned char *)cPtr->FbBase + addr, (mask&0xFF), 64); \
224    } \
225}
226
227#define ctWRITEPLANEMASK16(mask,addr) { \
228    if (cAcl->planemask != (mask&0xFFFF)) { \
229	cAcl->planemask = (mask&0xFFFF); \
230	{   int i; \
231	    for (i = 0; i < 64; i++) { \
232		memcpy((unsigned char *)cPtr->FbBase + addr \
233			+ i * 2, &mask, 2); \
234	    } \
235	} \
236    } \
237}
238