dRegs.c revision c06b6b69 
1/* $XConsortium: dRegs.c /main/2 1996/10/27 11:49:40 kaleb $ */
2
3
4
5
6
7/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/chips/util/dRegs.c,v 1.8 2001/10/01 13:44:04 eich Exp $ */
8
9#ifdef __NetBSD__
10#  include <sys/types.h>
11#  include <machine/pio.h>
12#  include <machine/sysarch.h>
13#else
14#  if defined(SVR4) && defined(i386)
15#    include <sys/types.h>
16#    ifdef NCR
17       /* broken NCR <sys/sysi86.h> */
18#      define __STDC
19#      include <sys/sysi86.h>
20#      undef __STDC
21#    else
22#      include <sys/sysi86.h>
23#    endif
24#    ifdef SVR4
25#      if !defined(sun)
26#        include <sys/seg.h>
27#      endif
28#    endif
29#    include <sys/v86.h>
30#    if defined(sun)
31#      include <sys/psw.h>
32#    endif
33#  endif
34#  include "AsmMacros.h"
35#endif /* NetBSD */
36
37#include <unistd.h>
38#include <stdio.h>
39#include <stdlib.h>
40
41#ifdef __NetBSD__
42#  define SET_IOPL() i386_iopl(3)
43#  define RESET_IOPL() i386_iopl(0)
44#else
45#  if defined(SVR4) && defined(i386)
46#    ifndef SI86IOPL
47#      define SET_IOPL() sysi86(SI86V86,V86SC_IOPL,PS_IOPL)
48#      define RESET_IOPL() sysi86(SI86V86,V86SC_IOPL,0)
49#    else
50#      define SET_IOPL() sysi86(SI86IOPL,3)
51#      define RESET_IOPL() sysi86(SI86IOPL,0)
52#    endif
53#  else
54#    ifdef linux
55#      define SET_IOPL() iopl(3)
56#      define RESET_IOPL() iopl(0)
57#    else
58#      define SET_IOPL() (void)0
59#      define RESET_IOPL() (void)0
60#    endif
61#  endif
62#endif
63
64int main(void)
65{
66    int i, HTotal, HDisplay, HSyncStart, HSyncEnd,
67    VTotal, VDisplay, VSyncStart, VSyncEnd;
68    unsigned char storeReg, bpp, shift, IOSS = 0, MSS = 0, again = 0;
69    unsigned short port;
70    int isHiQV = 0;
71    int is69030 = 0;
72
73    SET_IOPL();
74
75    printf("0x3C6\t0x%X\n",inw(0x3C6));
76
77/* Check to see if the Chip is HiQV */
78    outb(0x3D6,0x02);
79    storeReg = inb(0x3D7);
80    if (storeReg == 0xE0	/* CT65550 */
81	|| storeReg == 0xE4	/* CT65554 */
82	|| storeReg == 0xE5	/* CT65555 */
83	|| storeReg == 0xF4	/* CT68554 */
84	|| storeReg == 0xC0)	/* CT69000 */
85    {
86	isHiQV = 1;
87    } else if (storeReg == 0x30) {
88      outb(0x3D6,0x03);
89      storeReg = inb(0x3D7);
90      if (storeReg == 0xC) {
91	isHiQV = 1;
92	is69030 = 1;
93	IOSS=inb(0x3CD);
94	MSS=inb(0x3CB);
95	outb(0x3CD,((IOSS&0xE0)| 0x11));  /* Select Channel 0 */
96	outb(0x3CB,((MSS&0xF0)| 0x8));
97	again = 1;
98	printf("Pipeline A:\n");
99      }
100    }
101
102 again:
103    printf("port 0x3D6 (C&T)\n");
104    storeReg = inb(0x3D6);
105    shift = 3;
106    if (isHiQV==1) {
107	outw(0x102,1);	/*global enable, VGA awake*/
108	printf("0x%2.2X\n",inb(0x3C3)&0xFF);
109	outb(0x3C3,0);	/*disable VGA*/
110	outb(0x3C3,1);	/*enable VGA*/
111	for(i = 0;i < 0xFF;i++){
112	    outb(0x3D6,i);
113	    printf("XR 0x%2.2X\t0x%2.2X\n",i,inb(0x3D7)&0xFF);
114	}
115	outb(0x3D6,0xE2);
116	bpp = inb(0x3D7)&0xF0;
117    } else {
118	outb(0x3D6, 0x70);
119	outw(0x3D6, (inw(0x3D6) | 0x8070));
120	outw(0x46E8,0x0016);	/*setup mode*/
121	outw(0x102,1);	/*global enable, VGA awake*/
122	outw(0x46E8,0x000E);	/*exit from setup mode*/
123	printf("0x%2.2X\n",inb(0x3C3)&0xFF);
124	outb(0x3C3,0);	/*disable VGA*/
125	outw(0x46E8,0x0000);	/*exit from setup mode*/
126	outw(0x46E8,0x000E);	/*exit from setup mode*/
127	outb(0x3C3,1);	/*enable VGA*/
128	outw(0x46E8,0x0000);	/*exit from setup mode*/
129	for(i = 0;i < 0x80;i++){
130	    outb(0x3D6,i);
131	    printf("XR 0x%2.2X\t0x%2.2X\n",i,inb(0x3D7)&0xFF);
132	}
133	outb(0x3D6,0x2B);
134	bpp = inb(0x3D7)&0xF0;
135    }
136
137    switch(bpp){
138      case 0x20:
139	bpp = 4;
140	break;
141      case 0x30:
142	bpp = 8;
143	break;
144      case 0x40:
145	bpp = 16;
146	shift = 2;
147	break;
148      case 0x50:
149	bpp = 24;
150	break;
151      default:
152	bpp = 0;
153    }
154    outb(0x3D6,storeReg);
155
156    printf("\nport 0x3D4 (CRTC)\n");
157    storeReg = inb(0x3D4);
158    if (isHiQV==1) {
159	for(i = 0;i < 0x7F;i++){
160	    outb(0x3D4,i);
161	    printf("CR 0x%2.2X\t0x%2.2X\n",i,inb(0x3D5)&0xFF);
162	}
163	outb(0x3D4,storeReg);
164	printf("\nport 0x3D0 (Flat Panel)\n");
165	storeReg = inb(0x3D0);
166	for(i = 0;i < 0x7F;i++){
167	    outb(0x3D0,i);
168	    printf("FR 0x%2.2X\t0x%2.2X\n",i,inb(0x3D1)&0xFF);
169	}
170	outb(0x3D1,storeReg);
171	printf("\nport 0x3D2 (Multimedia)\n");
172	storeReg = inb(0x3D2);
173	for(i = 0;i < 0x7F;i++){
174	    outb(0x3D2,i);
175	    printf("MR 0x%2.2X\t0x%2.2X\n",i,inb(0x3D3)&0xFF);
176	}
177	outb(0x3D3,storeReg);
178    } else {
179	for(i = 0;i < 0x40;i++){
180	    outb(0x3D4,i);
181	    printf("CR 0x%2.2X\t0x%2.2X\n",i,inb(0x3D5)&0xFF);
182	}
183	outb(0x3D4,storeReg);
184    }
185
186
187    printf("port 0x3CE (GC)\n");
188    storeReg = inb(0x3CE);
189    for(i = 0;i < 0x10;i++){
190	outb(0x3CE,i);
191	printf("GC 0x%2.2X\t0x%2.2X\n",i,inb(0x3CF)&0xFF);
192    }
193    outb(0x3CE,storeReg);
194    printf("port 0x3C4 (Sequencer)\n");
195    storeReg = inb(0x3C4);
196    for(i = 0;i < 0x10;i++){
197	outb(0x3C4,i);
198	printf("SQ 0x%2.2X\t0x%X2.2\n",i,inb(0x3C5)&0xFF);
199    }
200    outb(0x3C4,storeReg);
201
202
203    printf("port 0x3C0 (Attribute)\n");
204    inb(0x3DA);
205    storeReg = inb(0x3C0);
206    for(i = 0;i < 0xFF;i++){
207	inb(0x3DA);
208	outb(0x3C0,i);
209	printf("AT 0x%2.2X\t0x%2.2X\n",i,inb(0x3C1)&0xFF);
210    }
211    inb(0x3DA);
212    outb(0x3C0,storeReg);
213
214    printf("0x3CC\t0x%X\n",inb(0x3CC)&0xFF);
215    printf("0x3C2\t0x%X\n",inb(0x3C2)&0xFF);
216    printf("0x3C3\t0x%X\n",inb(0x3C2)&0xFF);
217    printf("0x3CA\t0x%X\n",inb(0x3CA)&0xFF);
218    printf("0x3DA\t0x%X\n",inb(0x3DA)&0xFF);
219
220    printf("\nRAMDAC\nport\tvalue\n");
221    for(port = 0x83C6; port < 0x83CA;port++){
222      printf("0x%4X\t0x%4X\n",port,inw(port));
223    }
224
225    if (isHiQV!=1) {
226	printf("\nBitBLT\nport\tvalue\n");
227	for(port = 0x83D0; port <= 0x9FD0;port+=0x400){
228	    printf("0x%4.4X\t0x%4X\n",port,inw(port));
229	}
230
231	printf("\nH/W cursor\nport\tvalue\n");
232	for(port = 0xA3D0; port <= 0xB3D0;port+=0x400){
233	    printf("0x%4.4X\t0x%4X\n",port,inw(port));
234	}
235
236
237	outb(0x3D6, 0x70);
238	outw(0x3D6, (inw(0x3D6) | 0x8070));
239
240	printf("0x46E8\t0x%8X\n",inl(0x46E8));
241	printf("0x4AE8\t0x%8X\n",inl(0x4AE8));
242	printf("0x102\t0x%8X\n",inl(0x102));
243	printf("0x103\t0x%8X\n",inl(0x103));
244
245    }
246
247    storeReg = inb(0x3D4);
248    {
249	outb(0x3D4,0);
250	HTotal = ((inb(0x3D5)&0xFF) + 5) << shift;
251	outb(0x3D4,1);
252	HDisplay = ((inb(0x3D5)&0xFF) + 1) << shift;
253	outb(0x3D4,4);
254	HSyncStart = ((inb(0x3D5)&0xFF) + 1) << shift;
255	outb(0x3D4,5);
256	HSyncEnd = inb(0x3D5)&0x1F;
257	outb(0x3D4,5);
258	HSyncEnd += HSyncStart >> shift;
259	HSyncEnd <<= shift;
260
261	outb(0x3D4,6);
262	VTotal = inb(0x3D5)&0xFF;
263	outb(0x3D4,7);
264	VTotal |= (inb(0x3D5)&0x1) << 8;
265	VTotal |= (inb(0x3D5)&0x20) << 4;
266	VTotal += 2;
267	VDisplay = (inb(0x3D5)&0x2) << 7;
268	VDisplay |= (inb(0x3D5)&0x40) << 3;
269	VSyncStart = (inb(0x3D5)&0x4) << 6;
270	VSyncStart |= (inb(0x3D5)&0x80) << 2;
271	outb(0x3D4,0x12);
272	    VDisplay |= inb(0x3D5)&0xFF;
273	VDisplay += 1;
274	outb(0x3D4,0x10);
275	VSyncStart |= inb(0x3D5)&0xFF;
276
277	outb(0x3D4,0x11);
278	VSyncEnd = inb(0x3D5)&0xF;
279	VSyncEnd += VSyncStart;
280
281    }
282    outb(0x3D4,storeReg);
283
284    printf("\nModeLine with port 0x3D4 (CRTC) %d %d %d %d %d %d %d %d\n",
285	   HDisplay, HSyncStart, HSyncEnd, HTotal,
286	   VDisplay, VSyncStart, VSyncEnd, VTotal);
287
288
289    if (is69030==1) {
290      if (again==1) {
291	again=0;
292	printf("\n\nPipeline B:\n");
293	outb(0x3CD,((IOSS&0xE0)| 0x1F));  /* Select Channel 1 */
294	outb(0x3CB,((MSS&0xF0)| 0xF));
295	goto again;
296      } else {
297	outb(0x3CD,IOSS);
298	outb(0x3CB,MSS);
299	printf("\n\n0x3CB\t0x%X  (MSS)\n",inb(0x3CB)&0xFF);
300	printf("0x3CD\t0x%X  (IOSS)\n",inb(0x3CD)&0xFF);
301      }
302    }
303    RESET_IOPL();
304    return 0;
305}
306