1/* 2 * Copyright (c) 2006 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 * 22 * Neither the name of the Advanced Micro Devices, Inc. nor the names of its 23 * contributors may be used to endorse or promote products derived from this 24 * software without specific prior written permission. 25 */ 26 27 /* 28 * Cimarron register definitions 29 */ 30 31#ifndef _cim_regs_h 32#define _cim_regs_h 33 34/*----------------------------------------------------------------*/ 35/* GRAPHICS PROCESSOR DEFINITIONS */ 36/*----------------------------------------------------------------*/ 37 38/*----------------------------*/ 39/* COMMAND BUFFER DEFINITIONS */ 40/*----------------------------*/ 41 42#define GP3_BLT_COMMAND_SIZE 68 /* 18 DWORDS */ 43#define GP3_VECTOR_COMMAND_SIZE 56 /* 14 DWORDS */ 44#define GP3_4BPP_LUT_COMMAND_SIZE 76 /* 16 DWORDS + 3 CMD DWORDS */ 45#define GP3_8BPP_LUT_COMMAND_SIZE 1036 /* 256 DWORDS + 46 * 3 CMD DWORDS */ 47#define GP3_VECTOR_PATTERN_COMMAND_SIZE 20 /* 2 DWORDS + 3 CMD DWORDS */ 48#define GP3_MAX_COMMAND_SIZE 9000 /* 8K + 49 * WORKAROUND SPACE */ 50#define GP3_SCRATCH_BUFFER_SIZE 0x100000 /* 1MB SCRATCH 51 * BUFFER */ 52#define GP3_BLT_1PASS_SIZE 0xC7F8 /* (50K - 8) is largest 53 * 1-Pass load size */ 54 55/*-------------------------------------*/ 56/* BLT COMMAND BUFFER REGISTER OFFSETS */ 57/*-------------------------------------*/ 58 59#define GP3_BLT_CMD_HEADER 0x00000000 60#define GP3_BLT_RASTER_MODE 0x00000004 61#define GP3_BLT_DST_OFFSET 0x00000008 62#define GP3_BLT_SRC_OFFSET 0x0000000C 63#define GP3_BLT_STRIDE 0x00000010 64#define GP3_BLT_WID_HEIGHT 0x00000014 65#define GP3_BLT_SRC_COLOR_FG 0x00000018 66#define GP3_BLT_SRC_COLOR_BG 0x0000001C 67#define GP3_BLT_PAT_COLOR_0 0x00000020 68#define GP3_BLT_PAT_COLOR_1 0x00000024 69#define GP3_BLT_PAT_DATA_0 0x00000028 70#define GP3_BLT_PAT_DATA_1 0x0000002C 71#define GP3_BLT_CH3_OFFSET 0x00000030 72#define GP3_BLT_CH3_MODE_STR 0x00000034 73#define GP3_BLT_CH3_WIDHI 0x00000038 74#define GP3_BLT_BASE_OFFSET 0x0000003C 75#define GP3_BLT_MODE 0x00000040 76 77/*-----------------------------------------------------------------*/ 78/* VECTOR COMMAND BUFFER REGISTER OFFSETS */ 79/* Some of these are identical to the BLT registers (and we will */ 80/* be assumed to be such in the Cimarron code, but they are listed */ 81/* here for clarity and for future changes. */ 82/*-----------------------------------------------------------------*/ 83 84#define GP3_VEC_CMD_HEADER 0x00000000 85#define GP3_VECTOR_RASTER_MODE 0x00000004 86#define GP3_VECTOR_DST_OFFSET 0x00000008 87#define GP3_VECTOR_VEC_ERR 0x0000000C 88#define GP3_VECTOR_STRIDE 0x00000010 89#define GP3_VECTOR_VEC_LEN 0x00000014 90#define GP3_VECTOR_SRC_COLOR_FG 0x00000018 91#define GP3_VECTOR_PAT_COLOR_0 0x0000001C 92#define GP3_VECTOR_PAT_COLOR_1 0x00000020 93#define GP3_VECTOR_PAT_DATA_0 0x00000024 94#define GP3_VECTOR_PAT_DATA_1 0x00000028 95#define GP3_VECTOR_CH3_MODE_STR 0x0000002C 96#define GP3_VECTOR_BASE_OFFSET 0x00000030 97#define GP3_VECTOR_MODE 0x00000034 98 99/*---------------------------------------------------*/ 100/* GP REGISTER DEFINITIONS */ 101/* Addresses for writing or reading directly to/from */ 102/* the graphics processor. */ 103/*---------------------------------------------------*/ 104 105#define GP3_DST_OFFSET 0x00000000 106#define GP3_SRC_OFFSET 0x00000004 107#define GP3_VEC_ERR 0x00000004 108#define GP3_STRIDE 0x00000008 109#define GP3_WID_HEIGHT 0x0000000C 110#define GP3_VEC_LEN 0x0000000C 111#define GP3_SRC_COLOR_FG 0x00000010 112#define GP3_SRC_COLOR_BG 0x00000014 113#define GP3_PAT_COLOR_0 0x00000018 114#define GP3_PAT_COLOR_1 0x0000001C 115#define GP3_PAT_COLOR_2 0x00000020 116#define GP3_PAT_COLOR_3 0x00000024 117#define GP3_PAT_COLOR_4 0x00000028 118#define GP3_PAT_COLOR_5 0x0000002C 119#define GP3_PAT_DATA_0 0x00000030 120#define GP3_PAT_DATA_1 0x00000034 121#define GP3_RASTER_MODE 0x00000038 122#define GP3_VEC_MODE 0x0000003C 123#define GP3_BLT_MODE 0x00000040 124#define GP3_BLT_STATUS 0x00000044 125#define GP3_HST_SRC 0x00000048 126#define GP3_BASE_OFFSET 0x0000004C 127#define GP3_CMD_TOP 0x00000050 128#define GP3_CMD_BOT 0x00000054 129#define GP3_CMD_READ 0x00000058 130#define GP3_CMD_WRITE 0x0000005C 131#define GP3_CH3_OFFSET 0x00000060 132#define GP3_CH3_MODE_STR 0x00000064 133#define GP3_CH3_WIDHI 0x00000068 134#define GP3_CH3_HST_SRC 0x0000006C 135#define GP3_LUT_ADDRESS 0x00000070 136#define GP3_LUT_DATA 0x00000074 137#define GP3_INT_CTL 0x00000078 138#define GP3_HST_SRC_RANGE 0x00000100 139 140/*------------------------*/ 141/* REGISTER BIT FIELDS */ 142/*------------------------*/ 143 144/* GP3_BLT_CMD_HEADER BIT DEFINITIONS */ 145 146#define GP3_BLT_HDR_WRAP 0x80000000 147#define GP3_BLT_HDR_TYPE 0x00000000 148#define GP3_BLT_HDR_HAZARD_ENABLE 0x10000000 149#define GP3_BLT_HDR_RASTER_ENABLE 0x00000001 150#define GP3_BLT_HDR_DST_OFF_ENABLE 0x00000002 151#define GP3_BLT_HDR_SRC_OFF_ENABLE 0x00000004 152#define GP3_BLT_HDR_STRIDE_ENABLE 0x00000008 153#define GP3_BLT_HDR_WIDHI_ENABLE 0x00000010 154#define GP3_BLT_HDR_SRC_FG_ENABLE 0x00000020 155#define GP3_BLT_HDR_SRC_BG_ENABLE 0x00000040 156#define GP3_BLT_HDR_PAT_CLR0_ENABLE 0x00000080 157#define GP3_BLT_HDR_PAT_CLR1_ENABLE 0x00000100 158#define GP3_BLT_HDR_PAT_DATA0_ENABLE 0x00000200 159#define GP3_BLT_HDR_PAT_DATA1_ENABLE 0x00000400 160#define GP3_BLT_HDR_CH3_OFF_ENABLE 0x00000800 161#define GP3_BLT_HDR_CH3_STR_ENABLE 0x00001000 162#define GP3_BLT_HDR_CH3_WIDHI_ENABLE 0x00002000 163#define GP3_BLT_HDR_BASE_OFFSET_ENABLE 0x00004000 164#define GP3_BLT_HDR_BLT_MODE_ENABLE 0x00008000 165 166/* GP3_VEC_CMD_HEADER BIT DEFINITIONS */ 167 168#define GP3_VEC_HDR_WRAP 0x80000000 169#define GP3_VEC_HDR_TYPE 0x20000000 170#define GP3_VEC_HDR_HAZARD_ENABLE 0x10000000 171#define GP3_VEC_HDR_RASTER_ENABLE 0x00000001 172#define GP3_VEC_HDR_DST_OFF_ENABLE 0x00000002 173#define GP3_VEC_HDR_VEC_ERR_ENABLE 0x00000004 174#define GP3_VEC_HDR_STRIDE_ENABLE 0x00000008 175#define GP3_VEC_HDR_VEC_LEN_ENABLE 0x00000010 176#define GP3_VEC_HDR_SRC_FG_ENABLE 0x00000020 177#define GP3_VEC_HDR_PAT_CLR0_ENABLE 0x00000040 178#define GP3_VEC_HDR_PAT_CLR1_ENABLE 0x00000080 179#define GP3_VEC_HDR_PAT_DATA0_ENABLE 0x00000100 180#define GP3_VEC_HDR_PAT_DATA1_ENABLE 0x00000200 181#define GP3_VEC_HDR_CH3_STR_ENABLE 0x00000400 182#define GP3_VEC_HDR_BASE_OFFSET_ENABLE 0x00000800 183#define GP3_VEC_HDR_VEC_MODE_ENABLE 0x00001000 184 185/* GP3_RASTER_MODE BIT DEFINITIONS */ 186 187#define GP3_RM_BPPFMT_332 0x00000000 /* 8 BPP, palettized */ 188#define GP3_RM_BPPFMT_4444 0x40000000 /* 16 BPP, 4:4:4:4 */ 189#define GP3_RM_BPPFMT_1555 0x50000000 /* 16 BPP, 1:5:5:5 */ 190#define GP3_RM_BPPFMT_565 0x60000000 /* 16 BPP, 5:6:5 */ 191#define GP3_RM_BPPFMT_8888 0x80000000 /* 32 BPP, 8:8:8:8 */ 192#define GP3_RM_ALPHA_ALL 0x00C00000 /* Alpha enable */ 193#define GP3_RM_ALPHA_TO_RGB 0x00400000 /* Alpha applies to RGB */ 194#define GP3_RM_ALPHA_TO_ALPHA 0x00800000 /* Alpha applies to alpha */ 195#define GP3_RM_ALPHA_OP_MASK 0x00300000 /* Alpha operation */ 196#define GP3_RM_ALPHA_TIMES_A 0x00000000 /* Alpha * A */ 197#define GP3_RM_BETA_TIMES_B 0x00100000 /* (1-alpha) * B */ 198#define GP3_RM_A_PLUS_BETA_B 0x00200000 /* A + (1-alpha) * B */ 199#define GP3_RM_ALPHA_A_PLUS_BETA_B 0x00300000 /* alpha * A + (1 - alpha)B */ 200#define GP3_RM_ALPHA_SELECT 0x000E0000 /* Alpha Select */ 201#define GP3_RM_SELECT_ALPHA_A 0x00000000 /* Alpha from channel A */ 202#define GP3_RM_SELECT_ALPHA_B 0x00020000 /* Alpha from channel B */ 203#define GP3_RM_SELECT_ALPHA_R 0x00040000 /* Registered alpha */ 204#define GP3_RM_SELECT_ALPHA_1 0x00060000 /* Constant 1 */ 205#define GP3_RM_SELECT_ALPHA_CHAN_A 0x00080000 /* RGB Values from A */ 206#define GP3_RM_SELECT_ALPHA_CHAN_B 0x000A0000 /* RGB Values from B */ 207#define GP3_RM_SELECT_ALPHA_CHAN_3 0x000C0000 /* Alpha from channel 3 */ 208#define GP3_RM_DEST_FROM_CHAN_A 0x00010000 /* Alpha channel select */ 209#define GP3_RM_PATTERN_INVERT 0x00001000 /* Invert monochrome pat */ 210#define GP3_RM_SOURCE_INVERT 0x00002000 /* Invert monochrome src */ 211#define GP3_RM_PAT_FLAGS 0x00000700 /* pattern related bits */ 212#define GP3_RM_PAT_MONO 0x00000100 /* monochrome pattern */ 213#define GP3_RM_PAT_COLOR 0x00000200 /* color pattern */ 214#define GP3_RM_PAT_TRANS 0x00000400 /* pattern transparency */ 215#define GP3_RM_SRC_TRANS 0x00000800 /* source transparency */ 216 217/* GP3_VECTOR_MODE REGISTER DESCRIPTIONS */ 218 219#define GP3_VM_DST_REQ 0x00000008 /* dst data required */ 220#define GP3_VM_THROTTLE 0x00000010 /* sync to VBLANK */ 221 222/* GP3_BLT_MODE REGISTER DEFINITIONS */ 223 224#define GP3_BM_SRC_FB 0x00000001 /* src = frame buffer */ 225#define GP3_BM_SRC_HOST 0x00000002 /* src = host register */ 226#define GP3_BM_DST_REQ 0x00000004 /* dst data required */ 227#define GP3_BM_SRC_MONO 0x00000040 /* monochrome source data */ 228#define GP3_BM_SRC_BP_MONO 0x00000080 /* Byte-packed monochrome */ 229#define GP3_BM_NEG_YDIR 0x00000100 /* negative Y direction */ 230#define GP3_BM_NEG_XDIR 0x00000200 /* negative X direction */ 231#define GP3_BM_THROTTLE 0x00000400 /* sync to VBLANK */ 232 233/* GP3_BLT_STATUS REGISTER DEFINITIONS */ 234 235#define GP3_BS_BLT_BUSY 0x00000001 /* GP is not idle */ 236#define GP3_BS_BLT_PENDING 0x00000004 /* second BLT is pending */ 237#define GP3_BS_HALF_EMPTY 0x00000008 /* src FIFO half empty */ 238#define GP3_BS_CB_EMPTY 0x00000010 /* Command buffer empty. */ 239 240/* GP3_CH3_MODE_STR REGISTER DEFINITIONS */ 241 242#define GP3_CH3_C3EN 0x80000000 243#define GP3_CH3_REPLACE_SOURCE 0x40000000 244#define GP3_CH3_NEG_XDIR 0x20000000 245#define GP3_CH3_NEG_YDIR 0x10000000 246#define GP3_CH3_SRC_FMT_MASK 0x0f000000 247#define GP3_CH3_SRC_3_3_2 0x00000000 248#define GP3_CH3_SRC_8BPP_INDEXED 0x01000000 249#define GP3_CH3_SRC_8BPP_ALPHA 0x02000000 250#define GP3_CH3_SRC_4_4_4_4 0x04000000 251#define GP3_CH3_SRC_1_5_5_5 0x05000000 252#define GP3_CH3_SRC_0_5_6_5 0x06000000 253#define GP3_CH3_SRC_Y_U_V 0x07000000 254#define GP3_CH3_SRC_8_8_8_8 0x08000000 255#define GP3_CH3_SRC_24BPP_PACKED 0x0B000000 256#define GP3_CH3_SRC_4BPP_INDEXED 0x0D000000 257#define GP3_CH3_SRC_4BPP_ALPHA 0x0E000000 258#define GP3_CH3_SRC_MASK 0x0F000000 259#define GP3_CH3_ROTATE_ENABLE 0x00800000 260#define GP3_CH3_BGR_ORDER 0x00400000 261#define GP3_CH3_COLOR_PAT_ENABLE 0x00200000 262#define GP3_CH3_PRESERVE_LUT 0x00100000 263#define GP3_CH3_PREFETCH_ENABLE 0x00080000 264#define GP3_CH3_HST_SRC_ENABLE 0x00040000 265#define GP3_CH3_STRIDE_MASK 0x0000FFFF 266 267/* DATA AND LUT LOAD BIT DEFINITIONS */ 268 269#define GP3_LUT_HDR_WRAP 0x80000000 270#define GP3_LUT_HDR_TYPE 0x40000000 271#define GP3_LUT_HDR_DATA_ENABLE 0x00000003 272#define GP3_DATA_LOAD_HDR_WRAP 0x80000000 273#define GP3_DATA_LOAD_HDR_TYPE 0x60000000 274#define GP3_DATA_LOAD_HDR_ENABLE 0x00000001 275 276#define GP3_HOST_SOURCE_TYPE 0x00000000 277#define GP3_CH3_HOST_SOURCE_TYPE 0x20000000 278#define GP3_OLD_PATTERN_COLORS 0x40000000 279#define GP3_LUT_DATA_TYPE 0x60000000 280 281#define GP3_BASE_OFFSET_DSTMASK 0xFFC00000 282#define GP3_BASE_OFFSET_SRCMASK 0x003FF000 283#define GP3_BASE_OFFSET_CH3MASK 0x00000FFC 284 285/*----------------------------------------------------------------*/ 286/* VIDEO GENERATOR DEFINITIONS */ 287/*----------------------------------------------------------------*/ 288 289#define DC3_UNLOCK 0x00000000 /* Unlock register */ 290#define DC3_GENERAL_CFG 0x00000004 /* Config registers */ 291#define DC3_DISPLAY_CFG 0x00000008 292#define DC3_ARB_CFG 0x0000000C 293 294#define DC3_FB_ST_OFFSET 0x00000010 /* Frame buffer start offset */ 295#define DC3_CB_ST_OFFSET 0x00000014 /* Compression start offset */ 296#define DC3_CURS_ST_OFFSET 0x00000018 /* Cursor buffer start offset */ 297#define DC3_VID_Y_ST_OFFSET 0x00000020 /* Video Y Buffer start offset */ 298#define DC3_VID_U_ST_OFFSET 0x00000024 /* Video U Buffer start offset */ 299#define DC3_VID_V_ST_OFFSET 0x00000028 /* Video V Buffer start offset */ 300#define DC3_DV_TOP 0x0000002C /* DV Ram Limit Register */ 301#define DC3_LINE_SIZE 0x00000030 /* Video, CB, and FB line sizes */ 302#define DC3_GFX_PITCH 0x00000034 /* FB and DB skip counts */ 303#define DC3_VID_YUV_PITCH 0x00000038 /* Y, U and V buffer skip counts */ 304 305#define DC3_H_ACTIVE_TIMING 0x00000040 /* Horizontal timings */ 306#define DC3_H_BLANK_TIMING 0x00000044 307#define DC3_H_SYNC_TIMING 0x00000048 308#define DC3_V_ACTIVE_TIMING 0x00000050 /* Vertical Timings */ 309#define DC3_V_BLANK_TIMING 0x00000054 310#define DC3_V_SYNC_TIMING 0x00000058 311#define DC3_FB_ACTIVE 0x0000005C 312 313#define DC3_CURSOR_X 0x00000060 /* Cursor X position */ 314#define DC3_CURSOR_Y 0x00000064 /* Cursor Y Position */ 315#define DC3_LINE_CNT_STATUS 0x0000006C 316 317#define DC3_PAL_ADDRESS 0x00000070 /* Palette Address */ 318#define DC3_PAL_DATA 0x00000074 /* Palette Data */ 319#define DC3_DFIFO_DIAG 0x00000078 /* Display FIFO diagnostic */ 320#define DC3_CFIFO_DIAG 0x0000007C /* Compression FIFO diagnostic */ 321 322#define DC3_VID_DS_DELTA 0x00000080 /* Vertical Downscaling fraction */ 323 324#define DC3_PHY_MEM_OFFSET 0x00000084 /* VG Base Address Register */ 325#define DC3_DV_CTL 0x00000088 /* Dirty-Valid Control Register */ 326#define DC3_DV_ACC 0x0000008C /* Dirty-Valid RAM Access */ 327 328#define DC3_GFX_SCALE 0x00000090 /* Graphics Scaling */ 329#define DC3_IRQ_FILT_CTL 0x00000094 /* VBlank interrupt and filters */ 330#define DC3_FILT_COEFF1 0x00000098 331#define DC3_FILT_COEFF2 0x0000009C 332 333#define DC3_VBI_EVEN_CTL 0x000000A0 /* VBI Data Buffer Controls */ 334#define DC3_VBI_ODD_CTL 0x000000A4 335#define DC3_VBI_HOR 0x000000A8 336#define DC3_VBI_LN_ODD 0x000000AC 337#define DC3_VBI_LN_EVEN 0x000000B0 338#define DC3_VBI_PITCH 0x000000B4 339 340#define DC3_COLOR_KEY 0x000000B8 /* Graphics color key */ 341#define DC3_COLOR_MASK 0x000000BC /* Graphics color key mask */ 342#define DC3_CLR_KEY_X 0x000000C0 343#define DC3_CLR_KEY_Y 0x000000C4 344 345#define DC3_IRQ 0x000000C8 346#define DC3_GENLK_CTL 0x000000D4 347 348#define DC3_VID_EVEN_Y_ST_OFFSET 0x000000D8 /* Even field video buffers */ 349#define DC3_VID_EVEN_U_ST_OFFSET 0x000000DC 350#define DC3_VID_EVEN_V_ST_OFFSET 0x000000E0 351 352#define DC3_V_ACTIVE_EVEN 0x000000E4 /* Even field timing registers */ 353#define DC3_V_BLANK_EVEN 0x000000E8 354#define DC3_V_SYNC_EVEN 0x000000EC 355 356/* UNLOCK VALUE */ 357 358#define DC3_UNLOCK_VALUE 0x00004758 /* used to unlock DC regs */ 359 360/* VG GEODELINK DEVICE SMI MSR FIELDS */ 361 362#define DC3_VG_BL_MASK 0x00000001 363#define DC3_MISC_MASK 0x00000002 364#define DC3_ISR0_MASK 0x00000004 365#define DC3_VGA_BL_MASK 0x00000008 366#define DC3_CRTCIO_MSK 0x00000010 367#define DC3_VG_BLANK_SMI 0x00000001 368#define DC3_MISC_SMI 0x00000002 369#define DC3_ISR0_SMI 0x00000004 370#define DC3_VGA_BLANK_SMI 0x00000008 371#define DC3_CRTCIO_SMI 0x00000010 372 373/* DC3_GENERAL_CFG BIT FIELDS */ 374 375#define DC3_GCFG_DBUG 0x80000000 376#define DC3_GCFG_DBSL 0x40000000 377#define DC3_GCFG_CFRW 0x20000000 378#define DC3_GCFG_DIAG 0x10000000 379#define DC3_GCFG_CRC_MODE 0x08000000 380#define DC3_GCFG_SGFR 0x04000000 381#define DC3_GCFG_SGRE 0x02000000 382#define DC3_GCFG_SIGE 0x01000000 383#define DC3_GCFG_SIG_SEL 0x00800000 384#define DC3_GCFG_YUV_420 0x00100000 385#define DC3_GCFG_VDSE 0x00080000 386#define DC3_GCFG_VGAFT 0x00040000 387#define DC3_GCFG_FDTY 0x00020000 388#define DC3_GCFG_STFM 0x00010000 389#define DC3_GCFG_DFHPEL_MASK 0x0000F000 390#define DC3_GCFG_DFHPSL_MASK 0x00000F00 391#define DC3_GCFG_VGAE 0x00000080 392#define DC3_GCFG_DECE 0x00000040 393#define DC3_GCFG_CMPE 0x00000020 394#define DC3_GCFG_FILT_SIG_SEL 0x00000010 395#define DC3_GCFG_VIDE 0x00000008 396#define DC3_GCFG_CLR_CUR 0x00000004 397#define DC3_GCFG_CURE 0x00000002 398#define DC3_GCFG_DFLE 0x00000001 399 400/* DC3_DISPLAY_CFG BIT FIELDS */ 401 402#define DC3_DCFG_VISL 0x08000000 403#define DC3_DCFG_FRLK 0x04000000 404#define DC3_DCFG_PALB 0x02000000 405#define DC3_DCFG_DCEN 0x01000000 406#define DC3_DCFG_VFHPEL_MASK 0x000F0000 407#define DC3_DCFG_VFHPSL_MASK 0x0000F000 408#define DC3_DCFG_16BPP_MODE_MASK 0x00000C00 409#define DC3_DCFG_16BPP 0x00000000 410#define DC3_DCFG_15BPP 0x00000400 411#define DC3_DCFG_12BPP 0x00000800 412#define DC3_DCFG_DISP_MODE_MASK 0x00000300 413#define DC3_DCFG_DISP_MODE_8BPP 0x00000000 414#define DC3_DCFG_DISP_MODE_16BPP 0x00000100 415#define DC3_DCFG_DISP_MODE_24BPP 0x00000200 416#define DC3_DCFG_DISP_MODE_32BPP 0x00000300 417#define DC3_DCFG_TRUP 0x00000040 418#define DC3_DCFG_VDEN 0x00000010 419#define DC3_DCFG_GDEN 0x00000008 420#define DC3_DCFG_TGEN 0x00000001 421 422/* DC3_ARB_CFG BIT FIELDS */ 423 424#define DC3_ACFG_LB_LOAD_WM_EN 0x00100000 425#define DC3_ACFG_LB_LOAD_WM_MASK 0x000F0000 426#define DC3_ACFG_LPEN_END_COUNT_MASK 0x0000FE00 427#define DC3_ACFG_HPEN_SBINV 0x00000100 428#define DC3_ACFG_HPEN_FB_INV_HALFSB 0x00000080 429#define DC3_ACFG_HPEN_FB_INV_SBRD 0x00000040 430#define DC3_ACFG_HPEN_FB_INV 0x00000020 431#define DC3_ACFG_HPEN_1LB_INV 0x00000010 432#define DC3_ACFG_HPEN_2LB_INV 0x00000008 433#define DC3_ACFG_HPEN_3LB_INV 0x00000004 434#define DC3_ACFG_HPEN_LB_FILL 0x00000002 435#define DC3_ACFG_LPEN_VSYNC 0x00000001 436 437/* DC3_FB_ST_OFFSET BIT FIELDS */ 438 439#define DC3_FB_ST_OFFSET_MASK 0x0FFFFFFF 440 441/* DC3_CB_ST_OFFSET BIT FIELDS */ 442 443#define DC3_CB_ST_OFFSET_MASK 0x0FFFFFFF 444 445/* DC3_CURS_ST_OFFSET BIT FIELDS */ 446 447#define DC3_CURS_ST_OFFSET_MASK 0x0FFFFFFF 448 449/* DC3_ICON_ST_OFFSET BIT FIELDS */ 450 451#define DC3_ICON_ST_OFFSET_MASK 0x0FFFFFFF 452 453/* DC3_VID_Y_ST_OFFSET BIT FIELDS */ 454 455#define DC3_VID_Y_ST_OFFSET_MASK 0x0FFFFFFF 456 457/* DC3_VID_U_ST_OFFSET BIT FIELDS */ 458 459#define DC3_VID_U_ST_OFFSET_MASK 0x0FFFFFFF 460 461/* DC3_VID_V_ST_OFFSET BIT FIELDS */ 462 463#define DC3_VID_V_ST_OFFSET_MASK 0x0FFFFFFF 464 465/* DC3_DV_TOP BIT FIELDS */ 466 467#define DC3_DVTOP_ENABLE 0x00000001 468#define DC3_DVTOP_MAX_MASK 0x00FFFC00 469#define DC3_DVTOP_MAX_SHIFT 10 470 471/* DC3_LINE_SIZE BIT FIELDS */ 472 473#define DC3_LINE_SIZE_VLS_MASK 0x3FF00000 474#define DC3_LINE_SIZE_CBLS_MASK 0x0007F000 475#define DC3_LINE_SIZE_FBLS_MASK 0x000003FF 476#define DC3_LINE_SIZE_CB_SHIFT 12 477#define DC3_LINE_SIZE_VB_SHIFT 20 478 479/* DC3_GFX_PITCH BIT FIELDS */ 480 481#define DC3_GFX_PITCH_CBP_MASK 0xFFFF0000 482#define DC3_GFX_PITCH_FBP_MASK 0x0000FFFF 483 484/* DC3_VID_YUV_PITCH BIT FIELDS */ 485 486#define DC3_YUV_PITCH_UVP_MASK 0xFFFF0000 487#define DC3_YUV_PITCH_YBP_MASK 0x0000FFFF 488 489/* DC3_H_ACTIVE_TIMING BIT FIELDS */ 490 491#define DC3_HAT_HT_MASK 0x0FF80000 492#define DC3_HAT_HA_MASK 0x00000FF8 493 494/* DC3_H_BLANK_TIMING BIT FIELDS */ 495 496#define DC3_HBT_HBE_MASK 0x0FF80000 497#define DC3_HBT_HBS_MASK 0x00000FF8 498 499/* DC3_H_SYNC_TIMING BIT FIELDS */ 500 501#define DC3_HST_HSE_MASK 0x0FF80000 502#define DC3_HST_HSS_MASK 0x00000FF8 503 504/* DC3_V_ACTIVE_TIMING BIT FIELDS */ 505 506#define DC3_VAT_VT_MASK 0x07FF0000 507#define DC3_VAT_VA_MASK 0x000007FF 508 509/* DC3_V_BLANK_TIMING BIT FIELDS */ 510 511#define DC3_VBT_VBE_MASK 0x07FF0000 512#define DC3_VBT_VBS_MASK 0x000007FF 513 514/* DC3_V_SYNC_TIMING BIT FIELDS */ 515 516#define DC3_VST_VSE_MASK 0x07FF0000 517#define DC3_VST_VSS_MASK 0x000007FF 518 519/* DC3_LINE_CNT_STATUS BIT FIELDS */ 520 521#define DC3_LNCNT_DNA 0x80000000 522#define DC3_LNCNT_VNA 0x40000000 523#define DC3_LNCNT_VSA 0x20000000 524#define DC3_LNCNT_VINT 0x10000000 525#define DC3_LNCNT_FLIP 0x08000000 526#define DC3_LNCNT_V_LINE_CNT 0x07FF0000 527#define DC3_LNCNT_VFLIP 0x00008000 528#define DC3_LNCNT_SIGC 0x00004000 529#define DC3_LNCNT_EVEN_FIELD 0x00002000 530#define DC3_LNCNT_SS_LINE_CMP 0x000007FF 531 532/* DC3_VID_DS_DELTA BIT FIELDS */ 533 534#define DC3_DS_DELTA_MASK 0xFFFC0000 535#define DC3_601_VSYNC_SHIFT_MASK 0x00000FFF 536#define DC3_601_VSYNC_SHIFT_ENABLE 0x00008000 537 538/* DC3_DV_CTL BIT DEFINITIONS */ 539 540#define DC3_DV_LINE_SIZE_MASK 0x00000C00 541#define DC3_DV_LINE_SIZE_1024 0x00000000 542#define DC3_DV_LINE_SIZE_2048 0x00000400 543#define DC3_DV_LINE_SIZE_4096 0x00000800 544#define DC3_DV_LINE_SIZE_8192 0x00000C00 545 546/* DC3_IRQ_FILT_CTL DEFINITIONS */ 547 548#define DC3_IRQFILT_LB_MASK 0x80000200 549#define DC3_IRQFILT_LB_COEFF 0x00000000 550#define DC3_IRQFILT_SCALER_FILTER 0x00000200 551#define DC3_IRQFILT_SYNCHRONIZER 0x80000000 552#define DC3_IRQFILT_FLICKER_FILTER 0x80000200 553#define DC3_IRQFILT_LB_SEL_MASK 0x60000000 554#define DC3_IRQFILT_INTL_ADDR 0x10000000 555#define DC3_IRQFILT_LINE_MASK 0x07FF0000 556#define DC3_IRQFILT_ALPHA_FILT_EN 0x00004000 557#define DC3_IRQFILT_GFX_FILT_EN 0x00001000 558#define DC3_IRQFILT_INTL_EN 0x00000800 559#define DC3_IRQFILT_H_FILT_SEL 0x00000400 560#define DC3_IRQFILT_LB_ADDR 0x00000100 561 562/* DC3_VBI_EVEN_CTL DEFINITIONS */ 563 564#define DC3_VBI_EVEN_ENABLE_CRC (1L << 31) 565#define DC3_VBI_EVEN_CTL_ENABLE_16 (1L << 30) 566#define DC3_VBI_EVEN_CTL_UPSCALE (1L << 29) 567#define DC3_VBI_ENABLE (1L << 28) 568#define DC3_VBI_EVEN_CTL_OFFSET_MASK 0x0FFFFFFF 569 570/* DC3_VBI_ODD_CTL DEFINITIONS */ 571 572#define DC3_VBI_ODD_CTL_OFFSET_MASK 0x0FFFFFFF 573 574/* DC3_VBI_HOR BIT DEFINITIONS */ 575 576#define DC3_VBI_HOR_END_SHIFT 16 577#define DC3_VBI_HOR_END_MASK 0x0FFF0000 578#define DC3_VBI_HOR_START_MASK 0x00000FFF 579 580/* DC3_VBI_LN_ODD BIT DEFINITIONS */ 581 582#define DC3_VBI_ODD_ENABLE_SHIFT 2 583#define DC3_VBI_ODD_ENABLE_MASK 0x01FFFFFC 584#define DC3_VBI_ODD_LINE_SHIFT 25 585#define DC3_VBI_ODD_LINE_MASK 0xFE000000 586 587/* DC3_VBI_LN_EVEN BIT DEFINITIONS */ 588 589#define DC3_VBI_EVEN_ENABLE_SHIFT 2 590#define DC3_VBI_EVEN_ENABLE_MASK 0x01FFFFFC 591#define DC3_VBI_EVEN_LINE_SHIFT 25 592#define DC3_VBI_EVEN_LINE_MASK 0xFE000000 593 594/* DC3_COLOR_KEY DEFINITIONS */ 595 596#define DC3_CLR_KEY_DATA_MASK 0x00FFFFFF 597#define DC3_CLR_KEY_ENABLE 0x01000000 598 599/* DC3_IRQ DEFINITIONS */ 600 601#define DC3_IRQ_MASK 0x00000001 602#define DC3_VSYNC_IRQ_MASK 0x00000002 603#define DC3_IRQ_STATUS 0x00010000 604#define DC3_VSYNC_IRQ_STATUS 0x00020000 605 606/* DC3_GENLK_CTL DEFINITIONS */ 607 608#define DC3_GC_FLICKER_FILTER_NONE 0x00000000 609#define DC3_GC_FLICKER_FILTER_1_16 0x10000000 610#define DC3_GC_FLICKER_FILTER_1_8 0x20000000 611#define DC3_GC_FLICKER_FILTER_1_4 0x40000000 612#define DC3_GC_FLICKER_FILTER_5_16 0x50000000 613#define DC3_GC_FLICKER_FILTER_MASK 0xF0000000 614#define DC3_GC_ALPHA_FLICK_ENABLE 0x02000000 615#define DC3_GC_FLICKER_FILTER_ENABLE 0x01000000 616#define DC3_GC_VIP_VID_OK 0x00800000 617#define DC3_GC_GENLK_ACTIVE 0x00400000 618#define DC3_GC_SKEW_WAIT 0x00200000 619#define DC3_GC_VSYNC_WAIT 0x00100000 620#define DC3_GC_GENLOCK_TO_ENABLE 0x00080000 621#define DC3_GC_GENLOCK_ENABLE 0x00040000 622#define DC3_GC_GENLOCK_SKEW_MASK 0x0003FFFF 623 624/* VGA DEFINITIONS */ 625 626#define DC3_SEQUENCER_INDEX 0x03C4 627#define DC3_SEQUENCER_DATA 0x03C5 628#define DC3_SEQUENCER_RESET 0x00 629#define DC3_SEQUENCER_CLK_MODE 0x01 630 631#define DC3_RESET_VGA_DISP_ENABLE 0x03 632#define DC3_CLK_MODE_SCREEN_OFF 0x20 633 634/* DOT CLOCK FREQUENCY STRUCTURE */ 635/* Note that m, n and p refer to the register m, n and p */ 636/* and not the m, n and p from the PLL equation. The PLL */ 637/* equation adds 1 to each value. */ 638 639typedef struct tagPLLFrequency { 640 unsigned long pll_value; 641 unsigned long frequency; 642 643} PLL_FREQUENCY; 644 645/* VG MSRS */ 646 647#define DC3_SPARE_MSR 0x2011 648#define DC3_RAM_CTL 0x2012 649 650/* DC3_SPARE_MSR DEFINITIONS */ 651 652#define DC3_SPARE_DISABLE_CFIFO_HGO 0x00000800 653#define DC3_SPARE_VFIFO_ARB_SELECT 0x00000400 654#define DC3_SPARE_WM_LPEN_OVRD 0x00000200 655#define DC3_SPARE_LOAD_WM_LPEN_MASK 0x00000100 656#define DC3_SPARE_DISABLE_INIT_VID_PRI 0x00000080 657#define DC3_SPARE_DISABLE_VFIFO_WM 0x00000040 658#define DC3_SPARE_DISABLE_CWD_CHECK 0x00000020 659#define DC3_SPARE_PIX8_PAN_FIX 0x00000010 660#define DC3_SPARE_FIRST_REQ_MASK 0x00000002 661 662/* VG DIAG DEFINITIONS */ 663 664#define DC3_MBD_DIAG_EN0 0x00008000 665#define DC3_MBD_DIAG_EN1 0x80000000 666#define DC3_DIAG_DOT_CRTC_DP 0x00000082 667#define DC3_DIAG_DOT_CRTC_DP_HIGH 0x00820000 668#define DC3_DIAG_EVEN_FIELD 0x00002000 669 670/*----------------------------------------------------------------*/ 671/* DISPLAY FILTER DEFINITIONS */ 672/*----------------------------------------------------------------*/ 673 674#define DF_VIDEO_CONFIG 0x00000000 675#define DF_DISPLAY_CONFIG 0x00000008 676#define DF_VIDEO_X_POS 0x00000010 677#define DF_VIDEO_Y_POS 0x00000018 678#define DF_VIDEO_SCALER 0x00000020 679#define DF_VIDEO_COLOR_KEY 0x00000028 680#define DF_VIDEO_COLOR_MASK 0x00000030 681#define DF_PALETTE_ADDRESS 0x00000038 682#define DF_PALETTE_DATA 0x00000040 683#define DF_SATURATION_LIMIT 0x00000048 684#define DF_VID_MISC 0x00000050 685#define DF_VIDEO_YSCALE 0x00000060 686#define DF_VIDEO_XSCALE 0x00000068 687#define DF_VID_CRC 0x00000088 688#define DF_VID_CRC32 0x00000090 689#define DF_VID_ALPHA_CONTROL 0x00000098 690#define DF_CURSOR_COLOR_KEY 0x000000A0 691#define DF_CURSOR_COLOR_MASK 0x000000A8 692#define DF_CURSOR_COLOR_1 0x000000B0 693#define DF_CURSOR_COLOR_2 0x000000B8 694#define DF_ALPHA_XPOS_1 0x000000C0 695#define DF_ALPHA_YPOS_1 0x000000C8 696#define DF_ALPHA_COLOR_1 0x000000D0 697#define DF_ALPHA_CONTROL_1 0x000000D8 698#define DF_ALPHA_XPOS_2 0x000000E0 699#define DF_ALPHA_YPOS_2 0x000000E8 700#define DF_ALPHA_COLOR_2 0x000000F0 701#define DF_ALPHA_CONTROL_2 0x000000F8 702#define DF_ALPHA_XPOS_3 0x00000100 703#define DF_ALPHA_YPOS_3 0x00000108 704#define DF_ALPHA_COLOR_3 0x00000110 705#define DF_ALPHA_CONTROL_3 0x00000118 706#define DF_VIDEO_REQUEST 0x00000120 707#define DF_ALPHA_WATCH 0x00000128 708#define DF_VIDEO_TEST_MODE 0x00000130 709#define DF_VID_YPOS_EVEN 0x00000138 710#define DF_VID_ALPHA_Y_EVEN_1 0x00000140 711#define DF_VID_ALPHA_Y_EVEN_2 0x00000148 712#define DF_VID_ALPHA_Y_EVEN_3 0x00000150 713#define DF_VIDEO_PANEL_TIM1 0x00000400 714#define DF_VIDEO_PANEL_TIM2 0x00000408 715#define DF_POWER_MANAGEMENT 0x00000410 716#define DF_DITHER_CONTROL 0x00000418 717#define DF_DITHER_ACCESS 0x00000448 718#define DF_DITHER_DATA 0x00000450 719#define DF_PANEL_CRC 0x00000458 720#define DF_PANEL_CRC32 0x00000468 721#define DF_COEFFICIENT_BASE 0x00001000 722 723/* DF_VIDEO_CONFIG BIT DEFINITIONS */ 724 725#define DF_VCFG_VID_EN 0x00000001 726#define DF_VCFG_VID_INP_FORMAT 0x0000000C 727#define DF_VCFG_SC_BYP 0x00000020 728#define DF_VCFG_LINE_SIZE_LOWER_MASK 0x0000FF00 729#define DF_VCFG_INIT_READ_MASK 0x01FF0000 730#define DF_VCFG_LINE_SIZE_BIT8 0x08000000 731#define DF_VCFG_LINE_SIZE_BIT9 0x04000000 732#define DF_VCFG_4_2_0_MODE 0x10000000 733#define DF_VCFG_UYVY_FORMAT 0x00000000 734#define DF_VCFG_Y2YU_FORMAT 0x00000004 735#define DF_VCFG_YUYV_FORMAT 0x00000008 736#define DF_VCFG_YVYU_FORMAT 0x0000000C 737 738/* DF_DISPLAY_CONFIG BIT DEFINITIONS */ 739 740#define DF_DCFG_DIS_EN 0x00000001 741#define DF_DCFG_HSYNC_EN 0x00000002 742#define DF_DCFG_VSYNC_EN 0x00000004 743#define DF_DCFG_DAC_BL_EN 0x00000008 744#define DF_DCFG_CRT_HSYNC_POL 0x00000100 745#define DF_DCFG_CRT_VSYNC_POL 0x00000200 746#define DF_DCFG_CRT_SYNC_SKW_MASK 0x0001C000 747#define DF_DCFG_CRT_SYNC_SKW_INIT 0x00010000 748#define DF_DCFG_PWR_SEQ_DLY_MASK 0x000E0000 749#define DF_DCFG_PWR_SEQ_DLY_INIT 0x00080000 750#define DF_DCFG_VG_CK 0x00100000 751#define DF_DCFG_GV_PAL_BYP 0x00200000 752#define DF_DAC_VREF 0x04000000 753 754/* DF_VID_MISC BIT DEFINITIONS */ 755 756#define DF_GAMMA_BYPASS_BOTH 0x00000001 757#define DF_DAC_POWER_DOWN 0x00000400 758#define DF_ANALOG_POWER_DOWN 0x00000800 759#define DF_USER_IMPLICIT_SCALING 0x00001000 760 761/* DF_VID_ALPHA_CONTROL DEFINITIONS */ 762 763#define DF_HD_VIDEO 0x00000040 764#define DF_YUV_CSC_EN 0x00000080 765#define DF_NO_CK_OUTSIDE_ALPHA 0x00000100 766#define DF_HD_GRAPHICS 0x00000200 767#define DF_CSC_VIDEO_YUV_TO_RGB 0x00000400 768#define DF_CSC_GRAPHICS_RGB_TO_YUV 0x00000800 769#define DF_CSC_VOP_RGB_TO_YUV 0x00001000 770#define DF_VIDEO_INPUT_IS_RGB 0x00002000 771#define DF_VID_ALPHA_EN 0x00004000 772#define DF_ALPHA_DRGB 0x00008000 773 774/* VIDEO CURSOR COLOR KEY DEFINITIONS */ 775 776#define DF_CURSOR_COLOR_KEY_ENABLE 0x20000000 777 778/* ALPHA COLOR BIT DEFINITION */ 779 780#define DF_ALPHA_COLOR_ENABLE 0x01000000 781 782/* ALPHA CONTROL BIT DEFINITIONS */ 783 784#define DF_ACTRL_WIN_ENABLE 0x00010000 785#define DF_ACTRL_LOAD_ALPHA 0x00020000 786#define DF_ACTRL_PERPIXEL_EN 0x00040000 787 788/* DF_VIDEO_SCALER DEFINITIONS */ 789 790#define DF_SCALE_128_PHASES 0x00002000 791#define DF_SCALE_DOUBLE_H_DOWNSCALE 0x00004000 792 793/* DEFAULT PANEL TIMINGS DEFINITIONS */ 794 795#define DF_DEFAULT_TFT_PMTIM1 0x00000000 796#define DF_DEFAULT_XVGA_PMTIM1 0x00000000 797#define DF_DEFAULT_TFT_PMTIM2 0x08C00000 798#define DF_DEFAULT_XVGA_PMTIM2 0x08C10000 799#define DF_DEFAULT_TFT_PAD_SEL_LOW 0xDFFFFFFF 800#define DF_DEFAULT_TFT_PAD_SEL_HIGH 0x0000003F 801#define DF_DEFAULT_XVGA_PAD_SEL_LOW 0x00000000 802#define DF_DEFAULT_XVGA_PAD_SEL_HIGH 0x00000000 803#define DF_DEFAULT_DITHCTL 0x00000070 804#define DF_DEFAULT_TV_PAD_SEL_HIGH 0x000000BF 805#define DF_DEFAULT_TV_PAD_SEL_LOW 0xDFFFFFFF 806#define DF_INVERT_VOP_CLOCK 0x00000080 807 808/* DF_VIDEO_PANEL_TIM2 DEFINITIONS */ 809 810#define DF_PMTIM2_TFT_PASSHTHROUGH 0x40000000 811 812/* DF_POWER_MANAGEMENT DEFINITIONS */ 813 814#define DF_PM_PANEL_ON 0x01000000 815#define DF_PM_INVERT_SHFCLK 0x00002000 816 817/* DISPLAY FILTER MSRS */ 818 819#define DF_MBD_MSR_DIAG_DF 0x2010 820#define DF_MSR_PAD_SEL 0x2011 821#define DF_DIAG_32BIT_CRC 0x80000000 822 823#define DF_OUTPUT_CRT 0x00000000 824#define DF_OUTPUT_PANEL 0x00000008 825#define DF_OUTPUT_VOP 0x00000030 826#define DF_OUTPUT_DRGB 0x00000038 827#define DF_SIMULTANEOUS_CRT_FP 0x00008000 828#define DF_CONFIG_OUTPUT_MASK 0x00000038 829 830/*----------------------------------------------------------------*/ 831/* MSR DEFINITIONS */ 832/*----------------------------------------------------------------*/ 833 834/*----------------------------*/ 835/* STATIC GEODELINK ADDRESSES */ 836/*----------------------------*/ 837 838#define MSR_ADDRESS_GLIU0 0x10000000 839#define MSR_ADDRESS_GLIU1 0x40000000 840#define MSR_ADDRESS_GLIU2 0x51010000 841#define MSR_ADDRESS_5535MPCI 0x51000000 842#define MSR_ADDRESS_VAIL 0x00000000 843 844/*----------------------------*/ 845/* UNIVERSAL DEVICE MSRS */ 846/*----------------------------*/ 847 848#define MSR_GEODELINK_CAP 0x2000 849#define MSR_GEODELINK_CONFIG 0x2001 850#define MSR_GEODELINK_SMI 0x2002 851#define MSR_GEODELINK_ERROR 0x2003 852#define MSR_GEODELINK_PM 0x2004 853#define MSR_GEODELINK_DIAG 0x2005 854 855/*----------------------------*/ 856/* DEVICE CLASS CODES */ 857/*----------------------------*/ 858 859#define MSR_CLASS_CODE_GLIU 0x01 860#define MSR_CLASS_CODE_GLCP 0x02 861#define MSR_CLASS_CODE_MPCI 0x05 862#define MSR_CLASS_CODE_MC 0x20 863#define MSR_CLASS_CODE_GP 0x3D 864#define MSR_CLASS_CODE_VG 0x3E 865#define MSR_CLASS_CODE_DF 0x3F 866#define MSR_CLASS_CODE_FG 0xF0 867#define MSR_CLASS_CODE_VAIL 0x86 868#define MSR_CLASS_CODE_USB 0x42 869#define MSR_CLASS_CODE_USB2 0x43 870#define MSR_CLASS_CODE_ATAC 0x47 871#define MSR_CLASS_CODE_MDD 0xDF 872#define MSR_CLASS_CODE_ACC 0x33 873#define MSR_CLASS_CODE_AES 0x30 874#define MSR_CLASS_CODE_VIP 0x3C 875#define MSR_CLASS_CODE_REFLECTIVE 0xFFF 876#define MSR_CLASS_CODE_UNPOPULATED 0x7FF 877 878/*----------------------------*/ 879/* GLIU MSR DEFINITIONS */ 880/*----------------------------*/ 881 882#define MSR_GLIU_CAP 0x0086 883#define MSR_GLIU_WHOAMI 0x008B 884 885#define NUM_PORTS_MASK 0x00380000 886#define NUM_PORTS_SHIFT 19 887#define WHOAMI_MASK 0x07 888 889/*----------------------------*/ 890/* GLCP MSR DEFINITIONS */ 891/*----------------------------*/ 892 893#define GLCP_CLKOFF 0x0010 894#define GLCP_CLKACTIVE 0x0011 895#define GLCP_CLKDISABLE 0x0012 896#define GLCP_CLK4ACK 0x0013 897#define GLCP_SYS_RSTPLL 0x0014 898#define GLCP_DOTPLL 0x0015 899#define GLCP_DBGCLKCTL 0x0016 900#define GLCP_REVID 0x0017 901#define GLCP_RAW_DIAG 0x0028 902#define GLCP_SETM0CTL 0x0040 903#define GLCP_SETN0CTL 0x0048 904#define GLCP_CMPVAL0 0x0050 905#define GLCP_CMPMASK0 0x0051 906#define GLCP_REGA 0x0058 907#define GLCP_REGB 0x0059 908#define GLCP_REGAMASK 0x005A 909#define GLCP_REGAVAL 0x005B 910#define GLCP_REGBMASK 0x005C 911#define GLCP_REGBVAL 0x005D 912#define GLCP_FIFOCTL 0x005E 913#define GLCP_DIAGCTL 0x005F 914#define GLCP_H0CTL 0x0060 915#define GLCP_XSTATE 0x0066 916#define GLCP_YSTATE 0x0067 917#define GLCP_ACTION0 0x0068 918 919/* GLCP_DOTPLL DEFINITIONS */ 920 921#define GLCP_DOTPLL_RESET 0x00000001 922#define GLCP_DOTPLL_BYPASS 0x00008000 923#define GLCP_DOTPLL_HALFPIX 0x01000000 924#define GLCP_DOTPLL_LOCK 0x02000000 925#define GLCP_DOTPLL_VIPCLK 0x00008000 926#define GLCP_DOTPLL_DIV4 0x00010000 927 928/* GLCP DIAG DEFINITIONS */ 929 930#define GLCP_MBD_DIAG_SEL0 0x00000007 931#define GLCP_MBD_DIAG_EN0 0x00008000 932#define GLCP_MBD_DIAG_SEL1 0x00070000 933#define GLCP_MBD_DIAG_EN1 0x80000000 934 935/*--------------------------------*/ 936/* DISPLAY FILTER MSR DEFINITIONS */ 937/*--------------------------------*/ 938 939/* DISPLAY FILTER MBD_MSR_DIAG DEFINITIONS */ 940 941#define DF_MBD_DIAG_SEL0 0x00007FFF 942#define DF_MBD_DIAG_EN0 0x00008000 943#define DF_MBD_DIAG_SEL1 0x7FFF0000 944#define DF_MBD_DIAG_EN1 0x80000000 945 946/* DISPLAY FILTER MBD_MSR_CONFIG DEFINITIONS */ 947 948#define DF_CONFIG_FMT_MASK 0x00000038 949#define DF_CONFIG_FMT_CRT 0x00000000 950#define DF_CONFIG_FMT_FP 0x00000008 951 952/*----------------------------------------------------------------*/ 953/* PCI DEFINITIONS */ 954/*----------------------------------------------------------------*/ 955 956#define PCI_VENDOR_DEVICE_GEODEGX 0x0028100B 957#define PCI_VENDOR_DEVICE_GEODEGX_VIDEO 0x0030100B 958#define PCI_VENDOR_DEVICE_GEODELX 0x20801022 959#define PCI_VENDOR_DEVICE_GEODELX_VIDEO 0x20811022 960#define PCI_VENDOR_5535 0x002B100B 961#define PCI_VENDOR_5536 0x20901022 962 963/*----------------------------------------------------------------*/ 964/* VIP DEFINITIONS */ 965/*----------------------------------------------------------------*/ 966 967#define VIP_CONTROL1 0x00000000 968#define VIP_CONTROL2 0x00000004 969#define VIP_STATUS 0x00000008 970#define VIP_INTERRUPT 0x0000000C 971#define VIP_CURRENT_TARGET 0x00000010 972#define VIP_MAX_ADDRESS 0x00000014 973#define VIP_TASKA_VID_EVEN_BASE 0x00000018 974#define VIP_TASKA_VID_ODD_BASE 0x0000001C 975#define VIP_TASKA_VBI_EVEN_BASE 0x00000020 976#define VIP_TASKA_VBI_ODD_BASE 0x00000024 977#define VIP_TASKA_VID_PITCH 0x00000028 978#define VIP_CONTROL3 0x0000002C 979#define VIP_TASKA_V_OFFSET 0x00000030 980#define VIP_TASKA_U_OFFSET 0x00000034 981#define VIP_TASKB_VID_EVEN_BASE 0x00000038 982#define VIP_601_HORZ_END 0x00000038 983#define VIP_TASKB_VID_ODD_BASE 0x0000003C 984#define VIP_601_HORZ_START 0x0000003C 985#define VIP_TASKB_VBI_EVEN_BASE 0x00000040 986#define VIP_601_VBI_END 0x00000040 987#define VIP_TASKB_VBI_ODD_BASE 0x00000044 988#define VIP_601_VBI_START 0x00000044 989#define VIP_TASKB_VID_PITCH 0x00000048 990#define VIP_601_EVEN_START_STOP 0x00000048 991#define VIP_TASKB_V_OFFSET 0x00000050 992#define VIP_ODD_FIELD_DETECT 0x00000050 993#define VIP_TASKB_U_OFFSET 0x00000054 994#define VIP_ANC_MSG1_BASE 0x00000058 995#define VIP_ANC_MSG2_BASE 0x0000005C 996#define VIP_ANC_MSG_SIZE 0x00000060 997#define VIP_PAGE_OFFSET 0x00000068 998#define VIP_VERTICAL_START_STOP 0x0000006C 999#define VIP_601_ODD_START_STOP 0x0000006C 1000#define VIP_FIFO_ADDRESS 0x00000070 1001#define VIP_FIFO_DATA 0x00000074 1002#define VIP_VSYNC_ERR_COUNT 0x00000078 1003#define VIP_TASKA_U_EVEN_OFFSET 0x0000007C 1004#define VIP_TASKA_V_EVEN_OFFSET 0x00000080 1005 1006/* INDIVIDUAL REGISTER BIT DEFINITIONS */ 1007/* Multibit register subsets are expressed as a mask and shift. */ 1008/* Single bit values are represented as a mask. */ 1009 1010/* VIP_CONTROL1 REGISTER DEFINITIONS */ 1011 1012#define VIP_CONTROL1_DEFAULT_ANC_FF 2 1013#define VIP_CONTROL1_ANC_FF_MASK 0xE0000000 1014#define VIP_CONTROL1_ANC_FF_SHIFT 29 1015 1016#define VIP_CONTROL1_DEFAULT_VID_FF 2 1017#define VIP_CONTROL1_VID_FF_MASK 0x1F000000 1018#define VIP_CONTROL1_VID_FF_SHIFT 24 1019 1020#define VIP_CONTROL1_VDE_FF_MASK 0x00F00000 1021#define VIP_CONTROL1_VDE_FF_SHIFT 20 1022 1023#define VIP_CONTROL1_NON_INTERLACED (1L << 19) 1024#define VIP_CONTROL1_MSG_STRM_CTRL (1L << 18) 1025#define VIP_CONTROL1_DISABLE_ZERO_DETECT (1L << 17) 1026#define VIP_CONTROL1_DISABLE_DECIMATION (1L << 16) 1027 1028#define VIP_CONTROL1_CAPTURE_ENABLE_MASK 0x0000FF00 1029#define VIP_CONTROL1_CAPTURE_ENABLE_SHIFT 8 1030 1031#define VIP_CONTROL1_RUNMODE_MASK 0x000000E0 1032#define VIP_CONTROL1_RUNMODE_SHIFT 5 1033 1034#define VIP_CONTROL1_PLANAR (1L << 4) 1035 1036#define VIP_CONTROL1_MODE_MASK 0x0000000E 1037#define VIP_CONTROL1_MODE_SHIFT 1 1038 1039#define VIP_CONTROL1_RESET 0x00000001 1040 1041/* VIP_CONTROL2 REGISTER DEFINITIONS */ 1042 1043#define VIP_CONTROL2_INVERT_POLARITY (1L << 31) 1044#define VIP_CONTROL2_ADD_ERROR_ENABLE (1L << 30) 1045#define VIP_CONTROL2_REPEAT_ENABLE (1L << 29) 1046#define VIP_CONTROL2_SWC_ENABLE (1L << 28) 1047#define VIP_CONTROL2_ANC10 (1L << 27) 1048#define VIP_CONTROL2_ANCPEN (1L << 26) 1049#define VIP_CONTROL2_LOOPBACK_ENABLE (1L << 25) 1050#define VIP_CONTROL2_FIFO_ACCESS (1L << 24) 1051#define VIP_CONTROL2_VERTERROR_ENABLE (1L << 15) 1052 1053#define VIP_CONTROL2_PAGECNT_MASK 0x00E00000 1054#define VIP_CONTROL2_PAGECNT_SHIFT 21 1055 1056#define VIP_CONTROL2_DEFAULT_ANCTH 5 1057#define VIP_CONTROL2_ANCTH_MASK 0x001F0000 1058#define VIP_CONTROL2_ANCTH_SHIFT 16 1059 1060#define VIP_CONTROL2_DEFAULT_VIDTH_420 19 1061#define VIP_CONTROL2_DEFAULT_VIDTH_422 19 1062#define VIP_CONTROL2_VIDTH_MASK 0x00007F00 1063#define VIP_CONTROL2_VIDTH_SHIFT 8 1064 1065#define VIP_CONTROL2_SYNC2PIN_MASK 0x000000E0 1066#define VIP_CONTROL2_SYNC2PIN_SHIFT 5 1067 1068#define VIP_CONTROL2_FIELD2VG_MASK 0x00000018 1069#define VIP_CONTROL2_FIELD2VG_SHIFT 3 1070 1071#define VIP_CONTROL2_SYNC2VG_MASK 0x00000007 1072#define VIP_CONTROL2_SYNC2VG_SHIFT 0 1073 1074/* VIP_CONTROL3 REGISTER DEFINITIONS */ 1075 1076#define VIP_CONTROL3_PLANAR_DEINT 0x00000400 1077#define VIP_CONTROL3_BASE_UPDATE 0x00000200 1078#define VIP_CONTROL3_DISABLE_OVERFLOW 0x00000100 1079#define VIP_CONTROL3_DECIMATE_EVEN 0x00000080 1080#define VIP_CONTROL3_TASK_POLARITY 0x00000040 1081#define VIP_CONTROL3_VSYNC_POLARITY 0x00000020 1082#define VIP_CONTROL3_HSYNC_POLARITY 0x00000010 1083#define VIP_CONTROL3_FIFO_RESET 0x00000001 1084 1085/* VIP_STATUS REGISTER DEFINITIONS */ 1086 1087#define VIP_STATUS_ANC_COUNT_MASK 0xFF000000 1088#define VIP_STATUS_ANC_COUNT_SHIFT 24 1089 1090#define VIP_STATUS_FIFO_ERROR 0x00700000 1091#define VIP_STATUS_ERROR_SHIFT 20 1092#define VIP_STATUS_DEC_COUNT (1L << 18) 1093#define VIP_STATUS_SYNCOUT (1L << 17) 1094#define VIP_STATUS_BASEREG_NOTUPDT (1L << 16) 1095#define VIP_STATUS_MSGBUFF_ERR (1L << 14) 1096#define VIP_STATUS_MSGBUFF2_FULL (1L << 13) 1097#define VIP_STATUS_MSGBUFF1_FULL (1L << 12) 1098#define VIP_STATUS_WRITES_COMPLETE (1L << 9) 1099#define VIP_STATUS_FIFO_EMPTY (1L << 8) 1100#define VIP_STATUS_FIELD (1L << 4) 1101#define VIP_STATUS_VBLANK (1L << 3) 1102 1103#define VIP_STATUS_RUN_MASK 0x00000007 1104#define VIP_STATUS_RUN_SHIFT 0 1105 1106/* VIP_CURRENT_TARGET REGISTER DEFINITIONS */ 1107 1108#define VIP_CTARGET_TLINE_MASK 0xFFFF0000 1109#define VIP_CTARGET_TLINE_SHIFT 16 1110 1111#define VIP_CTARGET_CLINE_MASK 0x0000FFFF 1112#define VIP_CTARGET_CLINE_SHIFT 0 1113 1114/* VIP_MAX_ADDRESS REGISTER DEFINITIONS */ 1115 1116#define VIP_MAXADDR_MASK 0xFFFFFFFF 1117#define VIP_MAXADDR_SHIFT 0 1118 1119/* VIP BUFFER PITCH DEFINITIONS */ 1120 1121#define VIP_TASK_PITCH_MASK 0x0000FFFF 1122#define VIP_TASK_PITCH_SHIFT 0 1123 1124/* VERTICAL START/STOP */ 1125 1126#define VIP_VSTART_VERTEND_MASK 0x0FFF0000 1127#define VIP_VSTART_VERTEND_SHIFT 16 1128 1129#define VIP_VSTART_VERTSTART_MASK 0x00000FFF 1130#define VIP_VSTART_VERTSTART_SHIFT 0 1131 1132/* VIP FIFO ADDRESS DEFINITIONS */ 1133 1134#define VIP_FIFO_ADDRESS_MASK 0x000000FF 1135#define VIP_FIFO_ADDRESS_SHIFT 0 1136 1137/* VIP VSYNC ERROR DEFINITIONS */ 1138 1139#define VIP_VSYNC_ERR_WINDOW_MASK 0xFF000000 1140#define VIP_VSYNC_ERR_WINDOW_SHIFT 24 1141 1142#define VIP_VSYNC_ERR_COUNT_MASK 0x00FFFFFF 1143#define VIP_VSYNC_ERR_COUNT_SHIFT 0 1144 1145/*---------------------*/ 1146/* VIP MSR DEFINITIONS */ 1147/*---------------------*/ 1148 1149/* CAPABILITIES */ 1150 1151#define VIP_MSR_CAP_NSMI_MASK 0xF8000000 1152#define VIP_MSR_CAP_NSMI_SHIFT 27 1153#define VIP_MSR_CAP_NCLK_MASK 0x07000000 1154#define VIP_MSR_CAP_NCLK_SHIFT 24 1155#define VIP_MSR_CAP_DEVID_MASK 0x00FFFF00 1156#define VIP_MSR_CAP_DEVID_SHIFT 8 1157#define VIP_MSR_CAP_REVID_MASK 0x000000FF 1158#define VIP_MSR_CAP_REVID_SHIFT 0 1159 1160/* MASTER CONFIG */ 1161 1162#define VIP_MSR_MCR_SECOND_PRIORITY_MASK 0x00000700 1163#define VIP_MSR_MCR_SECOND_PRIORITY_SHIFT 8 1164#define VIP_MSR_MCR_PRIMARY_PRIORITY_MASK 0x00000070 1165#define VIP_MSR_MCR_PRIMARY_PRIORITY_SHIFT 4 1166#define VIP_MSR_MCR_PID_MASK 0x00000007 1167#define VIP_MSR_MCR_PID_SHIFT 0 1168 1169/* VIP SMI */ 1170 1171#define VIP_MSR_SMI_FIFO_OVERFLOW (1L << 29) 1172#define VIP_MSR_SMI_FIFO_THRESHOLD (1L << 28) 1173#define VIP_MSR_SMI_LONGLINE (1L << 27) 1174#define VIP_MSR_SMI_VERTICAL_TIMING (1L << 26) 1175#define VIP_MSR_SMI_ACTIVE_PIXELS (1L << 25) 1176#define VIP_MSR_SMI_CLOCK_INPUT (1L << 24) 1177#define VIP_MSR_SMI_ANC_CHECKSUM_PARITY (1L << 23) 1178#define VIP_MSR_SMI_MSG_BUFFER_FULL (1L << 22) 1179#define VIP_MSR_SMI_END_VBLANK (1L << 21) 1180#define VIP_MSR_SMI_START_VBLANK (1L << 20) 1181#define VIP_MSR_SMI_START_EVEN (1L << 19) 1182#define VIP_MSR_SMI_START_ODD (1L << 18) 1183#define VIP_MSR_SMI_LINE_MATCH_TARGET (1L << 17) 1184#define VIP_MSR_SMI_GLINK (1L << 16) 1185 1186/* VIP ERROR */ 1187 1188#define VIP_MSR_ERROR_ADDRESS_MASK (1L << 17) 1189#define VIP_MSR_ERROR_ADDRESS_SHIFT 17 1190#define VIP_MSR_ERROR_ADDRESS_ENABLE (1L << 1) 1191#define VIP_MSR_ERROR_ADDRESS_EN_SHIFT 1 1192#define VIP_MSR_ERROR_TYPE_MASK (1L << 16) 1193#define VIP_MSR_ERROR_TYPE_SHIFT 16 1194#define VIP_MSR_ERROR_TYPE_ENABLE 1 1195#define VIP_MSR_ERROR_TYPE_EN_SHIFT 0 1196 1197/* VIP POWER */ 1198 1199#define VIP_MSR_POWER_GLINK (1L << 0) 1200#define VIP_MSR_POWER_CLOCK (1L << 2) 1201 1202/* VIP DIAG */ 1203 1204#define VIP_MSR_DIAG_BIST_WMASK 0x00000003 1205#define VIP_MSR_DIAG_BIST_RMASK 0x00000007 1206#define VIP_MSR_DIAG_BIST_SHIFT 0 1207 1208#define VIP_MSR_DIAG_MSB_ENABLE (1L << 31) 1209#define VIP_MSR_DIAG_SEL_UPPER_MASK 0x7FFF0000 1210#define VIP_MSR_DIAG_SEL_UPPER_SHIFT 16 1211#define VIP_MSR_DIAG_LSB_ENABLE (1L << 15) 1212#define VIP_MSR_DIAG_SEL_LOWER_MASK 0x00007FFF 1213#define VIP_MSR_DIAG_SEL_LOWER_SHIFT 0 1214 1215/*----------------------------------------------------------------*/ 1216/* VOP DEFINITIONS */ 1217/*----------------------------------------------------------------*/ 1218 1219#define VOP_CONFIGURATION 0x00000800 1220#define VOP_SIGNATURE 0x00000808 1221 1222/* VOP_CONFIGURATION BIT DEFINITIONS */ 1223 1224#define VOP_CONFIG_SWAPVBI 0x01000000 1225#define VOP_CONFIG_RGBMODE 0x00200000 1226#define VOP_CONFIG_SIGVAL 0x00100000 1227#define VOP_CONFIG_INVERT_DISPE 0x00080000 1228#define VOP_CONFIG_INVERT_VSYNC 0x00040000 1229#define VOP_CONFIG_INVERT_HSYNC 0x00020000 1230#define VOP_CONFIG_SWAPUV 0x00010000 1231#define VOP_CONFIG_VSYNC_MASK 0x0000C000 1232#define VOP_CONFIG_DISABLE_DECIMATE 0x00002000 1233#define VOP_CONFIG_ENABLE_601 0x00001000 1234#define VOP_CONFIG_VBI 0x00000800 1235#define VOP_CONFIG_TASK 0x00000200 1236#define VOP_CONFIG_SIG_FREE_RUN 0x00000100 1237#define VOP_CONFIG_ENABLE_SIGNATURE 0x00000080 1238#define VOP_CONFIG_SC_COMPATIBLE 0x00000040 1239#define VOP_CONFIG_422_COSITED 0x00000000 1240#define VOP_CONFIG_422_INTERSPERSED 0x00000010 1241#define VOP_CONFIG_422_ALTERNATING 0x00000020 1242#define VOP_CONFIG_422_MASK 0x00000030 1243#define VOP_CONFIG_EXTENDED_SAV 0x00000008 1244#define VOP_CONFIG_VIP2_16BIT 0x00000004 1245#define VOP_CONFIG_DISABLED 0x00000000 1246#define VOP_CONFIG_VIP1_1 0x00000001 1247#define VOP_CONFIG_VIP2_0 0x00000002 1248#define VOP_CONFIG_CCIR656 0x00000003 1249#define VOP_CONFIG_MODE_MASK 0x00000003 1250 1251#endif 1252