1/* Copyright (c) 2005 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a copy 4 * of this software and associated documentation files (the "Software"), to 5 * deal in the Software without restriction, including without limitation the 6 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 7 * sell copies of the Software, and to permit persons to whom the Software is 8 * furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 18 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 19 * IN THE SOFTWARE. 20 * 21 * Neither the name of the Advanced Micro Devices, Inc. nor the names of its 22 * contributors may be used to endorse or promote products derived from this 23 * software without specific prior written permission. 24 * */ 25 26/* 27 * This header file contains the graphics register definitions. 28 * */ 29 30/*----------------------------------*/ 31/* FIRST GENERATION GRAPHICS UNIT */ 32/*----------------------------------*/ 33 34#define GP_DST_XCOOR 0x8100 /* x destination origin */ 35#define GP_DST_YCOOR 0x8102 /* y destination origin */ 36#define GP_WIDTH 0x8104 /* pixel width */ 37#define GP_HEIGHT 0x8106 /* pixel height */ 38#define GP_SRC_XCOOR 0x8108 /* x source origin */ 39#define GP_SRC_YCOOR 0x810A /* y source origin */ 40 41#define GP_VECTOR_LENGTH 0x8104 /* vector length */ 42#define GP_INIT_ERROR 0x8106 /* vector initial error */ 43#define GP_AXIAL_ERROR 0x8108 /* axial error increment */ 44#define GP_DIAG_ERROR 0x810A /* diagonal error increment */ 45 46#define GP_SRC_COLOR_0 0x810C /* source color 0 */ 47#define GP_SRC_COLOR_1 0x810E /* source color 1 */ 48#define GP_PAT_COLOR_0 0x8110 /* pattern color 0 */ 49#define GP_PAT_COLOR_1 0x8112 /* pattern color 1 */ 50#define GP_PAT_COLOR_2 0x8114 /* pattern color 2 */ 51#define GP_PAT_COLOR_3 0x8116 /* pattern color 3 */ 52#define GP_PAT_DATA_0 0x8120 /* bits 31:0 of pattern */ 53#define GP_PAT_DATA_1 0x8124 /* bits 63:32 of pattern */ 54#define GP_PAT_DATA_2 0x8128 /* bits 95:64 of pattern */ 55#define GP_PAT_DATA_3 0x812C /* bits 127:96 of pattern */ 56 57#define GP_VGA_WRITE 0x8140 /* VGA write path control */ 58#define GP_VGA_READ 0x8144 /* VGA read path control */ 59 60#define GP_RASTER_MODE 0x8200 /* raster operation */ 61#define GP_VECTOR_MODE 0x8204 /* vector mode register */ 62#define GP_BLIT_MODE 0x8208 /* blit mode register */ 63#define GP_BLIT_STATUS 0x820C /* blit status register */ 64 65#define GP_VGA_BASE 0x8210 /* VGA memory offset (x64K) */ 66#define GP_VGA_LATCH 0x8214 /* VGA display latch */ 67 68/* "GP_VECTOR_MODE" BIT DEFINITIONS */ 69 70#define VM_X_MAJOR 0x0000 /* X major vector */ 71#define VM_Y_MAJOR 0x0001 /* Y major vector */ 72#define VM_MAJOR_INC 0x0002 /* positive major axis step */ 73#define VM_MINOR_INC 0x0004 /* positive minor axis step */ 74#define VM_READ_DST_FB 0x0008 /* read destination data */ 75 76/* "GP_RASTER_MODE" BIT DEFINITIONS */ 77 78#define RM_PAT_DISABLE 0x0000 /* pattern is disabled */ 79#define RM_PAT_MONO 0x0100 /* 1BPP pattern expansion */ 80#define RM_PAT_DITHER 0x0200 /* 2BPP pattern expansion */ 81#define RM_PAT_COLOR 0x0300 /* 8BPP or 16BPP pattern */ 82#define RM_PAT_MASK 0x0300 /* mask for pattern mode */ 83#define RM_PAT_TRANSPARENT 0x0400 /* transparent 1BPP pattern */ 84#define RM_SRC_TRANSPARENT 0x0800 /* transparent 1BPP source */ 85 86/* "GP_BLIT_STATUS" BIT DEFINITIONS */ 87 88#define BS_BLIT_BUSY 0x0001 /* blit engine is busy */ 89#define BS_PIPELINE_BUSY 0x0002 /* graphics pipeline is busy */ 90#define BS_BLIT_PENDING 0x0004 /* blit pending */ 91#define BC_FLUSH 0x0080 /* flush pipeline requests */ 92#define BC_8BPP 0x0000 /* 8BPP mode */ 93#define BC_16BPP 0x0100 /* 16BPP mode */ 94#define BC_FB_WIDTH_1024 0x0000 /* framebuffer width = 1024 */ 95#define BC_FB_WIDTH_2048 0x0200 /* framebuffer width = 2048 */ 96#define BC_FB_WIDTH_4096 0x0400 /* framebuffer width = 4096 */ 97 98/* "GP_BLIT_MODE" BIT DEFINITIONS */ 99 100#define BM_READ_SRC_NONE 0x0000 /* source foreground color */ 101#define BM_READ_SRC_FB 0x0001 /* read source from FB */ 102#define BM_READ_SRC_BB0 0x0002 /* read source from BB0 */ 103#define BM_READ_SRC_BB1 0x0003 /* read source from BB1 */ 104#define BM_READ_SRC_MASK 0x0003 /* read source mask */ 105 106#define BM_READ_DST_NONE 0x0000 /* no destination data */ 107#define BM_READ_DST_BB0 0x0008 /* destination from BB0 */ 108#define BM_READ_DST_BB1 0x000C /* destination from BB1 */ 109#define BM_READ_DST_FB0 0x0010 /* dest from FB (store BB0) */ 110#define BM_READ_DST_FB1 0x0014 /* dest from FB (store BB1) */ 111#define BM_READ_DST_MASK 0x001C /* read destination mask */ 112 113#define BM_WRITE_FB 0x0000 /* write to framebuffer */ 114#define BM_WRITE_MEM 0x0020 /* write to memory */ 115#define BM_WRITE_MASK 0x0020 /* write mask */ 116 117#define BM_SOURCE_COLOR 0x0000 /* source is 8BPP or 16BPP */ 118#define BM_SOURCE_EXPAND 0x0040 /* source is 1BPP */ 119#define BM_SOURCE_TEXT 0x00C0 /* source is 1BPP text */ 120#define BM_SOURCE_MASK 0x00C0 /* source mask */ 121 122#define BM_REVERSE_Y 0x0100 /* reverse Y direction */ 123 124/*---------------------------------------*/ 125/* FIRST GENERATION DISPLAY CONTROLLER */ 126/*---------------------------------------*/ 127 128#define DC_UNLOCK 0x8300 /* lock register */ 129#define DC_GENERAL_CFG 0x8304 /* config registers... */ 130#define DC_TIMING_CFG 0x8308 131#define DC_OUTPUT_CFG 0x830C 132 133#define DC_FB_ST_OFFSET 0x8310 /* framebuffer start offset */ 134#define DC_CB_ST_OFFSET 0x8314 /* compression start offset */ 135#define DC_CURS_ST_OFFSET 0x8318 /* cursor start offset */ 136#define DC_ICON_ST_OFFSET 0x831C /* icon start offset */ 137#define DC_VID_ST_OFFSET 0x8320 /* video start offset */ 138#define DC_LINE_DELTA 0x8324 /* fb and cb skip counts */ 139#define DC_BUF_SIZE 0x8328 /* fb and cb line size */ 140 141#define DC_H_TIMING_1 0x8330 /* horizontal timing... */ 142#define DC_H_TIMING_2 0x8334 143#define DC_H_TIMING_3 0x8338 144#define DC_FP_H_TIMING 0x833C 145 146#define DC_V_TIMING_1 0x8340 /* vertical timing... */ 147#define DC_V_TIMING_2 0x8344 148#define DC_V_TIMING_3 0x8348 149#define DC_FP_V_TIMING 0x834C 150 151#define DC_CURSOR_X 0x8350 /* cursor x position */ 152#define DC_ICON_X 0x8354 /* HACK - 1.3 definition */ 153#define DC_V_LINE_CNT 0x8354 /* vertical line counter */ 154#define DC_CURSOR_Y 0x8358 /* cursor y position */ 155#define DC_ICON_Y 0x835C /* HACK - 1.3 definition */ 156#define DC_SS_LINE_CMP 0x835C /* line compare value */ 157#define DC_CURSOR_COLOR 0x8360 /* cursor colors */ 158#define DC_ICON_COLOR 0x8364 /* icon colors */ 159#define DC_BORDER_COLOR 0x8368 /* border color */ 160#define DC_PAL_ADDRESS 0x8370 /* palette address */ 161#define DC_PAL_DATA 0x8374 /* palette data */ 162#define DC_DFIFO_DIAG 0x8378 /* display FIFO diagnostic */ 163#define DC_CFIFO_DIAG 0x837C /* compression FIF0 diagnostic */ 164 165/* PALETTE LOCATIONS */ 166 167#define PAL_CURSOR_COLOR_0 0x100 168#define PAL_CURSOR_COLOR_1 0x101 169#define PAL_ICON_COLOR_0 0x102 170#define PAL_ICON_COLOR_1 0x103 171#define PAL_OVERSCAN_COLOR 0x104 172 173/* UNLOCK VALUE */ 174 175#define DC_UNLOCK_VALUE 0x00004758 /* used to unlock DC regs */ 176 177/* "DC_GENERAL_CFG" BIT DEFINITIONS */ 178 179#define DC_GCFG_DFLE 0x00000001 /* display FIFO load enable */ 180#define DC_GCFG_CURE 0x00000002 /* cursor enable */ 181#define DC_GCFG_VCLK_DIV 0x00000004 /* vid clock divisor */ 182#define DC_GCFG_PLNO 0x00000004 /* planar offset LSB */ 183#define DC_GCFG_PPC 0x00000008 /* pixel pan compatibility */ 184#define DC_GCFG_CMPE 0x00000010 /* compression enable */ 185#define DC_GCFG_DECE 0x00000020 /* decompression enable */ 186#define DC_GCFG_DCLK_MASK 0x000000C0 /* dotclock multiplier */ 187#define DC_GCFG_DCLK_POS 6 /* dotclock multiplier */ 188#define DC_GCFG_DFHPSL_MASK 0x00000F00 /* FIFO high-priority start */ 189#define DC_GCFG_DFHPSL_POS 8 /* FIFO high-priority start */ 190#define DC_GCFG_DFHPEL_MASK 0x0000F000 /* FIFO high-priority end */ 191#define DC_GCFG_DFHPEL_POS 12 /* FIFO high-priority end */ 192#define DC_GCFG_CIM_MASK 0x00030000 /* compressor insert mode */ 193#define DC_GCFG_CIM_POS 16 /* compressor insert mode */ 194#define DC_GCFG_FDTY 0x00040000 /* frame dirty mode */ 195#define DC_GCFG_RTPM 0x00080000 /* real-time perf. monitor */ 196#define DC_GCFG_DAC_RS_MASK 0x00700000 /* DAC register selects */ 197#define DC_GCFG_DAC_RS_POS 20 /* DAC register selects */ 198#define DC_GCFG_CKWR 0x00800000 /* clock write */ 199#define DC_GCFG_LDBL 0x01000000 /* line double */ 200#define DC_GCFG_DIAG 0x02000000 /* FIFO diagnostic mode */ 201#define DC_GCFG_CH4S 0x04000000 /* sparse refresh mode */ 202#define DC_GCFG_SSLC 0x08000000 /* enable line compare */ 203#define DC_GCFG_VIDE 0x10000000 /* video enable */ 204#define DC_GCFG_DFCK 0x20000000 /* divide flat-panel clock */ 205 /* - rev 2.3 down */ 206#define DC_GCFG_VRDY 0x20000000 /* video port speed */ 207 /* - rev 2.4 up */ 208#define DC_GCFG_DPCK 0x40000000 /* divide pixel clock */ 209#define DC_GCFG_DDCK 0x80000000 /* divide dot clock */ 210 211/* "DC_TIMING_CFG" BIT DEFINITIONS */ 212 213#define DC_TCFG_FPPE 0x00000001 /* flat-panel power enable */ 214#define DC_TCFG_HSYE 0x00000002 /* horizontal sync enable */ 215#define DC_TCFG_VSYE 0x00000004 /* vertical sync enable */ 216#define DC_TCFG_BLKE 0x00000008 /* blank enable */ 217#define DC_TCFG_DDCK 0x00000010 /* DDC clock */ 218#define DC_TCFG_TGEN 0x00000020 /* timing generator enable */ 219#define DC_TCFG_VIEN 0x00000040 /* vertical interrupt enable */ 220#define DC_TCFG_BLNK 0x00000080 /* blink enable */ 221#define DC_TCFG_CHSP 0x00000100 /* horizontal sync polarity */ 222#define DC_TCFG_CVSP 0x00000200 /* vertical sync polarity */ 223#define DC_TCFG_FHSP 0x00000400 /* panel horz sync polarity */ 224#define DC_TCFG_FVSP 0x00000800 /* panel vert sync polarity */ 225#define DC_TCFG_FCEN 0x00001000 /* flat-panel centering */ 226#define DC_TCFG_CDCE 0x00002000 /* HACK - 1.3 definition */ 227#define DC_TCFG_PLNR 0x00002000 /* planar mode enable */ 228#define DC_TCFG_INTL 0x00004000 /* interlace scan */ 229#define DC_TCFG_PXDB 0x00008000 /* pixel double */ 230#define DC_TCFG_BKRT 0x00010000 /* blink rate */ 231#define DC_TCFG_PSD_MASK 0x000E0000 /* power sequence delay */ 232#define DC_TCFG_PSD_POS 17 /* power sequence delay */ 233#define DC_TCFG_DDCI 0x08000000 /* DDC input (RO) */ 234#define DC_TCFG_SENS 0x10000000 /* monitor sense (RO) */ 235#define DC_TCFG_DNA 0x20000000 /* display not active (RO) */ 236#define DC_TCFG_VNA 0x40000000 /* vertical not active (RO) */ 237#define DC_TCFG_VINT 0x80000000 /* vertical interrupt (RO) */ 238 239/* "DC_OUTPUT_CFG" BIT DEFINITIONS */ 240 241#define DC_OCFG_8BPP 0x00000001 /* 8/16 bpp select */ 242#define DC_OCFG_555 0x00000002 /* 16 bpp format */ 243#define DC_OCFG_PCKE 0x00000004 /* PCLK enable */ 244#define DC_OCFG_FRME 0x00000008 /* frame rate mod enable */ 245#define DC_OCFG_DITE 0x00000010 /* dither enable */ 246#define DC_OCFG_2PXE 0x00000020 /* 2 pixel enable */ 247#define DC_OCFG_2XCK 0x00000040 /* 2 x pixel clock */ 248#define DC_OCFG_2IND 0x00000080 /* 2 index enable */ 249#define DC_OCFG_34ADD 0x00000100 /* 3- or 4-bit add */ 250#define DC_OCFG_FRMS 0x00000200 /* frame rate mod select */ 251#define DC_OCFG_CKSL 0x00000400 /* clock select */ 252#define DC_OCFG_PRMP 0x00000800 /* palette re-map */ 253#define DC_OCFG_PDEL 0x00001000 /* panel data enable low */ 254#define DC_OCFG_PDEH 0x00002000 /* panel data enable high */ 255#define DC_OCFG_CFRW 0x00004000 /* comp line buffer r/w sel */ 256#define DC_OCFG_DIAG 0x00008000 /* comp line buffer diag */ 257 258#define MC_MEM_CNTRL1 0x00008400 259#define MC_DR_ADD 0x00008418 260#define MC_DR_ACC 0x0000841C 261 262/* MC_MEM_CNTRL1 BIT DEFINITIONS */ 263 264#define MC_XBUSARB 0x00000008 /* 0 = GP priority < CPU priority */ 265 /* 1 = GP priority = CPU priority */ 266 /* GXm databook V2.0 is wrong ! */ 267/*----------*/ 268/* CS5530 */ 269/*----------*/ 270 271/* CS5530 REGISTER DEFINITIONS */ 272 273#define CS5530_VIDEO_CONFIG 0x0000 274#define CS5530_DISPLAY_CONFIG 0x0004 275#define CS5530_VIDEO_X_POS 0x0008 276#define CS5530_VIDEO_Y_POS 0x000C 277#define CS5530_VIDEO_SCALE 0x0010 278#define CS5530_VIDEO_COLOR_KEY 0x0014 279#define CS5530_VIDEO_COLOR_MASK 0x0018 280#define CS5530_PALETTE_ADDRESS 0x001C 281#define CS5530_PALETTE_DATA 0x0020 282#define CS5530_DOT_CLK_CONFIG 0x0024 283#define CS5530_CRCSIG_TFT_TV 0x0028 284 285/* "CS5530_VIDEO_CONFIG" BIT DEFINITIONS */ 286 287#define CS5530_VCFG_VID_EN 0x00000001 288#define CS5530_VCFG_VID_REG_UPDATE 0x00000002 289#define CS5530_VCFG_VID_INP_FORMAT 0x0000000C 290#define CS5530_VCFG_8_BIT_4_2_0 0x00000004 291#define CS5530_VCFG_16_BIT_4_2_0 0x00000008 292#define CS5530_VCFG_GV_SEL 0x00000010 293#define CS5530_VCFG_CSC_BYPASS 0x00000020 294#define CS5530_VCFG_X_FILTER_EN 0x00000040 295#define CS5530_VCFG_Y_FILTER_EN 0x00000080 296#define CS5530_VCFG_LINE_SIZE_LOWER_MASK 0x0000FF00 297#define CS5530_VCFG_INIT_READ_MASK 0x01FF0000 298#define CS5530_VCFG_EARLY_VID_RDY 0x02000000 299#define CS5530_VCFG_LINE_SIZE_UPPER 0x08000000 300#define CS5530_VCFG_4_2_0_MODE 0x10000000 301#define CS5530_VCFG_16_BIT_EN 0x20000000 302#define CS5530_VCFG_HIGH_SPD_INT 0x40000000 303 304/* "CS5530_DISPLAY_CONFIG" BIT DEFINITIONS */ 305 306#define CS5530_DCFG_DIS_EN 0x00000001 307#define CS5530_DCFG_HSYNC_EN 0x00000002 308#define CS5530_DCFG_VSYNC_EN 0x00000004 309#define CS5530_DCFG_DAC_BL_EN 0x00000008 310#define CS5530_DCFG_DAC_PWDNX 0x00000020 311#define CS5530_DCFG_FP_PWR_EN 0x00000040 312#define CS5530_DCFG_FP_DATA_EN 0x00000080 313#define CS5530_DCFG_CRT_HSYNC_POL 0x00000100 314#define CS5530_DCFG_CRT_VSYNC_POL 0x00000200 315#define CS5530_DCFG_FP_HSYNC_POL 0x00000400 316#define CS5530_DCFG_FP_VSYNC_POL 0x00000800 317#define CS5530_DCFG_XGA_FP 0x00001000 318#define CS5530_DCFG_FP_DITH_EN 0x00002000 319#define CS5530_DCFG_CRT_SYNC_SKW_MASK 0x0001C000 320#define CS5530_DCFG_CRT_SYNC_SKW_INIT 0x00010000 321#define CS5530_DCFG_PWR_SEQ_DLY_MASK 0x000E0000 322#define CS5530_DCFG_PWR_SEQ_DLY_INIT 0x00080000 323#define CS5530_DCFG_VG_CK 0x00100000 324#define CS5530_DCFG_GV_PAL_BYP 0x00200000 325#define CS5530_DCFG_DDC_SCL 0x00400000 326#define CS5530_DCFG_DDC_SDA 0x00800000 327#define CS5530_DCFG_DDC_OE 0x01000000 328#define CS5530_DCFG_16_BIT_EN 0x02000000 329 330/*----------*/ 331/* SC1200 */ 332/*----------*/ 333 334/* SC1200 VIDEO REGISTER DEFINITIONS */ 335 336#define SC1200_VIDEO_CONFIG 0x000 337#define SC1200_DISPLAY_CONFIG 0x004 338#define SC1200_VIDEO_X_POS 0x008 339#define SC1200_VIDEO_Y_POS 0x00C 340#define SC1200_VIDEO_UPSCALE 0x010 341#define SC1200_VIDEO_COLOR_KEY 0x014 342#define SC1200_VIDEO_COLOR_MASK 0x018 343#define SC1200_PALETTE_ADDRESS 0x01C 344#define SC1200_PALETTE_DATA 0x020 345#define SC1200_VID_MISC 0x028 346#define SC1200_VID_CLOCK_SELECT 0x02C 347#define SC1200_VIDEO_DOWNSCALER_CONTROL 0x03C 348#define SC1200_VIDEO_DOWNSCALER_COEFFICIENTS 0x40 349#define SC1200_VID_CRC 0x044 350#define SC1200_DEVICE_ID 0x048 351#define SC1200_VID_ALPHA_CONTROL 0x04C 352#define SC1200_CURSOR_COLOR_KEY 0x050 353#define SC1200_CURSOR_COLOR_MASK 0x054 354#define SC1200_CURSOR_COLOR_1 0x058 355#define SC1200_CURSOR_COLOR_2 0x05C 356#define SC1200_ALPHA_XPOS_1 0x060 357#define SC1200_ALPHA_YPOS_1 0x064 358#define SC1200_ALPHA_COLOR_1 0x068 359#define SC1200_ALPHA_CONTROL_1 0x06C 360#define SC1200_ALPHA_XPOS_2 0x070 361#define SC1200_ALPHA_YPOS_2 0x074 362#define SC1200_ALPHA_COLOR_2 0x078 363#define SC1200_ALPHA_CONTROL_2 0x07C 364#define SC1200_ALPHA_XPOS_3 0x080 365#define SC1200_ALPHA_YPOS_3 0x084 366#define SC1200_ALPHA_COLOR_3 0x088 367#define SC1200_ALPHA_CONTROL_3 0x08C 368#define SC1200_VIDEO_REQUEST 0x090 369#define SC1200_ALPHA_WATCH 0x094 370#define SC1200_VIDEO_DISPLAY_MODE 0x400 371#define SC1200_VIDEO_ODD_VBI_LINE_ENABLE 0x40C 372#define SC1200_VIDEO_EVEN_VBI_LINE_ENABLE 0x410 373#define SC1200_VIDEO_VBI_HORIZ_CONTROL 0x414 374#define SC1200_VIDEO_ODD_VBI_TOTAL_COUNT 0x418 375#define SC1200_VIDEO_EVEN_VBI_TOTAL_COUNT 0x41C 376#define SC1200_GENLOCK 0x420 377#define SC1200_GENLOCK_DELAY 0x424 378#define SC1200_TVOUT_HORZ_TIM 0x800 379#define SC1200_TVOUT_HORZ_SYNC 0x804 380#define SC1200_TVOUT_VERT_SYNC 0x808 381#define SC1200_TVOUT_LINE_END 0x80C 382#define SC1200_TVOUT_VERT_DOWNSCALE 0x810 /* REV. A & B */ 383#define SC1200_TVOUT_HORZ_PRE_ENCODER_SCALE 0x810 /* REV. C */ 384#define SC1200_TVOUT_HORZ_SCALING 0x814 385#define SC1200_TVOUT_DEBUG 0x818 386#define SC1200_TVENC_TIM_CTRL_1 0xC00 387#define SC1200_TVENC_TIM_CTRL_2 0xC04 388#define SC1200_TVENC_TIM_CTRL_3 0xC08 389#define SC1200_TVENC_SUB_FREQ 0xC0C 390#define SC1200_TVENC_DISP_POS 0xC10 391#define SC1200_TVENC_DISP_SIZE 0xC14 392#define SC1200_TVENC_CC_DATA 0xC18 393#define SC1200_TVENC_EDS_DATA 0xC1C 394#define SC1200_TVENC_CGMS_DATA 0xC20 395#define SC1200_TVENC_WSS_DATA 0xC24 396#define SC1200_TVENC_CC_CONTROL 0xC28 397#define SC1200_TVENC_DAC_CONTROL 0xC2C 398#define SC1200_TVENC_MV_CONTROL 0xC30 399 400/* "SC1200_VIDEO_CONFIG" BIT DEFINITIONS */ 401 402#define SC1200_VCFG_VID_EN 0x00000001 403#define SC1200_VCFG_VID_INP_FORMAT 0x0000000C 404#define SC1200_VCFG_UYVY_FORMAT 0x00000000 405#define SC1200_VCFG_Y2YU_FORMAT 0x00000004 406#define SC1200_VCFG_YUYV_FORMAT 0x00000008 407#define SC1200_VCFG_YVYU_FORMAT 0x0000000C 408#define SC1200_VCFG_X_FILTER_EN 0x00000040 409#define SC1200_VCFG_Y_FILTER_EN 0x00000080 410#define SC1200_VCFG_LINE_SIZE_LOWER_MASK 0x0000FF00 411#define SC1200_VCFG_INIT_READ_MASK 0x01FF0000 412#define SC1200_VCFG_LINE_SIZE_UPPER 0x08000000 413#define SC1200_VCFG_4_2_0_MODE 0x10000000 414 415/* "SC1200_DISPLAY_CONFIG" BIT DEFINITIONS */ 416 417#define SC1200_DCFG_DIS_EN 0x00000001 418#define SC1200_DCFG_HSYNC_EN 0x00000002 419#define SC1200_DCFG_VSYNC_EN 0x00000004 420#define SC1200_DCFG_DAC_BL_EN 0x00000008 421#define SC1200_DCFG_FP_PWR_EN 0x00000040 422#define SC1200_DCFG_FP_DATA_EN 0x00000080 423#define SC1200_DCFG_CRT_HSYNC_POL 0x00000100 424#define SC1200_DCFG_CRT_VSYNC_POL 0x00000200 425#define SC1200_DCFG_CRT_SYNC_SKW_MASK 0x0001C000 426#define SC1200_DCFG_CRT_SYNC_SKW_INIT 0x00010000 427#define SC1200_DCFG_PWR_SEQ_DLY_MASK 0x000E0000 428#define SC1200_DCFG_PWR_SEQ_DLY_INIT 0x00080000 429#define SC1200_DCFG_VG_CK 0x00100000 430#define SC1200_DCFG_GV_PAL_BYP 0x00200000 431#define SC1200_DCFG_DDC_SCL 0x00400000 432#define SC1200_DCFG_DDC_SDA 0x00800000 433#define SC1200_DCFG_DDC_OE 0x01000000 434 435/* "SC1200_VID_MISC" BIT DEFINITIONS */ 436 437#define SC1200_GAMMA_BYPASS_BOTH 0x00000001 438#define SC1200_DAC_POWER_DOWN 0x00000400 439#define SC1200_ANALOG_POWER_DOWN 0x00000800 440#define SC1200_PLL_POWER_NORMAL 0x00001000 441 442/* "SC1200_VIDEO_DOWNSCALER_CONTROL" BIT DEFINITIONS */ 443 444#define SC1200_VIDEO_DOWNSCALE_ENABLE 0x00000001 445#define SC1200_VIDEO_DOWNSCALE_FACTOR_POS 1 446#define SC1200_VIDEO_DOWNSCALE_FACTOR_MASK 0x0000001E 447#define SC1200_VIDEO_DOWNSCALE_TYPE_A 0x00000000 448#define SC1200_VIDEO_DOWNSCALE_TYPE_B 0x00000040 449#define SC1200_VIDEO_DOWNSCALE_TYPE_MASK 0x00000040 450 451/* "SC1200_VIDEO_DOWNSCALER_COEFFICIENTS" BIT DEFINITIONS */ 452 453#define SC1200_VIDEO_DOWNSCALER_COEF1_POS 0 454#define SC1200_VIDEO_DOWNSCALER_COEF2_POS 8 455#define SC1200_VIDEO_DOWNSCALER_COEF3_POS 16 456#define SC1200_VIDEO_DOWNSCALER_COEF4_POS 24 457#define SC1200_VIDEO_DOWNSCALER_COEF_MASK 0xF 458 459/* VIDEO DE-INTERLACING AND ALPHA CONTROL (REGISTER 0x4C) */ 460 461#define SC1200_VERTICAL_SCALER_SHIFT_MASK 0x00000007 462#define SC1200_VERTICAL_SCALER_SHIFT_INIT 0x00000004 463#define SC1200_VERTICAL_SCALER_SHIFT_EN 0x00000010 464#define SC1200_TOP_LINE_IN_ODD 0x00000040 465#define SC1200_NO_CK_OUTSIDE_ALPHA 0x00000100 466#define SC1200_VIDEO_IS_INTERLACED 0x00000200 467#define SC1200_CSC_VIDEO_YUV_TO_RGB 0x00000400 468#define SC1200_CSC_GFX_RGB_TO_YUV 0x00000800 469#define SC1200_VIDEO_INPUT_IS_RGB 0x00002000 470#define SC1200_VIDEO_LINE_OFFSET_ODD 0x00001000 471#define SC1200_ALPHA1_PRIORITY_POS 16 472#define SC1200_ALPHA1_PRIORITY_MASK 0x00030000 473#define SC1200_ALPHA2_PRIORITY_POS 18 474#define SC1200_ALPHA2_PRIORITY_MASK 0x000C0000 475#define SC1200_ALPHA3_PRIORITY_POS 20 476#define SC1200_ALPHA3_PRIORITY_MASK 0x00300000 477 478/* VIDEO CURSOR COLOR KEY DEFINITIONS (REGISTER 0x50) */ 479 480#define SC1200_CURSOR_COLOR_KEY_OFFSET_POS 24 481#define SC1200_CURSOR_COLOR_BITS 23 482#define SC1200_COLOR_MASK 0x00FFFFFF /* 24 significant 483 * bits */ 484 485/* ALPHA COLOR BIT DEFINITION (REGISTERS 0x68, 0x78, AND 0x88) */ 486 487#define SC1200_ALPHA_COLOR_ENABLE 0x01000000 488 489/* ALPHA CONTROL BIT DEFINITIONS (REGISTERS 0x6C, 0x7C, AND 0x8C) */ 490 491#define SC1200_ACTRL_WIN_ENABLE 0x00010000 492#define SC1200_ACTRL_LOAD_ALPHA 0x00020000 493 494/* VIDEO REQUEST DEFINITIONS (REGISTER 0x90) */ 495 496#define SC1200_VIDEO_Y_REQUEST_POS 0 497#define SC1200_VIDEO_X_REQUEST_POS 16 498#define SC1200_VIDEO_REQUEST_MASK 0x00000FFF 499 500/* VIDEO DISPLAY MODE (REGISTER 0x400) */ 501 502#define SC1200_VIDEO_SOURCE_MASK 0x00000003 503#define SC1200_VIDEO_SOURCE_GX1 0x00000000 504#define SC1200_VIDEO_SOURCE_DVIP 0x00000002 505#define SC1200_VBI_SOURCE_MASK 0x00000004 506#define SC1200_VBI_SOURCE_DVIP 0x00000000 507#define SC1200_VBI_SOURCE_GX1 0x00000004 508 509/* ODD/EVEN VBI LINE ENABLE (REGISTERS 0x40C, 0x410) */ 510 511#define SC1200_VIDEO_VBI_LINE_ENABLE_MASK 0x00FFFFFC 512#define SC1200_VIDEO_ALL_ACTIVE_IS_VBI 0x01000000 513#define SC1200_VIDEO_VBI_LINE_OFFSET_POS 25 514#define SC1200_VIDEO_VBI_LINE_OFFSET_MASK 0x3E000000 515 516/* ODD/EVEN VBI TOTAL COUNT (REGISTERS 0x418, 0x41C) */ 517 518#define SC1200_VIDEO_VBI_TOTAL_COUNT_MASK 0x000FFFFF 519 520/* GENLOCK BIT DEFINITIONS */ 521 522#define SC1200_GENLOCK_SINGLE_ENABLE 0x00000001 523#define SC1200_GENLOCK_FIELD_SYNC_ENABLE 0x00000001 524#define SC1200_GENLOCK_CONTINUOUS_ENABLE 0x00000002 525#define SC1200_GENLOCK_GX_VSYNC_FALLING_EDGE 0x00000004 526#define SC1200_GENLOCK_VIP_VSYNC_FALLING_EDGE 0x00000008 527#define SC1200_GENLOCK_TIMEOUT_ENABLE 0x00000010 528#define SC1200_GENLOCK_TVENC_RESET_EVEN_FIELD 0x00000020 529#define SC1200_GENLOCK_TVENC_RESET_BEFORE_DELAY 0x00000040 530#define SC1200_GENLOCK_TVENC_RESET_ENABLE 0x00000080 531#define SC1200_GENLOCK_SYNC_TO_TVENC 0x00000100 532#define SC1200_GENLOCK_DELAY_MASK 0x001FFFFF 533 534/* TVOUT HORIZONTAL PRE ENCODER SCALE BIT DEFINITIONS */ 535 536#define SC1200_TVOUT_YC_DELAY_MASK 0x00C00000 537#define SC1200_TVOUT_YC_DELAY_NONE 0x00000000 538#define SC1200_TVOUT_Y_DELAY_ONE_PIXEL 0x00400000 539#define SC1200_TVOUT_C_DELAY_ONE_PIXEL 0x00800000 540#define SC1200_TVOUT_C_DELAY_TWO_PIXELS 0x00C00000 541 542/* TVOUT HORIZONTAL SCALING/CONTROL BIT DEFINITIONS */ 543 544#define SC1200_TVOUT_FLICKER_FILTER_MASK 0x60000000 545#define SC1200_TVOUT_FLICKER_FILTER_FOURTH_HALF_FOURTH 0x00000000 546#define SC1200_TVOUT_FLICKER_FILTER_HALF_ONE_HALF 0x20000000 547#define SC1200_TVOUT_FLICKER_FILTER_DISABLED 0x40000000 548#define SC1200_TVENC_EXTERNAL_RESET_INTERVAL_MASK 0x0F000000 549#define SC1200_TVENC_EXTERNAL_RESET_EVERY_ODD_FIELD 0x00000000 550#define SC1200_TVENC_EXTERNAL_RESET_EVERY_EVEN_FIELD 0x02000000 551#define SC1200_TVENC_EXTERNAL_RESET_NEXT_ODD_FIELD 0x05000000 552#define SC1200_TVENC_EXTERNAL_RESET_NEXT_EVEN_FIELD 0x07000000 553#define SC1200_TVENC_EXTERNAL_RESET_EVERY_FIELD 0x0E000000 554#define SC1200_TVENC_EXTERNAL_RESET_EVERY_X_ODD_FIELDS 0x08000000 555#define SC1200_TVENC_EXTERNAL_RESET_EVERY_X_EVEN_FIELDS 0x0A000000 556 557/* TVOUT DEBUG BIT DEFINITIONS */ 558 559#define SC1200_TVOUT_FIELD_STATUS_EVEN 0x00000040 560#define SC1200_TVOUT_FIELD_STATUS_TV 0x00000080 561#define SC1200_TVOUT_CRT_VSYNC_STATUS_TRAILING 0x00000100 562#define SC1200_TVOUT_FIELD_STATUS_INVERT 0x00000200 563#define SC1200_TVOUT_CONVERTER_INTERPOLATION 0x00000400 564 565/* TVENC TIMING/CONTROL 1 BIT DEFINITIONS (REGISTER 0xC00) */ 566 567#define SC1200_TVENC_VPHASE_MASK 0x001FF800 568#define SC1200_TVENC_VPHASE_POS 11 569#define SC1200_TVENC_SUB_CARRIER_RESET_MASK 0x30000000 570#define SC1200_TVENC_SUB_CARRIER_RESET_NEVER 0x00000000 571#define SC1200_TVENC_SUB_CARRIER_RESET_EVERY_TWO_LINES 0x10000000 572#define SC1200_TVENC_SUB_CARRIER_RESET_EVERY_TWO_FRAMES 0x20000000 573#define SC1200_TVENC_SUB_CARRIER_RESET_EVERY_FOUR_FRAMES 0x30000000 574#define SC1200_TVENC_VIDEO_TIMING_ENABLE 0x80000000 575 576/* TVENC TIMING/CONTROL 2 BIT DEFINITIONS (REGISTER 0xC04) */ 577 578#define SC1200_TVENC_OUTPUT_YCBCR 0x40000000 579#define SC1200_TVENC_CFS_MASK 0x00030000 580#define SC1200_TVENC_CFS_BYPASS 0x00000000 581#define SC1200_TVENC_CFS_CVBS 0x00020000 582#define SC1200_TVENC_CFS_SVIDEO 0x00030000 583 584/* TVENC TIMING/CONTROL 3 BIT DEFINITIONS (REGISTER 0xC08) */ 585 586#define SC1200_TVENC_CS 0x00000001 587#define SC1200_TVENC_SYNCMODE_MASK 0x00000006 588#define SC1200_TVENC_SYNC_ON_GREEN 0x00000002 589#define SC1200_TVENC_SYNC_ON_CVBS 0x00000004 590#define SC1200_TVENC_CM 0x00000008 591 592/* TVENC DAC CONTROL BIT DEFINITIONS (REGISTER 0xC2C) */ 593#define SC1200_TVENC_TRIM_MASK 0x00000007 594#define SC1200_TVENC_POWER_DOWN 0x00000020 595 596/* TVENC MV CONTROL BIT DEFINITIONS (REGISTER 0xC30) */ 597#define SC1200_TVENC_MV_ENABLE 0xBE 598 599/* SC1200 VIP REGISTER DEFINITIONS */ 600 601#define SC1200_VIP_CONFIG 0x00000000 602#define SC1200_VIP_CONTROL 0x00000004 603#define SC1200_VIP_STATUS 0x00000008 604#define SC1200_VIP_CURRENT_LINE 0x00000010 605#define SC1200_VIP_LINE_TARGET 0x00000014 606#define SC1200_ODD_DIRECT_VBI_LINE_ENABLE 0x00000018 607#define SC1200_EVEN_DIRECT_VBI_LINE_ENABLE 0x0000001C 608#define SC1200_VIP_ODD_BASE 0x00000020 609#define SC1200_VIP_EVEN_BASE 0x00000024 610#define SC1200_VIP_PITCH 0x00000028 611#define SC1200_VBI_ODD_BASE 0x00000040 612#define SC1200_VBI_EVEN_BASE 0x00000044 613#define SC1200_VBI_PITCH 0x00000048 614 615/* "SC1200_VIP_CONFIG" BIT DEFINITIONS */ 616 617#define SC1200_VIP_MODE_MASK 0x00000003 618#define SC1200_VIP_MODE_C 0x00000002 619#define SC1200_VBI_ANCILLARY_TO_MEMORY 0x000C0000 620#define SC1200_VBI_TASK_A_TO_MEMORY 0x00140000 621#define SC1200_VBI_TASK_B_TO_MEMORY 0x00240000 622#define SC1200_VIP_BUS_REQUEST_THRESHOLD 0x00400000 623 624/* "SC1200_VIP_CONTROL" BIT DEFINITIONS */ 625 626#define SC1200_CAPTURE_RUN_MODE_MASK 0x00000003 627#define SC1200_CAPTURE_RUN_MODE_STOP_LINE 0x00000000 628#define SC1200_CAPTURE_RUN_MODE_STOP_FIELD 0x00000001 629#define SC1200_CAPTURE_RUN_MODE_START 0x00000003 630#define SC1200_VIP_DATA_CAPTURE_EN 0x00000100 631#define SC1200_VIP_VBI_CAPTURE_EN 0x00000200 632#define SC1200_VIP_VBI_FIELD_INTERRUPT_EN 0x00010000 633 634/* "SC1200_VIP_STATUS" BIT DEFINITIONS */ 635 636#define SC1200_VIP_CURRENT_FIELD_ODD 0x01000000 637#define SC1200_VIP_BASE_NOT_UPDATED 0x00200000 638#define SC1200_VIP_FIFO_OVERFLOW 0x00100000 639#define SC1200_VIP_CLEAR_LINE_INT 0x00020000 640#define SC1200_VIP_CLEAR_FIELD_INT 0x00010000 641#define SC1200_VBI_DATA_CAPTURE_ACTIVE 0x00000200 642#define SC1200_VIDEO_DATA_CAPTURE_ACTIVE 0x00000100 643 644/* "SC1200_VIP_CURRENT_LINE" BIT DEFINITIONS */ 645 646#define SC1200_VIP_CURRENT_LINE_MASK 0x000003FF 647 648/* "SC1200_VIP_LINE_TARGET" BIT DEFINITIONS */ 649 650#define SC1200_VIP_LAST_LINE_MASK 0x03FF0000 651 652/* "SC1200_VIP_PITCH" BIT DEFINITION */ 653 654#define SC1200_VIP_PITCH_MASK 0x0000FFFC 655 656/* "SC1200_VBI_PITCH" BIT DEFINITION */ 657 658#define SC1200_VBI_PITCH_MASK 0x0000FFFC 659 660/* SC1200 DIRECT VBI LINE ENABLE BIT DEFINITION */ 661 662#define SC1200_DIRECT_VBI_LINE_ENABLE_MASK 0x00FFFFFF 663 664/* SC1200 CONFIGURATION BLOCK */ 665 666#define SC1200_CB_BASE_ADDR 0x9000 667#define SC1200_CB_WDTO 0x0000 668#define SC1200_CB_WDCNFG 0x0002 669#define SC1200_CB_WDSTS 0x0004 670#define SC1200_CB_TMVALUE 0x0008 671#define SC1200_CB_TMCNFG 0x000D 672#define SC1200_CB_CCFC 0x001E 673#define SC1200_CB_PMR 0x0030 674#define SC1200_CB_MCR 0x0034 675#define SC1200_CB_INTSEL 0x0038 676#define SC1200_CB_PID 0x003C 677#define SC1200_CB_REV 0x003D 678 679/* SC1200 HIGH RESOLUTION TIMER CONFIGURATION REGISTER BITS */ 680 681#define SC1200_TMCLKSEL_27MHZ 0x2 682 683/*---------------------------------*/ 684/* PHILIPS SAA7114 VIDEO DECODER */ 685/*---------------------------------*/ 686 687#define SAA7114_CHIPADDR 0x42 688 689/* VIDEO DECODER REGISTER DEFINITIONS */ 690 691#define SAA7114_ANALOG_INPUT_CTRL1 0x02 692#define SAA7114_LUMINANCE_CONTROL 0x09 693#define SAA7114_BRIGHTNESS 0x0A 694#define SAA7114_CONTRAST 0x0B 695#define SAA7114_SATURATION 0x0C 696#define SAA7114_HUE 0x0D 697#define SAA7114_STATUS 0x1F 698#define SAA7114_IPORT_CONTROL 0x86 699 700/* TASK A REGISTER DEFINITIONS */ 701 702#define SAA7114_TASK_A_HORZ_OUTPUT_LO 0x9C 703#define SAA7114_TASK_A_HORZ_OUTPUT_HI 0x9D 704#define SAA7114_TASK_A_HSCALE_LUMA_LO 0xA8 705#define SAA7114_TASK_A_HSCALE_LUMA_HI 0xA9 706#define SAA7114_TASK_A_HSCALE_CHROMA_LO 0xAC 707#define SAA7114_TASK_A_HSCALE_CHROMA_HI 0xAD 708 709/* TASK B REGISTER DEFINITIONS */ 710 711#define SAA7114_HORZ_OFFSET_LO 0xC4 712#define SAA7114_HORZ_OFFSET_HI 0xC5 713#define SAA7114_HORZ_INPUT_LO 0xC6 714#define SAA7114_HORZ_INPUT_HI 0xC7 715#define SAA7114_VERT_OFFSET_LO 0xC8 716#define SAA7114_VERT_OFFSET_HI 0xC9 717#define SAA7114_VERT_INPUT_LO 0xCA 718#define SAA7114_VERT_INPUT_HI 0xCB 719#define SAA7114_HORZ_OUTPUT_LO 0xCC 720#define SAA7114_HORZ_OUTPUT_HI 0xCD 721#define SAA7114_VERT_OUTPUT_LO 0xCE 722#define SAA7114_VERT_OUTPUT_HI 0xCF 723#define SAA7114_HORZ_PRESCALER 0xD0 724#define SAA7114_HORZ_ACL 0xD1 725#define SAA7114_HORZ_FIR_PREFILTER 0xD2 726#define SAA7114_FILTER_CONTRAST 0xD5 727#define SAA7114_FILTER_SATURATION 0xD6 728#define SAA7114_HSCALE_LUMA_LO 0xD8 729#define SAA7114_HSCALE_LUMA_HI 0xD9 730#define SAA7114_HSCALE_CHROMA_LO 0xDC 731#define SAA7114_HSCALE_CHROMA_HI 0xDD 732#define SAA7114_VSCALE_LUMA_LO 0xE0 733#define SAA7114_VSCALE_LUMA_HI 0xE1 734#define SAA7114_VSCALE_CHROMA_LO 0xE2 735#define SAA7114_VSCALE_CHROMA_HI 0xE3 736#define SAA7114_VSCALE_CONTROL 0xE4 737#define SAA7114_VSCALE_CHROMA_OFFS0 0xE8 738#define SAA7114_VSCALE_CHROMA_OFFS1 0xE9 739#define SAA7114_VSCALE_CHROMA_OFFS2 0xEA 740#define SAA7114_VSCALE_CHROMA_OFFS3 0xEB 741#define SAA7114_VSCALE_LUMINA_OFFS0 0xEC 742#define SAA7114_VSCALE_LUMINA_OFFS1 0xED 743#define SAA7114_VSCALE_LUMINA_OFFS2 0xEE 744#define SAA7114_VSCALE_LUMINA_OFFS3 0xEF 745 746/* Still need to determine PHO value (common phase offset) */ 747#define SAA7114_VSCALE_PHO 0x00 748 749/*----------------------------------------------*/ 750/* SECOND GENERATION GRAPHICS UNIT (REDCLOUD) */ 751/*----------------------------------------------*/ 752 753#define MGP_DST_OFFSET 0x0000 /* dst address */ 754#define MGP_SRC_OFFSET 0x0004 /* src address */ 755#define MGP_VEC_ERR 0x0004 /* vector diag/axial errors */ 756#define MGP_STRIDE 0x0008 /* src and dst strides */ 757#define MGP_WID_HEIGHT 0x000C /* width and height of BLT */ 758#define MGP_VEC_LEN 0x000C /* vector length/init error */ 759#define MGP_SRC_COLOR_FG 0x0010 /* src mono data fgcolor */ 760#define MGP_SRC_COLOR_BG 0x0014 /* src mono data bkcolor */ 761#define MGP_PAT_COLOR_0 0x0018 /* pattern color 0 */ 762#define MGP_PAT_COLOR_1 0x001C /* pattern color 1 */ 763#define MGP_PAT_COLOR_2 0x0020 /* pattern color 2 */ 764#define MGP_PAT_COLOR_3 0x0024 /* pattern color 3 */ 765#define MGP_PAT_COLOR_4 0x0028 /* pattern color 4 */ 766#define MGP_PAT_COLOR_5 0x002C /* pattern color 5 */ 767#define MGP_PAT_DATA_0 0x0030 /* pattern data 0 */ 768#define MGP_PAT_DATA_1 0x0034 /* pattern data 1 */ 769#define MGP_RASTER_MODE 0x0038 /* raster operation */ 770#define MGP_VECTOR_MODE 0x003C /* render vector */ 771#define MGP_BLT_MODE 0x0040 /* render BLT */ 772#define MGP_BLT_STATUS 0x0044 /* BLT status register */ 773#define MGP_RESET 0x0044 /* reset register (write) */ 774#define MGP_HST_SOURCE 0x0048 /* host src data (bitmap) */ 775#define MGP_BASE_OFFSET 0x004C /* base render offset */ 776 777/* MGP_RASTER_MODE DEFINITIONS */ 778 779#define MGP_RM_BPPFMT_332 0x00000000 /* 8 BPP, 3:3:2 */ 780#define MGP_RM_BPPFMT_4444 0x40000000 /* 16 BPP, 4:4:4:4 */ 781#define MGP_RM_BPPFMT_1555 0x50000000 /* 16 BPP, 1:5:5:5 */ 782#define MGP_RM_BPPFMT_565 0x60000000 /* 16 BPP, 5:6:5 */ 783#define MGP_RM_BPPFMT_8888 0x80000000 /* 32 BPP, 8:8:8:8 */ 784#define MGP_RM_ALPHA_EN_MASK 0x00C00000 /* Alpha enable */ 785#define MGP_RM_ALPHA_TO_RGB 0x00400000 /* Alpha applies to RGB */ 786#define MGP_RM_ALPHA_TO_ALPHA 0x00800000 /* Alpha applies to alpha */ 787#define MGP_RM_ALPHA_OP_MASK 0x00300000 /* Alpha operation */ 788#define MGP_RM_ALPHA_TIMES_A 0x00000000 /* Alpha * A */ 789#define MGP_RM_BETA_TIMES_B 0x00100000 /* (1-alpha) * B */ 790#define MGP_RM_A_PLUS_BETA_B 0x00200000 /* A + (1-alpha) * B */ 791#define MGP_RM_ALPHA_A_PLUS_BETA_B 0x00300000 /* alpha * A + (1 - alpha)B */ 792#define MGP_RM_ALPHA_SELECT 0x000E0000 /* Alpha Select */ 793#define MGP_RM_SELECT_ALPHA_A 0x00000000 /* Alpha from channel A */ 794#define MGP_RM_SELECT_ALPHA_B 0x00020000 /* Alpha from channel B */ 795#define MGP_RM_SELECT_ALPHA_R 0x00040000 /* Registered alpha */ 796#define MGP_RM_SELECT_ALPHA_1 0x00060000 /* Constant 1 */ 797#define MGP_RM_SELECT_ALPHA_CHAN_A 0x00080000 /* RGB Values from A */ 798#define MGP_RM_SELECT_ALPHA_CHAN_B 0x000A0000 /* RGB Values from B */ 799#define MGP_RM_DEST_FROM_CHAN_A 0x00010000 /* Alpha channel select */ 800#define MGP_RM_PAT_FLAGS 0x00000700 /* pattern related bits */ 801#define MGP_RM_PAT_MONO 0x00000100 /* monochrome pattern */ 802#define MGP_RM_PAT_COLOR 0x00000200 /* color pattern */ 803#define MGP_RM_PAT_TRANS 0x00000400 /* pattern transparency */ 804#define MGP_RM_SRC_TRANS 0x00000800 /* source transparency */ 805 806/* MGP_VECTOR_MODE DEFINITIONS */ 807 808#define MGP_VM_DST_REQ 0x00000008 /* dst data required */ 809#define MGP_VM_THROTTLE 0x00000010 /* sync to VBLANK */ 810 811/* MGP_BLT_MODE DEFINITIONS */ 812 813#define MGP_BM_SRC_FB 0x00000001 /* src = frame buffer */ 814#define MGP_BM_SRC_HOST 0x00000002 /* src = host register */ 815#define MGP_BM_DST_REQ 0x00000004 /* dst data required */ 816#define MGP_BM_SRC_MONO 0x00000040 /* monochrome source data */ 817#define MGP_BM_SRC_BP_MONO 0x00000080 /* Byte-packed monochrome */ 818#define MGP_BM_SRC_TYPE_MASK 0x000000C0 /* Mask for all source fmts */ 819#define MGP_BM_NEG_YDIR 0x00000100 /* negative Y direction */ 820#define MGP_BM_NEG_XDIR 0x00000200 /* negative X direction */ 821#define MGP_BM_THROTTLE 0x00000400 /* sync to VBLANK */ 822 823/* MGP_BLT_STATUS DEFINITIONS */ 824 825#define MGP_BS_BLT_BUSY 0x00000001 /* GP is not idle */ 826#define MGP_BS_BLT_PENDING 0x00000004 /* second BLT is pending */ 827#define MGP_BS_HALF_EMPTY 0x00000008 /* src FIFO half empty */ 828 829/* ALPHA BLENDING MODES */ 830 831#define ALPHA_MODE_BLEND 0x00000000 832 833/*---------------------------------------------------*/ 834/* SECOND GENERATION DISPLAY CONTROLLER (REDCLOUD) */ 835/*---------------------------------------------------*/ 836 837#define MDC_UNLOCK 0x00000000 /* Unlock register */ 838#define MDC_GENERAL_CFG 0x00000004 /* Config registers */ 839#define MDC_DISPLAY_CFG 0x00000008 840#define MDC_GFX_SCL 0x0000000C /* Graphics scaling */ 841 842#define MDC_FB_ST_OFFSET 0x00000010 /* Frame buffer start offset */ 843#define MDC_CB_ST_OFFSET 0x00000014 /* Compression start offset */ 844#define MDC_CURS_ST_OFFSET 0x00000018 /* Cursor buffer start */ 845 /* offset */ 846#define MDC_ICON_ST_OFFSET 0x0000001C /* Icon buffer start offset */ 847#define MDC_VID_Y_ST_OFFSET 0x00000020 /* Video Y Buffer start */ 848 /* offset */ 849#define MDC_VID_U_ST_OFFSET 0x00000024 /* Video U Buffer start */ 850 /* offset */ 851#define MDC_VID_V_ST_OFFSET 0x00000028 /* Video V Buffer start */ 852 /* offset */ 853#define MDC_LINE_SIZE 0x00000030 /* Video, CB, and FB line */ 854 /* sizes */ 855#define MDC_GFX_PITCH 0x00000034 /* FB and DB skip counts */ 856#define MDC_VID_YUV_PITCH 0x00000038 /* Y, U and V buffer skip */ 857 /* counts */ 858 859#define MDC_H_ACTIVE_TIMING 0x00000040 /* Horizontal timings */ 860#define MDC_H_BLANK_TIMING 0x00000044 861#define MDC_H_SYNC_TIMING 0x00000048 862#define MDC_V_ACTIVE_TIMING 0x00000050 /* Vertical Timings */ 863#define MDC_V_BLANK_TIMING 0x00000054 864#define MDC_V_SYNC_TIMING 0x00000058 865 866#define MDC_CURSOR_X 0x00000060 /* Cursor X position */ 867#define MDC_CURSOR_Y 0x00000064 /* Cursor Y Position */ 868#define MDC_ICON_X 0x00000068 /* Icon X Position */ 869#define MDC_LINE_CNT_STATUS 0x0000006C /* Icon Y Position */ 870 871#define MDC_PAL_ADDRESS 0x00000070 /* Palette Address */ 872#define MDC_PAL_DATA 0x00000074 /* Palette Data */ 873#define MDC_DFIFO_DIAG 0x00000078 /* Display FIFO diagnostic */ 874#define MDC_CFIFO_DIAG 0x0000007C /* Compression FIFO */ 875 /* diagnostic */ 876 877#define MDC_VID_DS_DELTA 0x00000080 /* Vertical Downscaling */ 878 /* fraction */ 879 880#define MDC_PHY_MEM_OFFSET 0x00000084 /* VG Base Address Register */ 881#define MDC_DV_CTL 0x00000088 /* Dirty-Valid Control */ 882 /* Register */ 883#define MDC_DV_ACC 0x0000008C /* Dirty-Valid RAM Access */ 884 885/* UNLOCK VALUE */ 886 887#define MDC_UNLOCK_VALUE 0x00004758 /* used to unlock DC regs */ 888 889/* VG MBUS DEVICE SMI MSR FIELDS */ 890 891#define MDC_VG_BL_MASK 0x00000001 892#define MDC_MISC_MASK 0x00000002 893#define MDC_ISR0_MASK 0x00000004 894#define MDC_VGA_BL_MASK 0x00000008 895#define MDC_CRTCIO_MSK 0x00000010 896#define MDC_VG_BLANK_SMI 0x00000001 897#define MDC_MISC_SMI 0x00000002 898#define MDC_ISR0_SMI 0x00000004 899#define MDC_VGA_BLANK_SMI 0x00000008 900#define MDC_CRTCIO_SMI 0x00000010 901 902/* MDC_GENERAL_CFG BIT FIELDS */ 903 904#define MDC_GCFG_DBUG 0x80000000 905#define MDC_GCFG_DBSL 0x40000000 906#define MDC_GCFG_CFRW 0x20000000 907#define MDC_GCFG_DIAG 0x10000000 908#define MDC_GCFG_GXRFS4 0x08000000 909#define MDC_GCFG_SGFR 0x04000000 910#define MDC_GCFG_SGRE 0x02000000 911#define MDC_GCFG_SIGE 0x01000000 912#define MDC_GCFG_YUVM 0x00100000 913#define MDC_GCFG_VDSE 0x00080000 914#define MDC_GCFG_VGAFT 0x00040000 915#define MDC_GCFG_FDTY 0x00020000 916#define MDC_GCFG_STFM 0x00010000 917#define MDC_GCFG_DFHPEL_MASK 0x0000F000 918#define MDC_GCFG_DFHPSL_MASK 0x00000F00 919#define MDC_GCFG_VGAE 0x00000080 920#define MDC_GCFG_DECE 0x00000040 921#define MDC_GCFG_CMPE 0x00000020 922#define MDC_GCFG_VIDE 0x00000008 923#define MDC_GCFG_ICNE 0x00000004 924#define MDC_GCFG_CURE 0x00000002 925#define MDC_GCFG_DFLE 0x00000001 926 927/* MDC_DISPLAY_CFG BIT FIELDS */ 928 929#define MDC_DCFG_A20M 0x80000000 930#define MDC_DCFG_A18M 0x40000000 931#define MDC_DCFG_VISL 0x08000000 932#define MDC_DCFG_FRLK 0x04000000 933#define MDC_DCFG_PALB 0x02000000 934#define MDC_DCFG_PIX_PAN_MASK 0x00F00000 935#define MDC_DCFG_DCEN 0x00080000 936#define MDC_DCFG_16BPP_MODE_MASK 0x00000C00 937#define MDC_DCFG_16BPP 0x00000000 938#define MDC_DCFG_15BPP 0x00000400 939#define MDC_DCFG_12BPP 0x00000800 940#define MDC_DCFG_DISP_MODE_MASK 0x00000300 941#define MDC_DCFG_DISP_MODE_8BPP 0x00000000 942#define MDC_DCFG_DISP_MODE_16BPP 0x00000100 943#define MDC_DCFG_DISP_MODE_24BPP 0x00000200 944#define MDC_DCFG_SCLE 0x00000080 945#define MDC_DCFG_TRUP 0x00000040 946#define MDC_DCFG_VIEN 0x00000020 947#define MDC_DCFG_VDEN 0x00000010 948#define MDC_DCFG_GDEN 0x00000008 949#define MDC_DCFG_VCKE 0x00000004 950#define MDC_DCFG_PCKE 0x00000002 951#define MDC_DCFG_TGEN 0x00000001 952 953/* MDC_LINE_CNT BIT FIELDS */ 954 955#define MDC_LNCNT_DNA 0x80000000 956#define MDC_LNCNT_VNA 0x40000000 957#define MDC_LNCNT_VSA 0x20000000 958#define MDC_LNCNT_VINT 0x10000000 959#define MDC_LNCNT_FLIP 0x08000000 960#define MDC_LNCNT_V_LINE_CNT 0x07FF0000 961#define MDC_LNCNT_VFLIP 0x00008000 962#define MDC_LNCNT_SIGC 0x00004000 963#define MDC_LNCNT_SS_LINE_CMP 0x000007FF 964 965/* MDC_FB_ST_OFFSET BIT FIELDS */ 966 967#define MDC_FB_ST_OFFSET_MASK 0x0FFFFFFF 968 969/* MDC_CB_ST_OFFSET BIT FIELDS */ 970 971#define MDC_CB_ST_OFFSET_MASK 0x0FFFFFFF 972 973/* MDC_CURS_ST_OFFSET BIT FIELDS */ 974 975#define MDC_CURS_ST_OFFSET_MASK 0x0FFFFFFF 976 977/* MDC_ICON_ST_OFFSET BIT FIELDS */ 978 979#define MDC_ICON_ST_OFFSET_MASK 0x0FFFFFFF 980 981/* MDC_VID_Y_ST_OFFSET BIT FIELDS */ 982 983#define MDC_VID_Y_ST_OFFSET_MASK 0x0FFFFFFF 984 985/* MDC_VID_U_ST_OFFSET BIT FIELDS */ 986 987#define MDC_VID_U_ST_OFFSET_MASK 0x0FFFFFFF 988 989/* MDC_VID_V_ST_OFFSET BIT FIELDS */ 990 991#define MDC_VID_V_ST_OFFSET_MASK 0x0FFFFFFF 992 993/* MDC_LINE_SIZE BIT FIELDS */ 994 995#define MDC_LINE_SIZE_VLS_MASK 0xFF000000 996#define MDC_LINE_SIZE_CBLS_MASK 0x007F0000 997#define MDC_LINE_SIZE_FBLS_MASK 0x000007FF 998 999/* MDC_GFX_PITCH BIT FIELDS */ 1000 1001#define MDC_GFX_PITCH_CBP_MASK 0xFFFF0000 1002#define MDC_GFX_PITCH_FBP_MASK 0x0000FFFF 1003 1004/* MDC_VID_YUV_PITCH BIT FIELDS */ 1005 1006#define MDC_YUV_PITCH_UVP_MASK 0xFFFF0000 1007#define MDC_YUV_PITCH_YBP_MASK 0x0000FFFF 1008 1009/* MDC_H_ACTIVE_TIMING BIT FIELDS */ 1010 1011#define MDC_HAT_HT_MASK 0x0FF80000 1012#define MDC_HAT_HA_MASK 0x00000FF8 1013 1014/* MDC_H_BLANK_TIMING BIT FIELDS */ 1015 1016#define MDC_HBT_HBE_MASK 0x0FF80000 1017#define MDC_HBT_HBS_MASK 0x00000FF8 1018 1019/* MDC_H_SYNC_TIMING BIT FIELDS */ 1020 1021#define MDC_HST_HSE_MASK 0x0FF80000 1022#define MDC_HST_HSS_MASK 0x00000FF8 1023 1024/* MDC_V_ACTIVE_TIMING BIT FIELDS */ 1025 1026#define MDC_VAT_VT_MASK 0x07FF0000 1027#define MDC_VAT_VA_MASK 0x000007FF 1028 1029/* MDC_V_BLANK_TIMING BIT FIELDS */ 1030 1031#define MDC_VBT_VBE_MASK 0x07FF0000 1032#define MDC_VBT_VBS_MASK 0x000007FF 1033 1034/* MDC_V_SYNC_TIMING BIT FIELDS */ 1035 1036#define MDC_VST_VSE_MASK 0x07FF0000 1037#define MDC_VST_VSS_MASK 0x000007FF 1038 1039/* MDC_DV_CTL BIT DEFINITIONS */ 1040 1041#define MDC_DV_LINE_SIZE_MASK 0x00000C00 1042#define MDC_DV_LINE_SIZE_1024 0x00000000 1043#define MDC_DV_LINE_SIZE_2048 0x00000400 1044#define MDC_DV_LINE_SIZE_4096 0x00000800 1045#define MDC_DV_LINE_SIZE_8192 0x00000C00 1046 1047/* VGA DEFINITIONS */ 1048 1049#define MDC_SEQUENCER_INDEX 0x03C4 1050#define MDC_SEQUENCER_DATA 0x03C5 1051#define MDC_SEQUENCER_RESET 0x00 1052#define MDC_SEQUENCER_CLK_MODE 0x01 1053 1054#define MDC_RESET_VGA_DISP_ENABLE 0x03 1055#define MDC_CLK_MODE_SCREEN_OFF 0x20 1056 1057/*---------------------------------------------------*/ 1058/* REDCLOUD DISPLAY FILTER */ 1059/*---------------------------------------------------*/ 1060 1061/* RCDF VIDEO REGISTER DEFINITIONS */ 1062 1063#define RCDF_VIDEO_CONFIG 0x000 1064#define RCDF_DISPLAY_CONFIG 0x008 1065#define RCDF_VIDEO_X_POS 0x010 1066#define RCDF_VIDEO_Y_POS 0x018 1067#define RCDF_VIDEO_SCALE 0x020 1068#define RCDF_VIDEO_COLOR_KEY 0x028 1069#define RCDF_VIDEO_COLOR_MASK 0x030 1070#define RCDF_PALETTE_ADDRESS 0x038 1071#define RCDF_PALETTE_DATA 0x040 1072#define RCDF_VID_MISC 0x050 1073#define RCDF_VID_CLOCK_SELECT 0x058 1074#define RCDF_VIDEO_DOWNSCALER_CONTROL 0x078 1075#define RCDF_VIDEO_DOWNSCALER_COEFFICIENTS 0x080 1076#define RCDF_VID_CRC 0x088 1077#define RCDF_VID_CRC32 0x090 1078#define RCDF_VID_ALPHA_CONTROL 0x098 1079#define RCDF_CURSOR_COLOR_KEY 0x0A0 1080#define RCDF_CURSOR_COLOR_MASK 0x0A8 1081#define RCDF_CURSOR_COLOR_1 0x0B0 1082#define RCDF_CURSOR_COLOR_2 0x0B8 1083#define RCDF_ALPHA_XPOS_1 0x0C0 1084#define RCDF_ALPHA_YPOS_1 0x0C8 1085#define RCDF_ALPHA_COLOR_1 0x0D0 1086#define RCDF_ALPHA_CONTROL_1 0x0D8 1087#define RCDF_ALPHA_XPOS_2 0x0E0 1088#define RCDF_ALPHA_YPOS_2 0x0E8 1089#define RCDF_ALPHA_COLOR_2 0x0F0 1090#define RCDF_ALPHA_CONTROL_2 0x0F8 1091#define RCDF_ALPHA_XPOS_3 0x100 1092#define RCDF_ALPHA_YPOS_3 0x108 1093#define RCDF_ALPHA_COLOR_3 0x110 1094#define RCDF_ALPHA_CONTROL_3 0x118 1095#define RCDF_VIDEO_REQUEST 0x120 1096#define RCDF_ALPHA_WATCH 0x128 1097#define RCDF_VIDEO_TEST_MODE 0x210 1098#define RCDF_POWER_MANAGEMENT 0x410 1099 1100/* DISPLAY FILTER POWER MANAGEMENT DEFINITIONS */ 1101 1102#define RCDF_PM_PANEL_POWER_ON 0x01000000 1103 1104/* DISPLAY FILTER MSRS */ 1105 1106#define RCDF_MBD_MSR_DIAG_DF 0x2010 1107#define RCDF_DIAG_32BIT_CRC 0x80000000 1108 1109/* "RCDF_VIDEO_CONFIG" BIT DEFINITIONS */ 1110 1111#define RCDF_VCFG_VID_EN 0x00000001 1112#define RCDF_VCFG_VID_INP_FORMAT 0x0000000C 1113#define RCDF_VCFG_X_FILTER_EN 0x00000040 1114#define RCDF_VCFG_Y_FILTER_EN 0x00000080 1115#define RCDF_VCFG_LINE_SIZE_LOWER_MASK 0x0000FF00 1116#define RCDF_VCFG_INIT_READ_MASK 0x01FF0000 1117#define RCDF_VCFG_LINE_SIZE_UPPER 0x08000000 1118#define RCDF_VCFG_4_2_0_MODE 0x10000000 1119#define RCDF_VCFG_UYVY_FORMAT 0x00000000 1120#define RCDF_VCFG_Y2YU_FORMAT 0x00000004 1121#define RCDF_VCFG_YUYV_FORMAT 0x00000008 1122#define RCDF_VCFG_YVYU_FORMAT 0x0000000C 1123 1124/* "RCDF_DISPLAY_CONFIG" BIT DEFINITIONS */ 1125 1126#define RCDF_DCFG_DIS_EN 0x00000001 1127#define RCDF_DCFG_HSYNC_EN 0x00000002 1128#define RCDF_DCFG_VSYNC_EN 0x00000004 1129#define RCDF_DCFG_DAC_BL_EN 0x00000008 1130#define RCDF_DCFG_FP_PWR_EN 0x00000040 1131#define RCDF_DCFG_FP_DATA_EN 0x00000080 1132#define RCDF_DCFG_CRT_HSYNC_POL 0x00000100 1133#define RCDF_DCFG_CRT_VSYNC_POL 0x00000200 1134#define RCDF_DCFG_CRT_SYNC_SKW_MASK 0x0001C000 1135#define RCDF_DCFG_CRT_SYNC_SKW_INIT 0x00010000 1136#define RCDF_DCFG_PWR_SEQ_DLY_MASK 0x000E0000 1137#define RCDF_DCFG_PWR_SEQ_DLY_INIT 0x00080000 1138#define RCDF_DCFG_VG_CK 0x00100000 1139#define RCDF_DCFG_GV_PAL_BYP 0x00200000 1140#define RCDF_DAC_VREF 0x04000000 1141#define RCDF_FP_ON_STATUS 0x08000000 1142 1143/* "RCDF_VID_MISC" BIT DEFINITIONS */ 1144 1145#define RCDF_GAMMA_BYPASS_BOTH 0x00000001 1146#define RCDF_DAC_POWER_DOWN 0x00000400 1147#define RCDF_ANALOG_POWER_DOWN 0x00000800 1148 1149/* "RCDF_VIDEO_DOWNSCALER_CONTROL" BIT DEFINITIONS */ 1150 1151#define RCDF_VIDEO_DOWNSCALE_ENABLE 0x00000001 1152#define RCDF_VIDEO_DOWNSCALE_FACTOR_POS 1 1153#define RCDF_VIDEO_DOWNSCALE_FACTOR_MASK 0x0000001E 1154#define RCDF_VIDEO_DOWNSCALE_TYPE_A 0x00000000 1155#define RCDF_VIDEO_DOWNSCALE_TYPE_B 0x00000040 1156#define RCDF_VIDEO_DOWNSCALE_TYPE_MASK 0x00000040 1157 1158/* "RCDF_VIDEO_DOWNSCALER_COEFFICIENTS" BIT DEFINITIONS */ 1159 1160#define RCDF_VIDEO_DOWNSCALER_COEF1_POS 0 1161#define RCDF_VIDEO_DOWNSCALER_COEF2_POS 8 1162#define RCDF_VIDEO_DOWNSCALER_COEF3_POS 16 1163#define RCDF_VIDEO_DOWNSCALER_COEF4_POS 24 1164#define RCDF_VIDEO_DOWNSCALER_COEF_MASK 0xF 1165 1166/* VIDEO DE-INTERLACING AND ALPHA CONTROL */ 1167 1168#define RCDF_NO_CK_OUTSIDE_ALPHA 0x00000100 1169#define RCDF_CSC_VIDEO_YUV_TO_RGB 0x00000400 1170#define RCDF_VIDEO_INPUT_IS_RGB 0x00002000 1171#define RCDF_ALPHA1_PRIORITY_POS 16 1172#define RCDF_ALPHA1_PRIORITY_MASK 0x00030000 1173#define RCDF_ALPHA2_PRIORITY_POS 18 1174#define RCDF_ALPHA2_PRIORITY_MASK 0x000C0000 1175#define RCDF_ALPHA3_PRIORITY_POS 20 1176#define RCDF_ALPHA3_PRIORITY_MASK 0x00300000 1177 1178/* VIDEO CURSOR COLOR KEY DEFINITIONS */ 1179 1180#define RCDF_CURSOR_COLOR_KEY_ENABLE 0x20000000 1181#define RCDF_CURSOR_COLOR_KEY_OFFSET_POS 24 1182#define RCDF_CURSOR_COLOR_BITS 23 1183#define RCDF_COLOR_MASK 0x00FFFFFF 1184 /* 24 significant bits */ 1185 1186/* ALPHA COLOR BIT DEFINITION (REGISTERS 0x68, 0x78, AND 0x88) */ 1187 1188#define RCDF_ALPHA_COLOR_ENABLE 0x01000000 1189 1190/* ALPHA CONTROL BIT DEFINITIONS (REGISTERS 0x6C, 0x7C, AND 0x8C) */ 1191 1192#define RCDF_ACTRL_WIN_ENABLE 0x00010000 1193#define RCDF_ACTRL_LOAD_ALPHA 0x00020000 1194 1195/* VIDEO REQUEST DEFINITIONS (REGISTER 0x90) */ 1196 1197#define RCDF_VIDEO_Y_REQUEST_POS 0 1198#define RCDF_VIDEO_X_REQUEST_POS 16 1199#define RCDF_VIDEO_REQUEST_MASK 0x000007FF 1200 1201/* GEODELINK DEVICE MSR REGISTER SUMMARY */ 1202 1203#define MBD_MSR_CAP 0x2000 /* Device Capabilities */ 1204#define MBD_MSR_CONFIG 0x2001 /* Device Master Configuration */ 1205 /* Register */ 1206#define MBD_MSR_SMI 0x2002 /* MBus Device SMI Register */ 1207#define MBD_MSR_ERROR 0x2003 /* MBus Device Error */ 1208#define MBD_MSR_PM 0x2004 /* MBus Device Power Management */ 1209 /* Register */ 1210#define MBD_MSR_DIAG 0x2005 /* Mbus Device Diagnostic Register */ 1211 1212/* DISPLAY FILTER MBD_MSR_DIAG DEFINITIONS */ 1213 1214#define RCDF_MBD_DIAG_SEL0 0x00007FFF /* Lower 32-bits of Diag Bus 1215 * Select */ 1216#define RCDF_MBD_DIAG_EN0 0x00008000 /* Enable for lower 32-bits of 1217 * diag bus */ 1218#define RCDF_MBD_DIAG_SEL1 0x7FFF0000 /* Upper 32-bits of Diag Bus 1219 * Select */ 1220#define RCDF_MBD_DIAG_EN1 0x80000000 /* Enable for upper 32-bits of 1221 * diag bus */ 1222 1223/* DISPLAY FILTER MBD_MSR_CONFIG DEFINITIONS */ 1224 1225#define RCDF_CONFIG_FMT_MASK 0x00000038 /* Output Format */ 1226#define RCDF_CONFIG_FMT_CRT 0x00000000 1227#define RCDF_CONFIG_FMT_FP 0x00000008 1228 1229/* MCP MSR DEFINITIONS */ 1230 1231#define MCP_CLKOFF 0x0010 1232#define MCP_CLKACTIVE 0x0011 1233#define MCP_CLKDISABLE 0x0012 1234#define MCP_CLK4ACK 0x0013 1235#define MCP_SYS_RSTPLL 0x0014 1236#define MCP_DOTPLL 0x0015 1237#define MCP_DBGCLKCTL 0x0016 1238#define MCP_RC_REVID 0x0017 1239#define MCP_SETM0CTL 0x0040 1240#define MCP_SETN0CTL 0x0048 1241#define MCP_CMPVAL0 0x0050 1242#define MCP_CMPMASK0 0x0051 1243#define MCP_REGA 0x0058 1244#define MCP_REGB 0x0059 1245#define MCP_REGAMASK 0x005A 1246#define MCP_REGAVAL 0x005B 1247#define MCP_REGBMASK 0x005C 1248#define MCP_REGBVAL 0x005D 1249#define MCP_FIFOCTL 0x005E 1250#define MCP_DIAGCTL 0x005F 1251#define MCP_H0CTL 0x0060 1252#define MCP_XSTATE 0x0066 1253#define MCP_YSTATE 0x0067 1254#define MCP_ACTION0 0x0068 1255 1256/* MCP_SYS_RSTPLL DEFINITIONS */ 1257 1258#define MCP_DOTPOSTDIV3 0x00000008 1259#define MCP_DOTPREMULT2 0x00000004 1260#define MCP_DOTPREDIV2 0x00000002 1261#define MCP_DOTPLL_HALFPIX 0x01000000 1262 1263/* MCP MBD_MSR_DIAG DEFINITIONS */ 1264 1265#define MCP_MBD_DIAG_SEL0 0x00000007 1266#define MCP_MBD_DIAG_EN0 0x00008000 1267#define MCP_MBD_DIAG_SEL1 0x00070000 1268#define MCP_MBD_DIAG_EN1 0x80000000 1269 1270/* MCP_DOTPLL DEFINITIONS */ 1271 1272#define MCP_DOTPLL_P 0x00000003 1273#define MCP_DOTPLL_N 0x000001FC 1274#define MCP_DOTPLL_M 0x00001E00 1275#define MCP_DOTPLL_LOCK 0x02000000 1276#define MCP_DOTPLL_BYPASS 0x00008000 1277