1f29dbc25Smrg/* Copyright (c) 2005 Advanced Micro Devices, Inc.
2f29dbc25Smrg *
3f29dbc25Smrg * Permission is hereby granted, free of charge, to any person obtaining a copy
4f29dbc25Smrg * of this software and associated documentation files (the "Software"), to
5f29dbc25Smrg * deal in the Software without restriction, including without limitation the
6f29dbc25Smrg * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
7f29dbc25Smrg * sell copies of the Software, and to permit persons to whom the Software is
8f29dbc25Smrg * furnished to do so, subject to the following conditions:
9f29dbc25Smrg *
10f29dbc25Smrg * The above copyright notice and this permission notice shall be included in
11f29dbc25Smrg * all copies or substantial portions of the Software.
12f29dbc25Smrg *
13f29dbc25Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14f29dbc25Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15f29dbc25Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
16f29dbc25Smrg * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17f29dbc25Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
18f29dbc25Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
19f29dbc25Smrg * IN THE SOFTWARE.
20f29dbc25Smrg *
21f29dbc25Smrg * Neither the name of the Advanced Micro Devices, Inc. nor the names of its
22f29dbc25Smrg * contributors may be used to endorse or promote products derived from this
23f29dbc25Smrg * software without specific prior written permission.
24f29dbc25Smrg * */
25f29dbc25Smrg
26f29dbc25Smrg/*
27f29dbc25Smrg * This file contains routines to control the SC1200 video input port (VIP)
28f29dbc25Smrg * hardware.
29f29dbc25Smrg * */
30f29dbc25Smrg
31f29dbc25Smrg/*----------------------------------------------------------------------------
32f29dbc25Smrg * gfx_set_vip_enable
33f29dbc25Smrg *
34f29dbc25Smrg * This routine enables or disables the writes to memory from the video port.
35f29dbc25Smrg *----------------------------------------------------------------------------
36f29dbc25Smrg */
37f29dbc25Smrg#if GFX_VIP_DYNAMIC
38f29dbc25Smrgint
39f29dbc25Smrgsc1200_set_vip_enable(int enable)
40f29dbc25Smrg#else
41f29dbc25Smrgint
42f29dbc25Smrggfx_set_vip_enable(int enable)
43f29dbc25Smrg#endif
44f29dbc25Smrg{
45f29dbc25Smrg    unsigned long value;
46f29dbc25Smrg
47f29dbc25Smrg    value = READ_VIP32(SC1200_VIP_CONTROL);
48f29dbc25Smrg    if (enable)
49f29dbc25Smrg        value |= SC1200_VIP_DATA_CAPTURE_EN;
50f29dbc25Smrg    else
51f29dbc25Smrg        value &= ~SC1200_VIP_DATA_CAPTURE_EN;
52f29dbc25Smrg    WRITE_VIP32(SC1200_VIP_CONTROL, value);
53f29dbc25Smrg    return (0);
54f29dbc25Smrg}
55f29dbc25Smrg
56f29dbc25Smrg/*----------------------------------------------------------------------------
57f29dbc25Smrg * gfx_set_vip_capture_run_mode
58f29dbc25Smrg *
59f29dbc25Smrg * This routine selects VIP capture run mode.
60f29dbc25Smrg *----------------------------------------------------------------------------
61f29dbc25Smrg */
62f29dbc25Smrg#if GFX_VIP_DYNAMIC
63f29dbc25Smrgint
64f29dbc25Smrgsc1200_set_vip_capture_run_mode(int mode)
65f29dbc25Smrg#else
66f29dbc25Smrgint
67f29dbc25Smrggfx_set_vip_capture_run_mode(int mode)
68f29dbc25Smrg#endif
69f29dbc25Smrg{
70f29dbc25Smrg    unsigned long value;
71f29dbc25Smrg
72f29dbc25Smrg    value = READ_VIP32(SC1200_VIP_CONTROL);
73f29dbc25Smrg    value &= ~SC1200_CAPTURE_RUN_MODE_MASK;
74f29dbc25Smrg    switch (mode) {
75f29dbc25Smrg    case VIP_CAPTURE_STOP_LINE:
76f29dbc25Smrg        value |= SC1200_CAPTURE_RUN_MODE_STOP_LINE;
77f29dbc25Smrg        break;
78f29dbc25Smrg    case VIP_CAPTURE_STOP_FIELD:
79f29dbc25Smrg        value |= SC1200_CAPTURE_RUN_MODE_STOP_FIELD;
80f29dbc25Smrg        break;
81f29dbc25Smrg    case VIP_CAPTURE_START_FIELD:
82f29dbc25Smrg        value |= SC1200_CAPTURE_RUN_MODE_START;
83f29dbc25Smrg        break;
84f29dbc25Smrg    default:
85f29dbc25Smrg        return GFX_STATUS_BAD_PARAMETER;
86f29dbc25Smrg    }
87f29dbc25Smrg    WRITE_VIP32(SC1200_VIP_CONTROL, value);
88f29dbc25Smrg    return (0);
89f29dbc25Smrg}
90f29dbc25Smrg
91f29dbc25Smrg/*----------------------------------------------------------------------------
92f29dbc25Smrg * gfx_set_vip_base
93f29dbc25Smrg *
94f29dbc25Smrg * This routine sets the odd and even base address values for the VIP memory
95f29dbc25Smrg * buffer.
96f29dbc25Smrg *----------------------------------------------------------------------------
97f29dbc25Smrg */
98f29dbc25Smrg#if GFX_VIP_DYNAMIC
99f29dbc25Smrgint
100f29dbc25Smrgsc1200_set_vip_base(unsigned long even, unsigned long odd)
101f29dbc25Smrg#else
102f29dbc25Smrgint
103f29dbc25Smrggfx_set_vip_base(unsigned long even, unsigned long odd)
104f29dbc25Smrg#endif
105f29dbc25Smrg{
106f29dbc25Smrg    /* TRUE OFFSET IS SPECIFIED, NEED TO SET BIT 23 FOR HARDWARE */
107f29dbc25Smrg
108f29dbc25Smrg    if (even)
109f29dbc25Smrg        WRITE_VIP32(SC1200_VIP_EVEN_BASE,
11004007ebaSmrg                    even + (unsigned long) gfx_phys_fbptr);
111f29dbc25Smrg    if (odd)
11204007ebaSmrg        WRITE_VIP32(SC1200_VIP_ODD_BASE, odd + (unsigned long) gfx_phys_fbptr);
113f29dbc25Smrg    return (0);
114f29dbc25Smrg}
115f29dbc25Smrg
116f29dbc25Smrg/*----------------------------------------------------------------------------
117f29dbc25Smrg * gfx_set_vip_pitch
118f29dbc25Smrg *
119f29dbc25Smrg * This routine sets the number of bytes between scanlines for the VIP data.
120f29dbc25Smrg *----------------------------------------------------------------------------
121f29dbc25Smrg */
122f29dbc25Smrg#if GFX_VIP_DYNAMIC
123f29dbc25Smrgint
124f29dbc25Smrgsc1200_set_vip_pitch(unsigned long pitch)
125f29dbc25Smrg#else
126f29dbc25Smrgint
127f29dbc25Smrggfx_set_vip_pitch(unsigned long pitch)
128f29dbc25Smrg#endif
129f29dbc25Smrg{
130f29dbc25Smrg    WRITE_VIP32(SC1200_VIP_PITCH, pitch & SC1200_VIP_PITCH_MASK);
131f29dbc25Smrg    return (0);
132f29dbc25Smrg}
133f29dbc25Smrg
134f29dbc25Smrg/*----------------------------------------------------------------------------
135f29dbc25Smrg * gfx_set_vip_mode
136f29dbc25Smrg *
137f29dbc25Smrg * This routine sets the VIP operating mode.
138f29dbc25Smrg *----------------------------------------------------------------------------
139f29dbc25Smrg */
140f29dbc25Smrg#if GFX_VIP_DYNAMIC
141f29dbc25Smrgint
142f29dbc25Smrgsc1200_set_vip_mode(int mode)
143f29dbc25Smrg#else
144f29dbc25Smrgint
145f29dbc25Smrggfx_set_vip_mode(int mode)
146f29dbc25Smrg#endif
147f29dbc25Smrg{
148f29dbc25Smrg    unsigned long config;
149f29dbc25Smrg
150f29dbc25Smrg    config = READ_VIP32(SC1200_VIP_CONFIG);
151f29dbc25Smrg    config &= ~SC1200_VIP_MODE_MASK;
152f29dbc25Smrg    switch (mode) {
153f29dbc25Smrg    case VIP_MODE_C:
154f29dbc25Smrg        WRITE_VIP32(SC1200_VIP_CONFIG, config | SC1200_VIP_MODE_C);
155f29dbc25Smrg        break;
156f29dbc25Smrg    default:
157f29dbc25Smrg        return GFX_STATUS_BAD_PARAMETER;
158f29dbc25Smrg    }
159f29dbc25Smrg    return (0);
160f29dbc25Smrg}
161f29dbc25Smrg
162f29dbc25Smrg/*----------------------------------------------------------------------------
163f29dbc25Smrg * gfx_set_vbi_enable
164f29dbc25Smrg *
165f29dbc25Smrg * This routine enables or disables the VBI data capture.
166f29dbc25Smrg *----------------------------------------------------------------------------
167f29dbc25Smrg */
168f29dbc25Smrg#if GFX_VIP_DYNAMIC
169f29dbc25Smrgint
170f29dbc25Smrgsc1200_set_vbi_enable(int enable)
171f29dbc25Smrg#else
172f29dbc25Smrgint
173f29dbc25Smrggfx_set_vbi_enable(int enable)
174f29dbc25Smrg#endif
175f29dbc25Smrg{
176f29dbc25Smrg    unsigned long value;
177f29dbc25Smrg
178f29dbc25Smrg    value = READ_VIP32(SC1200_VIP_CONTROL);
179f29dbc25Smrg    if (enable)
180f29dbc25Smrg        value |= SC1200_VIP_VBI_CAPTURE_EN;
181f29dbc25Smrg    else
182f29dbc25Smrg        value &= ~SC1200_VIP_VBI_CAPTURE_EN;
183f29dbc25Smrg    WRITE_VIP32(SC1200_VIP_CONTROL, value);
184f29dbc25Smrg    return (0);
185f29dbc25Smrg}
186f29dbc25Smrg
187f29dbc25Smrg/*----------------------------------------------------------------------------
188f29dbc25Smrg * gfx_set_vbi_mode
189f29dbc25Smrg *
190f29dbc25Smrg * This routine sets the VBI data types captured to memory.
191f29dbc25Smrg * It receives a mask of all enabled types.
192f29dbc25Smrg *----------------------------------------------------------------------------
193f29dbc25Smrg */
194f29dbc25Smrg#if GFX_VIP_DYNAMIC
195f29dbc25Smrgint
196f29dbc25Smrgsc1200_set_vbi_mode(int mode)
197f29dbc25Smrg#else
198f29dbc25Smrgint
199f29dbc25Smrggfx_set_vbi_mode(int mode)
200f29dbc25Smrg#endif
201f29dbc25Smrg{
202f29dbc25Smrg    unsigned long config;
203f29dbc25Smrg
204f29dbc25Smrg    config = READ_VIP32(SC1200_VIP_CONFIG);
205f29dbc25Smrg    config &=
206f29dbc25Smrg        ~(SC1200_VBI_ANCILLARY_TO_MEMORY | SC1200_VBI_TASK_A_TO_MEMORY |
20704007ebaSmrg          SC1200_VBI_TASK_B_TO_MEMORY);
208f29dbc25Smrg
209f29dbc25Smrg    if (mode & VBI_ANCILLARY)
210f29dbc25Smrg        config |= SC1200_VBI_ANCILLARY_TO_MEMORY;
211f29dbc25Smrg    if (mode & VBI_TASK_A)
212f29dbc25Smrg        config |= SC1200_VBI_TASK_A_TO_MEMORY;
213f29dbc25Smrg    if (mode & VBI_TASK_B)
214f29dbc25Smrg        config |= SC1200_VBI_TASK_B_TO_MEMORY;
215f29dbc25Smrg    WRITE_VIP32(SC1200_VIP_CONFIG, config);
216f29dbc25Smrg    return (0);
217f29dbc25Smrg}
218f29dbc25Smrg
219f29dbc25Smrg/*----------------------------------------------------------------------------
220f29dbc25Smrg * gfx_set_vbi_base
221f29dbc25Smrg *
222f29dbc25Smrg * This routine sets the odd and even base address values for VBI capture.
223f29dbc25Smrg *
224f29dbc25Smrg * "even" and "odd" should contain 16-byte aligned physical addresses.
225f29dbc25Smrg *----------------------------------------------------------------------------
226f29dbc25Smrg */
227f29dbc25Smrg#if GFX_VIP_DYNAMIC
228f29dbc25Smrgint
229f29dbc25Smrgsc1200_set_vbi_base(unsigned long even, unsigned long odd)
230f29dbc25Smrg#else
231f29dbc25Smrgint
232f29dbc25Smrggfx_set_vbi_base(unsigned long even, unsigned long odd)
233f29dbc25Smrg#endif
234f29dbc25Smrg{
235f29dbc25Smrg    /* VIP HW REQUIRES THAT BASE ADDRESSES BE 16-BYTE ALIGNED */
236f29dbc25Smrg
237f29dbc25Smrg    if (even)
238f29dbc25Smrg        WRITE_VIP32(SC1200_VBI_EVEN_BASE, even & ~0xf);
239f29dbc25Smrg    if (odd)
240f29dbc25Smrg        WRITE_VIP32(SC1200_VBI_ODD_BASE, odd & ~0xf);
241f29dbc25Smrg
242f29dbc25Smrg    return (0);
243f29dbc25Smrg}
244f29dbc25Smrg
245f29dbc25Smrg/*----------------------------------------------------------------------------
246f29dbc25Smrg * gfx_set_vbi_pitch
247f29dbc25Smrg *
248f29dbc25Smrg * This routine sets the number of bytes between scanlines for VBI capture.
249f29dbc25Smrg *----------------------------------------------------------------------------
250f29dbc25Smrg */
251f29dbc25Smrg#if GFX_VIP_DYNAMIC
252f29dbc25Smrgint
253f29dbc25Smrgsc1200_set_vbi_pitch(unsigned long pitch)
254f29dbc25Smrg#else
255f29dbc25Smrgint
256f29dbc25Smrggfx_set_vbi_pitch(unsigned long pitch)
257f29dbc25Smrg#endif
258f29dbc25Smrg{
259f29dbc25Smrg    WRITE_VIP32(SC1200_VBI_PITCH, pitch & SC1200_VBI_PITCH_MASK);
260f29dbc25Smrg    return (0);
261f29dbc25Smrg}
262f29dbc25Smrg
263f29dbc25Smrg/*----------------------------------------------------------------------------
264f29dbc25Smrg * gfx_set_vbi_direct
265f29dbc25Smrg *
266f29dbc25Smrg * This routine sets the VBI lines to be passed to the Direct VIP.
267f29dbc25Smrg *----------------------------------------------------------------------------
268f29dbc25Smrg */
269f29dbc25Smrg#if GFX_VIP_DYNAMIC
270f29dbc25Smrgint
271f29dbc25Smrgsc1200_set_vbi_direct(unsigned long even_lines, unsigned long odd_lines)
272f29dbc25Smrg#else
273f29dbc25Smrgint
274f29dbc25Smrggfx_set_vbi_direct(unsigned long even_lines, unsigned long odd_lines)
275f29dbc25Smrg#endif
276f29dbc25Smrg{
277f29dbc25Smrg    WRITE_VIP32(SC1200_EVEN_DIRECT_VBI_LINE_ENABLE,
27804007ebaSmrg                even_lines & SC1200_DIRECT_VBI_LINE_ENABLE_MASK);
279f29dbc25Smrg    WRITE_VIP32(SC1200_ODD_DIRECT_VBI_LINE_ENABLE,
28004007ebaSmrg                odd_lines & SC1200_DIRECT_VBI_LINE_ENABLE_MASK);
281f29dbc25Smrg    return (0);
282f29dbc25Smrg}
283f29dbc25Smrg
284f29dbc25Smrg/*----------------------------------------------------------------------------
285f29dbc25Smrg * gfx_set_vbi_interrupt
286f29dbc25Smrg *
287f29dbc25Smrg * This routine enables or disables the VBI field interrupt.
288f29dbc25Smrg *----------------------------------------------------------------------------
289f29dbc25Smrg */
290f29dbc25Smrg#if GFX_VIP_DYNAMIC
291f29dbc25Smrgint
292f29dbc25Smrgsc1200_set_vbi_interrupt(int enable)
293f29dbc25Smrg#else
294f29dbc25Smrgint
295f29dbc25Smrggfx_set_vbi_interrupt(int enable)
296f29dbc25Smrg#endif
297f29dbc25Smrg{
298f29dbc25Smrg    unsigned long value;
299f29dbc25Smrg
300f29dbc25Smrg    value = READ_VIP32(SC1200_VIP_CONTROL);
301f29dbc25Smrg    if (enable)
302f29dbc25Smrg        value |= SC1200_VIP_VBI_FIELD_INTERRUPT_EN;
303f29dbc25Smrg    else
304f29dbc25Smrg        value &= ~SC1200_VIP_VBI_FIELD_INTERRUPT_EN;
305f29dbc25Smrg    WRITE_VIP32(SC1200_VIP_CONTROL, value);
306f29dbc25Smrg    return (0);
307f29dbc25Smrg}
308f29dbc25Smrg
309f29dbc25Smrg/*----------------------------------------------------------------------------
310f29dbc25Smrg * gfx_set_vip_bus_request_threshold_high
311f29dbc25Smrg *
312f29dbc25Smrg * This routine sets the VIP FIFO bus request threshold.
313f29dbc25Smrg * If enable is TRUE, VIP FIFO will be set to issue a bus request when it
314f29dbc25Smrg * filled with 64 bytes. If enable is FALSE, VIP FIFO will be set to issue a
315f29dbc25Smrg * bus request when it filled with 32 bytes.
316f29dbc25Smrg *----------------------------------------------------------------------------
317f29dbc25Smrg */
318f29dbc25Smrg#if GFX_VIP_DYNAMIC
319f29dbc25Smrgint
320f29dbc25Smrgsc1200_set_vip_bus_request_threshold_high(int enable)
321f29dbc25Smrg#else
322f29dbc25Smrgint
323f29dbc25Smrggfx_set_vip_bus_request_threshold_high(int enable)
324f29dbc25Smrg#endif
325f29dbc25Smrg{
326f29dbc25Smrg    unsigned long value;
327f29dbc25Smrg
328f29dbc25Smrg    value = READ_VIP32(SC1200_VIP_CONFIG);
329f29dbc25Smrg    if (enable)
330f29dbc25Smrg        value &= ~SC1200_VIP_BUS_REQUEST_THRESHOLD;
331f29dbc25Smrg    else
332f29dbc25Smrg        value |= SC1200_VIP_BUS_REQUEST_THRESHOLD;
333f29dbc25Smrg    WRITE_VIP32(SC1200_VIP_CONFIG, value);
334f29dbc25Smrg    return (0);
335f29dbc25Smrg}
336f29dbc25Smrg
337f29dbc25Smrg/*----------------------------------------------------------------------------
338f29dbc25Smrg * gfx_set_vip_last_line
339f29dbc25Smrg *
340f29dbc25Smrg * This routine sets the maximum number of lines captured in each field.
341f29dbc25Smrg *----------------------------------------------------------------------------
342f29dbc25Smrg */
343f29dbc25Smrg#if GFX_VIP_DYNAMIC
344f29dbc25Smrgint
345f29dbc25Smrgsc1200_set_vip_last_line(int last_line)
346f29dbc25Smrg#else
347f29dbc25Smrgint
348f29dbc25Smrggfx_set_vip_last_line(int last_line)
349f29dbc25Smrg#endif
350f29dbc25Smrg{
351f29dbc25Smrg    unsigned long value;
352f29dbc25Smrg
353f29dbc25Smrg    /* This feature is implemented in Rev C1 */
354f29dbc25Smrg    if (gfx_chip_revision < SC1200_REV_C1)
355f29dbc25Smrg        return (GFX_STATUS_OK);
356f29dbc25Smrg
357f29dbc25Smrg    value = READ_VIP32(SC1200_VIP_LINE_TARGET);
358f29dbc25Smrg    value &= ~SC1200_VIP_LAST_LINE_MASK;
359f29dbc25Smrg    value |= ((last_line & 0x3FF) << 16);
360f29dbc25Smrg    WRITE_VIP32(SC1200_VIP_LINE_TARGET, value);
361f29dbc25Smrg    return (GFX_STATUS_OK);
362f29dbc25Smrg}
363f29dbc25Smrg
364f29dbc25Smrg/*----------------------------------------------------------------------------
365f29dbc25Smrg * gfx_test_vip_odd_field
366f29dbc25Smrg *
367f29dbc25Smrg * This routine returns 1 if the current VIP field is odd. Otherwise returns 0
368f29dbc25Smrg *----------------------------------------------------------------------------
369f29dbc25Smrg */
370f29dbc25Smrg#if GFX_VIP_DYNAMIC
371f29dbc25Smrgint
372f29dbc25Smrgsc1200_test_vip_odd_field(void)
373f29dbc25Smrg#else
374f29dbc25Smrgint
375f29dbc25Smrggfx_test_vip_odd_field(void)
376f29dbc25Smrg#endif
377f29dbc25Smrg{
378f29dbc25Smrg    if (READ_VIP32(SC1200_VIP_STATUS) & SC1200_VIP_CURRENT_FIELD_ODD)
379f29dbc25Smrg        return (1);
380f29dbc25Smrg    else
381f29dbc25Smrg        return (0);
382f29dbc25Smrg}
383f29dbc25Smrg
384f29dbc25Smrg/*----------------------------------------------------------------------------
385f29dbc25Smrg * gfx_test_vip_bases_updated
386f29dbc25Smrg *
387f29dbc25Smrg * This routine returns 1 if all of the VIP base registers have been updated,
388f29dbc25Smrg * i.e. there is no base register which has been written with a new address,
389f29dbc25Smrg * that VIP has not already captured or started capturing into the new address
390f29dbc25Smrg *----------------------------------------------------------------------------
391f29dbc25Smrg */
392f29dbc25Smrg#if GFX_VIP_DYNAMIC
393f29dbc25Smrgint
394f29dbc25Smrgsc1200_test_vip_bases_updated(void)
395f29dbc25Smrg#else
396f29dbc25Smrgint
397f29dbc25Smrggfx_test_vip_bases_updated(void)
398f29dbc25Smrg#endif
399f29dbc25Smrg{
400f29dbc25Smrg    if (READ_VIP32(SC1200_VIP_STATUS) & SC1200_VIP_BASE_NOT_UPDATED)
401f29dbc25Smrg        return (0);
402f29dbc25Smrg    else
403f29dbc25Smrg        return (1);
404f29dbc25Smrg}
405f29dbc25Smrg
406f29dbc25Smrg/*----------------------------------------------------------------------------
407f29dbc25Smrg * gfx_test_vip_fifo_overflow
408f29dbc25Smrg *
409f29dbc25Smrg * This routine returns 1 if an overflow occurred on the FIFO between the VIP
410f29dbc25Smrg * and the fast X-bus, 0 otherwise.
411f29dbc25Smrg * If an overflow occurred, the overflow status indication is reset.
412f29dbc25Smrg *----------------------------------------------------------------------------
413f29dbc25Smrg */
414f29dbc25Smrg#if GFX_VIP_DYNAMIC
415f29dbc25Smrgint
416f29dbc25Smrgsc1200_test_vip_fifo_overflow(void)
417f29dbc25Smrg#else
418f29dbc25Smrgint
419f29dbc25Smrggfx_test_vip_fifo_overflow(void)
420f29dbc25Smrg#endif
421f29dbc25Smrg{
422f29dbc25Smrg    if (READ_VIP32(SC1200_VIP_STATUS) & SC1200_VIP_FIFO_OVERFLOW) {
423f29dbc25Smrg        /* Bits in vip status register are either read only or reset by
424f29dbc25Smrg         * writing 1 */
425f29dbc25Smrg        WRITE_VIP32(SC1200_VIP_STATUS, SC1200_VIP_FIFO_OVERFLOW);
426f29dbc25Smrg        return (1);
42704007ebaSmrg    }
42804007ebaSmrg    else {
429f29dbc25Smrg        return (0);
430f29dbc25Smrg    }
431f29dbc25Smrg}
432f29dbc25Smrg
433f29dbc25Smrg/*----------------------------------------------------------------------------
434f29dbc25Smrg * gfx_get_vip_line
435f29dbc25Smrg *
436f29dbc25Smrg * This routine returns the number of the current video line being
437f29dbc25Smrg * received by the VIP interface.
438f29dbc25Smrg *----------------------------------------------------------------------------
439f29dbc25Smrg */
440f29dbc25Smrg#if GFX_VIP_DYNAMIC
441f29dbc25Smrgint
442f29dbc25Smrgsc1200_get_vip_line(void)
443f29dbc25Smrg#else
444f29dbc25Smrgint
445f29dbc25Smrggfx_get_vip_line(void)
446f29dbc25Smrg#endif
447f29dbc25Smrg{
44804007ebaSmrg    return (int) (READ_VIP32(SC1200_VIP_CURRENT_LINE) &
44904007ebaSmrg                  SC1200_VIP_CURRENT_LINE_MASK);
450f29dbc25Smrg}
451f29dbc25Smrg
452f29dbc25Smrg/*----------------------------------------------------------------------------
453f29dbc25Smrg * gfx_get_vip_base
454f29dbc25Smrg *----------------------------------------------------------------------------
455f29dbc25Smrg */
456f29dbc25Smrg#if GFX_VIP_DYNAMIC
457f29dbc25Smrgunsigned long
458f29dbc25Smrgsc1200_get_vip_base(int odd)
459f29dbc25Smrg#else
460f29dbc25Smrgunsigned long
461f29dbc25Smrggfx_get_vip_base(int odd)
462f29dbc25Smrg#endif
463f29dbc25Smrg{
464f29dbc25Smrg    /* MASK BIT 23 AND ABOVE TO MAKE IT A TRUE OFFSET */
465f29dbc25Smrg
466f29dbc25Smrg    if (odd)
467f29dbc25Smrg        return (READ_VIP32(SC1200_VIP_ODD_BASE));
468f29dbc25Smrg    return (READ_VIP32(SC1200_VIP_EVEN_BASE));
469f29dbc25Smrg}
470f29dbc25Smrg
471f29dbc25Smrg/*----------------------------------------------------------------------------
472f29dbc25Smrg * gfx_get_vbi_pitch
473f29dbc25Smrg *----------------------------------------------------------------------------
474f29dbc25Smrg */
475f29dbc25Smrg#if GFX_VIP_DYNAMIC
476f29dbc25Smrgunsigned long
477f29dbc25Smrgsc1200_get_vbi_pitch(void)
478f29dbc25Smrg#else
479f29dbc25Smrgunsigned long
480f29dbc25Smrggfx_get_vbi_pitch(void)
481f29dbc25Smrg#endif
482f29dbc25Smrg{
483f29dbc25Smrg    return (READ_VIP32(SC1200_VBI_PITCH) & SC1200_VBI_PITCH_MASK);
484f29dbc25Smrg}
485f29dbc25Smrg
486f29dbc25Smrg/*************************************************************/
487f29dbc25Smrg/*  READ ROUTINES  |  INCLUDED FOR DIAGNOSTIC PURPOSES ONLY  */
488f29dbc25Smrg/*************************************************************/
489f29dbc25Smrg
490f29dbc25Smrg#if GFX_READ_ROUTINES
491f29dbc25Smrg
492f29dbc25Smrg/*----------------------------------------------------------------------------
493f29dbc25Smrg * gfx_get_vip_enable
494f29dbc25Smrg *----------------------------------------------------------------------------
495f29dbc25Smrg */
496f29dbc25Smrg#if GFX_VIP_DYNAMIC
497f29dbc25Smrgint
498f29dbc25Smrgsc1200_get_vip_enable(void)
499f29dbc25Smrg#else
500f29dbc25Smrgint
501f29dbc25Smrggfx_get_vip_enable(void)
502f29dbc25Smrg#endif
503f29dbc25Smrg{
504f29dbc25Smrg    if (READ_VIP32(SC1200_VIP_CONTROL) & SC1200_VIP_DATA_CAPTURE_EN)
505f29dbc25Smrg        return (1);
506f29dbc25Smrg    return (0);
507f29dbc25Smrg}
508f29dbc25Smrg
509f29dbc25Smrg/*----------------------------------------------------------------------------
510f29dbc25Smrg * gfx_get_vip_pitch
511f29dbc25Smrg *----------------------------------------------------------------------------
512f29dbc25Smrg */
513f29dbc25Smrg#if GFX_VIP_DYNAMIC
514f29dbc25Smrgunsigned long
515f29dbc25Smrgsc1200_get_vip_pitch(void)
516f29dbc25Smrg#else
517f29dbc25Smrgunsigned long
518f29dbc25Smrggfx_get_vip_pitch(void)
519f29dbc25Smrg#endif
520f29dbc25Smrg{
521f29dbc25Smrg    return (READ_VIP32(SC1200_VIP_PITCH) & SC1200_VIP_PITCH_MASK);
522f29dbc25Smrg}
523f29dbc25Smrg
524f29dbc25Smrg/*----------------------------------------------------------------------------
525f29dbc25Smrg * gfx_get_vip_mode
526f29dbc25Smrg *----------------------------------------------------------------------------
527f29dbc25Smrg */
528f29dbc25Smrg#if GFX_VIP_DYNAMIC
529f29dbc25Smrgint
530f29dbc25Smrgsc1200_get_vip_mode(void)
531f29dbc25Smrg#else
532f29dbc25Smrgint
533f29dbc25Smrggfx_get_vip_mode(void)
534f29dbc25Smrg#endif
535f29dbc25Smrg{
536f29dbc25Smrg    switch (READ_VIP32(SC1200_VIP_CONFIG) & SC1200_VIP_MODE_MASK) {
537f29dbc25Smrg    case SC1200_VIP_MODE_C:
538f29dbc25Smrg        return VIP_MODE_C;
539f29dbc25Smrg    default:
540f29dbc25Smrg        return (0);
541f29dbc25Smrg    }
542f29dbc25Smrg}
543f29dbc25Smrg
544f29dbc25Smrg/*----------------------------------------------------------------------------
545f29dbc25Smrg * gfx_get_vbi_enable
546f29dbc25Smrg *----------------------------------------------------------------------------
547f29dbc25Smrg */
548f29dbc25Smrg#if GFX_VIP_DYNAMIC
549f29dbc25Smrgint
550f29dbc25Smrgsc1200_get_vbi_enable(void)
551f29dbc25Smrg#else
552f29dbc25Smrgint
553f29dbc25Smrggfx_get_vbi_enable(void)
554f29dbc25Smrg#endif
555f29dbc25Smrg{
556f29dbc25Smrg    if (READ_VIP32(SC1200_VIP_CONTROL) & SC1200_VIP_VBI_CAPTURE_EN)
557f29dbc25Smrg        return (1);
558f29dbc25Smrg    return (0);
559f29dbc25Smrg}
560f29dbc25Smrg
561f29dbc25Smrg/*----------------------------------------------------------------------------
562f29dbc25Smrg * gfx_get_vbi_mode
563f29dbc25Smrg *----------------------------------------------------------------------------
564f29dbc25Smrg */
565f29dbc25Smrg#if GFX_VIP_DYNAMIC
566f29dbc25Smrgint
567f29dbc25Smrgsc1200_get_vbi_mode(void)
568f29dbc25Smrg#else
569f29dbc25Smrgint
570f29dbc25Smrggfx_get_vbi_mode(void)
571f29dbc25Smrg#endif
572f29dbc25Smrg{
573f29dbc25Smrg    int config;
574f29dbc25Smrg    int mode = 0;
575f29dbc25Smrg
576f29dbc25Smrg    config =
57704007ebaSmrg        (int) (READ_VIP32(SC1200_VIP_CONFIG) & (SC1200_VBI_ANCILLARY_TO_MEMORY
57804007ebaSmrg                                                | SC1200_VBI_TASK_A_TO_MEMORY |
57904007ebaSmrg                                                SC1200_VBI_TASK_B_TO_MEMORY));
580f29dbc25Smrg    if (config & SC1200_VBI_ANCILLARY_TO_MEMORY)
581f29dbc25Smrg        mode |= VBI_ANCILLARY;
582f29dbc25Smrg    if (config & SC1200_VBI_TASK_A_TO_MEMORY)
583f29dbc25Smrg        mode |= VBI_TASK_A;
584f29dbc25Smrg    if (config & SC1200_VBI_TASK_B_TO_MEMORY)
585f29dbc25Smrg        mode |= VBI_TASK_B;
586f29dbc25Smrg    return mode;
587f29dbc25Smrg}
588f29dbc25Smrg
589f29dbc25Smrg/*----------------------------------------------------------------------------
590f29dbc25Smrg * gfx_get_vbi_base
591f29dbc25Smrg *----------------------------------------------------------------------------
592f29dbc25Smrg */
593f29dbc25Smrg#if GFX_VIP_DYNAMIC
594f29dbc25Smrgunsigned long
595f29dbc25Smrgsc1200_get_vbi_base(int odd)
596f29dbc25Smrg#else
597f29dbc25Smrgunsigned long
598f29dbc25Smrggfx_get_vbi_base(int odd)
599f29dbc25Smrg#endif
600f29dbc25Smrg{
601f29dbc25Smrg    /* MASK BIT 23 AND ABOVE TO MAKE IT A TRUE OFFSET */
602f29dbc25Smrg
603f29dbc25Smrg    if (odd)
604f29dbc25Smrg        return (READ_VIP32(SC1200_VBI_ODD_BASE));
605f29dbc25Smrg    return (READ_VIP32(SC1200_VBI_EVEN_BASE));
606f29dbc25Smrg}
607f29dbc25Smrg
608f29dbc25Smrg/*----------------------------------------------------------------------------
609f29dbc25Smrg * gfx_get_vbi_direct
610f29dbc25Smrg *----------------------------------------------------------------------------
611f29dbc25Smrg */
612f29dbc25Smrg#if GFX_VIP_DYNAMIC
613f29dbc25Smrgunsigned long
614f29dbc25Smrgsc1200_get_vbi_direct(int odd)
615f29dbc25Smrg#else
616f29dbc25Smrgunsigned long
617f29dbc25Smrggfx_get_vbi_direct(int odd)
618f29dbc25Smrg#endif
619f29dbc25Smrg{
620f29dbc25Smrg    /* MASK BIT 23 AND ABOVE TO MAKE IT A TRUE OFFSET */
621f29dbc25Smrg
622f29dbc25Smrg    if (odd)
623f29dbc25Smrg        return (READ_VIP32(SC1200_ODD_DIRECT_VBI_LINE_ENABLE) &
62404007ebaSmrg                SC1200_DIRECT_VBI_LINE_ENABLE_MASK);
625f29dbc25Smrg    return (READ_VIP32(SC1200_EVEN_DIRECT_VBI_LINE_ENABLE) &
62604007ebaSmrg            SC1200_DIRECT_VBI_LINE_ENABLE_MASK);
627f29dbc25Smrg}
628f29dbc25Smrg
629f29dbc25Smrg/*---------------------------------------------------------------------------
630f29dbc25Smrg * gfx_get_vbi_interrupt
631f29dbc25Smrg *----------------------------------------------------------------------------
632f29dbc25Smrg */
633f29dbc25Smrg#if GFX_VIP_DYNAMIC
634f29dbc25Smrgint
635f29dbc25Smrgsc1200_get_vbi_interrupt(void)
636f29dbc25Smrg#else
637f29dbc25Smrgint
638f29dbc25Smrggfx_get_vbi_interrupt(void)
639f29dbc25Smrg#endif
640f29dbc25Smrg{
641f29dbc25Smrg    if (READ_VIP32(SC1200_VIP_CONTROL) & SC1200_VIP_VBI_FIELD_INTERRUPT_EN)
642f29dbc25Smrg        return (1);
643f29dbc25Smrg    return (0);
644f29dbc25Smrg}
645f29dbc25Smrg
646f29dbc25Smrg/*----------------------------------------------------------------------------
647f29dbc25Smrg * gfx_get_vip_bus_request_threshold_high
648f29dbc25Smrg *----------------------------------------------------------------------------
649f29dbc25Smrg */
650f29dbc25Smrg#if GFX_VIP_DYNAMIC
651f29dbc25Smrgint
652f29dbc25Smrgsc1200_get_vip_bus_request_threshold_high(void)
653f29dbc25Smrg#else
654f29dbc25Smrgint
655f29dbc25Smrggfx_get_vip_bus_request_threshold_high(void)
656f29dbc25Smrg#endif
657f29dbc25Smrg{
658f29dbc25Smrg    if (READ_VIP32(SC1200_VIP_CONFIG) & SC1200_VIP_BUS_REQUEST_THRESHOLD)
659f29dbc25Smrg        return (1);
660f29dbc25Smrg    return (0);
661f29dbc25Smrg}
662f29dbc25Smrg
66304007ebaSmrg#endif                          /* GFX_READ_ROUTINES */
664f29dbc25Smrg
665f29dbc25Smrg/* END OF FILE */
666