1/* Copyright (c) 2005 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a copy 4 * of this software and associated documentation files (the "Software"), to 5 * deal in the Software without restriction, including without limitation the 6 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 7 * sell copies of the Software, and to permit persons to whom the Software is 8 * furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 18 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 19 * IN THE SOFTWARE. 20 * 21 * Neither the name of the Advanced Micro Devices, Inc. nor the names of its 22 * contributors may be used to endorse or promote products derived from this 23 * software without specific prior written permission. 24 * */ 25 26/* 27 * File Contents: This file contains the panel library files to the 28 * GX2 platforms with 9211 support. 29 * 30 * SubModule: Geode FlatPanel library 31 * */ 32 33/* ----------------------------------------------------------- 34 * GX2 FLAT PANEL CONTROLLER REGISTER DEFINITIONS 35 *----------------------------------------------------------- 36 */ 37 38#define GX2_VP_MSR_PAD_SELECT 0x2011 39#define GX2_VP_PAD_SELECT_MASK 0x3FFFFFFF 40#define GX2_VP_PAD_SELECT_TFT 0x1FFFFFFF 41#define GX2_VP_PAD_SELECT_DSTN 0x00000000 42 43/* This is useful for generating addresses incrementally 44 * (ie, vidtest register display code). 45 */ 46 47#define GX2_FP_LCD_OFFSET 0x00000400 48#define CS9211_REDCLOUD 0x0400 /* Moved 9211 Rev C3 up to next major 49 * no. */ 50#define GX2_FP_PAN_TIMING1 0x0400 /* FP timings 1 */ 51#define GX2_FP_PAN_TIMING2 0x0408 /* FP timings 2 */ 52#define GX2_FP_PWR_MAN 0x0410 /* FP power management */ 53#define GX2_FP_DITH_FR_CNTRL 0x0418 /* FP dither and frame rate */ 54#define GX2_FP_BLFSR 0x0420 /* Blue LFSR seed */ 55#define GX2_FP_RLFSR 0x0428 /* Red and Green LFSR seed */ 56#define GX2_FP_FMI 0x0430 /* FRM Memory Index */ 57#define GX2_FP_FMD 0x0438 /* FRM Memory Data */ 58#define GX2_FP_DCA 0x0448 /* Dither ram control and address */ 59#define GX2_FP_DMD 0x0450 /* Dither memory data */ 60#define GX2_FP_PAN_CRC_SIG 0x0458 /* FP CRC signature */ 61#define GX2_FP_FBB 0x0460 /* Frame Buffer Base Address */ 62 63/* GX2_FP_PAN_TIMING2 bits */ 64 65#define GX2_FP_TFT_PASS_THRU 0x40000000 /* TFT pass through enable */ 66#define GX2_FP_PT2_PIX_OUT_MASK 0xFFF8FFFF /* panel output bit formats */ 67#define GX2_FP_PT2_PIX_OUT_TFT 0x00000000 /* 8 BIT DSTN or TFT panel */ 68#define GX2_FP_PT2_COLOR_MONO 0x00080000 /* color or monochrome */ 69#define GX2_FP_PT2_DSTN_TFT_MASK 0xFFCFFFFF /* panel type bits */ 70#define GX2_FP_PT2_DSTN_TFT_TFT 0x00100000 /* TFT panel */ 71#define GX2_FP_PT2_PSH_CLK_CTL 0x08000000 /* shift clock retrace 72 * activity control */ 73 74/* GX2_FP_PWR_MAN bits */ 75 76#define GX2_FP_PM_SHFCLK_INVERT 0x00002000 /* Invert shfclk to panel */ 77#define GX2_FP_PM_VSYNC_DELAY 0x0000C000 /* Vert Sync delay */ 78#define GX2_FP_PM_HSYNC_DELAY 0x00030000 /* Horiz Sync delay */ 79#define GX2_FP_PM_PWRDN_PHASE_BIT0 0x00040000 /* panel power down phase bit 80 * 0 */ 81#define GX2_FP_PM_PWRDN_PHASE_BIT1 0x00080000 /* panel power down phase bit 82 * 1 */ 83#define GX2_FP_PM_PWRDN_PHASE_BIT2 0x00100000 /* panel power down phase bit 84 * 2 */ 85#define GX2_FP_PM_PWRUP_PHASE_BIT0 0x00200000 /* panel power up phase bit 86 * 0 */ 87#define GX2_FP_PM_PWRUP_PHASE_BIT1 0x00400000 /* panel power up phase bit 88 * 1 */ 89#define GX2_FP_PM_PWRUP_PHASE_BIT2 0x00800000 /* panel power up phase bit 90 * 2 */ 91#define GX2_FP_PM_PWR_ON 0x01000000 /* panel power ON */ 92#define GX2_FP_PM_DIS_OFF_CTL 0x02000000 /* disable the panel back 93 * light */ 94#define GX2_FP_PM_EXT_PWR_SEQ 0x08000000 /* external power sequence */ 95 96/* GX2_FP_PAN_CRC_SIG bits */ 97 98#define GX2_FP_PAN_CRC_SIGE 0x00000001 /* CRC Sig Enable */ 99#define GX2_FP_PAN_CRC_SFR 0x00000002 /* CRC Sig Free Run */ 100 101/* This define is used by the hardware CRC mechanism */ 102#define GX2_FP_CRC_PASS_THRU_MASK 0x00000070 103 104#define GX2_READ 0 105#define GX2_WRITE 1 106 107void SetFPBaseAddr(unsigned long); 108void Redcloud_9211init(Pnl_PanelStat *); 109void protected_mode_access(unsigned long mode, 110 unsigned long width, unsigned long addr, 111 char *pdata); 112void write_video_reg64_low(unsigned long offset, unsigned long value); 113unsigned long read_video_reg64_low(unsigned long offset); 114void Redcloud_fp_reg(int mode, unsigned long address, unsigned long *data); 115void set_Redcloud_92xx_mode_params(int mode); 116unsigned char set_Redcloud_92xx_mode(Pnl_PanelStat * pstat); 117