glint_regs.h revision c35d236e
1c35d236eSmrg/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/glint/glint_regs.h,v 1.36tsi Exp $ */ 2c35d236eSmrg 3c35d236eSmrg/* 4c35d236eSmrg * glint register file 5c35d236eSmrg * 6c35d236eSmrg * Copyright by Stefan Dirsch, Dirk Hohndel, Alan Hourihane 7c35d236eSmrg * Authors: Alan Hourihane, <alanh@fairlite.demon.co.uk> 8c35d236eSmrg * Dirk Hohndel, <hohndel@suse.de> 9c35d236eSmrg * Stefan Dirsch, <sndirsch@suse.de> 10c35d236eSmrg * Simon P., <sim@suse.de> 11c35d236eSmrg * 12c35d236eSmrg * this work is sponsored by S.u.S.E. GmbH, Fuerth, Elsa GmbH, Aachen and 13c35d236eSmrg * Siemens Nixdorf Informationssysteme 14c35d236eSmrg * 15c35d236eSmrg */ 16c35d236eSmrg 17c35d236eSmrg#ifndef _GLINTREG_H_ 18c35d236eSmrg#define _GLINTREG_H_ 19c35d236eSmrg 20c35d236eSmrg#include "compiler.h" 21c35d236eSmrg 22c35d236eSmrg/* The chips we know */ 23c35d236eSmrg#define PCI_CHIP_3DLABS_300SX 0x01 24c35d236eSmrg#define PCI_CHIP_3DLABS_500TX 0x02 25c35d236eSmrg#define PCI_CHIP_3DLABS_DELTA 0x03 26c35d236eSmrg#define PCI_CHIP_3DLABS_PERMEDIA 0x04 27c35d236eSmrg#define PCI_CHIP_3DLABS_MX 0x06 28c35d236eSmrg#define PCI_CHIP_3DLABS_PERMEDIA2 0x07 29c35d236eSmrg#define PCI_CHIP_3DLABS_GAMMA 0x08 30c35d236eSmrg#define PCI_CHIP_3DLABS_PERMEDIA2V 0x09 31c35d236eSmrg#define PCI_CHIP_3DLABS_PERMEDIA3 0x0A 32c35d236eSmrg#define PCI_CHIP_3DLABS_PERMEDIA4 0x0C 33c35d236eSmrg#define PCI_CHIP_3DLABS_R4 0x0D 34c35d236eSmrg#define PCI_CHIP_3DLABS_GAMMA2 0x0E 35c35d236eSmrg 36c35d236eSmrg/* The boards we know */ 37c35d236eSmrg#define IS_GLORIAXXL ((pGlint->PciInfo->subsysVendor == 0x1048) && \ 38c35d236eSmrg (pGlint->PciInfo->subsysCard == 0x0a42)) 39c35d236eSmrg 40c35d236eSmrg#define IS_GLORIASYNERGY ((pGlint->PciInfo->subsysVendor == 0x1048) && \ 41c35d236eSmrg (pGlint->PciInfo->subsysCard == 0x0a32)) 42c35d236eSmrg 43c35d236eSmrg#define IS_GMX2000 ((pGlint->PciInfo->subsysVendor == 0x3d3d) && \ 44c35d236eSmrg (pGlint->PciInfo->subsysCard == 0x0106)) 45c35d236eSmrg 46c35d236eSmrg#define IS_J2000 ((pGlint->PciInfo->subsysVendor == 0x1097) && \ 47c35d236eSmrg (pGlint->PciInfo->subsysCard == 0x3d32)) 48c35d236eSmrg 49c35d236eSmrg#define IS_JPRO ((pGlint->PciInfo->subsysVendor == 0x1097) && \ 50c35d236eSmrg (pGlint->PciInfo->subsysCard == 0x3db3)) 51c35d236eSmrg 52c35d236eSmrg/* COMPAQ OEM VX1 PCI 53c35d236eSmrg * subsys == 0x0121 if VGA is enabled 54c35d236eSmrg * subsys == 0x000a if VGA has never been enabled 55c35d236eSmrg */ 56c35d236eSmrg#define IS_PCI_QVX1 (pGlint->PciInfo->subsysVendor == 0x3d3d && \ 57c35d236eSmrg ((pGlint->PciInfo->subsysCard == 0x0121) || \ 58c35d236eSmrg (pGlint->PciInfo->subsysCard == 0x000a))) 59c35d236eSmrg 60c35d236eSmrg/* COMPAQ OEM VX1 AGP 61c35d236eSmrg * subsys == 0x0144 if VGA is enabled 62c35d236eSmrg * subsys == 0x000c if VGA has never been enabled 63c35d236eSmrg */ 64c35d236eSmrg#define IS_AGP_QVX1 (pGlint->PciInfo->subsysVendor == 0x3d3d && \ 65c35d236eSmrg ((pGlint->PciInfo->subsysCard == 0x0144) || \ 66c35d236eSmrg (pGlint->PciInfo->subsysCard == 0x000c))) 67c35d236eSmrg 68c35d236eSmrg#define IS_QVX1 (IS_PCI_QVX1 || IS_AGP_QVX1) 69c35d236eSmrg 70c35d236eSmrg#define IS_ELSA_SYNERGY ((pGlint->PciInfo->subsysVendor == 0x1048) && \ 71c35d236eSmrg (pGlint->PciInfo->subsysCard == 0x0a32)) 72c35d236eSmrg 73c35d236eSmrg/* COMPAQ OEM Permedia 2V with VGA disable jumper - 0x13e9 ? */ 74c35d236eSmrg#define IS_QPM2V ((pGlint->PciInfo->subsysVendor == 0x13e9) && \ 75c35d236eSmrg ((pGlint->PciInfo->subsysCard == 0x0100) || \ 76c35d236eSmrg (pGlint->PciInfo->subsysCard == 0x0002))) 77c35d236eSmrg 78c35d236eSmrg/********************************************** 79c35d236eSmrg* GLINT 500TX Configuration Region Registers * 80c35d236eSmrg***********************************************/ 81c35d236eSmrg 82c35d236eSmrg/* Device Identification */ 83c35d236eSmrg#define CFGVendorId 0x0000 84c35d236eSmrg#define PCI_VENDOR_3DLABS 0x3D3D 85c35d236eSmrg#define PCI_VENDOR_TI 0x104C 86c35d236eSmrg#define CFGDeviceId 0x0002 87c35d236eSmrg 88c35d236eSmrg#define CFGRevisionId 0x08 89c35d236eSmrg#define CFGClassCode 0x09 90c35d236eSmrg#define CFGHeaderType 0x0E 91c35d236eSmrg 92c35d236eSmrg/* Device Control/Status */ 93c35d236eSmrg#define CFGCommand 0x04 94c35d236eSmrg#define CFGStatus 0x06 95c35d236eSmrg 96c35d236eSmrg/* Miscellaneous Functions */ 97c35d236eSmrg#define CFGBist 0x0f 98c35d236eSmrg#define CFGLatTimer 0x0d 99c35d236eSmrg#define CFGCacheLine 0x0c 100c35d236eSmrg#define CFGMaxLat 0x3f 101c35d236eSmrg#define CFGMinGrant 0x3e 102c35d236eSmrg#define CFGIntPin 0x3d 103c35d236eSmrg#define CFGIntLine 0x3c 104c35d236eSmrg 105c35d236eSmrg/* Base Adresses */ 106c35d236eSmrg#define CFGBaseAddr0 0x10 107c35d236eSmrg#define CFGBaseAddr1 0x14 108c35d236eSmrg#define CFGBaseAddr2 0x18 109c35d236eSmrg#define CFGBaseAddr3 0x1C 110c35d236eSmrg#define CFGBaseAddr4 0x20 111c35d236eSmrg#define CFGRomAddr 0x30 112c35d236eSmrg 113c35d236eSmrg 114c35d236eSmrg 115c35d236eSmrg/********************************** 116c35d236eSmrg * GLINT 500TX Region 0 Registers * 117c35d236eSmrg **********************************/ 118c35d236eSmrg 119c35d236eSmrg/* Control Status Registers */ 120c35d236eSmrg#define ResetStatus 0x0000 121c35d236eSmrg#define IntEnable 0x0008 122c35d236eSmrg#define IntFlags 0x0010 123c35d236eSmrg#define InFIFOSpace 0x0018 124c35d236eSmrg#define OutFIFOWords 0x0020 125c35d236eSmrg#define DMAAddress 0x0028 126c35d236eSmrg#define DMACount 0x0030 127c35d236eSmrg#define ErrorFlags 0x0038 128c35d236eSmrg#define VClkCtl 0x0040 129c35d236eSmrg#define TestRegister 0x0048 130c35d236eSmrg#define Aperture0 0x0050 131c35d236eSmrg#define Aperture1 0x0058 132c35d236eSmrg#define DMAControl 0x0060 133c35d236eSmrg#define FIFODis 0x0068 134c35d236eSmrg 135c35d236eSmrg/* GLINT PerMedia Region 0 additional Registers */ 136c35d236eSmrg#define ChipConfig 0x0070 137c35d236eSmrg#define SCLK_SEL_MASK (3 << 10) 138c35d236eSmrg#define SCLK_SEL_MCLK_HALF (3 << 10) 139c35d236eSmrg#define ByDMAControl 0x00D8 140c35d236eSmrg 141c35d236eSmrg/* GLINT 500TX LocalBuffer Registers */ 142c35d236eSmrg#define LBMemoryCtl 0x1000 143c35d236eSmrg#define LBNumBanksMask 0x00000001 144c35d236eSmrg#define LBNumBanks1 (0) 145c35d236eSmrg#define LBNumBanks2 (1) 146c35d236eSmrg#define LBPageSizeMask 0x00000006 147c35d236eSmrg#define LBPageSize256 (0<<1) 148c35d236eSmrg#define LBPageSize512 (1<<1) 149c35d236eSmrg#define LBPageSize1024 (2<<1) 150c35d236eSmrg#define LBPageSize2048 (3<<1) 151c35d236eSmrg#define LBRASCASLowMask 0x00000018 152c35d236eSmrg#define LBRASCASLow2 (0<<3) 153c35d236eSmrg#define LBRASCASLow3 (1<<3) 154c35d236eSmrg#define LBRASCASLow4 (2<<3) 155c35d236eSmrg#define LBRASCASLow5 (3<<3) 156c35d236eSmrg#define LBRASPrechargeMask 0x00000060 157c35d236eSmrg#define LBRASPrecharge2 (0<<5) 158c35d236eSmrg#define LBRASPrecharge3 (1<<5) 159c35d236eSmrg#define LBRASPrecharge4 (2<<5) 160c35d236eSmrg#define LBRASPrecharge5 (3<<5) 161c35d236eSmrg#define LBCASLowMask 0x00000180 162c35d236eSmrg#define LBCASLow1 (0<<7) 163c35d236eSmrg#define LBCASLow2 (1<<7) 164c35d236eSmrg#define LBCASLow3 (2<<7) 165c35d236eSmrg#define LBCASLow4 (3<<7) 166c35d236eSmrg#define LBPageModeMask 0x00000200 167c35d236eSmrg#define LBPageModeEnabled (0<<9) 168c35d236eSmrg#define LBPageModeDisabled (1<<9) 169c35d236eSmrg#define LBRefreshCountMask 0x0003fc00 170c35d236eSmrg#define LBRefreshCountShift 10 171c35d236eSmrg 172c35d236eSmrg#define LBMemoryEDO 0x1008 173c35d236eSmrg#define LBEDOMask 0x00000001 174c35d236eSmrg#define LBEDODisabled (0) 175c35d236eSmrg#define LBEDOEnabled (1) 176c35d236eSmrg#define LBEDOBankSizeMask 0x0000000e 177c35d236eSmrg#define LBEDOBankSizeDiabled (0<<1) 178c35d236eSmrg#define LBEDOBankSize256K (1<<1) 179c35d236eSmrg#define LBEDOBankSize512K (2<<1) 180c35d236eSmrg#define LBEDOBankSize1M (3<<1) 181c35d236eSmrg#define LBEDOBankSize2M (4<<1) 182c35d236eSmrg#define LBEDOBankSize4M (5<<1) 183c35d236eSmrg#define LBEDOBankSize8M (6<<1) 184c35d236eSmrg#define LBEDOBankSize16M (7<<1) 185c35d236eSmrg#define LBTwoPageDetectorMask 0x00000010 186c35d236eSmrg#define LBSinglePageDetector (0<<4) 187c35d236eSmrg#define LBTwoPageDetector (1<<4) 188c35d236eSmrg 189c35d236eSmrg/* GLINT PerMedia Memory Control Registers */ 190c35d236eSmrg#define PMReboot 0x1000 191c35d236eSmrg#define PMRomControl 0x1040 192c35d236eSmrg#define PMBootAddress 0x1080 193c35d236eSmrg#define PMMemConfig 0x10C0 194c35d236eSmrg# define RowCharge8 1 << 10 195c35d236eSmrg# define TimeRCD8 1 << 7 196c35d236eSmrg# define TimeRC8 0x6 << 3 197c35d236eSmrg# define TimeRP8 1 198c35d236eSmrg# define CAS3Latency8 0 << 16 199c35d236eSmrg# define BootAdress8 0x10 200c35d236eSmrg# define NumberBanks8 0x3 << 29 201c35d236eSmrg# define RefreshCount8 0x41 << 21 202c35d236eSmrg# define TimeRASMin8 1 << 13 203c35d236eSmrg# define DeadCycle8 1 << 17 204c35d236eSmrg# define BankDelay8 0 << 18 205c35d236eSmrg# define Burst1Cycle8 1 << 31 206c35d236eSmrg# define SDRAM8 0 << 4 207c35d236eSmrg 208c35d236eSmrg# define RowCharge6 1 << 10 209c35d236eSmrg# define TimeRCD6 1 << 7 210c35d236eSmrg# define TimeRC6 0x6 << 3 211c35d236eSmrg# define TimeRP6 0x2 212c35d236eSmrg# define CAS3Latency6 1 << 16 213c35d236eSmrg# define BootAdress6 0x60 214c35d236eSmrg# define NumberBanks6 0x2 << 29 215c35d236eSmrg# define RefreshCount6 0x41 << 21 216c35d236eSmrg# define TimeRASMin6 1 << 13 217c35d236eSmrg# define DeadCycle6 1 << 17 218c35d236eSmrg# define BankDelay6 0 << 18 219c35d236eSmrg# define Burst1Cycle6 1 << 31 220c35d236eSmrg# define SDRAM6 0 << 4 221c35d236eSmrg 222c35d236eSmrg# define RowCharge4 0 << 10 223c35d236eSmrg# define TimeRCD4 0 << 7 224c35d236eSmrg# define TimeRC4 0x4 << 3 225c35d236eSmrg# define TimeRP4 1 226c35d236eSmrg# define CAS3Latency4 0 << 16 227c35d236eSmrg# define BootAdress4 0x10 228c35d236eSmrg# define NumberBanks4 1 << 29 229c35d236eSmrg# define RefreshCount4 0x30 << 21 230c35d236eSmrg# define TimeRASMin4 1 << 13 231c35d236eSmrg# define DeadCycle4 0 << 17 232c35d236eSmrg# define BankDelay4 0 << 18 233c35d236eSmrg# define Burst1Cycle4 1 << 31 234c35d236eSmrg# define SDRAM4 0 << 4 235c35d236eSmrg 236c35d236eSmrg/* Permedia 2 Control */ 237c35d236eSmrg#define MemControl 0x1040 238c35d236eSmrg 239c35d236eSmrg#define PMBypassWriteMask 0x1100 240c35d236eSmrg#define PMFramebufferWriteMask 0x1140 241c35d236eSmrg#define PMCount 0x1180 242c35d236eSmrg 243c35d236eSmrg/* Framebuffer Registers */ 244c35d236eSmrg#define FBMemoryCtl 0x1800 245c35d236eSmrg#define FBModeSel 0x1808 246c35d236eSmrg#define FBGCWrMask 0x1810 247c35d236eSmrg#define FBGCColorLower 0x1818 248c35d236eSmrg#define FBTXMemCtl 0x1820 249c35d236eSmrg#define FBWrMaskk 0x1830 250c35d236eSmrg#define FBGCColorUpper 0x1838 251c35d236eSmrg 252c35d236eSmrg/* Core FIFO */ 253c35d236eSmrg#define OutputFIFO 0x2000 254c35d236eSmrg 255c35d236eSmrg/* 500TX Internal Video Registers */ 256c35d236eSmrg#define VTGHLimit 0x3000 257c35d236eSmrg#define VTGHSyncStart 0x3008 258c35d236eSmrg#define VTGHSyncEnd 0x3010 259c35d236eSmrg#define VTGHBlankEnd 0x3018 260c35d236eSmrg#define VTGVLimit 0x3020 261c35d236eSmrg#define VTGVSyncStart 0x3028 262c35d236eSmrg#define VTGVSyncEnd 0x3030 263c35d236eSmrg#define VTGVBlankEnd 0x3038 264c35d236eSmrg#define VTGHGateStart 0x3040 265c35d236eSmrg#define VTGHGateEnd 0x3048 266c35d236eSmrg#define VTGVGateStart 0x3050 267c35d236eSmrg#define VTGVGateEnd 0x3058 268c35d236eSmrg#define VTGPolarity 0x3060 269c35d236eSmrg#define VTGFrameRowAddr 0x3068 270c35d236eSmrg#define VTGVLineNumber 0x3070 271c35d236eSmrg#define VTGSerialClk 0x3078 272c35d236eSmrg#define VTGModeCtl 0x3080 273c35d236eSmrg 274c35d236eSmrg/* Permedia Video Control Registers */ 275c35d236eSmrg#define PMScreenBase 0x3000 276c35d236eSmrg#define PMScreenStride 0x3008 277c35d236eSmrg#define PMHTotal 0x3010 278c35d236eSmrg#define PMHgEnd 0x3018 279c35d236eSmrg#define PMHbEnd 0x3020 280c35d236eSmrg#define PMHsStart 0x3028 281c35d236eSmrg#define PMHsEnd 0x3030 282c35d236eSmrg#define PMVTotal 0x3038 283c35d236eSmrg#define PMVbEnd 0x3040 284c35d236eSmrg#define PMVsStart 0x3048 285c35d236eSmrg#define PMVsEnd 0x3050 286c35d236eSmrg#define PMVideoControl 0x3058 287c35d236eSmrg#define PMInterruptLine 0x3060 288c35d236eSmrg#define PMDDCData 0x3068 289c35d236eSmrg#define DataIn (1<<0) 290c35d236eSmrg#define ClkIn (1<<1) 291c35d236eSmrg#define DataOut (1<<2) 292c35d236eSmrg#define ClkOut (1<<3) 293c35d236eSmrg#define PMLineCount 0x3070 294c35d236eSmrg#define PMFifoControl 0x3078 295c35d236eSmrg 296c35d236eSmrg/* Permedia 2 RAMDAC Registers */ 297c35d236eSmrg#define PM2DACWriteAddress 0x4000 298c35d236eSmrg#define PM2DACIndexReg 0x4000 299c35d236eSmrg#define PM2DACData 0x4008 300c35d236eSmrg#define PM2DACReadMask 0x4010 301c35d236eSmrg#define PM2DACReadAddress 0x4018 302c35d236eSmrg#define PM2DACCursorColorAddress 0x4020 303c35d236eSmrg#define PM2DACCursorColorData 0x4028 304c35d236eSmrg#define PM2DACIndexData 0x4050 305c35d236eSmrg#define PM2DACCursorData 0x4058 306c35d236eSmrg#define PM2DACCursorXLsb 0x4060 307c35d236eSmrg#define PM2DACCursorXMsb 0x4068 308c35d236eSmrg#define PM2DACCursorYLsb 0x4070 309c35d236eSmrg#define PM2DACCursorYMsb 0x4078 310c35d236eSmrg#define PM2DACCursorControl 0x06 311c35d236eSmrg#define PM2DACIndexCMR 0x18 312c35d236eSmrg#define PM2DAC_TRUECOLOR 0x80 313c35d236eSmrg#define PM2DAC_RGB 0x20 314c35d236eSmrg#define PM2DAC_GRAPHICS 0x10 315c35d236eSmrg#define PM2DAC_PACKED 0x09 316c35d236eSmrg#define PM2DAC_8888 0x08 317c35d236eSmrg#define PM2DAC_565 0x06 318c35d236eSmrg#define PM2DAC_4444 0x05 319c35d236eSmrg#define PM2DAC_5551 0x04 320c35d236eSmrg#define PM2DAC_2321 0x03 321c35d236eSmrg#define PM2DAC_2320 0x02 322c35d236eSmrg#define PM2DAC_332 0x01 323c35d236eSmrg#define PM2DAC_CI8 0x00 324c35d236eSmrg#define PM2DACIndexMDCR 0x19 325c35d236eSmrg#define PM2DACIndexPalettePage 0x1c 326c35d236eSmrg#define PM2DACIndexMCR 0x1e 327c35d236eSmrg#define PM2DACIndexClockAM 0x20 328c35d236eSmrg#define PM2DACIndexClockAN 0x21 329c35d236eSmrg#define PM2DACIndexClockAP 0x22 330c35d236eSmrg#define PM2DACIndexClockBM 0x23 331c35d236eSmrg#define PM2DACIndexClockBN 0x24 332c35d236eSmrg#define PM2DACIndexClockBP 0x25 333c35d236eSmrg#define PM2DACIndexClockCM 0x26 334c35d236eSmrg#define PM2DACIndexClockCN 0x27 335c35d236eSmrg#define PM2DACIndexClockCP 0x28 336c35d236eSmrg#define PM2DACIndexClockStatus 0x29 337c35d236eSmrg#define PM2DACIndexMemClockM 0x30 338c35d236eSmrg#define PM2DACIndexMemClockN 0x31 339c35d236eSmrg#define PM2DACIndexMemClockP 0x32 340c35d236eSmrg#define PM2DACIndexMemClockStatus 0x33 341c35d236eSmrg#define PM2DACIndexColorKeyControl 0x40 342c35d236eSmrg#define PM2DACIndexColorKeyOverlay 0x41 343c35d236eSmrg#define PM2DACIndexColorKeyRed 0x42 344c35d236eSmrg#define PM2DACIndexColorKeyGreen 0x43 345c35d236eSmrg#define PM2DACIndexColorKeyBlue 0x44 346c35d236eSmrg 347c35d236eSmrg/* Permedia 2V extensions */ 348c35d236eSmrg#define PM2VDACRDMiscControl 0x000 349c35d236eSmrg#define PM2VDACRDSyncControl 0x001 350c35d236eSmrg#define PM2VDACRDDACControl 0x002 351c35d236eSmrg#define PM2VDACRDPixelSize 0x003 352c35d236eSmrg#define PM2VDACRDColorFormat 0x004 353c35d236eSmrg#define PM2VDACRDCursorMode 0x005 354c35d236eSmrg#define PM2VDACRDCursorXLow 0x007 355c35d236eSmrg#define PM2VDACRDCursorXHigh 0x008 356c35d236eSmrg#define PM2VDACRDCursorYLow 0x009 357c35d236eSmrg#define PM2VDACRDCursorYHigh 0x00A 358c35d236eSmrg#define PM2VDACRDCursorHotSpotX 0x00B 359c35d236eSmrg#define PM2VDACRDCursorHotSpotY 0x00C 360c35d236eSmrg#define PM2VDACRDOverlayKey 0x00D 361c35d236eSmrg#define PM2VDACRDPan 0x00E 362c35d236eSmrg#define PM2VDACRDSense 0x00F 363c35d236eSmrg#define PM2VDACRDCheckControl 0x018 364c35d236eSmrg#define PM2VDACIndexClockControl 0x200 365c35d236eSmrg#define PM2VDACRDDClk0PreScale 0x201 366c35d236eSmrg#define PM2VDACRDDClk0FeedbackScale 0x202 367c35d236eSmrg#define PM2VDACRDDClk0PostScale 0x203 368c35d236eSmrg#define PM2VDACRDDClk1PreScale 0x204 369c35d236eSmrg#define PM2VDACRDDClk1FeedbackScale 0x205 370c35d236eSmrg#define PM2VDACRDDClk1PostScale 0x206 371c35d236eSmrg#define PM2VDACRDMClkControl 0x20D 372c35d236eSmrg#define PM2VDACRDMClkPreScale 0x20E 373c35d236eSmrg#define PM2VDACRDMClkFeedbackScale 0x20F 374c35d236eSmrg#define PM2VDACRDMClkPostScale 0x210 375c35d236eSmrg#define PM2VDACRDCursorPalette 0x303 376c35d236eSmrg#define PM2VDACRDCursorPattern 0x400 377c35d236eSmrg#define PM2VDACIndexRegLow 0x4020 378c35d236eSmrg#define PM2VDACIndexRegHigh 0x4028 379c35d236eSmrg#define PM2VDACIndexData 0x4030 380c35d236eSmrg#define PM2VDACRDIndexControl 0x4038 381c35d236eSmrg 382c35d236eSmrg/* Permedia 2 Video Streams Unit Registers */ 383c35d236eSmrg#define VSBIntFlag (1<<8) 384c35d236eSmrg#define VSAIntFlag (1<<9) 385c35d236eSmrg 386c35d236eSmrg#define VSConfiguration 0x5800 387c35d236eSmrg#define VS_UnitMode_ROM 0 388c35d236eSmrg#define VS_UnitMode_AB8 3 389c35d236eSmrg#define VS_UnitMode_Mask 7 390c35d236eSmrg#define VS_GPBusMode_A (1<<3) 391c35d236eSmrg#define VS_HRefPolarityA (1<<9) 392c35d236eSmrg#define VS_VRefPolarityA (1<<10) 393c35d236eSmrg#define VS_VActivePolarityA (1<<11) 394c35d236eSmrg#define VS_UseFieldA (1<<12) 395c35d236eSmrg#define VS_FieldPolarityA (1<<13) 396c35d236eSmrg#define VS_FieldEdgeA (1<<14) 397c35d236eSmrg#define VS_VActiveVBIA (1<<15) 398c35d236eSmrg#define VS_InterlaceA (1<<16) 399c35d236eSmrg#define VS_ReverseDataA (1<<17) 400c35d236eSmrg#define VS_HRefPolarityB (1<<18) 401c35d236eSmrg#define VS_VRefPolarityB (1<<19) 402c35d236eSmrg#define VS_VActivePolarityB (1<<20) 403c35d236eSmrg#define VS_UseFieldB (1<<21) 404c35d236eSmrg#define VS_FieldPolarityB (1<<22) 405c35d236eSmrg#define VS_FieldEdgeB (1<<23) 406c35d236eSmrg#define VS_VActiveVBIB (1<<24) 407c35d236eSmrg#define VS_InterlaceB (1<<25) 408c35d236eSmrg#define VS_ColorSpaceB_RGB (1<<26) 409c35d236eSmrg#define VS_ReverseDataB (1<<27) 410c35d236eSmrg#define VS_DoubleEdgeB (1<<28) 411c35d236eSmrg 412c35d236eSmrg#define VSStatus 0x5808 413c35d236eSmrg#define VS_FieldOne0A (1<<9) 414c35d236eSmrg#define VS_FieldOne1A (1<<10) 415c35d236eSmrg#define VS_FieldOne2A (1<<11) 416c35d236eSmrg#define VS_InvalidInterlaceA (1<<12) 417c35d236eSmrg#define VS_FieldOne0B (1<<17) 418c35d236eSmrg#define VS_FieldOne1B (1<<18) 419c35d236eSmrg#define VS_FieldOne2B (1<<19) 420c35d236eSmrg#define VS_InvalidInterlaceB (1<<20) 421c35d236eSmrg 422c35d236eSmrg#define VSSerialBusControl 0x5810 423c35d236eSmrg 424c35d236eSmrg#define VSABase 0x5900 425c35d236eSmrg#define VSA_Video (1<<0) 426c35d236eSmrg#define VSA_VBI (1<<1) 427c35d236eSmrg#define VSA_BufferCtl (1<<2) 428c35d236eSmrg#define VSA_MirrorX (1<<7) 429c35d236eSmrg#define VSA_MirrorY (1<<8) 430c35d236eSmrg#define VSA_Discard_None (0<<9) 431c35d236eSmrg#define VSA_Discard_FieldOne (1<<9) 432c35d236eSmrg#define VSA_Discard_FieldTwo (2<<9) 433c35d236eSmrg#define VSA_CombineFields (1<<11) 434c35d236eSmrg#define VSA_LockToStreamB (1<<12) 435c35d236eSmrg#define VSBBase 0x5A00 436c35d236eSmrg#define VSB_Video (1<<0) 437c35d236eSmrg#define VSB_VBI (1<<1) 438c35d236eSmrg#define VSB_BufferCtl (1<<2) 439c35d236eSmrg#define VSB_CombineFields (1<<3) 440c35d236eSmrg#define VSB_RGBOrder (1<<11) 441c35d236eSmrg#define VSB_GammaCorrect (1<<12) 442c35d236eSmrg#define VSB_LockToStreamA (1<<13) 443c35d236eSmrg 444c35d236eSmrg#define VSControl 0x0000 445c35d236eSmrg#define VSInterrupt 0x0008 446c35d236eSmrg#define VSCurrentLine 0x0010 447c35d236eSmrg#define VSVideoAddressHost 0x0018 448c35d236eSmrg#define VSVideoAddressIndex 0x0020 449c35d236eSmrg#define VSVideoAddress0 0x0028 450c35d236eSmrg#define VSVideoAddress1 0x0030 451c35d236eSmrg#define VSVideoAddress2 0x0038 452c35d236eSmrg#define VSVideoStride 0x0040 453c35d236eSmrg#define VSVideoStartLine 0x0048 454c35d236eSmrg#define VSVideoEndLine 0x0050 455c35d236eSmrg#define VSVideoStartData 0x0058 456c35d236eSmrg#define VSVideoEndData 0x0060 457c35d236eSmrg#define VSVBIAddressHost 0x0068 458c35d236eSmrg#define VSVBIAddressIndex 0x0070 459c35d236eSmrg#define VSVBIAddress0 0x0078 460c35d236eSmrg#define VSVBIAddress1 0x0080 461c35d236eSmrg#define VSVBIAddress2 0x0088 462c35d236eSmrg#define VSVBIStride 0x0090 463c35d236eSmrg#define VSVBIStartLine 0x0098 464c35d236eSmrg#define VSVBIEndLine 0x00A0 465c35d236eSmrg#define VSVBIStartData 0x00A8 466c35d236eSmrg#define VSVBIEndData 0x00B0 467c35d236eSmrg#define VSFifoControl 0x00B8 468c35d236eSmrg 469c35d236eSmrg/********************************** 470c35d236eSmrg * GLINT Delta Region 0 Registers * 471c35d236eSmrg **********************************/ 472c35d236eSmrg 473c35d236eSmrg/* Control Status Registers */ 474c35d236eSmrg#define DResetStatus 0x0800 475c35d236eSmrg#define DIntEnable 0x0808 476c35d236eSmrg#define DIntFlags 0x0810 477c35d236eSmrg#define DErrorFlags 0x0838 478c35d236eSmrg#define DTestRegister 0x0848 479c35d236eSmrg#define DFIFODis 0x0868 480c35d236eSmrg 481c35d236eSmrg 482c35d236eSmrg 483c35d236eSmrg/********************************** 484c35d236eSmrg * GLINT Gamma Region 0 Registers * 485c35d236eSmrg **********************************/ 486c35d236eSmrg 487c35d236eSmrg/* Control Status Registers */ 488c35d236eSmrg#define GInFIFOSpace 0x0018 489c35d236eSmrg#define GDMAAddress 0x0028 490c35d236eSmrg#define GDMACount 0x0030 491c35d236eSmrg#define GDMAControl 0x0060 492c35d236eSmrg#define GOutDMA 0x0080 493c35d236eSmrg#define GOutDMACount 0x0088 494c35d236eSmrg#define GResetStatus 0x0800 495c35d236eSmrg#define GIntEnable 0x0808 496c35d236eSmrg#define GIntFlags 0x0810 497c35d236eSmrg#define GErrorFlags 0x0838 498c35d236eSmrg#define GTestRegister 0x0848 499c35d236eSmrg#define GFIFODis 0x0868 500c35d236eSmrg 501c35d236eSmrg#define GChipConfig 0x0870 502c35d236eSmrg#define GChipAGPCapable 1 << 0 503c35d236eSmrg#define GChipAGPSideband 1 << 1 504c35d236eSmrg#define GChipMultiGLINTApMask 3 << 19 505c35d236eSmrg#define GChipMultiGLINTAp_0M 0 << 19 506c35d236eSmrg#define GChipMultiGLINTAp_16M 1 << 19 507c35d236eSmrg#define GChipMultiGLINTAp_32M 2 << 19 508c35d236eSmrg#define GChipMultiGLINTAp_64M 3 << 19 509c35d236eSmrg 510c35d236eSmrg#define GCSRAperture 0x0878 511c35d236eSmrg#define GCSRSecondaryGLINTMapEn 1 << 0 512c35d236eSmrg#define GCSRBitSwap 1 << 1 513c35d236eSmrg 514c35d236eSmrg#define GPageTableAddr 0x0c00 515c35d236eSmrg#define GPageTableLength 0x0c08 516c35d236eSmrg#define GDelayTimer 0x0c38 517c35d236eSmrg#define GCommandMode 0x0c40 518c35d236eSmrg#define GCommandIntEnable 0x0c48 519c35d236eSmrg#define GCommandIntFlags 0x0c50 520c35d236eSmrg#define GCommandErrorFlags 0x0c58 521c35d236eSmrg#define GCommandStatus 0x0c60 522c35d236eSmrg#define GCommandFaultingAddr 0x0c68 523c35d236eSmrg#define GVertexFaultingAddr 0x0c70 524c35d236eSmrg#define GWriteFaultingAddr 0x0c88 525c35d236eSmrg#define GFeedbackSelectCount 0x0c98 526c35d236eSmrg#define GGammaProcessorMode 0x0cb8 527c35d236eSmrg#define GVGAShadow 0x0d00 528c35d236eSmrg#define GMultGLINTAperture 0x0d08 529c35d236eSmrg#define GMultGLINT1 0x0d10 530c35d236eSmrg#define GMultGLINT2 0x0d18 531c35d236eSmrg 532c35d236eSmrg/************************ 533c35d236eSmrg * GLINT Core Registers * 534c35d236eSmrg ************************/ 535c35d236eSmrg 536c35d236eSmrg#define GLINT_TAG(major,offset) (((major) << 7) | ((offset) << 3)) 537c35d236eSmrg#define GLINT_TAG_ADDR(major,offset) (0x8000 | GLINT_TAG((major),(offset))) 538c35d236eSmrg 539c35d236eSmrg#define UNIT_DISABLE 0 540c35d236eSmrg#define UNIT_ENABLE 1 541c35d236eSmrg 542c35d236eSmrg#define StartXDom GLINT_TAG_ADDR(0x00,0x00) 543c35d236eSmrg#define dXDom GLINT_TAG_ADDR(0x00,0x01) 544c35d236eSmrg#define StartXSub GLINT_TAG_ADDR(0x00,0x02) 545c35d236eSmrg#define dXSub GLINT_TAG_ADDR(0x00,0x03) 546c35d236eSmrg#define StartY GLINT_TAG_ADDR(0x00,0x04) 547c35d236eSmrg#define dY GLINT_TAG_ADDR(0x00,0x05) 548c35d236eSmrg#define GLINTCount GLINT_TAG_ADDR(0x00,0x06) 549c35d236eSmrg#define Render GLINT_TAG_ADDR(0x00,0x07) 550c35d236eSmrg# define AreaStippleEnable 0x00001 551c35d236eSmrg# define LineStippleEnable 0x00002 552c35d236eSmrg# define ResetLineStipple 0x00004 553c35d236eSmrg# define FastFillEnable 0x00008 554c35d236eSmrg# define PrimitiveLine 0 555c35d236eSmrg# define PrimitiveTrapezoid 0x00040 556c35d236eSmrg# define PrimitivePoint 0x00080 557c35d236eSmrg# define PrimitiveRectangle 0x000C0 558c35d236eSmrg# define AntialiasEnable 0x00100 559c35d236eSmrg# define AntialiasingQuality 0x00200 560c35d236eSmrg# define UsePointTable 0x00400 561c35d236eSmrg# define SyncOnBitMask 0x00800 562c35d236eSmrg# define SyncOnHostData 0x01000 563c35d236eSmrg# define TextureEnable 0x02000 564c35d236eSmrg# define FogEnable 0x04000 565c35d236eSmrg# define CoverageEnable 0x08000 566c35d236eSmrg# define SubPixelCorrectionEnable 0x10000 567c35d236eSmrg# define SpanOperation 0x40000 568c35d236eSmrg# define XPositive 1<<21 569c35d236eSmrg# define YPositive 1<<22 570c35d236eSmrg 571c35d236eSmrg 572c35d236eSmrg#define ContinueNewLine GLINT_TAG_ADDR(0x00,0x08) 573c35d236eSmrg#define ContinueNewDom GLINT_TAG_ADDR(0x00,0x09) 574c35d236eSmrg#define ContinueNewSub GLINT_TAG_ADDR(0x00,0x0a) 575c35d236eSmrg#define Continue GLINT_TAG_ADDR(0x00,0x0b) 576c35d236eSmrg#define FlushSpan GLINT_TAG_ADDR(0x00,0x0c) 577c35d236eSmrg#define BitMaskPattern GLINT_TAG_ADDR(0x00,0x0d) 578c35d236eSmrg 579c35d236eSmrg#define PointTable0 GLINT_TAG_ADDR(0x01,0x00) 580c35d236eSmrg#define PointTable1 GLINT_TAG_ADDR(0x01,0x01) 581c35d236eSmrg#define PointTable2 GLINT_TAG_ADDR(0x01,0x02) 582c35d236eSmrg#define PointTable3 GLINT_TAG_ADDR(0x01,0x03) 583c35d236eSmrg#define RasterizerMode GLINT_TAG_ADDR(0x01,0x04) 584c35d236eSmrg#define RMMultiGLINT 1<<17 585c35d236eSmrg#define BitMaskPackingEachScanline 1<<9 586c35d236eSmrg#define ForceBackgroundColor 1<<6 587c35d236eSmrg#define InvertBitMask 1<<1 588c35d236eSmrg#define YLimits GLINT_TAG_ADDR(0x01,0x05) 589c35d236eSmrg#define ScanLineOwnership GLINT_TAG_ADDR(0x01,0x06) 590c35d236eSmrg#define WaitForCompletion GLINT_TAG_ADDR(0x01,0x07) 591c35d236eSmrg#define PixelSize GLINT_TAG_ADDR(0x01,0x08) 592c35d236eSmrg#define XLimits GLINT_TAG_ADDR(0x01,0x09) /* PM only */ 593c35d236eSmrg 594c35d236eSmrg#define RectangleOrigin GLINT_TAG_ADDR(0x01,0x0A) /* PM2 only */ 595c35d236eSmrg#define RectangleSize GLINT_TAG_ADDR(0x01,0x0B) /* PM2 only */ 596c35d236eSmrg 597c35d236eSmrg#define PackedDataLimits GLINT_TAG_ADDR(0x02,0x0a) /* PM only */ 598c35d236eSmrg 599c35d236eSmrg#define ScissorMode GLINT_TAG_ADDR(0x03,0x00) 600c35d236eSmrg# define SCI_USER 0x01 601c35d236eSmrg# define SCI_SCREEN 0x02 602c35d236eSmrg# define SCI_USERANDSCREEN 0x03 603c35d236eSmrg 604c35d236eSmrg#define ScissorMinXY GLINT_TAG_ADDR(0x03,0x01) 605c35d236eSmrg#define ScissorMaxXY GLINT_TAG_ADDR(0x03,0x02) 606c35d236eSmrg#define ScreenSize GLINT_TAG_ADDR(0x03,0x03) 607c35d236eSmrg#define AreaStippleMode GLINT_TAG_ADDR(0x03,0x04) 608c35d236eSmrg /* 0: */ 609c35d236eSmrg /* NoMirrorY */ 610c35d236eSmrg /* NoMirrorX */ 611c35d236eSmrg /* NoInvertPattern */ 612c35d236eSmrg /* YAddress_1bit */ 613c35d236eSmrg /* XAddress_1bit */ 614c35d236eSmrg /* UNIT_DISABLE */ 615c35d236eSmrg 616c35d236eSmrg# define ASM_XAddress_2bit 1 << 1 617c35d236eSmrg# define ASM_XAddress_3bit 2 << 1 618c35d236eSmrg# define ASM_XAddress_4bit 3 << 1 619c35d236eSmrg# define ASM_XAddress_5bit 4 << 1 620c35d236eSmrg# define ASM_YAddress_2bit 1 << 4 621c35d236eSmrg# define ASM_YAddress_3bit 2 << 4 622c35d236eSmrg# define ASM_YAddress_4bit 3 << 4 623c35d236eSmrg# define ASM_YAddress_5bit 4 << 4 624c35d236eSmrg# define ASM_InvertPattern 1 << 17 625c35d236eSmrg# define ASM_MirrorX 1 << 18 626c35d236eSmrg# define ASM_MirrorY 1 << 19 627c35d236eSmrg 628c35d236eSmrg#define LineStippleMode GLINT_TAG_ADDR(0x03,0x05) 629c35d236eSmrg#define LoadLineStippleCounters GLINT_TAG_ADDR(0x03,0x06) 630c35d236eSmrg#define UpdateLineStippleCounters GLINT_TAG_ADDR(0x03,0x07) 631c35d236eSmrg#define SaveLineStippleState GLINT_TAG_ADDR(0x03,0x08) 632c35d236eSmrg#define WindowOrigin GLINT_TAG_ADDR(0x03,0x09) 633c35d236eSmrg 634c35d236eSmrg#define AreaStipplePattern0 GLINT_TAG_ADDR(0x04,0x00) 635c35d236eSmrg#define AreaStipplePattern1 GLINT_TAG_ADDR(0x04,0x01) 636c35d236eSmrg#define AreaStipplePattern2 GLINT_TAG_ADDR(0x04,0x02) 637c35d236eSmrg#define AreaStipplePattern3 GLINT_TAG_ADDR(0x04,0x03) 638c35d236eSmrg#define AreaStipplePattern4 GLINT_TAG_ADDR(0x04,0x04) 639c35d236eSmrg#define AreaStipplePattern5 GLINT_TAG_ADDR(0x04,0x05) 640c35d236eSmrg#define AreaStipplePattern6 GLINT_TAG_ADDR(0x04,0x06) 641c35d236eSmrg#define AreaStipplePattern7 GLINT_TAG_ADDR(0x04,0x07) 642c35d236eSmrg 643c35d236eSmrg#define TextureAddressMode GLINT_TAG_ADDR(0x07,0x00) 644c35d236eSmrg#define SStart GLINT_TAG_ADDR(0x07,0x01) 645c35d236eSmrg#define dSdx GLINT_TAG_ADDR(0x07,0x02) 646c35d236eSmrg#define dSdyDom GLINT_TAG_ADDR(0x07,0x03) 647c35d236eSmrg#define TStart GLINT_TAG_ADDR(0x07,0x04) 648c35d236eSmrg#define dTdx GLINT_TAG_ADDR(0x07,0x05) 649c35d236eSmrg#define dTdyDom GLINT_TAG_ADDR(0x07,0x06) 650c35d236eSmrg#define QStart GLINT_TAG_ADDR(0x07,0x07) 651c35d236eSmrg#define dQdx GLINT_TAG_ADDR(0x07,0x08) 652c35d236eSmrg#define dQdyDom GLINT_TAG_ADDR(0x07,0x09) 653c35d236eSmrg#define LOD GLINT_TAG_ADDR(0x07,0x0A) 654c35d236eSmrg#define dSdy GLINT_TAG_ADDR(0x07,0x0B) 655c35d236eSmrg#define dTdy GLINT_TAG_ADDR(0x07,0x0C) 656c35d236eSmrg#define dQdy GLINT_TAG_ADDR(0x07,0x0D) 657c35d236eSmrg 658c35d236eSmrg#define TextureReadMode GLINT_TAG_ADDR(0x09,0x00) 659c35d236eSmrg#define TextureFormat GLINT_TAG_ADDR(0x09,0x01) 660c35d236eSmrg# define Texture_4_Components 3 << 3 661c35d236eSmrg# define Texture_Texel 0 662c35d236eSmrg 663c35d236eSmrg#define TextureCacheControl GLINT_TAG_ADDR(0x09,0x02) 664c35d236eSmrg# define TextureCacheControlEnable 2 665c35d236eSmrg# define TextureCacheControlInvalidate 1 666c35d236eSmrg 667c35d236eSmrg#define GLINTBorderColor GLINT_TAG_ADDR(0x09,0x05) 668c35d236eSmrg 669c35d236eSmrg#define TexelLUTIndex GLINT_TAG_ADDR(0x09,0x08) 670c35d236eSmrg#define TexelLUTData GLINT_TAG_ADDR(0x09,0x09) 671c35d236eSmrg#define TexelLUTAddress GLINT_TAG_ADDR(0x09,0x0A) 672c35d236eSmrg#define TexelLUTTransfer GLINT_TAG_ADDR(0x09,0x0B) 673c35d236eSmrg#define TextureFilterMode GLINT_TAG_ADDR(0x09,0x0C) 674c35d236eSmrg#define TextureChromaUpper GLINT_TAG_ADDR(0x09,0x0D) 675c35d236eSmrg#define TextureChromaLower GLINT_TAG_ADDR(0x09,0x0E) 676c35d236eSmrg 677c35d236eSmrg#define TxBaseAddr0 GLINT_TAG_ADDR(0x0A,0x00) 678c35d236eSmrg#define TxBaseAddr1 GLINT_TAG_ADDR(0x0A,0x01) 679c35d236eSmrg#define TxBaseAddr2 GLINT_TAG_ADDR(0x0A,0x02) 680c35d236eSmrg#define TxBaseAddr3 GLINT_TAG_ADDR(0x0A,0x03) 681c35d236eSmrg#define TxBaseAddr4 GLINT_TAG_ADDR(0x0A,0x04) 682c35d236eSmrg#define TxBaseAddr5 GLINT_TAG_ADDR(0x0A,0x05) 683c35d236eSmrg#define TxBaseAddr6 GLINT_TAG_ADDR(0x0A,0x06) 684c35d236eSmrg#define TxBaseAddr7 GLINT_TAG_ADDR(0x0A,0x07) 685c35d236eSmrg#define TxBaseAddr8 GLINT_TAG_ADDR(0x0A,0x08) 686c35d236eSmrg#define TxBaseAddr9 GLINT_TAG_ADDR(0x0A,0x09) 687c35d236eSmrg#define TxBaseAddr10 GLINT_TAG_ADDR(0x0A,0x0A) 688c35d236eSmrg#define TxBaseAddr11 GLINT_TAG_ADDR(0x0A,0x0B) 689c35d236eSmrg 690c35d236eSmrg#define PMTextureBaseAddress GLINT_TAG_ADDR(0x0b,0x00) 691c35d236eSmrg#define PMTextureMapFormat GLINT_TAG_ADDR(0x0b,0x01) 692c35d236eSmrg#define PMTextureDataFormat GLINT_TAG_ADDR(0x0b,0x02) 693c35d236eSmrg 694c35d236eSmrg#define Texel0 GLINT_TAG_ADDR(0x0c,0x00) 695c35d236eSmrg#define Texel1 GLINT_TAG_ADDR(0x0c,0x01) 696c35d236eSmrg#define Texel2 GLINT_TAG_ADDR(0x0c,0x02) 697c35d236eSmrg#define Texel3 GLINT_TAG_ADDR(0x0c,0x03) 698c35d236eSmrg#define Texel4 GLINT_TAG_ADDR(0x0c,0x04) 699c35d236eSmrg#define Texel5 GLINT_TAG_ADDR(0x0c,0x05) 700c35d236eSmrg#define Texel6 GLINT_TAG_ADDR(0x0c,0x06) 701c35d236eSmrg#define Texel7 GLINT_TAG_ADDR(0x0c,0x07) 702c35d236eSmrg#define Interp0 GLINT_TAG_ADDR(0x0c,0x08) 703c35d236eSmrg#define Interp1 GLINT_TAG_ADDR(0x0c,0x09) 704c35d236eSmrg#define Interp2 GLINT_TAG_ADDR(0x0c,0x0a) 705c35d236eSmrg#define Interp3 GLINT_TAG_ADDR(0x0c,0x0b) 706c35d236eSmrg#define Interp4 GLINT_TAG_ADDR(0x0c,0x0c) 707c35d236eSmrg#define TextureFilter GLINT_TAG_ADDR(0x0c,0x0d) 708c35d236eSmrg#define PMTextureReadMode GLINT_TAG_ADDR(0x0c,0x0e) 709c35d236eSmrg#define TexelLUTMode GLINT_TAG_ADDR(0x0c,0x0f) 710c35d236eSmrg 711c35d236eSmrg#define TextureColorMode GLINT_TAG_ADDR(0x0d,0x00) 712c35d236eSmrg# define TextureTypeOpenGL 0 713c35d236eSmrg# define TextureTypeApple 1 << 4 714c35d236eSmrg# define TextureKsDDA 1 << 5 /* only Apple-Mode */ 715c35d236eSmrg# define TextureKdDDA 1 << 6 /* only Apple-Mode */ 716c35d236eSmrg 717c35d236eSmrg#define TextureEnvColor GLINT_TAG_ADDR(0x0d,0x01) 718c35d236eSmrg#define FogMode GLINT_TAG_ADDR(0x0d,0x02) 719c35d236eSmrg /* 0: */ 720c35d236eSmrg /* FOG RGBA */ 721c35d236eSmrg /* UNIT_DISABLE */ 722c35d236eSmrg 723c35d236eSmrg# define FOG_CI 0x0002 724c35d236eSmrg 725c35d236eSmrg#define FogColor GLINT_TAG_ADDR(0x0d,0x03) 726c35d236eSmrg#define FStart GLINT_TAG_ADDR(0x0d,0x04) 727c35d236eSmrg#define dFdx GLINT_TAG_ADDR(0x0d,0x05) 728c35d236eSmrg#define dFdyDom GLINT_TAG_ADDR(0x0d,0x06) 729c35d236eSmrg#define KsStart GLINT_TAG_ADDR(0x0d,0x09) 730c35d236eSmrg#define dKsdx GLINT_TAG_ADDR(0x0d,0x0a) 731c35d236eSmrg#define dKsdyDom GLINT_TAG_ADDR(0x0d,0x0b) 732c35d236eSmrg#define KdStart GLINT_TAG_ADDR(0x0d,0x0c) 733c35d236eSmrg#define dKdStart GLINT_TAG_ADDR(0x0d,0x0d) 734c35d236eSmrg#define dKddyDom GLINT_TAG_ADDR(0x0d,0x0e) 735c35d236eSmrg 736c35d236eSmrg#define RStart GLINT_TAG_ADDR(0x0f,0x00) 737c35d236eSmrg#define dRdx GLINT_TAG_ADDR(0x0f,0x01) 738c35d236eSmrg#define dRdyDom GLINT_TAG_ADDR(0x0f,0x02) 739c35d236eSmrg#define GStart GLINT_TAG_ADDR(0x0f,0x03) 740c35d236eSmrg#define dGdx GLINT_TAG_ADDR(0x0f,0x04) 741c35d236eSmrg#define dGdyDom GLINT_TAG_ADDR(0x0f,0x05) 742c35d236eSmrg#define BStart GLINT_TAG_ADDR(0x0f,0x06) 743c35d236eSmrg#define dBdx GLINT_TAG_ADDR(0x0f,0x07) 744c35d236eSmrg#define dBdyDom GLINT_TAG_ADDR(0x0f,0x08) 745c35d236eSmrg#define AStart GLINT_TAG_ADDR(0x0f,0x09) 746c35d236eSmrg#define dAdx GLINT_TAG_ADDR(0x0f,0x0a) 747c35d236eSmrg#define dAdyDom GLINT_TAG_ADDR(0x0f,0x0b) 748c35d236eSmrg#define ColorDDAMode GLINT_TAG_ADDR(0x0f,0x0c) 749c35d236eSmrg /* 0: */ 750c35d236eSmrg# define CDDA_FlatShading 0 751c35d236eSmrg /* UNIT_DISABLE */ 752c35d236eSmrg# define CDDA_GouraudShading 0x0002 753c35d236eSmrg 754c35d236eSmrg 755c35d236eSmrg#define ConstantColor GLINT_TAG_ADDR(0x0f,0x0d) 756c35d236eSmrg#define GLINTColor GLINT_TAG_ADDR(0x0f,0x0e) 757c35d236eSmrg#define AlphaTestMode GLINT_TAG_ADDR(0x10,0x00) 758c35d236eSmrg#define AntialiasMode GLINT_TAG_ADDR(0x10,0x01) 759c35d236eSmrg#define AlphaBlendMode GLINT_TAG_ADDR(0x10,0x02) 760c35d236eSmrg /* 0: */ 761c35d236eSmrg /* SrcZERO */ 762c35d236eSmrg /* DstZERO */ 763c35d236eSmrg /* ColorFormat8888 */ 764c35d236eSmrg /* AlphaBuffer present */ 765c35d236eSmrg /* ColorOrderBGR */ 766c35d236eSmrg /* TypeOpenGL */ 767c35d236eSmrg /* DstFBData */ 768c35d236eSmrg /* UNIT_DISABLE */ 769c35d236eSmrg 770c35d236eSmrg# define ABM_SrcONE 1 << 1 771c35d236eSmrg# define ABM_SrcDST_COLOR 2 << 1 772c35d236eSmrg# define ABM_SrcONE_MINUS_DST_COLOR 3 << 1 773c35d236eSmrg# define ABM_SrcSRC_ALPHA 4 << 1 774c35d236eSmrg# define ABM_SrcONE_MINUS_SRC_ALPHA 5 << 1 775c35d236eSmrg# define ABM_SrcDST_ALPHA 6 << 1 776c35d236eSmrg# define ABM_SrcONE_MINUS_DST_ALPHA 7 << 1 777c35d236eSmrg# define ABM_SrcSRC_ALPHA_SATURATE 8 << 1 778c35d236eSmrg# define ABM_DstONE 1 << 5 779c35d236eSmrg# define ABM_DstSRC_COLOR 2 << 5 780c35d236eSmrg# define ABM_DstONE_MINUS_SRC_COLOR 3 << 5 781c35d236eSmrg# define ABM_DstSRC_ALPHA 4 << 5 782c35d236eSmrg# define ABM_DstONE_MINUS_SRC_ALPHA 5 << 5 783c35d236eSmrg# define ABM_DstDST_ALPHA 6 << 5 784c35d236eSmrg# define ABM_DstONE_MINUS_DST_ALPHA 7 << 5 785c35d236eSmrg# define ABM_ColorFormat5555 1 << 8 786c35d236eSmrg# define ABM_ColorFormat4444 2 << 8 787c35d236eSmrg# define ABM_ColorFormat4444_Front 3 << 8 788c35d236eSmrg# define ABM_ColorFormat4444_Back 4 << 8 789c35d236eSmrg# define ABM_ColorFormat332_Front 5 << 8 790c35d236eSmrg# define ABM_ColorFormat332_Back 6 << 8 791c35d236eSmrg# define ABM_ColorFormat121_Front 7 << 8 792c35d236eSmrg# define ABM_ColorFormat121_Back 8 << 8 793c35d236eSmrg# define ABM_ColorFormat555_Back 13 << 8 794c35d236eSmrg# define ABM_ColorFormat_CI8 14 << 8 795c35d236eSmrg# define ABM_ColorFormat_CI4 15 << 8 796c35d236eSmrg# define ABM_NoAlphaBuffer 0x1000 797c35d236eSmrg# define ABM_ColorOrderRGB 0x2000 798c35d236eSmrg# define ABM_TypeQuickDraw3D 0x4000 799c35d236eSmrg# define ABM_DstFBSourceData 0x8000 800c35d236eSmrg 801c35d236eSmrg#define DitherMode GLINT_TAG_ADDR(0x10,0x03) 802c35d236eSmrg /* 0: */ 803c35d236eSmrg /* ColorOrder BGR */ 804c35d236eSmrg /* AlphaDitherDefault */ 805c35d236eSmrg /* ColorFormat8888 */ 806c35d236eSmrg /* TruncateMode */ 807c35d236eSmrg /* DitherDisable */ 808c35d236eSmrg /* UNIT_DISABLE */ 809c35d236eSmrg 810c35d236eSmrg# define DTM_DitherEnable 1 << 1 811c35d236eSmrg# define DTM_ColorFormat5555 1 << 2 812c35d236eSmrg# define DTM_ColorFormat4444 2 << 2 813c35d236eSmrg# define DTM_ColorFormat4444_Front 3 << 2 814c35d236eSmrg# define DTM_ColorFormat4444_Back 4 << 2 815c35d236eSmrg# define DTM_ColorFormat332_Front 5 << 2 816c35d236eSmrg# define DTM_ColorFormat332_Back 6 << 2 817c35d236eSmrg# define DTM_ColorFormat121_Front 7 << 2 818c35d236eSmrg# define DTM_ColorFormat121_Back 8 << 2 819c35d236eSmrg# define DTM_ColorFormat555_Back 13 << 2 820c35d236eSmrg# define DTM_ColorFormat_CI8 14 << 2 821c35d236eSmrg# define DTM_ColorFormat_CI4 15 << 2 822c35d236eSmrg# define DTM_ColorOrderRGB 1 << 10 823c35d236eSmrg# define DTM_NoAlphaDither 1 << 14 824c35d236eSmrg# define DTM_RoundMode 1 << 15 825c35d236eSmrg 826c35d236eSmrg#define FBSoftwareWriteMask GLINT_TAG_ADDR(0x10,0x04) 827c35d236eSmrg#define LogicalOpMode GLINT_TAG_ADDR(0x10,0x05) 828c35d236eSmrg# define Use_ConstantFBWriteData 0x40 829c35d236eSmrg 830c35d236eSmrg 831c35d236eSmrg#define FBWriteData GLINT_TAG_ADDR(0x10,0x06) 832c35d236eSmrg#define RouterMode GLINT_TAG_ADDR(0x10,0x08) 833c35d236eSmrg# define ROUTER_Depth_Texture 1 834c35d236eSmrg# define ROUTER_Texture_Depth 0 835c35d236eSmrg 836c35d236eSmrg 837c35d236eSmrg#define LBReadMode GLINT_TAG_ADDR(0x11,0x00) 838c35d236eSmrg /* 0: */ 839c35d236eSmrg /* SrcNoRead */ 840c35d236eSmrg /* DstNoRead */ 841c35d236eSmrg /* DataLBDefault */ 842c35d236eSmrg /* WinTopLeft */ 843c35d236eSmrg /* NoPatch */ 844c35d236eSmrg /* ScanlineInterval1 */ 845c35d236eSmrg 846c35d236eSmrg# define LBRM_SrcEnable 1 << 9 847c35d236eSmrg# define LBRM_DstEnable 1 << 10 848c35d236eSmrg# define LBRM_DataLBStencil 1 << 16 849c35d236eSmrg# define LBRM_DataLBDepth 2 << 16 850c35d236eSmrg# define LBRM_WinBottomLeft 1 << 18 851c35d236eSmrg# define LBRM_DoPatch 1 << 19 852c35d236eSmrg 853c35d236eSmrg# define LBRM_ScanlineInt2 1 << 20 854c35d236eSmrg# define LBRM_ScanlineInt4 2 << 20 855c35d236eSmrg# define LBRM_ScanlineInt8 3 << 20 856c35d236eSmrg 857c35d236eSmrg 858c35d236eSmrg#define LBReadFormat GLINT_TAG_ADDR(0x11,0x01) 859c35d236eSmrg# define LBRF_DepthWidth15 0x03 /* only permedia */ 860c35d236eSmrg# define LBRF_DepthWidth16 0x00 861c35d236eSmrg# define LBRF_DepthWidth24 0x01 862c35d236eSmrg# define LBRF_DepthWidth32 0x02 863c35d236eSmrg 864c35d236eSmrg# define LBRF_StencilWidth0 (0 << 2) 865c35d236eSmrg# define LBRF_StencilWidth4 (1 << 2) 866c35d236eSmrg# define LBRF_StencilWidth8 (2 << 2) 867c35d236eSmrg 868c35d236eSmrg# define LBRF_StencilPos16 (0 << 4) 869c35d236eSmrg# define LBRF_StencilPos20 (1 << 4) 870c35d236eSmrg# define LBRF_StencilPos24 (2 << 4) 871c35d236eSmrg# define LBRF_StencilPos28 (3 << 4) 872c35d236eSmrg# define LBRF_StencilPos32 (4 << 4) 873c35d236eSmrg 874c35d236eSmrg# define LBRF_FrameCount0 (0 << 7) 875c35d236eSmrg# define LBRF_FrameCount4 (1 << 7) 876c35d236eSmrg# define LBRF_FrameCount8 (2 << 7) 877c35d236eSmrg 878c35d236eSmrg# define LBRF_FrameCountPos16 (0 << 9) 879c35d236eSmrg# define LBRF_FrameCountPos20 (1 << 9) 880c35d236eSmrg# define LBRF_FrameCountPos24 (2 << 9) 881c35d236eSmrg# define LBRF_FrameCountPos28 (3 << 9) 882c35d236eSmrg# define LBRF_FrameCountPos32 (4 << 9) 883c35d236eSmrg# define LBRF_FrameCountPos36 (5 << 9) 884c35d236eSmrg# define LBRF_FrameCountPos40 (6 << 9) 885c35d236eSmrg 886c35d236eSmrg# define LBRF_GIDWidth0 (0 << 12) 887c35d236eSmrg# define LBRF_GIDWidth4 (1 << 12) 888c35d236eSmrg 889c35d236eSmrg# define LBRF_GIDPos16 (0 << 13) 890c35d236eSmrg# define LBRF_GIDPos20 (1 << 13) 891c35d236eSmrg# define LBRF_GIDPos24 (2 << 13) 892c35d236eSmrg# define LBRF_GIDPos28 (3 << 13) 893c35d236eSmrg# define LBRF_GIDPos32 (4 << 13) 894c35d236eSmrg# define LBRF_GIDPos36 (5 << 13) 895c35d236eSmrg# define LBRF_GIDPos40 (6 << 13) 896c35d236eSmrg# define LBRF_GIDPos44 (7 << 13) 897c35d236eSmrg# define LBRF_GIDPos48 (8 << 13) 898c35d236eSmrg 899c35d236eSmrg# define LBRF_Compact32 (1 << 17) 900c35d236eSmrg 901c35d236eSmrg 902c35d236eSmrg 903c35d236eSmrg#define LBSourceOffset GLINT_TAG_ADDR(0x11,0x02) 904c35d236eSmrg#define LBStencil GLINT_TAG_ADDR(0x11,0x05) 905c35d236eSmrg#define LBDepth GLINT_TAG_ADDR(0x11,0x06) 906c35d236eSmrg#define LBWindowBase GLINT_TAG_ADDR(0x11,0x07) 907c35d236eSmrg#define LBWriteMode GLINT_TAG_ADDR(0x11,0x08) 908c35d236eSmrg# define LBWM_WriteEnable 0x1 909c35d236eSmrg# define LBWM_UpLoad_LBDepth 0x2 910c35d236eSmrg# define LBWM_UpLoad_LBStencil 0x4 911c35d236eSmrg 912c35d236eSmrg#define LBWriteFormat GLINT_TAG_ADDR(0x11,0x09) 913c35d236eSmrg 914c35d236eSmrg 915c35d236eSmrg#define TextureData GLINT_TAG_ADDR(0x11,0x0d) 916c35d236eSmrg#define TextureDownloadOffset GLINT_TAG_ADDR(0x11,0x0e) 917c35d236eSmrg#define LBWindowOffset GLINT_TAG_ADDR(0x11,0x0f) 918c35d236eSmrg 919c35d236eSmrg#define GLINTWindow GLINT_TAG_ADDR(0x13,0x00) 920c35d236eSmrg# define GWIN_UnitEnable (1 << 0) 921c35d236eSmrg# define GWIN_ForceLBUpdate (1 << 3) 922c35d236eSmrg# define GWIN_LBUpdateSourceREG (1 << 4) 923c35d236eSmrg# define GWIN_LBUpdateSourceLB (0 << 4) 924c35d236eSmrg# define GWIN_StencilFCP (1 << 17) 925c35d236eSmrg# define GWIN_DepthFCP (1 << 18) 926c35d236eSmrg# define GWIN_OverrideWriteFilter (1 << 19) 927c35d236eSmrg 928c35d236eSmrg /* ??? is this needed, set by permedia (2) modules */ 929c35d236eSmrg# define GWIN_DisableLBUpdate 0x40000 930c35d236eSmrg 931c35d236eSmrg#define StencilMode GLINT_TAG_ADDR(0x13,0x01) 932c35d236eSmrg#define StencilData GLINT_TAG_ADDR(0x13,0x02) 933c35d236eSmrg#define GLINTStencil GLINT_TAG_ADDR(0x13,0x03) 934c35d236eSmrg#define DepthMode GLINT_TAG_ADDR(0x13,0x04) 935c35d236eSmrg /* 0: */ 936c35d236eSmrg /* WriteDisable */ 937c35d236eSmrg /* SrcCompFragment */ 938c35d236eSmrg /* CompFuncNEVER */ 939c35d236eSmrg /* UNIT_DISABLE */ 940c35d236eSmrg 941c35d236eSmrg# define DPM_WriteEnable 1 << 1 942c35d236eSmrg# define DPM_SrcCompLBData 1 << 2 943c35d236eSmrg# define DPM_SrcCompDregister 2 << 2 944c35d236eSmrg# define DPM_SrcCompLBSourceData 3 << 2 945c35d236eSmrg# define DPM_CompFuncLESS 1 << 4 946c35d236eSmrg# define DPM_CompFuncEQUAL 2 << 4 947c35d236eSmrg# define DPM_CompFuncLESS_OR_EQ 3 << 4 948c35d236eSmrg# define DPM_CompFuncGREATER 4 << 4 949c35d236eSmrg# define DPM_CompFuncNOT_EQ 5 << 4 950c35d236eSmrg# define DPM_CompFuncGREATER_OR_EQ 6 << 4 951c35d236eSmrg# define DPM_CompFuncALWAYS 7 << 4 952c35d236eSmrg 953c35d236eSmrg#define GLINTDepth GLINT_TAG_ADDR(0x13,0x05) 954c35d236eSmrg#define ZStartU GLINT_TAG_ADDR(0x13,0x06) 955c35d236eSmrg#define ZStartL GLINT_TAG_ADDR(0x13,0x07) 956c35d236eSmrg#define dZdxU GLINT_TAG_ADDR(0x13,0x08) 957c35d236eSmrg#define dZdxL GLINT_TAG_ADDR(0x13,0x09) 958c35d236eSmrg#define dZdyDomU GLINT_TAG_ADDR(0x13,0x0a) 959c35d236eSmrg#define dZdyDomL GLINT_TAG_ADDR(0x13,0x0b) 960c35d236eSmrg#define FastClearDepth GLINT_TAG_ADDR(0x13,0x0c) 961c35d236eSmrg 962c35d236eSmrg#define FBReadMode GLINT_TAG_ADDR(0x15,0x00) 963c35d236eSmrg /* 0: */ 964c35d236eSmrg /* SrcNoRead */ 965c35d236eSmrg /* DstNoRead */ 966c35d236eSmrg /* DataFBDefault */ 967c35d236eSmrg /* WinTopLeft */ 968c35d236eSmrg /* ScanlineInterval1 */ 969c35d236eSmrg 970c35d236eSmrg# define FBRM_SrcEnable 1 << 9 971c35d236eSmrg# define FBRM_DstEnable 1 << 10 972c35d236eSmrg# define FBRM_DataFBColor 1 << 15 973c35d236eSmrg# define FBRM_WinBottomLeft 1 << 16 974c35d236eSmrg# define FBRM_Packed 1 << 19 975c35d236eSmrg# define FBRM_ScanlineInt2 1 << 23 976c35d236eSmrg# define FBRM_ScanlineInt4 2 << 23 977c35d236eSmrg# define FBRM_ScanlineInt8 3 << 23 978c35d236eSmrg 979c35d236eSmrg 980c35d236eSmrg#define FBSourceOffset GLINT_TAG_ADDR(0x15,0x01) 981c35d236eSmrg#define FBPixelOffset GLINT_TAG_ADDR(0x15,0x02) 982c35d236eSmrg#define FBColor GLINT_TAG_ADDR(0x15,0x03) 983c35d236eSmrg#define FBData GLINT_TAG_ADDR(0x15,0x04) 984c35d236eSmrg#define FBSourceData GLINT_TAG_ADDR(0x15,0x05) 985c35d236eSmrg 986c35d236eSmrg#define FBWindowBase GLINT_TAG_ADDR(0x15,0x06) 987c35d236eSmrg#define FBWriteMode GLINT_TAG_ADDR(0x15,0x07) 988c35d236eSmrg /* 0: */ 989c35d236eSmrg /* FBWM_NoColorUpload */ 990c35d236eSmrg /* FBWM_WriteDisable */ 991c35d236eSmrg# define FBWM_WriteEnable 1 992c35d236eSmrg# define FBWM_UploadColor 1 << 3 993c35d236eSmrg/* Permedia3 extensions */ 994c35d236eSmrg# define FBWM_Enable0 1 << 12 995c35d236eSmrg 996c35d236eSmrg#define FBHardwareWriteMask GLINT_TAG_ADDR(0x15,0x08) 997c35d236eSmrg#define FBBlockColor GLINT_TAG_ADDR(0x15,0x09) 998c35d236eSmrg#define FBReadPixel GLINT_TAG_ADDR(0x15,0x0a) /* PM */ 999c35d236eSmrg#define PatternRamMode GLINT_TAG_ADDR(0x15,0x0f) 1000c35d236eSmrg 1001c35d236eSmrg#define PatternRamData0 GLINT_TAG_ADDR(0x16,0x00) 1002c35d236eSmrg#define PatternRamData1 GLINT_TAG_ADDR(0x16,0x01) 1003c35d236eSmrg#define PatternRamData2 GLINT_TAG_ADDR(0x16,0x02) 1004c35d236eSmrg#define PatternRamData3 GLINT_TAG_ADDR(0x16,0x03) 1005c35d236eSmrg#define PatternRamData4 GLINT_TAG_ADDR(0x16,0x04) 1006c35d236eSmrg#define PatternRamData5 GLINT_TAG_ADDR(0x16,0x05) 1007c35d236eSmrg#define PatternRamData6 GLINT_TAG_ADDR(0x16,0x06) 1008c35d236eSmrg#define PatternRamData7 GLINT_TAG_ADDR(0x16,0x07) 1009c35d236eSmrg 1010c35d236eSmrg#define FilterMode GLINT_TAG_ADDR(0x18,0x00) 1011c35d236eSmrg /* 0: */ 1012c35d236eSmrg /* CullDepthTags */ 1013c35d236eSmrg /* CullDepthData */ 1014c35d236eSmrg /* CullStencilTags */ 1015c35d236eSmrg /* CullStencilData */ 1016c35d236eSmrg /* CullColorTag */ 1017c35d236eSmrg /* CullColorData */ 1018c35d236eSmrg /* CullSyncTag */ 1019c35d236eSmrg /* CullSyncData */ 1020c35d236eSmrg /* CullStatisticTag */ 1021c35d236eSmrg /* CullStatisticData */ 1022c35d236eSmrg 1023c35d236eSmrg# define FM_PassDepthTags 0x0010 1024c35d236eSmrg# define FM_PassDepthData 0x0020 1025c35d236eSmrg# define FM_PassStencilTags 0x0040 1026c35d236eSmrg# define FM_PassStencilData 0x0080 1027c35d236eSmrg# define FM_PassColorTag 0x0100 1028c35d236eSmrg# define FM_PassColorData 0x0200 1029c35d236eSmrg# define FM_PassSyncTag 0x0400 1030c35d236eSmrg# define FM_PassSyncData 0x0800 1031c35d236eSmrg# define FM_PassStatisticTag 0x1000 1032c35d236eSmrg# define FM_PassStatisticData 0x2000 1033c35d236eSmrg 1034c35d236eSmrg#define Sync_tag 0x0188 1035c35d236eSmrg 1036c35d236eSmrg#define StatisticMode GLINT_TAG_ADDR(0x18,0x01) 1037c35d236eSmrg#define MinRegion GLINT_TAG_ADDR(0x18,0x02) 1038c35d236eSmrg#define MaxRegion GLINT_TAG_ADDR(0x18,0x03) 1039c35d236eSmrg#define ResetPickResult GLINT_TAG_ADDR(0x18,0x04) 1040c35d236eSmrg#define MitHitRegion GLINT_TAG_ADDR(0x18,0x05) 1041c35d236eSmrg#define MaxHitRegion GLINT_TAG_ADDR(0x18,0x06) 1042c35d236eSmrg#define PickResult GLINT_TAG_ADDR(0x18,0x07) 1043c35d236eSmrg#define GlintSync GLINT_TAG_ADDR(0x18,0x08) 1044c35d236eSmrg 1045c35d236eSmrg#define FBBlockColorU GLINT_TAG_ADDR(0x18,0x0d) 1046c35d236eSmrg#define FBBlockColorL GLINT_TAG_ADDR(0x18,0x0e) 1047c35d236eSmrg#define SuspendUntilFrameBlank GLINT_TAG_ADDR(0x18,0x0f) 1048c35d236eSmrg 1049c35d236eSmrg#define KsRStart GLINT_TAG_ADDR(0x19,0x00) 1050c35d236eSmrg#define dKsRdx GLINT_TAG_ADDR(0x19,0x01) 1051c35d236eSmrg#define dKsRdyDom GLINT_TAG_ADDR(0x19,0x02) 1052c35d236eSmrg#define KsGStart GLINT_TAG_ADDR(0x19,0x03) 1053c35d236eSmrg#define dKsGdx GLINT_TAG_ADDR(0x19,0x04) 1054c35d236eSmrg#define dKsGdyDom GLINT_TAG_ADDR(0x19,0x05) 1055c35d236eSmrg#define KsBStart GLINT_TAG_ADDR(0x19,0x06) 1056c35d236eSmrg#define dKsBdx GLINT_TAG_ADDR(0x19,0x07) 1057c35d236eSmrg#define dKsBdyDom GLINT_TAG_ADDR(0x19,0x08) 1058c35d236eSmrg 1059c35d236eSmrg#define KdRStart GLINT_TAG_ADDR(0x1A,0x00) 1060c35d236eSmrg#define dKdRdx GLINT_TAG_ADDR(0x1A,0x01) 1061c35d236eSmrg#define dKdRdyDom GLINT_TAG_ADDR(0x1A,0x02) 1062c35d236eSmrg#define KdGStart GLINT_TAG_ADDR(0x1A,0x03) 1063c35d236eSmrg#define dKdGdx GLINT_TAG_ADDR(0x1A,0x04) 1064c35d236eSmrg#define dKdGdyDom GLINT_TAG_ADDR(0x1A,0x05) 1065c35d236eSmrg#define KdBStart GLINT_TAG_ADDR(0x1A,0x06) 1066c35d236eSmrg#define dKdBdx GLINT_TAG_ADDR(0x1A,0x07) 1067c35d236eSmrg#define dKdBdyDom GLINT_TAG_ADDR(0x1A,0x08) 1068c35d236eSmrg 1069c35d236eSmrg#define FBSourceBase GLINT_TAG_ADDR(0x1B,0x00) 1070c35d236eSmrg#define FBSourceDelta GLINT_TAG_ADDR(0x1B,0x01) 1071c35d236eSmrg#define Config GLINT_TAG_ADDR(0x1B,0x02) 1072c35d236eSmrg#define CFBRM_SrcEnable 1<<0 1073c35d236eSmrg#define CFBRM_DstEnable 1<<1 1074c35d236eSmrg#define CFBRM_Packed 1<<2 1075c35d236eSmrg#define CWM_Enable 1<<3 1076c35d236eSmrg#define CCDDA_Enable 1<<4 1077c35d236eSmrg#define CLogOp_Enable 1<<5 1078c35d236eSmrg#define ContextDump GLINT_TAG_ADDR(0x1B,0x08) 1079c35d236eSmrg#define ContextRestore GLINT_TAG_ADDR(0x1B,0x09) 1080c35d236eSmrg#define ContextData GLINT_TAG_ADDR(0x1B,0x0a) 1081c35d236eSmrg 1082c35d236eSmrg#define TexelLUT0 GLINT_TAG_ADDR(0x1D,0x00) 1083c35d236eSmrg#define TexelLUT1 GLINT_TAG_ADDR(0x1D,0x01) 1084c35d236eSmrg#define TexelLUT2 GLINT_TAG_ADDR(0x1D,0x02) 1085c35d236eSmrg#define TexelLUT3 GLINT_TAG_ADDR(0x1D,0x03) 1086c35d236eSmrg#define TexelLUT4 GLINT_TAG_ADDR(0x1D,0x04) 1087c35d236eSmrg#define TexelLUT5 GLINT_TAG_ADDR(0x1D,0x05) 1088c35d236eSmrg#define TexelLUT6 GLINT_TAG_ADDR(0x1D,0x06) 1089c35d236eSmrg#define TexelLUT7 GLINT_TAG_ADDR(0x1D,0x07) 1090c35d236eSmrg#define TexelLUT8 GLINT_TAG_ADDR(0x1D,0x08) 1091c35d236eSmrg#define TexelLUT9 GLINT_TAG_ADDR(0x1D,0x09) 1092c35d236eSmrg#define TexelLUT10 GLINT_TAG_ADDR(0x1D,0x0A) 1093c35d236eSmrg#define TexelLUT11 GLINT_TAG_ADDR(0x1D,0x0B) 1094c35d236eSmrg#define TexelLUT12 GLINT_TAG_ADDR(0x1D,0x0C) 1095c35d236eSmrg#define TexelLUT13 GLINT_TAG_ADDR(0x1D,0x0D) 1096c35d236eSmrg#define TexelLUT14 GLINT_TAG_ADDR(0x1D,0x0E) 1097c35d236eSmrg#define TexelLUT15 GLINT_TAG_ADDR(0x1D,0x0F) 1098c35d236eSmrg 1099c35d236eSmrg#define YUVMode GLINT_TAG_ADDR(0x1E,0x00) 1100c35d236eSmrg#define ChromaUpper GLINT_TAG_ADDR(0x1E,0x01) 1101c35d236eSmrg#define ChromaLower GLINT_TAG_ADDR(0x1E,0x02) 1102c35d236eSmrg#define ChromaTestMode GLINT_TAG_ADDR(0x1E,0x03) 1103c35d236eSmrg 1104c35d236eSmrg 1105c35d236eSmrg/****************************** 1106c35d236eSmrg * GLINT Delta Core Registers * 1107c35d236eSmrg ******************************/ 1108c35d236eSmrg 1109c35d236eSmrg#define V0FixedTag GLINT_TAG_ADDR(0x20,0x00) 1110c35d236eSmrg#define V1FixedTag GLINT_TAG_ADDR(0x21,0x00) 1111c35d236eSmrg#define V2FixedTag GLINT_TAG_ADDR(0x22,0x00) 1112c35d236eSmrg#define V0FloatTag GLINT_TAG_ADDR(0x23,0x00) 1113c35d236eSmrg#define V1FloatTag GLINT_TAG_ADDR(0x24,0x00) 1114c35d236eSmrg#define V2FloatTag GLINT_TAG_ADDR(0x25,0x00) 1115c35d236eSmrg 1116c35d236eSmrg#define VPAR_s 0x00 1117c35d236eSmrg#define VPAR_t 0x08 1118c35d236eSmrg#define VPAR_q 0x10 1119c35d236eSmrg#define VPAR_Ks 0x18 1120c35d236eSmrg#define VPAR_Kd 0x20 1121c35d236eSmrg 1122c35d236eSmrg/* have changed colors in ramdac ! 1123c35d236eSmrg#define VPAR_R 0x28 1124c35d236eSmrg#define VPAR_G 0x30 1125c35d236eSmrg#define VPAR_B 0x38 1126c35d236eSmrg#define VPAR_A 0x40 1127c35d236eSmrg*/ 1128c35d236eSmrg#define VPAR_B 0x28 1129c35d236eSmrg#define VPAR_G 0x30 1130c35d236eSmrg#define VPAR_R 0x38 1131c35d236eSmrg#define VPAR_A 0x40 1132c35d236eSmrg 1133c35d236eSmrg#define VPAR_f 0x48 1134c35d236eSmrg 1135c35d236eSmrg#define VPAR_x 0x50 1136c35d236eSmrg#define VPAR_y 0x58 1137c35d236eSmrg#define VPAR_z 0x60 1138c35d236eSmrg 1139c35d236eSmrg#define DeltaModeTag GLINT_TAG_ADDR(0x26,0x00) 1140c35d236eSmrg /* 0: */ 1141c35d236eSmrg /* GLINT_300SX */ 1142c35d236eSmrg 1143c35d236eSmrg /* DeltaMode Register Bit Field Assignments */ 1144c35d236eSmrg# define DM_GLINT_300SX 0x0000 1145c35d236eSmrg# define DM_GLINT_500TX 0x0001 1146c35d236eSmrg# define DM_PERMEDIA 0x0002 1147c35d236eSmrg# define DM_Depth_16BPP (1 << 2) 1148c35d236eSmrg# define DM_Depth_24BPP (2 << 2) 1149c35d236eSmrg# define DM_Depth_32BPP (3 << 2) 1150c35d236eSmrg# define DM_FogEnable 0x0010 1151c35d236eSmrg# define DM_TextureEnable 0x0020 1152c35d236eSmrg# define DM_SmoothShadingEnable 0x0040 1153c35d236eSmrg# define DM_DepthEnable 0x0080 1154c35d236eSmrg# define DM_SpecularTextureEnable 0x0100 1155c35d236eSmrg# define DM_DiffuseTextureEnable 0x0200 1156c35d236eSmrg# define DM_SubPixelCorrectionEnable 0x0400 1157c35d236eSmrg# define DM_DiamondExit 0x0800 1158c35d236eSmrg# define DM_NoDraw 0x1000 1159c35d236eSmrg# define DM_ClampEnable 0x2000 1160c35d236eSmrg# define DM_ClampedTexParMode 0x4000 1161c35d236eSmrg# define DM_NormalizedTexParMode 0xC000 1162c35d236eSmrg 1163c35d236eSmrg 1164c35d236eSmrg# define DDCMD_AreaStrippleEnable 0x0001 1165c35d236eSmrg# define DDCMD_LineStrippleEnable 0x0002 1166c35d236eSmrg# define DDCMD_ResetLineStripple 1 << 2 1167c35d236eSmrg# define DDCMD_FastFillEnable 1 << 3 1168c35d236eSmrg /* 2 Bits reserved */ 1169c35d236eSmrg# define DDCMD_PrimitiveType_Point 2 << 6 1170c35d236eSmrg# define DDCMD_PrimitiveType_Line 0 << 6 1171c35d236eSmrg# define DDCMD_PrimitiveType_Trapezoid 1 << 6 1172c35d236eSmrg# define DDCMD_AntialiasEnable 1 << 8 1173c35d236eSmrg# define DDCMD_AntialiasingQuality 1 << 9 1174c35d236eSmrg# define DDCMD_UsePointTable 1 << 10 1175c35d236eSmrg# define DDCMD_SyncOnBitMask 1 << 11 1176c35d236eSmrg# define DDCMD_SyncOnHostDate 1 << 12 1177c35d236eSmrg# define DDCMD_TextureEnable 1 << 13 1178c35d236eSmrg# define DDCMD_FogEnable 1 << 14 1179c35d236eSmrg# define DDCMD_CoverageEnable 1 << 15 1180c35d236eSmrg# define DDCMD_SubPixelCorrectionEnable 1 << 16 1181c35d236eSmrg 1182c35d236eSmrg 1183c35d236eSmrg 1184c35d236eSmrg#define DrawTriangle GLINT_TAG_ADDR(0x26,0x01) 1185c35d236eSmrg#define RepeatTriangle GLINT_TAG_ADDR(0x26,0x02) 1186c35d236eSmrg#define DrawLine01 GLINT_TAG_ADDR(0x26,0x03) 1187c35d236eSmrg#define DrawLine10 GLINT_TAG_ADDR(0x26,0x04) 1188c35d236eSmrg#define RepeatLine GLINT_TAG_ADDR(0x26,0x05) 1189c35d236eSmrg#define BroadcastMask GLINT_TAG_ADDR(0x26,0x0F) 1190c35d236eSmrg 1191c35d236eSmrg/* Permedia 3 - Accelerator Extensions */ 1192c35d236eSmrg#define FillRectanglePosition 0x8348 1193c35d236eSmrg#define FillRender2D 0x8350 1194c35d236eSmrg#define FBDstReadBufAddr0 0xAE80 1195c35d236eSmrg#define FBDstReadBufOffset0 0xAEA0 1196c35d236eSmrg#define FBDstReadBufWidth0 0xAEC0 1197c35d236eSmrg#define FBDstReadMode 0xAEE0 1198c35d236eSmrg#define FBDRM_Enable0 1<<8 1199c35d236eSmrg#define FBDRM_Blocking 1<<24 1200c35d236eSmrg#define FBDstReadEnables 0xAEE8 1201c35d236eSmrg#define FBSrcReadMode 0xAF00 1202c35d236eSmrg#define FBSRM_Blocking 1<<11 1203c35d236eSmrg#define FBSrcReadBufAddr 0xAF08 1204c35d236eSmrg#define FBSrcReadBufOffset0 0xAF10 1205c35d236eSmrg#define FBSrcReadBufWidth 0xAF18 1206c35d236eSmrg#define FBWriteBufAddr0 0xB000 1207c35d236eSmrg#define FBWriteBufOffset0 0xB020 1208c35d236eSmrg#define FBWriteBufWidth0 0xB040 1209c35d236eSmrg#define FBBlockColorBack 0xB0A0 1210c35d236eSmrg#define ForegroundColor 0xB0C0 1211c35d236eSmrg#define BackgroundColor 0xB0C8 1212c35d236eSmrg#define RectanglePosition 0xB600 1213c35d236eSmrg#define Render2D 0xB640 1214c35d236eSmrg 1215c35d236eSmrg/* Colorformats */ 1216c35d236eSmrg#define BGR555 1 1217c35d236eSmrg#define BGR565 16 1218c35d236eSmrg#define CI8 14 1219c35d236eSmrg#define CI4 15 1220c35d236eSmrg 1221c35d236eSmrg#ifdef DEBUG 1222c35d236eSmrg#define GLINT_WRITE_REG(v,r) \ 1223c35d236eSmrg GLINT_VERB_WRITE_REG(pGlint,v,r,__FILE__,__LINE__) 1224c35d236eSmrg#define GLINT_READ_REG(r) \ 1225c35d236eSmrg GLINT_VERB_READ_REG(pGlint,r,__FILE__,__LINE__) 1226c35d236eSmrg#else 1227c35d236eSmrg 1228c35d236eSmrg#define GLINT_WRITE_REG(v,r) \ 1229c35d236eSmrg MMIO_OUT32(pGlint->IOBase + pGlint->IOOffset,(unsigned long)(r), (v)) 1230c35d236eSmrg#define GLINT_READ_REG(r) \ 1231c35d236eSmrg MMIO_IN32(pGlint->IOBase + pGlint->IOOffset,(unsigned long)(r)) 1232c35d236eSmrg 1233c35d236eSmrg#endif /* DEBUG */ 1234c35d236eSmrg 1235c35d236eSmrg#define GLINT_WAIT(n) \ 1236c35d236eSmrgdo{ \ 1237c35d236eSmrg if (pGlint->InFifoSpace>=(n)) \ 1238c35d236eSmrg pGlint->InFifoSpace -= (n); \ 1239c35d236eSmrg else { \ 1240c35d236eSmrg int tmp; \ 1241c35d236eSmrg while((tmp=GLINT_READ_REG(InFIFOSpace))<(n)); \ 1242c35d236eSmrg /* Clamp value due to bugs in PM3 */ \ 1243c35d236eSmrg if (tmp > pGlint->FIFOSize) \ 1244c35d236eSmrg tmp = pGlint->FIFOSize; \ 1245c35d236eSmrg pGlint->InFifoSpace = tmp - (n); \ 1246c35d236eSmrg } \ 1247c35d236eSmrg}while(0) 1248c35d236eSmrg 1249c35d236eSmrg#define GLINTDACDelay(x) do { \ 1250c35d236eSmrg int delay = x; \ 1251c35d236eSmrg while(delay--){(void)GLINT_READ_REG(InFIFOSpace);}; \ 1252c35d236eSmrg } while(0) 1253c35d236eSmrg 1254c35d236eSmrg#define GLINT_MASK_WRITE_REG(v,m,r) \ 1255c35d236eSmrg GLINT_WRITE_REG((GLINT_READ_REG(r)&(m))|(v),r) 1256c35d236eSmrg 1257c35d236eSmrg#define GLINT_SLOW_WRITE_REG(v,r) \ 1258c35d236eSmrgdo{ \ 1259c35d236eSmrg mem_barrier(); \ 1260c35d236eSmrg GLINT_WAIT(pGlint->FIFOSize); \ 1261c35d236eSmrg mem_barrier(); \ 1262c35d236eSmrg GLINT_WRITE_REG(v,r); \ 1263c35d236eSmrg}while(0) 1264c35d236eSmrg 1265c35d236eSmrg#define GLINT_SET_INDEX(index) \ 1266c35d236eSmrgdo{ \ 1267c35d236eSmrg GLINT_SLOW_WRITE_REG(((index)>>8)&0xff,PM2VDACIndexRegHigh); \ 1268c35d236eSmrg GLINT_SLOW_WRITE_REG((index)&0xff,PM2VDACIndexRegLow); \ 1269c35d236eSmrg} while(0) 1270c35d236eSmrg 1271c35d236eSmrg#define REPLICATE(r) \ 1272c35d236eSmrg{ \ 1273c35d236eSmrg if (pScrn->bitsPerPixel == 16) { \ 1274c35d236eSmrg r &= 0xFFFF; \ 1275c35d236eSmrg r |= (r<<16); \ 1276c35d236eSmrg } else \ 1277c35d236eSmrg if (pScrn->bitsPerPixel == 8) { \ 1278c35d236eSmrg r &= 0xFF; \ 1279c35d236eSmrg r |= (r<<8); \ 1280c35d236eSmrg r |= (r<<16); \ 1281c35d236eSmrg } \ 1282c35d236eSmrg} 1283c35d236eSmrg 1284c35d236eSmrg#ifndef XF86DRI 1285c35d236eSmrg#define LOADROP(rop) \ 1286c35d236eSmrg{ \ 1287c35d236eSmrg if (pGlint->ROP != rop) { \ 1288c35d236eSmrg GLINT_WRITE_REG(rop<<1|UNIT_ENABLE, LogicalOpMode); \ 1289c35d236eSmrg pGlint->ROP = rop; \ 1290c35d236eSmrg } \ 1291c35d236eSmrg} 1292c35d236eSmrg#else 1293c35d236eSmrg#define LOADROP(rop) \ 1294c35d236eSmrg { \ 1295c35d236eSmrg GLINT_WRITE_REG(rop<<1|UNIT_ENABLE, LogicalOpMode); \ 1296c35d236eSmrg pGlint->ROP = rop; \ 1297c35d236eSmrg } 1298c35d236eSmrg#endif 1299c35d236eSmrg 1300c35d236eSmrg#define CHECKCLIPPING \ 1301c35d236eSmrg{ \ 1302c35d236eSmrg if (pGlint->ClippingOn) { \ 1303c35d236eSmrg pGlint->ClippingOn = FALSE; \ 1304c35d236eSmrg GLINT_WAIT(1); \ 1305c35d236eSmrg GLINT_WRITE_REG(0, ScissorMode); \ 1306c35d236eSmrg } \ 1307c35d236eSmrg} 1308c35d236eSmrg 1309c35d236eSmrg#ifndef XF86DRI 1310c35d236eSmrg#define DO_PLANEMASK(planemask) \ 1311c35d236eSmrg{ \ 1312c35d236eSmrg if (planemask != pGlint->planemask) { \ 1313c35d236eSmrg pGlint->planemask = planemask; \ 1314c35d236eSmrg REPLICATE(planemask); \ 1315c35d236eSmrg GLINT_WRITE_REG(planemask, FBHardwareWriteMask);\ 1316c35d236eSmrg } \ 1317c35d236eSmrg} 1318c35d236eSmrg#else 1319c35d236eSmrg#define DO_PLANEMASK(planemask) \ 1320c35d236eSmrg { \ 1321c35d236eSmrg pGlint->planemask = planemask; \ 1322c35d236eSmrg REPLICATE(planemask); \ 1323c35d236eSmrg GLINT_WRITE_REG(planemask, FBHardwareWriteMask);\ 1324c35d236eSmrg } 1325c35d236eSmrg#endif 1326c35d236eSmrg 1327c35d236eSmrg/* Permedia Save/Restore functions */ 1328c35d236eSmrg 1329c35d236eSmrg#define STOREREG(address,value) \ 1330c35d236eSmrg pReg->glintRegs[address >> 3] = value; 1331c35d236eSmrg 1332c35d236eSmrg#define SAVEREG(address) \ 1333c35d236eSmrg pReg->glintRegs[address >> 3] = GLINT_READ_REG(address); 1334c35d236eSmrg 1335c35d236eSmrg#define RESTOREREG(address) \ 1336c35d236eSmrg GLINT_SLOW_WRITE_REG(pReg->glintRegs[address >> 3], address); 1337c35d236eSmrg 1338c35d236eSmrg#define STOREDAC(address,value) \ 1339c35d236eSmrg pReg->DacRegs[address] = value; 1340c35d236eSmrg 1341c35d236eSmrg#define P2VOUT(address) \ 1342c35d236eSmrg Permedia2vOutIndReg(pScrn, address, 0x00, pReg->DacRegs[address]); 1343c35d236eSmrg 1344c35d236eSmrg#define P2VIN(address) \ 1345c35d236eSmrg pReg->DacRegs[address] = Permedia2vInIndReg(pScrn, address); 1346c35d236eSmrg 1347c35d236eSmrg/* RamDac Save/Restore functions, used by external DAC's */ 1348c35d236eSmrg 1349c35d236eSmrg#define STORERAMDAC(address,value) \ 1350c35d236eSmrg ramdacReg->DacRegs[address] = value; 1351c35d236eSmrg 1352c35d236eSmrg/* Multi Chip access */ 1353c35d236eSmrg 1354c35d236eSmrg#define ACCESSCHIP1() \ 1355c35d236eSmrg pGlint->IOOffset = 0; 1356c35d236eSmrg 1357c35d236eSmrg#define ACCESSCHIP2() \ 1358c35d236eSmrg pGlint->IOOffset = 0x10000; 1359c35d236eSmrg 1360c35d236eSmrg#endif 1361