1/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/imstt/imstt_reg.h,v 1.5 2002/08/06 19:57:30 herrb Exp $ */ 2 3#ifndef _IMSTT_REG_H 4#define _IMSTT_REG_H 5 6 7 8#if defined(__powerpc__) 9 10static __inline__ void regw(unsigned long base_addr, unsigned long regindex, unsigned long regdata) 11{ 12 __asm__ __volatile__ ("stwbrx %1,%2,%3; eieio" 13 : "=m" (*(volatile unsigned *)(base_addr+regindex)) 14 : "r" (regdata), "b" (regindex), "r" (base_addr)); 15} 16 17 18static __inline__ unsigned long regr(unsigned long base_addr, unsigned long regindex) 19{ 20 register unsigned long val; 21 22 __asm__ __volatile__ ("lwbrx %0,%1,%2; eieio" 23 : "=r" (val) 24 : "b" (regindex), "r" (base_addr), 25 "m" (*(volatile unsigned *)(base_addr+regindex))); 26 27 return (val); 28} 29 30 31#define INREG(addr) regr(((unsigned long)(iptr->MMIOBase)), (addr)) 32#define OUTREG(addr, val) regw(((unsigned long)(iptr->MMIOBase)), (addr), (val)) 33 34#else 35 36#define INREG(addr) MMIO_IN32(iptr->MMIOBase, addr) 37#define OUTREG(addr, val) MMIO_OUT32(iptr->MMIOBase, addr, val) 38 39#endif 40 41#define OUTREGPI(addr, val) iptr->CMAPBase[IBM624_PIDXLO] = addr; eieio(); \ 42 iptr->CMAPBase[IBM624_PIDXDATA] = val; eieio() 43#define OUTREGPT(addr, val) iptr->CMAPBase[TVP_ADDRW] = addr; eieio(); \ 44 iptr->CMAPBase[TVP_IDATA] = val; eieio() 45 46#define IMSTTMMIO_VARS() \ 47 unsigned long *IMSTTMMIO = IMSTTPTR(pScrn)->MMIOBase 48 49 50/* TwinTurbo (Cosmo) registers */ 51 52#define IMSTT_S1SA 0x00 53#define IMSTT_S2SA 0x04 54#define IMSTT_SP 0x08 55#define IMSTT_DSA 0x0c 56#define IMSTT_CNT 0x10 57#define IMSTT_DP_OCTL 0x14 58#define IMSTT_CLR 0x18 59#define IMSTT_BI 0x20 60#define IMSTT_MBC 0x24 61#define IMSTT_BLTCTL 0x28 62 63/* scan timing generator registers */ 64 65#define IMSTT_HES 0x30 66#define IMSTT_HEB 0x34 67#define IMSTT_HSB 0x38 68#define IMSTT_HT 0x3c 69#define IMSTT_VES 0x40 70#define IMSTT_VEB 0x44 71#define IMSTT_VSB 0x48 72#define IMSTT_VT 0x4c 73#define IMSTT_HCIV 0x50 74#define IMSTT_VCIV 0x54 75#define IMSTT_TCDR 0x58 76#define IMSTT_VIL 0x5c 77#define IMSTT_STGCTL 0x60 78 79/* screen refresh generator registers */ 80 81#define IMSTT_SSR 0x64 82#define IMSTT_HRIR 0x68 83#define IMSTT_SPR 0x6c 84#define IMSTT_CMR 0x70 85#define IMSTT_SRGCTL 0x74 86 87/* RAM refresh generator registers */ 88 89#define IMSTT_RRCIV 0x78 90#define IMSTT_RRSC 0x7c 91#define IMSTT_RRCR 0x88 92 93/* system registers */ 94 95#define IMSTT_GIOE 0x80 96#define IMSTT_GIO 0x84 97#define IMSTT_SCR 0x8c 98#define IMSTT_SSTATUS 0x90 99#define IMSTT_PRC 0x94 100 101 102/* IBM 624 RAMDAC direct registers */ 103 104#define IBM624_PADDRW 0x00 105#define IBM624_PDATA 0x04 106#define IBM624_PPMASK 0x08 107#define IBM624_PADDRR 0x0c 108#define IBM624_PIDXLO 0x10 109#define IBM624_PIDXHI 0x14 110#define IBM624_PIDXDATA 0x18 111#define IBM624_PIDXCTL 0x1c 112 113/* IBM 624 RAMDAC indirect registers */ 114 115#define IBM624_CLKCTL 0x02 /* Misc Clock Control */ 116#define IBM624_SYNCCTL 0x03 /* Sync Control */ 117#define IBM624_HSYNCPOS 0x04 /* Horiz Sync Position */ 118#define IBM624_PWRMNGMT 0x05 /* Power Management */ 119#define IBM624_DACOP 0x06 /* DAC Operation */ 120#define IBM624_PALETCTL 0x07 /* Palette Control */ 121#define IBM624_SYSCLKCTL 0x08 /* System Clock Control */ 122#define IBM624_PIXFMT 0x0a /* Pixel Format [bpp >> 3 + 2] */ 123#define IBM624_BPP8 0x0b /* 8bpp */ 124#define IBM624_BPP16 0x0c /* 16bpp */ 125#define IBM624_BPP24 0x0d /* 24bpp */ 126#define IBM624_BPP32 0x0e /* 32bpp */ 127#define IBM624_PIXCTL1 0x10 /* Pixel PLL Control 1 */ 128#define IBM624_PIXCTL2 0x11 /* Pixel PLL Control 2 */ 129#define IBM624_SYSCLKN 0x15 /* System Clock N */ 130#define IBM624_SYSCLKM 0x16 /* System Clock M */ 131#define IBM624_SYSCLKP 0x17 /* System Clock P */ 132#define IBM624_SYSCLKC 0x18 /* System Clock C */ 133#define IBM624_PIXM0 0x20 /* Pixel M 0 */ 134#define IBM624_PIXN0 0x21 /* Pixel N 0 */ 135#define IBM624_PIXP0 0x22 /* Pixel P 0 */ 136#define IBM624_PIXC0 0x23 /* Pixel C 0 */ 137#define IBM624_CURSCTL 0x30 /* Cursor Control */ 138#define IBM624_CURSXLO 0x31 /* Cursor X position, low 8 bits */ 139#define IBM624_CURSXHI 0x32 /* Cursor X position, high 8 bits */ 140#define IBM624_CURSYLO 0x33 /* Cursor Y position, low 8 bits */ 141#define IBM624_CURSYHI 0x34 /* Cursor Y postition, high 8 bits */ 142#define IBM624_CURSHOTX 0x35 /* Cursor Hot Spot X */ 143#define IBM624_CURSHOTY 0x36 /* Cursor Hot Spot Y */ 144#define IBM624_CURSACCTL 0x37 /* Advanced Cursor Control Enable */ 145#define IBM624_CURSACATTR 0x38 /* Advanced Cursor Attribute */ 146#define IBM624_CURS1R 0x40 /* Cursor 1 red */ 147#define IBM624_CURS1G 0x41 /* Cursor 1 green */ 148#define IBM624_CURS1B 0x42 /* Cursor 1 blue */ 149#define IBM624_CURS2R 0x43 /* Cursor 2 red */ 150#define IBM624_CURS2G 0x44 /* Cursor 2 green */ 151#define IBM624_CURS2B 0x45 /* Cursor 2 blue */ 152#define IBM624_CURS3R 0x46 /* Cursor 3 red */ 153#define IBM624_CURS3G 0x47 /* Cursor 3 green */ 154#define IBM624_CURS3B 0x48 /* Cursor 3 blue */ 155#define IBM624_BORDR 0x60 /* Border color red */ 156#define IBM624_BORDG 0x61 /* Border color green */ 157#define IBM624_BORDB 0x62 /* Border color blue */ 158#define IBM624_MISCTL1 0x70 /* Misc control 1 */ 159#define IBM624_MISCTL2 0x71 /* Misc control 2 */ 160#define IBM624_MISCTL3 0x72 /* Misc control 3 */ 161#define IBM624_KEYCTL 0x78 /* Key Control/DB operation */ 162 163/* TI TVP 3030 RAMDAC direct registers */ 164 165#define TVP_ADDRW 0x00 166#define TVP_PDATA 0x04 167#define TVP_PMASK 0x08 168#define TVP_PADRR 0x0c 169#define TVP_CADRW 0x10 170#define TVP_CDATA 0x14 171#define TVP_CADRR 0x1c 172#define TVP_DCCTL 0x24 173#define TVP_IDATA 0x28 174#define TVP_CRDAT 0x2c 175#define TVP_CXPOL 0x30 176#define TVP_CXPOH 0x34 177#define TVP_CYPOL 0x38 178#define TVP_CYPOH 0x3c 179 180/* TI TVP 3030 RAMDAC indirect registers */ 181 182 183#define TVP_IRREV 0x01 184#define TVP_IRICC 0x06 185#define TVP_IRBRC 0x07 186#define TVP_IRLAC 0x0f 187#define TVP_IRTCC 0x18 188#define TVP_IRMXC 0x19 189#define TVP_IRCLS 0x1a 190#define TVP_IRPPG 0x1c 191#define TVP_IRGEC 0x1d 192#define TVP_IRMIC 0x1e 193#define TVP_IRPLA 0x2c 194#define TVP_IRPPD 0x2d 195#define TVP_IRMPD 0x2e 196#define TVP_IRLPD 0x2f 197#define TVP_IRCKL 0x30 198#define TVP_IRCKH 0x31 199#define TVP_IRCRL 0x32 200#define TVP_IRCRH 0x33 201#define TVP_IRCGL 0x34 202#define TVP_IRCGH 0x35 203#define TVP_IRCBL 0x36 204#define TVP_IRCBH 0x37 205#define TVP_IRCKC 0x38 206#define TVP_IRMLC 0x39 207#define TVP_IRSEN 0x3a 208#define TVP_IRTMD 0x3b 209#define TVP_IRRML 0x3c 210#define TVP_IRRMM 0x3d 211#define TVP_IRRMS 0x3e 212#define TVP_IRDID 0x3f 213#define TVP_IRRES 0xff 214 215#endif /* _IMSTT_REG_H */ 216