1428d7b3dSmrg/* 2428d7b3dSmrg Copyright (C) Intel Corp. 2006. All Rights Reserved. 3428d7b3dSmrg Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to 4428d7b3dSmrg develop this 3D driver. 5428d7b3dSmrg 6428d7b3dSmrg Permission is hereby granted, free of charge, to any person obtaining 7428d7b3dSmrg a copy of this software and associated documentation files (the 8428d7b3dSmrg "Software"), to deal in the Software without restriction, including 9428d7b3dSmrg without limitation the rights to use, copy, modify, merge, publish, 10428d7b3dSmrg distribute, sublicense, and/or sell copies of the Software, and to 11428d7b3dSmrg permit persons to whom the Software is furnished to do so, subject to 12428d7b3dSmrg the following conditions: 13428d7b3dSmrg 14428d7b3dSmrg The above copyright notice and this permission notice (including the 15428d7b3dSmrg next paragraph) shall be included in all copies or substantial 16428d7b3dSmrg portions of the Software. 17428d7b3dSmrg 18428d7b3dSmrg THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19428d7b3dSmrg EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20428d7b3dSmrg MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21428d7b3dSmrg IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 22428d7b3dSmrg LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23428d7b3dSmrg OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 24428d7b3dSmrg WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25428d7b3dSmrg 26428d7b3dSmrg **********************************************************************/ 27428d7b3dSmrg /* 28428d7b3dSmrg * Authors: 29428d7b3dSmrg * Keith Whitwell <keith@tungstengraphics.com> 30428d7b3dSmrg */ 31428d7b3dSmrg 32428d7b3dSmrg#ifdef HAVE_CONFIG_H 33428d7b3dSmrg#include "config.h" 34428d7b3dSmrg#endif 35428d7b3dSmrg 36428d7b3dSmrg#include "brw_eu.h" 37428d7b3dSmrg 38428d7b3dSmrg#include <string.h> 39428d7b3dSmrg#include <stdlib.h> 40428d7b3dSmrg 41428d7b3dSmrg/* Returns the corresponding conditional mod for swapping src0 and 42428d7b3dSmrg * src1 in e.g. CMP. 43428d7b3dSmrg */ 44428d7b3dSmrguint32_t 45428d7b3dSmrgbrw_swap_cmod(uint32_t cmod) 46428d7b3dSmrg{ 47428d7b3dSmrg switch (cmod) { 48428d7b3dSmrg case BRW_CONDITIONAL_Z: 49428d7b3dSmrg case BRW_CONDITIONAL_NZ: 50428d7b3dSmrg return cmod; 51428d7b3dSmrg case BRW_CONDITIONAL_G: 52428d7b3dSmrg return BRW_CONDITIONAL_LE; 53428d7b3dSmrg case BRW_CONDITIONAL_GE: 54428d7b3dSmrg return BRW_CONDITIONAL_L; 55428d7b3dSmrg case BRW_CONDITIONAL_L: 56428d7b3dSmrg return BRW_CONDITIONAL_GE; 57428d7b3dSmrg case BRW_CONDITIONAL_LE: 58428d7b3dSmrg return BRW_CONDITIONAL_G; 59428d7b3dSmrg default: 60428d7b3dSmrg return ~0; 61428d7b3dSmrg } 62428d7b3dSmrg} 63428d7b3dSmrg 64428d7b3dSmrg/* How does predicate control work when execution_size != 8? Do I 65428d7b3dSmrg * need to test/set for 0xffff when execution_size is 16? 66428d7b3dSmrg */ 67428d7b3dSmrgvoid brw_set_predicate_control_flag_value( struct brw_compile *p, unsigned value ) 68428d7b3dSmrg{ 69428d7b3dSmrg p->current->header.predicate_control = BRW_PREDICATE_NONE; 70428d7b3dSmrg 71428d7b3dSmrg if (value != 0xff) { 72428d7b3dSmrg if (value != p->flag_value) { 73428d7b3dSmrg brw_MOV(p, brw_flag_reg(), brw_imm_uw(value)); 74428d7b3dSmrg p->flag_value = value; 75428d7b3dSmrg } 76428d7b3dSmrg 77428d7b3dSmrg p->current->header.predicate_control = BRW_PREDICATE_NORMAL; 78428d7b3dSmrg } 79428d7b3dSmrg} 80428d7b3dSmrg 81428d7b3dSmrgvoid brw_set_compression_control(struct brw_compile *p, 82428d7b3dSmrg enum brw_compression compression_control) 83428d7b3dSmrg{ 84428d7b3dSmrg p->compressed = (compression_control == BRW_COMPRESSION_COMPRESSED); 85428d7b3dSmrg 86428d7b3dSmrg if (p->gen >= 060) { 87428d7b3dSmrg /* Since we don't use the 32-wide support in gen6, we translate 88428d7b3dSmrg * the pre-gen6 compression control here. 89428d7b3dSmrg */ 90428d7b3dSmrg switch (compression_control) { 91428d7b3dSmrg case BRW_COMPRESSION_NONE: 92428d7b3dSmrg /* This is the "use the first set of bits of dmask/vmask/arf 93428d7b3dSmrg * according to execsize" option. 94428d7b3dSmrg */ 95428d7b3dSmrg p->current->header.compression_control = GEN6_COMPRESSION_1Q; 96428d7b3dSmrg break; 97428d7b3dSmrg case BRW_COMPRESSION_2NDHALF: 98428d7b3dSmrg /* For 8-wide, this is "use the second set of 8 bits." */ 99428d7b3dSmrg p->current->header.compression_control = GEN6_COMPRESSION_2Q; 100428d7b3dSmrg break; 101428d7b3dSmrg case BRW_COMPRESSION_COMPRESSED: 102428d7b3dSmrg /* For 16-wide instruction compression, use the first set of 16 bits 103428d7b3dSmrg * since we don't do 32-wide dispatch. 104428d7b3dSmrg */ 105428d7b3dSmrg p->current->header.compression_control = GEN6_COMPRESSION_1H; 106428d7b3dSmrg break; 107428d7b3dSmrg default: 108428d7b3dSmrg assert(!"not reached"); 109428d7b3dSmrg p->current->header.compression_control = GEN6_COMPRESSION_1H; 110428d7b3dSmrg break; 111428d7b3dSmrg } 112428d7b3dSmrg } else { 113428d7b3dSmrg p->current->header.compression_control = compression_control; 114428d7b3dSmrg } 115428d7b3dSmrg} 116428d7b3dSmrg 117428d7b3dSmrgvoid brw_push_insn_state( struct brw_compile *p ) 118428d7b3dSmrg{ 119428d7b3dSmrg assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]); 120428d7b3dSmrg memcpy(p->current+1, p->current, sizeof(struct brw_instruction)); 121428d7b3dSmrg p->compressed_stack[p->current - p->stack] = p->compressed; 122428d7b3dSmrg p->current++; 123428d7b3dSmrg} 124428d7b3dSmrg 125428d7b3dSmrgvoid brw_pop_insn_state( struct brw_compile *p ) 126428d7b3dSmrg{ 127428d7b3dSmrg assert(p->current != p->stack); 128428d7b3dSmrg p->current--; 129428d7b3dSmrg p->compressed = p->compressed_stack[p->current - p->stack]; 130428d7b3dSmrg} 131428d7b3dSmrg 132428d7b3dSmrgvoid brw_compile_init(struct brw_compile *p, int gen, void *store) 133428d7b3dSmrg{ 134428d7b3dSmrg assert(gen); 135428d7b3dSmrg 136428d7b3dSmrg p->gen = gen; 137428d7b3dSmrg p->store = store; 138428d7b3dSmrg 139428d7b3dSmrg p->nr_insn = 0; 140428d7b3dSmrg p->current = p->stack; 141428d7b3dSmrg p->compressed = false; 142428d7b3dSmrg memset(p->current, 0, sizeof(p->current[0])); 143428d7b3dSmrg 144428d7b3dSmrg /* Some defaults? 145428d7b3dSmrg */ 146428d7b3dSmrg brw_set_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */ 147428d7b3dSmrg brw_set_saturate(p, 0); 148428d7b3dSmrg brw_set_compression_control(p, BRW_COMPRESSION_NONE); 149428d7b3dSmrg brw_set_predicate_control_flag_value(p, 0xff); 150428d7b3dSmrg 151428d7b3dSmrg p->if_stack_depth = 0; 152428d7b3dSmrg p->if_stack_array_size = 0; 153428d7b3dSmrg p->if_stack = NULL; 154428d7b3dSmrg} 155