1/************************************************************************** 2 * 3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28#ifndef _I915_REG_H_ 29#define _I915_REG_H_ 30 31#define CMD_3D (3 << 29) 32 33#define I915_SET_FIELD( var, mask, value ) (var &= ~(mask), var |= value) 34 35#define PRIM3D (CMD_3D | (0x1f<<24)) 36#define PRIM3D_INDIRECT_SEQUENTIAL ((1<<23) | (0<<17)) 37#define PRIM3D_TRILIST (PRIM3D | (0x0<<18)) 38#define PRIM3D_TRISTRIP (PRIM3D | (0x1<<18)) 39#define PRIM3D_TRISTRIP_RVRSE (PRIM3D | (0x2<<18)) 40#define PRIM3D_TRIFAN (PRIM3D | (0x3<<18)) 41#define PRIM3D_POLY (PRIM3D | (0x4<<18)) 42#define PRIM3D_LINELIST (PRIM3D | (0x5<<18)) 43#define PRIM3D_LINESTRIP (PRIM3D | (0x6<<18)) 44#define PRIM3D_RECTLIST (PRIM3D | (0x7<<18)) 45#define PRIM3D_POINTLIST (PRIM3D | (0x8<<18)) 46#define PRIM3D_DIB (PRIM3D | (0x9<<18)) 47#define PRIM3D_CLEAR_RECT (PRIM3D | (0xa<<18)) 48#define PRIM3D_ZONE_INIT (PRIM3D | (0xd<<18)) 49#define PRIM3D_MASK (0x1f<<18) 50 51 52/* p137 */ 53#define _3DSTATE_AA_CMD (CMD_3D | (0x06<<24)) 54#define AA_LINE_ECAAR_WIDTH_ENABLE (1<<16) 55#define AA_LINE_ECAAR_WIDTH_0_5 0 56#define AA_LINE_ECAAR_WIDTH_1_0 (1<<14) 57#define AA_LINE_ECAAR_WIDTH_2_0 (2<<14) 58#define AA_LINE_ECAAR_WIDTH_4_0 (3<<14) 59#define AA_LINE_REGION_WIDTH_ENABLE (1<<8) 60#define AA_LINE_REGION_WIDTH_0_5 0 61#define AA_LINE_REGION_WIDTH_1_0 (1<<6) 62#define AA_LINE_REGION_WIDTH_2_0 (2<<6) 63#define AA_LINE_REGION_WIDTH_4_0 (3<<6) 64 65/* 3DSTATE_BACKFACE_STENCIL_OPS, p138*/ 66#define _3DSTATE_BACKFACE_STENCIL_OPS (CMD_3D | (0x8<<24)) 67#define BFO_ENABLE_STENCIL_REF (1<<23) 68#define BFO_STENCIL_REF_SHIFT 15 69#define BFO_STENCIL_REF_MASK (0xff<<15) 70#define BFO_ENABLE_STENCIL_FUNCS (1<<14) 71#define BFO_STENCIL_TEST_SHIFT 11 72#define BFO_STENCIL_TEST_MASK (0x7<<11) 73#define BFO_STENCIL_FAIL_SHIFT 8 74#define BFO_STENCIL_FAIL_MASK (0x7<<8) 75#define BFO_STENCIL_PASS_Z_FAIL_SHIFT 5 76#define BFO_STENCIL_PASS_Z_FAIL_MASK (0x7<<5) 77#define BFO_STENCIL_PASS_Z_PASS_SHIFT 2 78#define BFO_STENCIL_PASS_Z_PASS_MASK (0x7<<2) 79#define BFO_ENABLE_STENCIL_TWO_SIDE (1<<1) 80#define BFO_STENCIL_TWO_SIDE (1<<0) 81 82/* 3DSTATE_BACKFACE_STENCIL_MASKS, p140 */ 83#define _3DSTATE_BACKFACE_STENCIL_MASKS (CMD_3D | (0x9<<24)) 84#define BFM_ENABLE_STENCIL_TEST_MASK (1<<17) 85#define BFM_ENABLE_STENCIL_WRITE_MASK (1<<16) 86#define BFM_STENCIL_TEST_MASK_SHIFT 8 87#define BFM_STENCIL_TEST_MASK_MASK (0xff<<8) 88#define BFM_STENCIL_WRITE_MASK_SHIFT 0 89#define BFM_STENCIL_WRITE_MASK_MASK (0xff<<0) 90 91/* 3DSTATE_BIN_CONTROL p141 */ 92 93/* p143 */ 94#define _3DSTATE_BUF_INFO_CMD (CMD_3D | (0x1d<<24) | (0x8e<<16) | 1) 95/* Dword 1 */ 96#define BUF_3D_ID_COLOR_BACK (0x3<<24) 97#define BUF_3D_ID_DEPTH (0x7<<24) 98#define BUF_3D_USE_FENCE (1<<23) 99#define BUF_3D_TILED_SURFACE (1<<22) 100#define BUF_3D_TILE_WALK_X 0 101#define BUF_3D_TILE_WALK_Y (1<<21) 102/* Dword 2 */ 103#define BUF_3D_ADDR(x) ((x) & ~0x3) 104 105/* 3DSTATE_CHROMA_KEY */ 106 107/* 3DSTATE_CLEAR_PARAMETERS, p150 */ 108#define _3DSTATE_CLEAR_PARAMETERS (CMD_3D | (0x1d<<24) | (0x9c<<16) | 5) 109/* Dword 1 */ 110#define CLEARPARAM_CLEAR_RECT (1 << 16) 111#define CLEARPARAM_ZONE_INIT (0 << 16) 112#define CLEARPARAM_WRITE_COLOR (1 << 2) 113#define CLEARPARAM_WRITE_DEPTH (1 << 1) 114#define CLEARPARAM_WRITE_STENCIL (1 << 0) 115 116/* 3DSTATE_CONSTANT_BLEND_COLOR, p153 */ 117#define _3DSTATE_CONST_BLEND_COLOR_CMD (CMD_3D | (0x1d<<24) | (0x88<<16)) 118 119/* 3DSTATE_COORD_SET_BINDINGS, p154 */ 120#define _3DSTATE_COORD_SET_BINDINGS (CMD_3D | (0x16<<24)) 121#define CSB_TCB(iunit, eunit) ((eunit)<<(iunit*3)) 122 123/* p156 */ 124#define _3DSTATE_DFLT_DIFFUSE_CMD (CMD_3D | (0x1d<<24) | (0x99<<16)) 125 126/* p157 */ 127#define _3DSTATE_DFLT_SPEC_CMD (CMD_3D | (0x1d<<24) | (0x9a<<16)) 128 129/* p158 */ 130#define _3DSTATE_DFLT_Z_CMD (CMD_3D | (0x1d<<24) | (0x98<<16)) 131 132/* 3DSTATE_DEPTH_OFFSET_SCALE, p159 */ 133#define _3DSTATE_DEPTH_OFFSET_SCALE (CMD_3D | (0x1d<<24) | (0x97<<16)) 134/* scale in dword 1 */ 135 136/* The depth subrectangle is not supported, but must be disabled. */ 137/* 3DSTATE_DEPTH_SUBRECT_DISABLE, p160 */ 138#define _3DSTATE_DEPTH_SUBRECT_DISABLE (CMD_3D | (0x1c<<24) | (0x11<<19) | (1 << 1) | (0 << 0)) 139 140/* p161 */ 141#define _3DSTATE_DST_BUF_VARS_CMD (CMD_3D | (0x1d<<24) | (0x85<<16)) 142/* Dword 1 */ 143#define TEX_DEFAULT_COLOR_OGL (0<<30) 144#define TEX_DEFAULT_COLOR_D3D (1<<30) 145#define ZR_EARLY_DEPTH (1<<29) 146#define LOD_PRECLAMP_OGL (1<<28) 147#define LOD_PRECLAMP_D3D (0<<28) 148#define DITHER_FULL_ALWAYS (0<<26) 149#define DITHER_FULL_ON_FB_BLEND (1<<26) 150#define DITHER_CLAMPED_ALWAYS (2<<26) 151#define LINEAR_GAMMA_BLEND_32BPP (1<<25) 152#define DEBUG_DISABLE_ENH_DITHER (1<<24) 153#define DSTORG_HORT_BIAS(x) ((x)<<20) 154#define DSTORG_VERT_BIAS(x) ((x)<<16) 155#define COLOR_4_2_2_CHNL_WRT_ALL 0 156#define COLOR_4_2_2_CHNL_WRT_Y (1<<12) 157#define COLOR_4_2_2_CHNL_WRT_CR (2<<12) 158#define COLOR_4_2_2_CHNL_WRT_CB (3<<12) 159#define COLOR_4_2_2_CHNL_WRT_CRCB (4<<12) 160#define COLR_BUF_8BIT 0 161#define COLR_BUF_RGB555 (1<<8) 162#define COLR_BUF_RGB565 (2<<8) 163#define COLR_BUF_ARGB8888 (3<<8) 164#define COLR_BUF_ARGB4444 (8<<8) 165#define COLR_BUF_ARGB1555 (9<<8) 166#define COLR_BUF_ARGB2AAA (0xa<<8) 167#define DEPTH_IS_Z 0 168#define DEPTH_IS_W (1<<6) 169#define DEPTH_FRMT_16_FIXED 0 170#define DEPTH_FRMT_16_FLOAT (1<<2) 171#define DEPTH_FRMT_24_FIXED_8_OTHER (2<<2) 172#define DEPTH_FRMT_24_FLOAT_8_OTHER (3<<2) 173#define VERT_LINE_STRIDE_1 (1<<1) 174#define VERT_LINE_STRIDE_0 0 175#define VERT_LINE_STRIDE_OFS_1 1 176#define VERT_LINE_STRIDE_OFS_0 0 177 178/* p166 */ 179#define _3DSTATE_DRAW_RECT_CMD (CMD_3D|(0x1d<<24)|(0x80<<16)|3) 180/* Dword 1 */ 181#define DRAW_RECT_DIS_DEPTH_OFS (1<<30) 182#define DRAW_DITHER_OFS_X(x) ((x)<<26) 183#define DRAW_DITHER_OFS_Y(x) ((x)<<24) 184/* Dword 2 */ 185#define DRAW_YMIN(x) ((uint16_t)(x)<<16) 186#define DRAW_XMIN(x) ((uint16_t)(x)) 187/* Dword 3 */ 188#define DRAW_YMAX(x) ((uint16_t)(x)<<16) 189#define DRAW_XMAX(x) ((uint16_t)(x)) 190/* Dword 4 */ 191#define DRAW_YORG(x) ((uint16_t)(x)<<16) 192#define DRAW_XORG(x) ((uint16_t)(x)) 193 194/* 3DSTATE_FILTER_COEFFICIENTS_4X4, p170 */ 195 196/* 3DSTATE_FILTER_COEFFICIENTS_6X5, p172 */ 197 198/* _3DSTATE_FOG_COLOR, p173 */ 199#define _3DSTATE_FOG_COLOR_CMD (CMD_3D|(0x15<<24)) 200#define FOG_COLOR_RED(x) ((x)<<16) 201#define FOG_COLOR_GREEN(x) ((x)<<8) 202#define FOG_COLOR_BLUE(x) (x) 203 204/* _3DSTATE_FOG_MODE, p174 */ 205#define _3DSTATE_FOG_MODE_CMD (CMD_3D|(0x1d<<24)|(0x89<<16)|2) 206/* Dword 1 */ 207#define FMC1_FOGFUNC_MODIFY_ENABLE (1<<31) 208#define FMC1_FOGFUNC_VERTEX (0<<28) 209#define FMC1_FOGFUNC_PIXEL_EXP (1<<28) 210#define FMC1_FOGFUNC_PIXEL_EXP2 (2<<28) 211#define FMC1_FOGFUNC_PIXEL_LINEAR (3<<28) 212#define FMC1_FOGFUNC_MASK (3<<28) 213#define FMC1_FOGINDEX_MODIFY_ENABLE (1<<27) 214#define FMC1_FOGINDEX_Z (0<<25) 215#define FMC1_FOGINDEX_W (1<<25) 216#define FMC1_C1_C2_MODIFY_ENABLE (1<<24) 217#define FMC1_DENSITY_MODIFY_ENABLE (1<<23) 218#define FMC1_C1_ONE (1<<13) 219#define FMC1_C1_MASK (0xffff<<4) 220/* Dword 2 */ 221#define FMC2_C2_ONE (1<<16) 222/* Dword 3 */ 223#define FMC3_D_ONE (1<<16) 224 225/* _3DSTATE_INDEPENDENT_ALPHA_BLEND, p177 */ 226#define _3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD (CMD_3D|(0x0b<<24)) 227#define IAB_MODIFY_ENABLE (1<<23) 228#define IAB_ENABLE (1<<22) 229#define IAB_MODIFY_FUNC (1<<21) 230#define IAB_FUNC_SHIFT 16 231#define IAB_MODIFY_SRC_FACTOR (1<<11) 232#define IAB_SRC_FACTOR_SHIFT 6 233#define IAB_SRC_FACTOR_MASK (BLENDFACT_MASK<<6) 234#define IAB_MODIFY_DST_FACTOR (1<<5) 235#define IAB_DST_FACTOR_SHIFT 0 236#define IAB_DST_FACTOR_MASK (BLENDFACT_MASK<<0) 237 238#define BLENDFACT_ZERO 0x01 239#define BLENDFACT_ONE 0x02 240#define BLENDFACT_SRC_COLR 0x03 241#define BLENDFACT_INV_SRC_COLR 0x04 242#define BLENDFACT_SRC_ALPHA 0x05 243#define BLENDFACT_INV_SRC_ALPHA 0x06 244#define BLENDFACT_DST_ALPHA 0x07 245#define BLENDFACT_INV_DST_ALPHA 0x08 246#define BLENDFACT_DST_COLR 0x09 247#define BLENDFACT_INV_DST_COLR 0x0a 248#define BLENDFACT_SRC_ALPHA_SATURATE 0x0b 249#define BLENDFACT_CONST_COLOR 0x0c 250#define BLENDFACT_INV_CONST_COLOR 0x0d 251#define BLENDFACT_CONST_ALPHA 0x0e 252#define BLENDFACT_INV_CONST_ALPHA 0x0f 253#define BLENDFACT_MASK 0x0f 254 255#define BLENDFUNC_ADD 0x0 256#define BLENDFUNC_SUBTRACT 0x1 257#define BLENDFUNC_REVERSE_SUBTRACT 0x2 258#define BLENDFUNC_MIN 0x3 259#define BLENDFUNC_MAX 0x4 260#define BLENDFUNC_MASK 0x7 261 262/* 3DSTATE_LOAD_INDIRECT, p180 */ 263 264#define _3DSTATE_LOAD_INDIRECT (CMD_3D|(0x1d<<24)|(0x7<<16)) 265#define LI0_STATE_STATIC_INDIRECT (0x01<<8) 266#define LI0_STATE_DYNAMIC_INDIRECT (0x02<<8) 267#define LI0_STATE_SAMPLER (0x04<<8) 268#define LI0_STATE_MAP (0x08<<8) 269#define LI0_STATE_PROGRAM (0x10<<8) 270#define LI0_STATE_CONSTANTS (0x20<<8) 271 272#define SIS0_BUFFER_ADDRESS(x) ((x)&~0x3) 273#define SIS0_FORCE_LOAD (1<<1) 274#define SIS0_BUFFER_VALID (1<<0) 275#define SIS1_BUFFER_LENGTH(x) ((x)&0xff) 276 277#define DIS0_BUFFER_ADDRESS(x) ((x)&~0x3) 278#define DIS0_BUFFER_RESET (1<<1) 279#define DIS0_BUFFER_VALID (1<<0) 280 281#define SSB0_BUFFER_ADDRESS(x) ((x)&~0x3) 282#define SSB0_FORCE_LOAD (1<<1) 283#define SSB0_BUFFER_VALID (1<<0) 284#define SSB1_BUFFER_LENGTH(x) ((x)&0xff) 285 286#define MSB0_BUFFER_ADDRESS(x) ((x)&~0x3) 287#define MSB0_FORCE_LOAD (1<<1) 288#define MSB0_BUFFER_VALID (1<<0) 289#define MSB1_BUFFER_LENGTH(x) ((x)&0xff) 290 291#define PSP0_BUFFER_ADDRESS(x) ((x)&~0x3) 292#define PSP0_FORCE_LOAD (1<<1) 293#define PSP0_BUFFER_VALID (1<<0) 294#define PSP1_BUFFER_LENGTH(x) ((x)&0xff) 295 296#define PSC0_BUFFER_ADDRESS(x) ((x)&~0x3) 297#define PSC0_FORCE_LOAD (1<<1) 298#define PSC0_BUFFER_VALID (1<<0) 299#define PSC1_BUFFER_LENGTH(x) ((x)&0xff) 300 301/* _3DSTATE_RASTERIZATION_RULES */ 302#define _3DSTATE_RASTER_RULES_CMD (CMD_3D|(0x07<<24)) 303#define ENABLE_POINT_RASTER_RULE (1<<15) 304#define OGL_POINT_RASTER_RULE (1<<13) 305#define ENABLE_TEXKILL_3D_4D (1<<10) 306#define TEXKILL_3D (0<<9) 307#define TEXKILL_4D (1<<9) 308#define ENABLE_LINE_STRIP_PROVOKE_VRTX (1<<8) 309#define ENABLE_TRI_FAN_PROVOKE_VRTX (1<<5) 310#define LINE_STRIP_PROVOKE_VRTX(x) ((x)<<6) 311#define TRI_FAN_PROVOKE_VRTX(x) ((x)<<3) 312 313/* _3DSTATE_SCISSOR_ENABLE, p256 */ 314#define _3DSTATE_SCISSOR_ENABLE_CMD (CMD_3D|(0x1c<<24)|(0x10<<19)) 315#define ENABLE_SCISSOR_RECT ((1<<1) | 1) 316#define DISABLE_SCISSOR_RECT (1<<1) 317 318/* _3DSTATE_SCISSOR_RECTANGLE_0, p257 */ 319#define _3DSTATE_SCISSOR_RECT_0_CMD (CMD_3D|(0x1d<<24)|(0x81<<16)|1) 320/* Dword 1 */ 321#define SCISSOR_RECT_0_YMIN(x) ((x)<<16) 322#define SCISSOR_RECT_0_XMIN(x) (x) 323/* Dword 2 */ 324#define SCISSOR_RECT_0_YMAX(x) ((x)<<16) 325#define SCISSOR_RECT_0_XMAX(x) (x) 326 327/* p189 */ 328#define _3DSTATE_LOAD_STATE_IMMEDIATE_1 ((0x3<<29)|(0x1d<<24)|(0x04<<16)) 329#define I1_LOAD_S(n) (1<<(4+n)) 330 331#define S0_VB_OFFSET_MASK 0xffffffc 332#define S0_AUTO_CACHE_INV_DISABLE (1<<0) 333 334#define S1_VERTEX_WIDTH_SHIFT 24 335#define S1_VERTEX_WIDTH_MASK (0x3f<<24) 336#define S1_VERTEX_PITCH_SHIFT 16 337#define S1_VERTEX_PITCH_MASK (0x3f<<16) 338 339#define TEXCOORDFMT_2D 0x0 340#define TEXCOORDFMT_3D 0x1 341#define TEXCOORDFMT_4D 0x2 342#define TEXCOORDFMT_1D 0x3 343#define TEXCOORDFMT_2D_16 0x4 344#define TEXCOORDFMT_4D_16 0x5 345#define TEXCOORDFMT_NOT_PRESENT 0xf 346#define S2_TEXCOORD_FMT0_MASK 0xf 347#define S2_TEXCOORD_FMT1_SHIFT 4 348#define S2_TEXCOORD_FMT(unit, type) ((type)<<(unit*4)) 349#define S2_TEXCOORD_NONE (~0) 350 351#define TEXCOORD_WRAP_SHORTEST_TCX 8 352#define TEXCOORD_WRAP_SHORTEST_TCY 4 353#define TEXCOORD_WRAP_SHORTEST_TCZ 2 354#define TEXCOORD_PERSPECTIVE_DISABLE 1 355 356#define S3_WRAP_SHORTEST_TCX(unit) (TEXCOORD_WRAP_SHORTEST_TCX << ((unit) * 4)) 357#define S3_WRAP_SHORTEST_TCY(unit) (TEXCOORD_WRAP_SHORTEST_TCY << ((unit) * 4)) 358#define S3_WRAP_SHORTEST_TCZ(unit) (TEXCOORD_WRAP_SHORTEST_TCZ << ((unit) * 4)) 359#define S3_PERSPECTIVE_DISABLE(unit) (TEXCOORD_PERSPECTIVE_DISABLE << ((unit) * 4)) 360 361/* S3 not interesting */ 362 363#define S4_POINT_WIDTH_SHIFT 23 364#define S4_POINT_WIDTH_MASK (0x1ff<<23) 365#define S4_LINE_WIDTH_SHIFT 19 366#define S4_LINE_WIDTH_ONE (0x2<<19) 367#define S4_LINE_WIDTH_MASK (0xf<<19) 368#define S4_FLATSHADE_ALPHA (1<<18) 369#define S4_FLATSHADE_FOG (1<<17) 370#define S4_FLATSHADE_SPECULAR (1<<16) 371#define S4_FLATSHADE_COLOR (1<<15) 372#define S4_CULLMODE_BOTH (0<<13) 373#define S4_CULLMODE_NONE (1<<13) 374#define S4_CULLMODE_CW (2<<13) 375#define S4_CULLMODE_CCW (3<<13) 376#define S4_CULLMODE_MASK (3<<13) 377#define S4_VFMT_POINT_WIDTH (1<<12) 378#define S4_VFMT_SPEC_FOG (1<<11) 379#define S4_VFMT_COLOR (1<<10) 380#define S4_VFMT_DEPTH_OFFSET (1<<9) 381#define S4_VFMT_XYZ (1<<6) 382#define S4_VFMT_XYZW (2<<6) 383#define S4_VFMT_XY (3<<6) 384#define S4_VFMT_XYW (4<<6) 385#define S4_VFMT_XYZW_MASK (7<<6) 386#define S4_FORCE_DEFAULT_DIFFUSE (1<<5) 387#define S4_FORCE_DEFAULT_SPECULAR (1<<4) 388#define S4_LOCAL_DEPTH_OFFSET_ENABLE (1<<3) 389#define S4_VFMT_FOG_PARAM (1<<2) 390#define S4_SPRITE_POINT_ENABLE (1<<1) 391#define S4_LINE_ANTIALIAS_ENABLE (1<<0) 392 393#define S4_VFMT_MASK (S4_VFMT_POINT_WIDTH | \ 394 S4_VFMT_SPEC_FOG | \ 395 S4_VFMT_COLOR | \ 396 S4_VFMT_DEPTH_OFFSET | \ 397 S4_VFMT_XYZW_MASK | \ 398 S4_VFMT_FOG_PARAM) 399 400#define S5_WRITEDISABLE_ALPHA (1<<31) 401#define S5_WRITEDISABLE_RED (1<<30) 402#define S5_WRITEDISABLE_GREEN (1<<29) 403#define S5_WRITEDISABLE_BLUE (1<<28) 404#define S5_WRITEDISABLE_MASK (0xf<<28) 405#define S5_FORCE_DEFAULT_POINT_SIZE (1<<27) 406#define S5_LAST_PIXEL_ENABLE (1<<26) 407#define S5_GLOBAL_DEPTH_OFFSET_ENABLE (1<<25) 408#define S5_FOG_ENABLE (1<<24) 409#define S5_STENCIL_REF_SHIFT 16 410#define S5_STENCIL_REF_MASK (0xff<<16) 411#define S5_STENCIL_TEST_FUNC_SHIFT 13 412#define S5_STENCIL_TEST_FUNC_MASK (0x7<<13) 413#define S5_STENCIL_FAIL_SHIFT 10 414#define S5_STENCIL_FAIL_MASK (0x7<<10) 415#define S5_STENCIL_PASS_Z_FAIL_SHIFT 7 416#define S5_STENCIL_PASS_Z_FAIL_MASK (0x7<<7) 417#define S5_STENCIL_PASS_Z_PASS_SHIFT 4 418#define S5_STENCIL_PASS_Z_PASS_MASK (0x7<<4) 419#define S5_STENCIL_WRITE_ENABLE (1<<3) 420#define S5_STENCIL_TEST_ENABLE (1<<2) 421#define S5_COLOR_DITHER_ENABLE (1<<1) 422#define S5_LOGICOP_ENABLE (1<<0) 423 424#define S6_ALPHA_TEST_ENABLE (1<<31) 425#define S6_ALPHA_TEST_FUNC_SHIFT 28 426#define S6_ALPHA_TEST_FUNC_MASK (0x7<<28) 427#define S6_ALPHA_REF_SHIFT 20 428#define S6_ALPHA_REF_MASK (0xff<<20) 429#define S6_DEPTH_TEST_ENABLE (1<<19) 430#define S6_DEPTH_TEST_FUNC_SHIFT 16 431#define S6_DEPTH_TEST_FUNC_MASK (0x7<<16) 432#define S6_CBUF_BLEND_ENABLE (1<<15) 433#define S6_CBUF_BLEND_FUNC_SHIFT 12 434#define S6_CBUF_BLEND_FUNC_MASK (0x7<<12) 435#define S6_CBUF_SRC_BLEND_FACT_SHIFT 8 436#define S6_CBUF_SRC_BLEND_FACT_MASK (0xf<<8) 437#define S6_CBUF_DST_BLEND_FACT_SHIFT 4 438#define S6_CBUF_DST_BLEND_FACT_MASK (0xf<<4) 439#define S6_DEPTH_WRITE_ENABLE (1<<3) 440#define S6_COLOR_WRITE_ENABLE (1<<2) 441#define S6_TRISTRIP_PV_SHIFT 0 442#define S6_TRISTRIP_PV_MASK (0x3<<0) 443 444#define S7_DEPTH_OFFSET_CONST_MASK ~0 445 446/* 3DSTATE_MAP_DEINTERLACER_PARAMETERS */ 447/* 3DSTATE_MAP_PALETTE_LOAD_32, p206 */ 448 449/* _3DSTATE_MODES_4, p218 */ 450#define _3DSTATE_MODES_4_CMD (CMD_3D|(0x0d<<24)) 451#define ENABLE_LOGIC_OP_FUNC (1<<23) 452#define LOGIC_OP_FUNC(x) ((x)<<18) 453#define LOGICOP_MASK (0xf<<18) 454#define LOGICOP_COPY 0xc 455#define MODE4_ENABLE_STENCIL_TEST_MASK ((1<<17)|(0xff00)) 456#define ENABLE_STENCIL_TEST_MASK (1<<17) 457#define STENCIL_TEST_MASK(x) ((x)<<8) 458#define MODE4_ENABLE_STENCIL_WRITE_MASK ((1<<16)|(0x00ff)) 459#define ENABLE_STENCIL_WRITE_MASK (1<<16) 460#define STENCIL_WRITE_MASK(x) ((x)&0xff) 461 462/* _3DSTATE_MODES_5, p220 */ 463#define _3DSTATE_MODES_5_CMD (CMD_3D|(0x0c<<24)) 464#define PIPELINE_FLUSH_RENDER_CACHE (1<<18) 465#define PIPELINE_FLUSH_TEXTURE_CACHE (1<<16) 466 467/* p221 */ 468#define _3DSTATE_PIXEL_SHADER_CONSTANTS (CMD_3D|(0x1d<<24)|(0x6<<16)) 469#define PS1_REG(n) (1<<(n)) 470#define PS2_CONST_X(n) (n) 471#define PS3_CONST_Y(n) (n) 472#define PS4_CONST_Z(n) (n) 473#define PS5_CONST_W(n) (n) 474 475/* p222 */ 476 477#define I915_MAX_TEX_INDIRECT 4 478#define I915_MAX_TEX_INSN 32 479#define I915_MAX_ALU_INSN 64 480#define I915_MAX_DECL_INSN 27 481#define I915_MAX_TEMPORARY 16 482 483/* Each instruction is 3 dwords long, though most don't require all 484 * this space. Maximum of 123 instructions. Smaller maxes per insn 485 * type. 486 */ 487#define _3DSTATE_PIXEL_SHADER_PROGRAM (CMD_3D|(0x1d<<24)|(0x5<<16)) 488 489#define REG_TYPE_R 0 /* temporary regs, no need to 490 * dcl, must be written before 491 * read -- Preserved between 492 * phases. 493 */ 494#define REG_TYPE_T 1 /* Interpolated values, must be 495 * dcl'ed before use. 496 * 497 * 0..7: texture coord, 498 * 8: diffuse spec, 499 * 9: specular color, 500 * 10: fog parameter in w. 501 */ 502#define REG_TYPE_CONST 2 /* Restriction: only one const 503 * can be referenced per 504 * instruction, though it may be 505 * selected for multiple inputs. 506 * Constants not initialized 507 * default to zero. 508 */ 509#define REG_TYPE_S 3 /* sampler */ 510#define REG_TYPE_OC 4 /* output color (rgba) */ 511#define REG_TYPE_OD 5 /* output depth (w), xyz are 512 * temporaries. If not written, 513 * interpolated depth is used? 514 */ 515#define REG_TYPE_U 6 /* unpreserved temporaries */ 516#define REG_TYPE_MASK 0x7 517#define REG_NR_MASK 0xf 518 519/* REG_TYPE_T: 520 */ 521#define T_TEX0 0 522#define T_TEX1 1 523#define T_TEX2 2 524#define T_TEX3 3 525#define T_TEX4 4 526#define T_TEX5 5 527#define T_TEX6 6 528#define T_TEX7 7 529#define T_DIFFUSE 8 530#define T_SPECULAR 9 531#define T_FOG_W 10 /* interpolated fog is in W coord */ 532 533/* Arithmetic instructions */ 534 535/* .replicate_swizzle == selection and replication of a particular 536 * scalar channel, ie., .xxxx, .yyyy, .zzzz or .wwww 537 */ 538#define A0_NOP (0x0<<24) /* no operation */ 539#define A0_ADD (0x1<<24) /* dst = src0 + src1 */ 540#define A0_MOV (0x2<<24) /* dst = src0 */ 541#define A0_MUL (0x3<<24) /* dst = src0 * src1 */ 542#define A0_MAD (0x4<<24) /* dst = src0 * src1 + src2 */ 543#define A0_DP2ADD (0x5<<24) /* dst.xyzw = src0.xy dot src1.xy + src2.replicate_swizzle */ 544#define A0_DP3 (0x6<<24) /* dst.xyzw = src0.xyz dot src1.xyz */ 545#define A0_DP4 (0x7<<24) /* dst.xyzw = src0.xyzw dot src1.xyzw */ 546#define A0_FRC (0x8<<24) /* dst = src0 - floor(src0) */ 547#define A0_RCP (0x9<<24) /* dst.xyzw = 1/(src0.replicate_swizzle) */ 548#define A0_RSQ (0xa<<24) /* dst.xyzw = 1/(sqrt(abs(src0.replicate_swizzle))) */ 549#define A0_EXP (0xb<<24) /* dst.xyzw = exp2(src0.replicate_swizzle) */ 550#define A0_LOG (0xc<<24) /* dst.xyzw = log2(abs(src0.replicate_swizzle)) */ 551#define A0_CMP (0xd<<24) /* dst = (src0 >= 0.0) ? src1 : src2 */ 552#define A0_MIN (0xe<<24) /* dst = (src0 < src1) ? src0 : src1 */ 553#define A0_MAX (0xf<<24) /* dst = (src0 >= src1) ? src0 : src1 */ 554#define A0_FLR (0x10<<24) /* dst = floor(src0) */ 555#define A0_MOD (0x11<<24) /* dst = src0 fmod 1.0 */ 556#define A0_TRC (0x12<<24) /* dst = int(src0) */ 557#define A0_SGE (0x13<<24) /* dst = src0 >= src1 ? 1.0 : 0.0 */ 558#define A0_SLT (0x14<<24) /* dst = src0 < src1 ? 1.0 : 0.0 */ 559#define A0_DEST_SATURATE (1<<22) 560#define A0_DEST_TYPE_SHIFT 19 561/* Allow: R, OC, OD, U */ 562#define A0_DEST_NR_SHIFT 14 563/* Allow R: 0..15, OC,OD: 0..0, U: 0..2 */ 564#define A0_DEST_CHANNEL_X (1<<10) 565#define A0_DEST_CHANNEL_Y (2<<10) 566#define A0_DEST_CHANNEL_Z (4<<10) 567#define A0_DEST_CHANNEL_W (8<<10) 568#define A0_DEST_CHANNEL_ALL (0xf<<10) 569#define A0_DEST_CHANNEL_SHIFT 10 570#define A0_SRC0_TYPE_SHIFT 7 571#define A0_SRC0_NR_SHIFT 2 572 573#define A0_DEST_CHANNEL_XY (A0_DEST_CHANNEL_X|A0_DEST_CHANNEL_Y) 574#define A0_DEST_CHANNEL_XYZ (A0_DEST_CHANNEL_XY|A0_DEST_CHANNEL_Z) 575 576#define SRC_X 0 577#define SRC_Y 1 578#define SRC_Z 2 579#define SRC_W 3 580#define SRC_ZERO 4 581#define SRC_ONE 5 582 583#define A1_SRC0_CHANNEL_X_NEGATE (1<<31) 584#define A1_SRC0_CHANNEL_X_SHIFT 28 585#define A1_SRC0_CHANNEL_Y_NEGATE (1<<27) 586#define A1_SRC0_CHANNEL_Y_SHIFT 24 587#define A1_SRC0_CHANNEL_Z_NEGATE (1<<23) 588#define A1_SRC0_CHANNEL_Z_SHIFT 20 589#define A1_SRC0_CHANNEL_W_NEGATE (1<<19) 590#define A1_SRC0_CHANNEL_W_SHIFT 16 591#define A1_SRC1_TYPE_SHIFT 13 592#define A1_SRC1_NR_SHIFT 8 593#define A1_SRC1_CHANNEL_X_NEGATE (1<<7) 594#define A1_SRC1_CHANNEL_X_SHIFT 4 595#define A1_SRC1_CHANNEL_Y_NEGATE (1<<3) 596#define A1_SRC1_CHANNEL_Y_SHIFT 0 597 598#define A2_SRC1_CHANNEL_Z_NEGATE (1<<31) 599#define A2_SRC1_CHANNEL_Z_SHIFT 28 600#define A2_SRC1_CHANNEL_W_NEGATE (1<<27) 601#define A2_SRC1_CHANNEL_W_SHIFT 24 602#define A2_SRC2_TYPE_SHIFT 21 603#define A2_SRC2_NR_SHIFT 16 604#define A2_SRC2_CHANNEL_X_NEGATE (1<<15) 605#define A2_SRC2_CHANNEL_X_SHIFT 12 606#define A2_SRC2_CHANNEL_Y_NEGATE (1<<11) 607#define A2_SRC2_CHANNEL_Y_SHIFT 8 608#define A2_SRC2_CHANNEL_Z_NEGATE (1<<7) 609#define A2_SRC2_CHANNEL_Z_SHIFT 4 610#define A2_SRC2_CHANNEL_W_NEGATE (1<<3) 611#define A2_SRC2_CHANNEL_W_SHIFT 0 612 613/* Texture instructions */ 614#define T0_TEXLD (0x15<<24) /* Sample texture using predeclared 615 * sampler and address, and output 616 * filtered texel data to destination 617 * register */ 618#define T0_TEXLDP (0x16<<24) /* Same as texld but performs a 619 * perspective divide of the texture 620 * coordinate .xyz values by .w before 621 * sampling. */ 622#define T0_TEXLDB (0x17<<24) /* Same as texld but biases the 623 * computed LOD by w. Only S4.6 two's 624 * comp is used. This implies that a 625 * float to fixed conversion is 626 * done. */ 627#define T0_TEXKILL (0x18<<24) /* Does not perform a sampling 628 * operation. Simply kills the pixel 629 * if any channel of the address 630 * register is < 0.0. */ 631#define T0_DEST_TYPE_SHIFT 19 632/* Allow: R, OC, OD, U */ 633/* Note: U (unpreserved) regs do not retain their values between 634 * phases (cannot be used for feedback) 635 * 636 * Note: oC and OD registers can only be used as the destination of a 637 * texture instruction once per phase (this is an implementation 638 * restriction). 639 */ 640#define T0_DEST_NR_SHIFT 14 641/* Allow R: 0..15, OC,OD: 0..0, U: 0..2 */ 642#define T0_SAMPLER_NR_SHIFT 0 /* This field ignored for TEXKILL */ 643#define T0_SAMPLER_NR_MASK (0xf<<0) 644 645#define T1_ADDRESS_REG_TYPE_SHIFT 24 /* Reg to use as texture coord */ 646/* Allow R, T, OC, OD -- R, OC, OD are 'dependent' reads, new program phase */ 647#define T1_ADDRESS_REG_NR_SHIFT 17 648#define T2_MBZ 0 649 650/* Declaration instructions */ 651#define D0_DCL (0x19<<24) /* Declare a t (interpolated attrib) 652 * register or an s (sampler) 653 * register. */ 654#define D0_SAMPLE_TYPE_SHIFT 22 655#define D0_SAMPLE_TYPE_2D (0x0<<22) 656#define D0_SAMPLE_TYPE_CUBE (0x1<<22) 657#define D0_SAMPLE_TYPE_VOLUME (0x2<<22) 658#define D0_SAMPLE_TYPE_MASK (0x3<<22) 659 660#define D0_TYPE_SHIFT 19 661/* Allow: T, S */ 662#define D0_NR_SHIFT 14 663/* Allow T: 0..10, S: 0..15 */ 664#define D0_CHANNEL_X (1<<10) 665#define D0_CHANNEL_Y (2<<10) 666#define D0_CHANNEL_Z (4<<10) 667#define D0_CHANNEL_W (8<<10) 668#define D0_CHANNEL_ALL (0xf<<10) 669#define D0_CHANNEL_NONE (0<<10) 670 671#define D0_CHANNEL_XY (D0_CHANNEL_X|D0_CHANNEL_Y) 672#define D0_CHANNEL_XYZ (D0_CHANNEL_XY|D0_CHANNEL_Z) 673 674/* I915 Errata: Do not allow (xz), (xw), (xzw) combinations for diffuse 675 * or specular declarations. 676 * 677 * For T dcls, only allow: (x), (xy), (xyz), (w), (xyzw) 678 * 679 * Must be zero for S (sampler) dcls 680 */ 681#define D1_MBZ 0 682#define D2_MBZ 0 683 684/* p207. 685 * The DWORD count is 3 times the number of bits set in MS1_MAPMASK_MASK 686 */ 687#define _3DSTATE_MAP_STATE (CMD_3D|(0x1d<<24)|(0x0<<16)) 688 689#define MS1_MAPMASK_SHIFT 0 690#define MS1_MAPMASK_MASK (0x8fff<<0) 691 692#define MS2_UNTRUSTED_SURFACE (1<<31) 693#define MS2_ADDRESS_MASK 0xfffffffc 694#define MS2_VERTICAL_LINE_STRIDE (1<<1) 695#define MS2_VERTICAL_OFFSET (1<<1) 696 697#define MS3_HEIGHT_SHIFT 21 698#define MS3_WIDTH_SHIFT 10 699#define MS3_PALETTE_SELECT (1<<9) 700#define MS3_MAPSURF_FORMAT_SHIFT 7 701#define MS3_MAPSURF_FORMAT_MASK (0x7<<7) 702#define MAPSURF_8BIT (1<<7) 703#define MAPSURF_16BIT (2<<7) 704#define MAPSURF_32BIT (3<<7) 705#define MAPSURF_422 (5<<7) 706#define MAPSURF_COMPRESSED (6<<7) 707#define MAPSURF_4BIT_INDEXED (7<<7) 708#define MS3_MT_FORMAT_MASK (0x7 << 3) 709#define MS3_MT_FORMAT_SHIFT 3 710#define MT_4BIT_IDX_ARGB8888 (7<<3) /* SURFACE_4BIT_INDEXED */ 711#define MT_8BIT_I8 (0<<3) /* SURFACE_8BIT */ 712#define MT_8BIT_L8 (1<<3) 713#define MT_8BIT_A8 (4<<3) 714#define MT_8BIT_MONO8 (5<<3) 715#define MT_16BIT_RGB565 (0<<3) /* SURFACE_16BIT */ 716#define MT_16BIT_ARGB1555 (1<<3) 717#define MT_16BIT_ARGB4444 (2<<3) 718#define MT_16BIT_AY88 (3<<3) 719#define MT_16BIT_88DVDU (5<<3) 720#define MT_16BIT_BUMP_655LDVDU (6<<3) 721#define MT_16BIT_I16 (7<<3) 722#define MT_16BIT_L16 (8<<3) 723#define MT_16BIT_A16 (9<<3) 724#define MT_32BIT_ARGB8888 (0<<3) /* SURFACE_32BIT */ 725#define MT_32BIT_ABGR8888 (1<<3) 726#define MT_32BIT_XRGB8888 (2<<3) 727#define MT_32BIT_XBGR8888 (3<<3) 728#define MT_32BIT_QWVU8888 (4<<3) 729#define MT_32BIT_AXVU8888 (5<<3) 730#define MT_32BIT_LXVU8888 (6<<3) 731#define MT_32BIT_XLVU8888 (7<<3) 732#define MT_32BIT_ARGB2101010 (8<<3) 733#define MT_32BIT_ABGR2101010 (9<<3) 734#define MT_32BIT_AWVU2101010 (0xA<<3) 735#define MT_32BIT_GR1616 (0xB<<3) 736#define MT_32BIT_VU1616 (0xC<<3) 737#define MT_32BIT_xI824 (0xD<<3) 738#define MT_32BIT_xA824 (0xE<<3) 739#define MT_32BIT_xL824 (0xF<<3) 740#define MT_422_YCRCB_SWAPY (0<<3) /* SURFACE_422 */ 741#define MT_422_YCRCB_NORMAL (1<<3) 742#define MT_422_YCRCB_SWAPUV (2<<3) 743#define MT_422_YCRCB_SWAPUVY (3<<3) 744#define MT_COMPRESS_DXT1 (0<<3) /* SURFACE_COMPRESSED */ 745#define MT_COMPRESS_DXT2_3 (1<<3) 746#define MT_COMPRESS_DXT4_5 (2<<3) 747#define MT_COMPRESS_FXT1 (3<<3) 748#define MT_COMPRESS_DXT1_RGB (4<<3) 749#define MS3_USE_FENCE_REGS (1<<2) 750#define MS3_TILED_SURFACE (1<<1) 751#define MS3_TILE_WALK (1<<0) 752 753/* The pitch is the pitch measured in DWORDS, minus 1 */ 754#define MS4_PITCH_SHIFT 21 755#define MS4_CUBE_FACE_ENA_NEGX (1<<20) 756#define MS4_CUBE_FACE_ENA_POSX (1<<19) 757#define MS4_CUBE_FACE_ENA_NEGY (1<<18) 758#define MS4_CUBE_FACE_ENA_POSY (1<<17) 759#define MS4_CUBE_FACE_ENA_NEGZ (1<<16) 760#define MS4_CUBE_FACE_ENA_POSZ (1<<15) 761#define MS4_CUBE_FACE_ENA_MASK (0x3f<<15) 762#define MS4_MAX_LOD_SHIFT 9 763#define MS4_MAX_LOD_MASK (0x3f<<9) 764#define MS4_MIP_LAYOUT_LEGACY (0<<8) 765#define MS4_MIP_LAYOUT_BELOW_LPT (0<<8) 766#define MS4_MIP_LAYOUT_RIGHT_LPT (1<<8) 767#define MS4_VOLUME_DEPTH_SHIFT 0 768#define MS4_VOLUME_DEPTH_MASK (0xff<<0) 769 770/* p244. 771 * The DWORD count is 3 times the number of bits set in SS1_MAPMASK_MASK. 772 */ 773#define _3DSTATE_SAMPLER_STATE (CMD_3D|(0x1d<<24)|(0x1<<16)) 774 775#define SS1_MAPMASK_SHIFT 0 776#define SS1_MAPMASK_MASK (0x8fff<<0) 777 778#define SS2_REVERSE_GAMMA_ENABLE (1<<31) 779#define SS2_PACKED_TO_PLANAR_ENABLE (1<<30) 780#define SS2_COLORSPACE_CONVERSION (1<<29) 781#define SS2_CHROMAKEY_SHIFT 27 782#define SS2_BASE_MIP_LEVEL_SHIFT 22 783#define SS2_BASE_MIP_LEVEL_MASK (0x1f<<22) 784#define SS2_MIP_FILTER_SHIFT 20 785#define SS2_MIP_FILTER_MASK (0x3<<20) 786#define MIPFILTER_NONE 0 787#define MIPFILTER_NEAREST 1 788#define MIPFILTER_LINEAR 3 789#define SS2_MAG_FILTER_SHIFT 17 790#define SS2_MAG_FILTER_MASK (0x7<<17) 791#define FILTER_NEAREST 0 792#define FILTER_LINEAR 1 793#define FILTER_ANISOTROPIC 2 794#define FILTER_4X4_1 3 795#define FILTER_4X4_2 4 796#define FILTER_4X4_FLAT 5 797#define FILTER_6X5_MONO 6 /* XXX - check */ 798#define SS2_MIN_FILTER_SHIFT 14 799#define SS2_MIN_FILTER_MASK (0x7<<14) 800#define SS2_LOD_BIAS_SHIFT 5 801#define SS2_LOD_BIAS_ONE (0x10<<5) 802#define SS2_LOD_BIAS_MASK (0x1ff<<5) 803/* Shadow requires: 804 * MT_X8{I,L,A}24 or MT_{I,L,A}16 texture format 805 * FILTER_4X4_x MIN and MAG filters 806 */ 807#define SS2_SHADOW_ENABLE (1<<4) 808#define SS2_MAX_ANISO_MASK (1<<3) 809#define SS2_MAX_ANISO_2 (0<<3) 810#define SS2_MAX_ANISO_4 (1<<3) 811#define SS2_SHADOW_FUNC_SHIFT 0 812#define SS2_SHADOW_FUNC_MASK (0x7<<0) 813/* SS2_SHADOW_FUNC values: see COMPAREFUNC_* */ 814 815#define SS3_MIN_LOD_SHIFT 24 816#define SS3_MIN_LOD_ONE (0x10<<24) 817#define SS3_MIN_LOD_MASK (0xff<<24) 818#define SS3_KILL_PIXEL_ENABLE (1<<17) 819#define SS3_TCX_ADDR_MODE_SHIFT 12 820#define SS3_TCX_ADDR_MODE_MASK (0x7<<12) 821#define TEXCOORDMODE_WRAP 0 822#define TEXCOORDMODE_MIRROR 1 823#define TEXCOORDMODE_CLAMP_EDGE 2 824#define TEXCOORDMODE_CUBE 3 825#define TEXCOORDMODE_CLAMP_BORDER 4 826#define TEXCOORDMODE_MIRROR_ONCE 5 827#define SS3_TCY_ADDR_MODE_SHIFT 9 828#define SS3_TCY_ADDR_MODE_MASK (0x7<<9) 829#define SS3_TCZ_ADDR_MODE_SHIFT 6 830#define SS3_TCZ_ADDR_MODE_MASK (0x7<<6) 831#define SS3_NORMALIZED_COORDS (1<<5) 832#define SS3_TEXTUREMAP_INDEX_SHIFT 1 833#define SS3_TEXTUREMAP_INDEX_MASK (0xf<<1) 834#define SS3_DEINTERLACER_ENABLE (1<<0) 835 836#define SS4_BORDER_COLOR_MASK (~0) 837 838/* 3DSTATE_SPAN_STIPPLE, p258 839 */ 840#define _3DSTATE_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 841#define ST1_ENABLE (1<<16) 842#define ST1_MASK (0xffff) 843 844#define FLUSH_MAP_CACHE (1<<0) 845#define FLUSH_RENDER_CACHE (1<<1) 846 847#endif 848/* -*- c-basic-offset: 4 -*- */ 849/* 850 * Copyright © 2006,2010 Intel Corporation 851 * 852 * Permission is hereby granted, free of charge, to any person obtaining a 853 * copy of this software and associated documentation files (the "Software"), 854 * to deal in the Software without restriction, including without limitation 855 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 856 * and/or sell copies of the Software, and to permit persons to whom the 857 * Software is furnished to do so, subject to the following conditions: 858 * 859 * The above copyright notice and this permission notice (including the next 860 * paragraph) shall be included in all copies or substantial portions of the 861 * Software. 862 * 863 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 864 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 865 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 866 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 867 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 868 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 869 * SOFTWARE. 870 * 871 * Authors: 872 * Eric Anholt <eric@anholt.net> 873 * Chris Wilson <chris@chris-wilson.co.uk> 874 * 875 */ 876 877/* Each instruction is 3 dwords long, though most don't require all 878 * this space. Maximum of 123 instructions. Smaller maxes per insn 879 * type. 880 */ 881#define _3DSTATE_PIXEL_SHADER_PROGRAM (CMD_3D|(0x1d<<24)|(0x5<<16)) 882 883#define REG_TYPE_R 0 /* temporary regs, no need to 884 * dcl, must be written before 885 * read -- Preserved between 886 * phases. 887 */ 888#define REG_TYPE_T 1 /* Interpolated values, must be 889 * dcl'ed before use. 890 * 891 * 0..7: texture coord, 892 * 8: diffuse spec, 893 * 9: specular color, 894 * 10: fog parameter in w. 895 */ 896#define REG_TYPE_CONST 2 /* Restriction: only one const 897 * can be referenced per 898 * instruction, though it may be 899 * selected for multiple inputs. 900 * Constants not initialized 901 * default to zero. 902 */ 903#define REG_TYPE_S 3 /* sampler */ 904#define REG_TYPE_OC 4 /* output color (rgba) */ 905#define REG_TYPE_OD 5 /* output depth (w), xyz are 906 * temporaries. If not written, 907 * interpolated depth is used? 908 */ 909#define REG_TYPE_U 6 /* unpreserved temporaries */ 910#define REG_TYPE_MASK 0x7 911#define REG_TYPE_SHIFT 4 912#define REG_NR_MASK 0xf 913 914/* REG_TYPE_T: 915*/ 916#define T_TEX0 0 917#define T_TEX1 1 918#define T_TEX2 2 919#define T_TEX3 3 920#define T_TEX4 4 921#define T_TEX5 5 922#define T_TEX6 6 923#define T_TEX7 7 924#define T_DIFFUSE 8 925#define T_SPECULAR 9 926#define T_FOG_W 10 /* interpolated fog is in W coord */ 927 928/* Arithmetic instructions */ 929 930/* .replicate_swizzle == selection and replication of a particular 931 * scalar channel, ie., .xxxx, .yyyy, .zzzz or .wwww 932 */ 933#define A0_NOP (0x0<<24) /* no operation */ 934#define A0_ADD (0x1<<24) /* dst = src0 + src1 */ 935#define A0_MOV (0x2<<24) /* dst = src0 */ 936#define A0_MUL (0x3<<24) /* dst = src0 * src1 */ 937#define A0_MAD (0x4<<24) /* dst = src0 * src1 + src2 */ 938#define A0_DP2ADD (0x5<<24) /* dst.xyzw = src0.xy dot src1.xy + src2.replicate_swizzle */ 939#define A0_DP3 (0x6<<24) /* dst.xyzw = src0.xyz dot src1.xyz */ 940#define A0_DP4 (0x7<<24) /* dst.xyzw = src0.xyzw dot src1.xyzw */ 941#define A0_FRC (0x8<<24) /* dst = src0 - floor(src0) */ 942#define A0_RCP (0x9<<24) /* dst.xyzw = 1/(src0.replicate_swizzle) */ 943#define A0_RSQ (0xa<<24) /* dst.xyzw = 1/(sqrt(abs(src0.replicate_swizzle))) */ 944#define A0_EXP (0xb<<24) /* dst.xyzw = exp2(src0.replicate_swizzle) */ 945#define A0_LOG (0xc<<24) /* dst.xyzw = log2(abs(src0.replicate_swizzle)) */ 946#define A0_CMP (0xd<<24) /* dst = (src0 >= 0.0) ? src1 : src2 */ 947#define A0_MIN (0xe<<24) /* dst = (src0 < src1) ? src0 : src1 */ 948#define A0_MAX (0xf<<24) /* dst = (src0 >= src1) ? src0 : src1 */ 949#define A0_FLR (0x10<<24) /* dst = floor(src0) */ 950#define A0_MOD (0x11<<24) /* dst = src0 fmod 1.0 */ 951#define A0_TRC (0x12<<24) /* dst = int(src0) */ 952#define A0_SGE (0x13<<24) /* dst = src0 >= src1 ? 1.0 : 0.0 */ 953#define A0_SLT (0x14<<24) /* dst = src0 < src1 ? 1.0 : 0.0 */ 954#define A0_DEST_SATURATE (1<<22) 955#define A0_DEST_TYPE_SHIFT 19 956/* Allow: R, OC, OD, U */ 957#define A0_DEST_NR_SHIFT 14 958/* Allow R: 0..15, OC,OD: 0..0, U: 0..2 */ 959#define A0_DEST_CHANNEL_X (1<<10) 960#define A0_DEST_CHANNEL_Y (2<<10) 961#define A0_DEST_CHANNEL_Z (4<<10) 962#define A0_DEST_CHANNEL_W (8<<10) 963#define A0_DEST_CHANNEL_ALL (0xf<<10) 964#define A0_DEST_CHANNEL_SHIFT 10 965#define A0_SRC0_TYPE_SHIFT 7 966#define A0_SRC0_NR_SHIFT 2 967 968#define A0_DEST_CHANNEL_XY (A0_DEST_CHANNEL_X|A0_DEST_CHANNEL_Y) 969#define A0_DEST_CHANNEL_XYZ (A0_DEST_CHANNEL_XY|A0_DEST_CHANNEL_Z) 970 971#define SRC_X 0 972#define SRC_Y 1 973#define SRC_Z 2 974#define SRC_W 3 975#define SRC_ZERO 4 976#define SRC_ONE 5 977 978#define A1_SRC0_CHANNEL_X_NEGATE (1<<31) 979#define A1_SRC0_CHANNEL_X_SHIFT 28 980#define A1_SRC0_CHANNEL_Y_NEGATE (1<<27) 981#define A1_SRC0_CHANNEL_Y_SHIFT 24 982#define A1_SRC0_CHANNEL_Z_NEGATE (1<<23) 983#define A1_SRC0_CHANNEL_Z_SHIFT 20 984#define A1_SRC0_CHANNEL_W_NEGATE (1<<19) 985#define A1_SRC0_CHANNEL_W_SHIFT 16 986#define A1_SRC1_TYPE_SHIFT 13 987#define A1_SRC1_NR_SHIFT 8 988#define A1_SRC1_CHANNEL_X_NEGATE (1<<7) 989#define A1_SRC1_CHANNEL_X_SHIFT 4 990#define A1_SRC1_CHANNEL_Y_NEGATE (1<<3) 991#define A1_SRC1_CHANNEL_Y_SHIFT 0 992 993#define A2_SRC1_CHANNEL_Z_NEGATE (1<<31) 994#define A2_SRC1_CHANNEL_Z_SHIFT 28 995#define A2_SRC1_CHANNEL_W_NEGATE (1<<27) 996#define A2_SRC1_CHANNEL_W_SHIFT 24 997#define A2_SRC2_TYPE_SHIFT 21 998#define A2_SRC2_NR_SHIFT 16 999#define A2_SRC2_CHANNEL_X_NEGATE (1<<15) 1000#define A2_SRC2_CHANNEL_X_SHIFT 12 1001#define A2_SRC2_CHANNEL_Y_NEGATE (1<<11) 1002#define A2_SRC2_CHANNEL_Y_SHIFT 8 1003#define A2_SRC2_CHANNEL_Z_NEGATE (1<<7) 1004#define A2_SRC2_CHANNEL_Z_SHIFT 4 1005#define A2_SRC2_CHANNEL_W_NEGATE (1<<3) 1006#define A2_SRC2_CHANNEL_W_SHIFT 0 1007 1008/* Texture instructions */ 1009#define T0_TEXLD (0x15<<24) /* Sample texture using predeclared 1010 * sampler and address, and output 1011 * filtered texel data to destination 1012 * register */ 1013#define T0_TEXLDP (0x16<<24) /* Same as texld but performs a 1014 * perspective divide of the texture 1015 * coordinate .xyz values by .w before 1016 * sampling. */ 1017#define T0_TEXLDB (0x17<<24) /* Same as texld but biases the 1018 * computed LOD by w. Only S4.6 two's 1019 * comp is used. This implies that a 1020 * float to fixed conversion is 1021 * done. */ 1022#define T0_TEXKILL (0x18<<24) /* Does not perform a sampling 1023 * operation. Simply kills the pixel 1024 * if any channel of the address 1025 * register is < 0.0. */ 1026#define T0_DEST_TYPE_SHIFT 19 1027/* Allow: R, OC, OD, U */ 1028/* Note: U (unpreserved) regs do not retain their values between 1029 * phases (cannot be used for feedback) 1030 * 1031 * Note: oC and OD registers can only be used as the destination of a 1032 * texture instruction once per phase (this is an implementation 1033 * restriction). 1034 */ 1035#define T0_DEST_NR_SHIFT 14 1036/* Allow R: 0..15, OC,OD: 0..0, U: 0..2 */ 1037#define T0_SAMPLER_NR_SHIFT 0 /* This field ignored for TEXKILL */ 1038#define T0_SAMPLER_NR_MASK (0xf<<0) 1039 1040#define T1_ADDRESS_REG_TYPE_SHIFT 24 /* Reg to use as texture coord */ 1041/* Allow R, T, OC, OD -- R, OC, OD are 'dependent' reads, new program phase */ 1042#define T1_ADDRESS_REG_NR_SHIFT 17 1043#define T2_MBZ 0 1044 1045/* Declaration instructions */ 1046#define D0_DCL (0x19<<24) /* Declare a t (interpolated attrib) 1047 * register or an s (sampler) 1048 * register. */ 1049#define D0_SAMPLE_TYPE_SHIFT 22 1050#define D0_SAMPLE_TYPE_2D (0x0<<22) 1051#define D0_SAMPLE_TYPE_CUBE (0x1<<22) 1052#define D0_SAMPLE_TYPE_VOLUME (0x2<<22) 1053#define D0_SAMPLE_TYPE_MASK (0x3<<22) 1054 1055#define D0_TYPE_SHIFT 19 1056/* Allow: T, S */ 1057#define D0_NR_SHIFT 14 1058/* Allow T: 0..10, S: 0..15 */ 1059#define D0_CHANNEL_X (1<<10) 1060#define D0_CHANNEL_Y (2<<10) 1061#define D0_CHANNEL_Z (4<<10) 1062#define D0_CHANNEL_W (8<<10) 1063#define D0_CHANNEL_ALL (0xf<<10) 1064#define D0_CHANNEL_NONE (0<<10) 1065 1066#define D0_CHANNEL_XY (D0_CHANNEL_X|D0_CHANNEL_Y) 1067#define D0_CHANNEL_XYZ (D0_CHANNEL_XY|D0_CHANNEL_Z) 1068 1069/* I915 Errata: Do not allow (xz), (xw), (xzw) combinations for diffuse 1070 * or specular declarations. 1071 * 1072 * For T dcls, only allow: (x), (xy), (xyz), (w), (xyzw) 1073 * 1074 * Must be zero for S (sampler) dcls 1075 */ 1076#define D1_MBZ 0 1077#define D2_MBZ 0 1078 1079 1080/* MASK_* are the unshifted bitmasks of the destination mask in arithmetic 1081 * operations 1082 */ 1083#define MASK_X 0x1 1084#define MASK_Y 0x2 1085#define MASK_Z 0x4 1086#define MASK_W 0x8 1087#define MASK_XYZ (MASK_X | MASK_Y | MASK_Z) 1088#define MASK_XYZW (MASK_XYZ | MASK_W) 1089#define MASK_SATURATE 0x10 1090 1091/* Temporary, undeclared regs. Preserved between phases */ 1092#define FS_R0 ((REG_TYPE_R << REG_TYPE_SHIFT) | 0) 1093#define FS_R1 ((REG_TYPE_R << REG_TYPE_SHIFT) | 1) 1094#define FS_R2 ((REG_TYPE_R << REG_TYPE_SHIFT) | 2) 1095#define FS_R3 ((REG_TYPE_R << REG_TYPE_SHIFT) | 3) 1096 1097/* Texture coordinate regs. Must be declared. */ 1098#define FS_T0 ((REG_TYPE_T << REG_TYPE_SHIFT) | 0) 1099#define FS_T1 ((REG_TYPE_T << REG_TYPE_SHIFT) | 1) 1100#define FS_T2 ((REG_TYPE_T << REG_TYPE_SHIFT) | 2) 1101#define FS_T3 ((REG_TYPE_T << REG_TYPE_SHIFT) | 3) 1102#define FS_T4 ((REG_TYPE_T << REG_TYPE_SHIFT) | 4) 1103#define FS_T5 ((REG_TYPE_T << REG_TYPE_SHIFT) | 5) 1104#define FS_T6 ((REG_TYPE_T << REG_TYPE_SHIFT) | 6) 1105#define FS_T7 ((REG_TYPE_T << REG_TYPE_SHIFT) | 7) 1106#define FS_T8 ((REG_TYPE_T << REG_TYPE_SHIFT) | 8) 1107#define FS_T9 ((REG_TYPE_T << REG_TYPE_SHIFT) | 9) 1108#define FS_T10 ((REG_TYPE_T << REG_TYPE_SHIFT) | 10) 1109 1110/* Constant values */ 1111#define FS_C0 ((REG_TYPE_CONST << REG_TYPE_SHIFT) | 0) 1112#define FS_C1 ((REG_TYPE_CONST << REG_TYPE_SHIFT) | 1) 1113#define FS_C2 ((REG_TYPE_CONST << REG_TYPE_SHIFT) | 2) 1114#define FS_C3 ((REG_TYPE_CONST << REG_TYPE_SHIFT) | 3) 1115#define FS_C4 ((REG_TYPE_CONST << REG_TYPE_SHIFT) | 4) 1116#define FS_C5 ((REG_TYPE_CONST << REG_TYPE_SHIFT) | 5) 1117#define FS_C6 ((REG_TYPE_CONST << REG_TYPE_SHIFT) | 6) 1118#define FS_C7 ((REG_TYPE_CONST << REG_TYPE_SHIFT) | 7) 1119 1120/* Sampler regs */ 1121#define FS_S0 ((REG_TYPE_S << REG_TYPE_SHIFT) | 0) 1122#define FS_S1 ((REG_TYPE_S << REG_TYPE_SHIFT) | 1) 1123#define FS_S2 ((REG_TYPE_S << REG_TYPE_SHIFT) | 2) 1124#define FS_S3 ((REG_TYPE_S << REG_TYPE_SHIFT) | 3) 1125 1126/* Output color */ 1127#define FS_OC ((REG_TYPE_OC << REG_TYPE_SHIFT) | 0) 1128 1129/* Output depth */ 1130#define FS_OD ((REG_TYPE_OD << REG_TYPE_SHIFT) | 0) 1131 1132/* Unpreserved temporary regs */ 1133#define FS_U0 ((REG_TYPE_U << REG_TYPE_SHIFT) | 0) 1134#define FS_U1 ((REG_TYPE_U << REG_TYPE_SHIFT) | 1) 1135#define FS_U2 ((REG_TYPE_U << REG_TYPE_SHIFT) | 2) 1136#define FS_U3 ((REG_TYPE_U << REG_TYPE_SHIFT) | 3) 1137 1138#define X_CHANNEL_SHIFT (REG_TYPE_SHIFT + 3) 1139#define Y_CHANNEL_SHIFT (X_CHANNEL_SHIFT + 4) 1140#define Z_CHANNEL_SHIFT (Y_CHANNEL_SHIFT + 4) 1141#define W_CHANNEL_SHIFT (Z_CHANNEL_SHIFT + 4) 1142 1143#define REG_CHANNEL_MASK 0xf 1144 1145#define REG_NR(reg) ((reg) & REG_NR_MASK) 1146#define REG_TYPE(reg) (((reg) >> REG_TYPE_SHIFT) & REG_TYPE_MASK) 1147#define REG_X(reg) (((reg) >> X_CHANNEL_SHIFT) & REG_CHANNEL_MASK) 1148#define REG_Y(reg) (((reg) >> Y_CHANNEL_SHIFT) & REG_CHANNEL_MASK) 1149#define REG_Z(reg) (((reg) >> Z_CHANNEL_SHIFT) & REG_CHANNEL_MASK) 1150#define REG_W(reg) (((reg) >> W_CHANNEL_SHIFT) & REG_CHANNEL_MASK) 1151 1152enum gen3_fs_channel { 1153 X_CHANNEL_VAL = 0, 1154 Y_CHANNEL_VAL, 1155 Z_CHANNEL_VAL, 1156 W_CHANNEL_VAL, 1157 ZERO_CHANNEL_VAL, 1158 ONE_CHANNEL_VAL, 1159 1160 NEG_X_CHANNEL_VAL = X_CHANNEL_VAL | 0x8, 1161 NEG_Y_CHANNEL_VAL = Y_CHANNEL_VAL | 0x8, 1162 NEG_Z_CHANNEL_VAL = Z_CHANNEL_VAL | 0x8, 1163 NEG_W_CHANNEL_VAL = W_CHANNEL_VAL | 0x8, 1164 NEG_ONE_CHANNEL_VAL = ONE_CHANNEL_VAL | 0x8 1165}; 1166 1167#define gen3_fs_operand(reg, x, y, z, w) \ 1168 (reg) | \ 1169(x##_CHANNEL_VAL << X_CHANNEL_SHIFT) | \ 1170(y##_CHANNEL_VAL << Y_CHANNEL_SHIFT) | \ 1171(z##_CHANNEL_VAL << Z_CHANNEL_SHIFT) | \ 1172(w##_CHANNEL_VAL << W_CHANNEL_SHIFT) 1173 1174/** 1175 * Construct an operand description for using a register with no swizzling 1176 */ 1177#define gen3_fs_operand_reg(reg) \ 1178 gen3_fs_operand(reg, X, Y, Z, W) 1179 1180#define gen3_fs_operand_reg_negate(reg) \ 1181 gen3_fs_operand(reg, NEG_X, NEG_Y, NEG_Z, NEG_W) 1182 1183/** 1184 * Returns an operand containing (0.0, 0.0, 0.0, 0.0). 1185 */ 1186#define gen3_fs_operand_zero() gen3_fs_operand(FS_R0, ZERO, ZERO, ZERO, ZERO) 1187 1188/** 1189 * Returns an unused operand 1190 */ 1191#define gen3_fs_operand_none() gen3_fs_operand_zero() 1192 1193/** 1194 * Returns an operand containing (1.0, 1.0, 1.0, 1.0). 1195 */ 1196#define gen3_fs_operand_one() gen3_fs_operand(FS_R0, ONE, ONE, ONE, ONE) 1197 1198#define gen3_get_hardware_channel_val(val, shift, negate) \ 1199 (((val & 0x7) << shift) | ((val & 0x8) ? negate : 0)) 1200 1201/** 1202 * Outputs a fragment shader command to declare a sampler or texture register. 1203 */ 1204#define gen3_fs_dcl(reg) \ 1205 do { \ 1206 OUT_BATCH(D0_DCL | \ 1207 (REG_TYPE(reg) << D0_TYPE_SHIFT) | \ 1208 (REG_NR(reg) << D0_NR_SHIFT) | \ 1209 ((REG_TYPE(reg) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0)); \ 1210 OUT_BATCH(0); \ 1211 OUT_BATCH(0); \ 1212 } while (0) 1213 1214#define gen3_fs_texld(dest_reg, sampler_reg, address_reg) \ 1215 do { \ 1216 OUT_BATCH(T0_TEXLD | \ 1217 (REG_TYPE(dest_reg) << T0_DEST_TYPE_SHIFT) | \ 1218 (REG_NR(dest_reg) << T0_DEST_NR_SHIFT) | \ 1219 (REG_NR(sampler_reg) << T0_SAMPLER_NR_SHIFT)); \ 1220 OUT_BATCH((REG_TYPE(address_reg) << T1_ADDRESS_REG_TYPE_SHIFT) | \ 1221 (REG_NR(address_reg) << T1_ADDRESS_REG_NR_SHIFT)); \ 1222 OUT_BATCH(0); \ 1223 } while (0) 1224 1225#define gen3_fs_texldp(dest_reg, sampler_reg, address_reg) \ 1226 do { \ 1227 OUT_BATCH(T0_TEXLDP | \ 1228 (REG_TYPE(dest_reg) << T0_DEST_TYPE_SHIFT) | \ 1229 (REG_NR(dest_reg) << T0_DEST_NR_SHIFT) | \ 1230 (REG_NR(sampler_reg) << T0_SAMPLER_NR_SHIFT)); \ 1231 OUT_BATCH((REG_TYPE(address_reg) << T1_ADDRESS_REG_TYPE_SHIFT) | \ 1232 (REG_NR(address_reg) << T1_ADDRESS_REG_NR_SHIFT)); \ 1233 OUT_BATCH(0); \ 1234 } while (0) 1235 1236#define gen3_fs_arith_masked(op, dest_reg, dest_mask, operand0, operand1, operand2) \ 1237 _gen3_fs_arith_masked(A0_##op, dest_reg, dest_mask, operand0, operand1, operand2) 1238 1239#define gen3_fs_arith(op, dest_reg, operand0, operand1, operand2) \ 1240 _gen3_fs_arith(A0_##op, dest_reg, operand0, operand1, operand2) 1241 1242#define _gen3_fs_arith_masked(cmd, dest_reg, dest_mask, operand0, operand1, operand2) \ 1243 do { \ 1244 /* Set up destination register and write mask */ \ 1245 OUT_BATCH(cmd | \ 1246 (REG_TYPE(dest_reg) << A0_DEST_TYPE_SHIFT) | \ 1247 (REG_NR(dest_reg) << A0_DEST_NR_SHIFT) | \ 1248 (((dest_mask) & ~MASK_SATURATE) << A0_DEST_CHANNEL_SHIFT) | \ 1249 (((dest_mask) & MASK_SATURATE) ? A0_DEST_SATURATE : 0) | \ 1250 /* Set up operand 0 */ \ 1251 (REG_TYPE(operand0) << A0_SRC0_TYPE_SHIFT) | \ 1252 (REG_NR(operand0) << A0_SRC0_NR_SHIFT)); \ 1253 OUT_BATCH(gen3_get_hardware_channel_val(REG_X(operand0), \ 1254 A1_SRC0_CHANNEL_X_SHIFT, \ 1255 A1_SRC0_CHANNEL_X_NEGATE) | \ 1256 gen3_get_hardware_channel_val(REG_Y(operand0), \ 1257 A1_SRC0_CHANNEL_Y_SHIFT, \ 1258 A1_SRC0_CHANNEL_Y_NEGATE) | \ 1259 gen3_get_hardware_channel_val(REG_Z(operand0), \ 1260 A1_SRC0_CHANNEL_Z_SHIFT, \ 1261 A1_SRC0_CHANNEL_Z_NEGATE) | \ 1262 gen3_get_hardware_channel_val(REG_W(operand0), \ 1263 A1_SRC0_CHANNEL_W_SHIFT, \ 1264 A1_SRC0_CHANNEL_W_NEGATE) | \ 1265 /* Set up operand 1 */ \ 1266 (REG_TYPE(operand1) << A1_SRC1_TYPE_SHIFT) | \ 1267 (REG_NR(operand1) << A1_SRC1_NR_SHIFT) | \ 1268 gen3_get_hardware_channel_val(REG_X(operand1), \ 1269 A1_SRC1_CHANNEL_X_SHIFT, \ 1270 A1_SRC1_CHANNEL_X_NEGATE) | \ 1271 gen3_get_hardware_channel_val(REG_Y(operand1), \ 1272 A1_SRC1_CHANNEL_Y_SHIFT, \ 1273 A1_SRC1_CHANNEL_Y_NEGATE)); \ 1274 OUT_BATCH(gen3_get_hardware_channel_val(REG_Z(operand1), \ 1275 A2_SRC1_CHANNEL_Z_SHIFT, \ 1276 A2_SRC1_CHANNEL_Z_NEGATE) | \ 1277 gen3_get_hardware_channel_val(REG_W(operand1), \ 1278 A2_SRC1_CHANNEL_W_SHIFT, \ 1279 A2_SRC1_CHANNEL_W_NEGATE) | \ 1280 /* Set up operand 2 */ \ 1281 (REG_TYPE(operand2) << A2_SRC2_TYPE_SHIFT) | \ 1282 (REG_NR(operand2) << A2_SRC2_NR_SHIFT) | \ 1283 gen3_get_hardware_channel_val(REG_X(operand2), \ 1284 A2_SRC2_CHANNEL_X_SHIFT, \ 1285 A2_SRC2_CHANNEL_X_NEGATE) | \ 1286 gen3_get_hardware_channel_val(REG_Y(operand2), \ 1287 A2_SRC2_CHANNEL_Y_SHIFT, \ 1288 A2_SRC2_CHANNEL_Y_NEGATE) | \ 1289 gen3_get_hardware_channel_val(REG_Z(operand2), \ 1290 A2_SRC2_CHANNEL_Z_SHIFT, \ 1291 A2_SRC2_CHANNEL_Z_NEGATE) | \ 1292 gen3_get_hardware_channel_val(REG_W(operand2), \ 1293 A2_SRC2_CHANNEL_W_SHIFT, \ 1294 A2_SRC2_CHANNEL_W_NEGATE)); \ 1295 } while (0) 1296 1297#define _gen3_fs_arith(cmd, dest_reg, operand0, operand1, operand2) do {\ 1298 /* Set up destination register and write mask */ \ 1299 OUT_BATCH(cmd | \ 1300 (REG_TYPE(dest_reg) << A0_DEST_TYPE_SHIFT) | \ 1301 (REG_NR(dest_reg) << A0_DEST_NR_SHIFT) | \ 1302 (A0_DEST_CHANNEL_ALL) | \ 1303 /* Set up operand 0 */ \ 1304 (REG_TYPE(operand0) << A0_SRC0_TYPE_SHIFT) | \ 1305 (REG_NR(operand0) << A0_SRC0_NR_SHIFT)); \ 1306 OUT_BATCH(gen3_get_hardware_channel_val(REG_X(operand0), \ 1307 A1_SRC0_CHANNEL_X_SHIFT, \ 1308 A1_SRC0_CHANNEL_X_NEGATE) | \ 1309 gen3_get_hardware_channel_val(REG_Y(operand0), \ 1310 A1_SRC0_CHANNEL_Y_SHIFT, \ 1311 A1_SRC0_CHANNEL_Y_NEGATE) | \ 1312 gen3_get_hardware_channel_val(REG_Z(operand0), \ 1313 A1_SRC0_CHANNEL_Z_SHIFT, \ 1314 A1_SRC0_CHANNEL_Z_NEGATE) | \ 1315 gen3_get_hardware_channel_val(REG_W(operand0), \ 1316 A1_SRC0_CHANNEL_W_SHIFT, \ 1317 A1_SRC0_CHANNEL_W_NEGATE) | \ 1318 /* Set up operand 1 */ \ 1319 (REG_TYPE(operand1) << A1_SRC1_TYPE_SHIFT) | \ 1320 (REG_NR(operand1) << A1_SRC1_NR_SHIFT) | \ 1321 gen3_get_hardware_channel_val(REG_X(operand1), \ 1322 A1_SRC1_CHANNEL_X_SHIFT, \ 1323 A1_SRC1_CHANNEL_X_NEGATE) | \ 1324 gen3_get_hardware_channel_val(REG_Y(operand1), \ 1325 A1_SRC1_CHANNEL_Y_SHIFT, \ 1326 A1_SRC1_CHANNEL_Y_NEGATE)); \ 1327 OUT_BATCH(gen3_get_hardware_channel_val(REG_Z(operand1), \ 1328 A2_SRC1_CHANNEL_Z_SHIFT, \ 1329 A2_SRC1_CHANNEL_Z_NEGATE) | \ 1330 gen3_get_hardware_channel_val(REG_W(operand1), \ 1331 A2_SRC1_CHANNEL_W_SHIFT, \ 1332 A2_SRC1_CHANNEL_W_NEGATE) | \ 1333 /* Set up operand 2 */ \ 1334 (REG_TYPE(operand2) << A2_SRC2_TYPE_SHIFT) | \ 1335 (REG_NR(operand2) << A2_SRC2_NR_SHIFT) | \ 1336 gen3_get_hardware_channel_val(REG_X(operand2), \ 1337 A2_SRC2_CHANNEL_X_SHIFT, \ 1338 A2_SRC2_CHANNEL_X_NEGATE) | \ 1339 gen3_get_hardware_channel_val(REG_Y(operand2), \ 1340 A2_SRC2_CHANNEL_Y_SHIFT, \ 1341 A2_SRC2_CHANNEL_Y_NEGATE) | \ 1342 gen3_get_hardware_channel_val(REG_Z(operand2), \ 1343 A2_SRC2_CHANNEL_Z_SHIFT, \ 1344 A2_SRC2_CHANNEL_Z_NEGATE) | \ 1345 gen3_get_hardware_channel_val(REG_W(operand2), \ 1346 A2_SRC2_CHANNEL_W_SHIFT, \ 1347 A2_SRC2_CHANNEL_W_NEGATE)); \ 1348} while (0) 1349 1350#define gen3_fs_mov(dest_reg, operand0) \ 1351 gen3_fs_arith(MOV, dest_reg, \ 1352 operand0, \ 1353 gen3_fs_operand_none(), \ 1354 gen3_fs_operand_none()) 1355 1356#define gen3_fs_mov_masked(dest_reg, dest_mask, operand0) \ 1357 gen3_fs_arith_masked (MOV, dest_reg, dest_mask, \ 1358 operand0, \ 1359 gen3_fs_operand_none(), \ 1360 gen3_fs_operand_none()) 1361 1362 1363#define gen3_fs_frc(dest_reg, operand0) \ 1364 gen3_fs_arith (FRC, dest_reg, \ 1365 operand0, \ 1366 gen3_fs_operand_none(), \ 1367 gen3_fs_operand_none()) 1368 1369/** Add operand0 and operand1 and put the result in dest_reg */ 1370#define gen3_fs_add(dest_reg, operand0, operand1) \ 1371 gen3_fs_arith (ADD, dest_reg, \ 1372 operand0, operand1, \ 1373 gen3_fs_operand_none()) 1374 1375/** Multiply operand0 and operand1 and put the result in dest_reg */ 1376#define gen3_fs_mul(dest_reg, operand0, operand1) \ 1377 gen3_fs_arith (MUL, dest_reg, \ 1378 operand0, operand1, \ 1379 gen3_fs_operand_none()) 1380 1381/** Computes 1/(operand0.replicate_swizzle) puts the result in dest_reg */ 1382#define gen3_fs_rcp(dest_reg, dest_mask, operand0) \ 1383 do { \ 1384 if (dest_mask) { \ 1385 gen3_fs_arith_masked (RCP, dest_reg, dest_mask, \ 1386 operand0, \ 1387 gen3_fs_operand_none (), \ 1388 gen3_fs_operand_none ()); \ 1389 } else { \ 1390 gen3_fs_arith (RCP, dest_reg, \ 1391 operand0, \ 1392 gen3_fs_operand_none (), \ 1393 gen3_fs_operand_none ()); \ 1394 } \ 1395 } while (0) 1396 1397/** Computes 1/sqrt(operand0.replicate_swizzle) puts the result in dest_reg */ 1398#define gen3_fs_rsq(dest_reg, dest_mask, operand0) \ 1399 do { \ 1400 if (dest_mask) { \ 1401 gen3_fs_arith_masked (RSQ, dest_reg, dest_mask, \ 1402 operand0, \ 1403 gen3_fs_operand_none (), \ 1404 gen3_fs_operand_none ()); \ 1405 } else { \ 1406 gen3_fs_arith (RSQ, dest_reg, \ 1407 operand0, \ 1408 gen3_fs_operand_none (), \ 1409 gen3_fs_operand_none ()); \ 1410 } \ 1411 } while (0) 1412 1413/** Puts the minimum of operand0 and operand1 in dest_reg */ 1414#define gen3_fs_min(dest_reg, operand0, operand1) \ 1415 gen3_fs_arith (MIN, dest_reg, \ 1416 operand0, operand1, \ 1417 gen3_fs_operand_none()) 1418 1419/** Puts the maximum of operand0 and operand1 in dest_reg */ 1420#define gen3_fs_max(dest_reg, operand0, operand1) \ 1421 gen3_fs_arith (MAX, dest_reg, \ 1422 operand0, operand1, \ 1423 gen3_fs_operand_none()) 1424 1425#define gen3_fs_cmp(dest_reg, operand0, operand1, operand2) \ 1426 gen3_fs_arith (CMP, dest_reg, operand0, operand1, operand2) 1427 1428/** Perform operand0 * operand1 + operand2 and put the result in dest_reg */ 1429#define gen3_fs_mad(dest_reg, dest_mask, op0, op1, op2) \ 1430 do { \ 1431 if (dest_mask) { \ 1432 gen3_fs_arith_masked (MAD, dest_reg, dest_mask, op0, op1, op2); \ 1433 } else { \ 1434 gen3_fs_arith (MAD, dest_reg, op0, op1, op2); \ 1435 } \ 1436 } while (0) 1437 1438#define gen3_fs_dp2add(dest_reg, dest_mask, op0, op1, op2) \ 1439 do { \ 1440 if (dest_mask) { \ 1441 gen3_fs_arith_masked (DP2ADD, dest_reg, dest_mask, op0, op1, op2); \ 1442 } else { \ 1443 gen3_fs_arith (DP2ADD, dest_reg, op0, op1, op2); \ 1444 } \ 1445 } while (0) 1446 1447/** 1448 * Perform a 3-component dot-product of operand0 and operand1 and put the 1449 * resulting scalar in the channels of dest_reg specified by the dest_mask. 1450 */ 1451#define gen3_fs_dp3(dest_reg, dest_mask, op0, op1) \ 1452 do { \ 1453 if (dest_mask) { \ 1454 gen3_fs_arith_masked (DP3, dest_reg, dest_mask, \ 1455 op0, op1,\ 1456 gen3_fs_operand_none()); \ 1457 } else { \ 1458 gen3_fs_arith (DP3, dest_reg, op0, op1,\ 1459 gen3_fs_operand_none()); \ 1460 } \ 1461 } while (0) 1462 1463/** 1464 * Perform a 4-component dot-product of operand0 and operand1 and put the 1465 * resulting scalar in the channels of dest_reg specified by the dest_mask. 1466 */ 1467#define gen3_fs_dp4(dest_reg, dest_mask, op0, op1) \ 1468 do { \ 1469 if (dest_mask) { \ 1470 gen3_fs_arith_masked (DP4, dest_reg, dest_mask, \ 1471 op0, op1,\ 1472 gen3_fs_operand_none()); \ 1473 } else { \ 1474 gen3_fs_arith (DP4, dest_reg, op0, op1,\ 1475 gen3_fs_operand_none()); \ 1476 } \ 1477 } while (0) 1478 1479#define SHADER_TRAPEZOIDS (1 << 24) 1480