1428d7b3dSmrg/* 2428d7b3dSmrg * Copyright (c) 2013 Intel Corporation 3428d7b3dSmrg * 4428d7b3dSmrg * Permission is hereby granted, free of charge, to any person obtaining a 5428d7b3dSmrg * copy of this software and associated documentation files (the "Software"), 6428d7b3dSmrg * to deal in the Software without restriction, including without limitation 7428d7b3dSmrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8428d7b3dSmrg * and/or sell copies of the Software, and to permit persons to whom the 9428d7b3dSmrg * Software is furnished to do so, subject to the following conditions: 10428d7b3dSmrg * 11428d7b3dSmrg * The above copyright notice and this permission notice (including the next 12428d7b3dSmrg * paragraph) shall be included in all copies or substantial portions of the 13428d7b3dSmrg * Software. 14428d7b3dSmrg * 15428d7b3dSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16428d7b3dSmrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17428d7b3dSmrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18428d7b3dSmrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19428d7b3dSmrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20428d7b3dSmrg * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21428d7b3dSmrg * SOFTWARE. 22428d7b3dSmrg * 23428d7b3dSmrg * Authors: 24428d7b3dSmrg * Chris Wilson <chris@chris-wilson.co.uk> 25428d7b3dSmrg * 26428d7b3dSmrg */ 27428d7b3dSmrg 28428d7b3dSmrg/* Small wrapper around compiler specific implementation details of cpuid */ 29428d7b3dSmrg 30428d7b3dSmrg#ifndef SNA_CPUID_H 31428d7b3dSmrg#define SNA_CPUID_H 32428d7b3dSmrg 33428d7b3dSmrg#ifdef HAVE_CPUID_H 34428d7b3dSmrg#include <cpuid.h> 35428d7b3dSmrg#else 36428d7b3dSmrg#define __get_cpuid_max(x, y) 0 37428d7b3dSmrg#define __cpuid(level, a, b, c, d) a = b = c = d = 0 38428d7b3dSmrg#define __cpuid_count(level, count, a, b, c, d) a = b = c = d = 0 39428d7b3dSmrg#endif 40428d7b3dSmrg 41428d7b3dSmrg#define BASIC_CPUID 0x0 42428d7b3dSmrg#define EXTENDED_CPUID 0x80000000 43428d7b3dSmrg 44428d7b3dSmrg#ifndef bit_MMX 45428d7b3dSmrg#define bit_MMX (1 << 23) 46428d7b3dSmrg#endif 47428d7b3dSmrg 48428d7b3dSmrg#ifndef bit_SSE 49428d7b3dSmrg#define bit_SSE (1 << 25) 50428d7b3dSmrg#endif 51428d7b3dSmrg 52428d7b3dSmrg#ifndef bit_SSE2 53428d7b3dSmrg#define bit_SSE2 (1 << 26) 54428d7b3dSmrg#endif 55428d7b3dSmrg 56428d7b3dSmrg#ifndef bit_SSE3 57428d7b3dSmrg#define bit_SSE3 (1 << 0) 58428d7b3dSmrg#endif 59428d7b3dSmrg 60428d7b3dSmrg#ifndef bit_SSSE3 61428d7b3dSmrg#define bit_SSSE3 (1 << 9) 62428d7b3dSmrg#endif 63428d7b3dSmrg 64428d7b3dSmrg#ifndef bit_SSE4_1 65428d7b3dSmrg#define bit_SSE4_1 (1 << 19) 66428d7b3dSmrg#endif 67428d7b3dSmrg 68428d7b3dSmrg#ifndef bit_SSE4_2 69428d7b3dSmrg#define bit_SSE4_2 (1 << 20) 70428d7b3dSmrg#endif 71428d7b3dSmrg 72428d7b3dSmrg#ifndef bit_OSXSAVE 73428d7b3dSmrg#define bit_OSXSAVE (1 << 27) 74428d7b3dSmrg#endif 75428d7b3dSmrg 76428d7b3dSmrg#ifndef bit_AVX 77428d7b3dSmrg#define bit_AVX (1 << 28) 78428d7b3dSmrg#endif 79428d7b3dSmrg 80428d7b3dSmrg#ifndef bit_AVX2 81428d7b3dSmrg#define bit_AVX2 (1<<5) 82428d7b3dSmrg#endif 83428d7b3dSmrg 84428d7b3dSmrg#endif /* SNA_CPUID_H */ 85