1/**************************************************************************
2
3Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
4Copyright © 2002 David Dawes
5
6All Rights Reserved.
7
8Permission is hereby granted, free of charge, to any person obtaining a
9copy of this software and associated documentation files (the
10"Software"), to deal in the Software without restriction, including
11without limitation the rights to use, copy, modify, merge, publish,
12distribute, sub license, and/or sell copies of the Software, and to
13permit persons to whom the Software is furnished to do so, subject to
14the following conditions:
15
16The above copyright notice and this permission notice (including the
17next paragraph) shall be included in all copies or substantial portions
18of the Software.
19
20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
24ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28**************************************************************************/
29
30/*
31 * Authors:
32 *   Keith Whitwell <keith@tungstengraphics.com>
33 *   David Dawes <dawes@xfree86.org>
34 *
35 */
36
37#ifdef HAVE_CONFIG_H
38#include "config.h"
39#endif
40
41#if 0
42#define I830DEBUG
43#endif
44
45#include <stdint.h>
46
47#ifndef REMAP_RESERVED
48#define REMAP_RESERVED 0
49#endif
50
51#ifndef _I830_H_
52#define _I830_H_
53
54#include "xorg-server.h"
55#include "xf86_OSproc.h"
56#include "compiler.h"
57#include "xf86Cursor.h"
58#include "xf86xv.h"
59#include "xf86Crtc.h"
60#include "xf86RandR12.h"
61
62#include "xorg-server.h"
63#include <pciaccess.h>
64
65#define _XF86DRI_SERVER_
66#include "drm.h"
67#include "dri2.h"
68#include "intel_bufmgr.h"
69#include "i915_drm.h"
70
71#include "intel_driver.h"
72#include "intel_options.h"
73#include "intel_list.h"
74#include "compat-api.h"
75
76#if HAVE_UDEV
77#include <libudev.h>
78#endif
79
80#if HAVE_DRI3
81#include "misync.h"
82#endif
83
84/* remain compatible to xorg-server 1.6 */
85#ifndef MONITOR_EDID_COMPLETE_RAWDATA
86#define MONITOR_EDID_COMPLETE_RAWDATA EDID_COMPLETE_RAWDATA
87#endif
88
89#if XF86_CRTC_VERSION >= 5
90#define INTEL_PIXMAP_SHARING 1
91#endif
92
93#define MAX_PIPES 4 /* consider making all users dynamic */
94
95#include "common.h"
96
97#define PITCH_NONE 0
98
99/** enumeration of 3d consumers so some can maintain invariant state. */
100enum last_3d {
101	LAST_3D_OTHER,
102	LAST_3D_VIDEO,
103	LAST_3D_RENDER,
104	LAST_3D_ROTATION
105};
106
107enum dri_type {
108	DRI_DISABLED,
109	DRI_NONE,
110	DRI_ACTIVE
111};
112
113typedef struct intel_screen_private {
114	ScrnInfoPtr scrn;
115	struct intel_device *dev;
116	int cpp;
117
118#define RENDER_BATCH			I915_EXEC_RENDER
119#define BLT_BATCH			I915_EXEC_BLT
120	unsigned int current_batch;
121
122	void *modes;
123	drm_intel_bo *front_buffer, *back_buffer;
124	unsigned int back_name;
125	long front_pitch, front_tiling;
126
127	dri_bufmgr *bufmgr;
128
129#if USE_UXA
130	uint32_t batch_ptr[4096];
131	/** Byte offset in batch_ptr for the next dword to be emitted. */
132	unsigned int batch_used;
133	/** Position in batch_ptr at the start of the current BEGIN_BATCH */
134	unsigned int batch_emit_start;
135	/** Number of bytes to be emitted in the current BEGIN_BATCH. */
136	uint32_t batch_emitting;
137	dri_bo *batch_bo, *last_batch_bo[2];
138	/** Whether we're in a section of code that can't tolerate flushing */
139	Bool in_batch_atomic;
140	/** Ending batch_used that was verified by intel_start_batch_atomic() */
141	int batch_atomic_limit;
142	struct list batch_pixmaps;
143	drm_intel_bo *wa_scratch_bo;
144	OsTimerPtr cache_expire;
145#endif
146
147	/* For Xvideo */
148	Bool use_overlay;
149#ifdef INTEL_XVMC
150	/* For XvMC */
151	Bool XvMCEnabled;
152#endif
153
154	CreateScreenResourcesProcPtr CreateScreenResources;
155
156	Bool shadow_present;
157
158	unsigned int tiling;
159#define INTEL_TILING_FB		0x1
160#define INTEL_TILING_2D		0x2
161#define INTEL_TILING_3D		0x4
162#define INTEL_TILING_ALL (~0)
163
164	Bool swapbuffers_wait;
165	Bool has_relaxed_fencing;
166
167	int Chipset;
168	EntityInfoPtr pEnt;
169	const struct intel_device_info *info;
170
171	unsigned int BR[20];
172
173	CloseScreenProcPtr CloseScreen;
174
175	void (*context_switch) (struct intel_screen_private *intel,
176				int new_mode);
177	void (*vertex_flush) (struct intel_screen_private *intel);
178	void (*batch_flush) (struct intel_screen_private *intel);
179	void (*batch_commit_notify) (struct intel_screen_private *intel);
180
181#if USE_UXA
182	struct _UxaDriver *uxa_driver;
183	int uxa_flags;
184#endif
185	Bool need_sync;
186	int accel_pixmap_offset_alignment;
187	int accel_max_x;
188	int accel_max_y;
189	int max_bo_size;
190	int max_gtt_map_size;
191	int max_tiling_size;
192
193	Bool XvDisabled;	/* Xv disabled in PreInit. */
194	Bool XvEnabled;		/* Xv enabled for this generation. */
195	Bool XvPreferOverlay;
196
197	int colorKey;
198	XF86VideoAdaptorPtr adaptor;
199	ScreenBlockHandlerProcPtr BlockHandler;
200	Bool overlayOn;
201
202	struct {
203		drm_intel_bo *gen4_vs_bo;
204		drm_intel_bo *gen4_sf_bo;
205		drm_intel_bo *gen4_wm_packed_bo;
206		drm_intel_bo *gen4_wm_planar_bo;
207		drm_intel_bo *gen4_cc_bo;
208		drm_intel_bo *gen4_cc_vp_bo;
209		drm_intel_bo *gen4_sampler_bo;
210		drm_intel_bo *gen4_sip_kernel_bo;
211		drm_intel_bo *wm_prog_packed_bo;
212		drm_intel_bo *wm_prog_planar_bo;
213		drm_intel_bo *gen6_blend_bo;
214		drm_intel_bo *gen6_depth_stencil_bo;
215	} video;
216
217#if USE_UXA
218	/* Render accel state */
219	float scale_units[2][2];
220	/** Transform pointers for src/mask, or NULL if identity */
221	PictTransform *transform[2];
222
223	PixmapPtr render_source, render_mask, render_dest;
224	PicturePtr render_source_picture, render_mask_picture, render_dest_picture;
225	Bool needs_3d_invariant;
226	Bool needs_render_state_emit;
227	Bool needs_render_vertex_emit;
228
229	/* i830 render accel state */
230	uint32_t render_dest_format;
231	uint32_t cblend, ablend, s8_blendctl;
232
233	/* i915 render accel state */
234	PixmapPtr texture[2];
235	uint32_t mapstate[6];
236	uint32_t samplerstate[6];
237
238	struct {
239		int op;
240		uint32_t dst_format;
241	} i915_render_state;
242
243	struct {
244		int num_sf_outputs;
245		int drawrect;
246		uint32_t blend;
247		dri_bo *samplers;
248		dri_bo *kernel;
249	} gen6_render_state;
250
251	uint32_t prim_offset;
252	void (*prim_emit)(struct intel_screen_private *intel,
253			  int srcX, int srcY,
254			  int maskX, int maskY,
255			  int dstX, int dstY,
256			  int w, int h);
257	int floats_per_vertex;
258	int last_floats_per_vertex;
259	uint16_t vertex_offset;
260	uint16_t vertex_count;
261	uint16_t vertex_index;
262	uint16_t vertex_used;
263	uint32_t vertex_id;
264	float vertex_ptr[4*1024];
265	dri_bo *vertex_bo;
266
267	uint8_t surface_data[16*1024];
268	uint16_t surface_used;
269	uint16_t surface_table;
270	uint32_t surface_reloc;
271	dri_bo *surface_bo;
272
273	/* 965 render acceleration state */
274	struct gen4_render_state *gen4_render_state;
275#endif
276
277	/* DRI enabled this generation. */
278	enum dri_type dri2, dri3;
279	int drmSubFD;
280	char *deviceName;
281
282	Bool use_pageflipping;
283	Bool use_triple_buffer;
284	Bool force_fallback;
285	Bool has_kernel_flush;
286	Bool needs_flush;
287
288	struct _DRI2FrameEvent *pending_flip[MAX_PIPES];
289
290	/* Broken-out options. */
291	OptionInfoPtr Options;
292
293	/* Driver phase/state information */
294	Bool suspended;
295
296	enum last_3d last_3d;
297
298	/**
299	 * User option to print acceleration fallback info to the server log.
300	 */
301	Bool fallback_debug;
302	unsigned debug_flush;
303#if HAVE_UDEV
304	struct udev_monitor *uevent_monitor;
305	pointer uevent_handler;
306#endif
307	Bool has_prime_vmap_flush;
308
309#if HAVE_DRI3
310	SyncScreenFuncsRec save_sync_screen_funcs;
311#endif
312	void (*flush_rendering)(struct intel_screen_private *intel);
313} intel_screen_private;
314
315#define INTEL_INFO(intel) ((intel)->info)
316#define IS_GENx(intel, X) (INTEL_INFO(intel)->gen >= 8*(X) && INTEL_INFO(intel)->gen < 8*((X)+1))
317#define IS_GEN1(intel) IS_GENx(intel, 1)
318#define IS_GEN2(intel) IS_GENx(intel, 2)
319#define IS_GEN3(intel) IS_GENx(intel, 3)
320#define IS_GEN4(intel) IS_GENx(intel, 4)
321#define IS_GEN5(intel) IS_GENx(intel, 5)
322#define IS_GEN6(intel) IS_GENx(intel, 6)
323#define IS_GEN7(intel) IS_GENx(intel, 7)
324#define IS_HSW(intel) (INTEL_INFO(intel)->gen == 075)
325
326/* Some chips have specific errata (or limits) that we need to workaround. */
327#define IS_I830(intel) (intel_get_device_id((intel)->dev) == PCI_CHIP_I830_M)
328#define IS_845G(intel) (intel_get_device_id((intel)->dev) == PCI_CHIP_845_G)
329#define IS_I865G(intel) (intel_get_device_id((intel)->dev) == PCI_CHIP_I865_G)
330
331#define IS_I915G(pI810) (intel_get_device_id((intel)->dev) == PCI_CHIP_I915_G || intel_get_device_id((intel)->dev) == PCI_CHIP_E7221_G)
332#define IS_I915GM(pI810) (intel_get_device_id((intel)->dev) == PCI_CHIP_I915_GM)
333
334#define IS_965_Q(pI810) (intel_get_device_id((intel)->dev) == PCI_CHIP_I965_Q)
335
336/* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */
337#define SUPPORTS_YTILING(pI810) (INTEL_INFO(intel)->gen >= 040)
338#define HAS_BLT(pI810) (INTEL_INFO(intel)->gen >= 060)
339
340#ifndef I915_PARAM_HAS_PRIME_VMAP_FLUSH
341#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
342#endif
343
344enum {
345	DEBUG_FLUSH_BATCHES = 0x1,
346	DEBUG_FLUSH_CACHES = 0x2,
347	DEBUG_FLUSH_WAIT = 0x4,
348};
349
350extern Bool intel_mode_pre_init(ScrnInfoPtr pScrn, int fd, int cpp);
351extern void intel_mode_init(struct intel_screen_private *intel);
352extern void intel_mode_disable_unused_functions(ScrnInfoPtr scrn);
353extern void intel_mode_remove_fb(intel_screen_private *intel);
354extern void intel_mode_close(intel_screen_private *intel);
355extern void intel_mode_fini(intel_screen_private *intel);
356extern int intel_mode_read_drm_events(intel_screen_private *intel);
357extern void intel_mode_hotplug(intel_screen_private *intel);
358
359typedef void (*intel_drm_handler_proc)(ScrnInfoPtr scrn,
360                                       xf86CrtcPtr crtc,
361                                       uint64_t seq,
362                                       uint64_t usec,
363                                       void *data);
364
365typedef void (*intel_drm_abort_proc)(ScrnInfoPtr scrn,
366                                     xf86CrtcPtr crtc,
367                                     void *data);
368
369extern uint32_t intel_drm_queue_alloc(ScrnInfoPtr scrn, xf86CrtcPtr crtc, void *data, intel_drm_handler_proc handler, intel_drm_abort_proc abort);
370extern void intel_drm_abort(ScrnInfoPtr scrn, Bool (*match)(void *data, void *match_data), void *match_data);
371
372extern int intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, xf86CrtcPtr crtc);
373extern int intel_crtc_id(xf86CrtcPtr crtc);
374extern int intel_output_dpms_status(xf86OutputPtr output);
375extern void intel_copy_fb(ScrnInfoPtr scrn);
376
377int
378intel_get_crtc_msc_ust(ScrnInfoPtr scrn, xf86CrtcPtr crtc, uint64_t *msc, uint64_t *ust);
379
380uint32_t
381intel_crtc_msc_to_sequence(ScrnInfoPtr scrn, xf86CrtcPtr crtc, uint64_t expect);
382
383uint64_t
384intel_sequence_to_crtc_msc(xf86CrtcPtr crtc, uint32_t sequence);
385
386enum DRI2FrameEventType {
387	DRI2_SWAP,
388	DRI2_SWAP_CHAIN,
389	DRI2_FLIP,
390	DRI2_WAITMSC,
391};
392
393#if XORG_VERSION_CURRENT <= XORG_VERSION_NUMERIC(1,7,99,3,0)
394typedef void (*DRI2SwapEventPtr)(ClientPtr client, void *data, int type,
395				 CARD64 ust, CARD64 msc, CARD64 sbc);
396#endif
397
398typedef void (*intel_pageflip_handler_proc) (uint64_t frame,
399                                             uint64_t usec,
400                                             void *data);
401
402typedef void (*intel_pageflip_abort_proc) (void *data);
403
404typedef struct _DRI2FrameEvent {
405	struct intel_screen_private *intel;
406
407	XID drawable_id;
408	ClientPtr client;
409	enum DRI2FrameEventType type;
410	int frame;
411	int pipe;
412
413	struct list drawable_resource, client_resource;
414
415	/* for swaps & flips only */
416	DRI2SwapEventPtr event_complete;
417	void *event_data;
418	DRI2BufferPtr front;
419	DRI2BufferPtr back;
420
421	struct _DRI2FrameEvent *chain;
422} DRI2FrameEventRec, *DRI2FrameEventPtr;
423
424extern Bool intel_do_pageflip(intel_screen_private *intel,
425			      dri_bo *new_front,
426			      int ref_crtc_hw_id,
427			      Bool async,
428			      void *pageflip_data,
429			      intel_pageflip_handler_proc pageflip_handler,
430			      intel_pageflip_abort_proc pageflip_abort);
431
432static inline intel_screen_private *
433intel_get_screen_private(ScrnInfoPtr scrn)
434{
435	return (intel_screen_private *)(scrn->driverPrivate);
436}
437
438#ifndef ARRAY_SIZE
439#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
440#endif
441
442#ifndef ALIGN
443#define ALIGN(i,m)	(((i) + (m) - 1) & ~((m) - 1))
444#endif
445
446#ifndef MIN
447#define MIN(a,b)	((a) < (b) ? (a) : (b))
448#endif
449
450extern void intel_video_init(ScreenPtr pScreen);
451extern void intel_box_intersect(BoxPtr dest, BoxPtr a, BoxPtr b);
452extern void intel_crtc_box(xf86CrtcPtr crtc, BoxPtr crtc_box);
453
454extern xf86CrtcPtr intel_covering_crtc(ScrnInfoPtr scrn, BoxPtr box,
455				      xf86CrtcPtr desired, BoxPtr crtc_box_ret);
456
457Bool I830DRI2ScreenInit(ScreenPtr pScreen);
458void I830DRI2CloseScreen(ScreenPtr pScreen);
459void I830DRI2FrameEventHandler(unsigned int frame, unsigned int tv_sec,
460			       unsigned int tv_usec, DRI2FrameEventPtr flip_info);
461void I830DRI2FlipEventHandler(unsigned int frame, unsigned int tv_sec,
462			      unsigned int tv_usec, DRI2FrameEventPtr flip_info);
463
464/* intel_dri3.c */
465Bool intel_dri3_screen_init(ScreenPtr screen);
466
467extern Bool intel_crtc_on(xf86CrtcPtr crtc);
468int intel_crtc_to_pipe(xf86CrtcPtr crtc);
469
470/* intel_memory.c */
471unsigned long intel_get_fence_size(intel_screen_private *intel, unsigned long size);
472unsigned long intel_get_fence_pitch(intel_screen_private *intel, unsigned long pitch,
473				   uint32_t tiling_mode);
474Bool intel_check_display_stride(ScrnInfoPtr scrn, int stride, Bool tiling);
475void intel_set_gem_max_sizes(ScrnInfoPtr scrn);
476
477unsigned int
478intel_compute_size(struct intel_screen_private *intel,
479                   int w, int h, int bpp, unsigned usage,
480                   uint32_t *tiling, int *stride);
481
482drm_intel_bo *intel_allocate_framebuffer(ScrnInfoPtr scrn,
483					 int width, int height, int cpp,
484					 int *out_stride,
485					 uint32_t *out_tiling);
486
487static inline PixmapPtr get_drawable_pixmap(DrawablePtr drawable)
488{
489	ScreenPtr screen = drawable->pScreen;
490
491	if (drawable->type == DRAWABLE_PIXMAP)
492		return (PixmapPtr) drawable;
493	else
494		return screen->GetWindowPixmap((WindowPtr) drawable);
495}
496
497static inline Bool pixmap_is_scanout(PixmapPtr pixmap)
498{
499	ScreenPtr screen = pixmap->drawable.pScreen;
500
501	return pixmap == screen->GetScreenPixmap(screen);
502}
503
504static inline int
505intel_pixmap_pitch(PixmapPtr pixmap)
506{
507	return (unsigned long)pixmap->devKind;
508}
509
510/*
511 * intel_sync.c
512 */
513
514#if HAVE_DRI3
515Bool intel_sync_init(ScreenPtr screen);
516void intel_sync_close(ScreenPtr screen);
517#else
518static inline Bool intel_sync_init(ScreenPtr screen) { return 0; }
519static inline void intel_sync_close(ScreenPtr screen) { }
520#endif
521
522/*
523 * intel_present.c
524 */
525
526#if 0
527#define DebugPresent(x) ErrorF x
528#else
529#define DebugPresent(x)
530#endif
531
532#if HAVE_PRESENT
533Bool intel_present_screen_init(ScreenPtr screen);
534#else
535static inline Bool intel_present_screen_init(ScreenPtr screen) { return 0; }
536#endif
537
538dri_bo *
539intel_get_pixmap_bo(PixmapPtr pixmap);
540
541void
542intel_set_pixmap_bo(PixmapPtr pixmap, dri_bo *bo);
543
544void
545intel_flush(intel_screen_private *intel);
546
547#endif /* _I830_H_ */
548