1428d7b3dSmrg/*
2428d7b3dSmrg * Copyright © 2006 Intel Corporation
3428d7b3dSmrg *
4428d7b3dSmrg * Permission is hereby granted, free of charge, to any person obtaining a
5428d7b3dSmrg * copy of this software and associated documentation files (the "Software"),
6428d7b3dSmrg * to deal in the Software without restriction, including without limitation
7428d7b3dSmrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8428d7b3dSmrg * and/or sell copies of the Software, and to permit persons to whom the
9428d7b3dSmrg * Software is furnished to do so, subject to the following conditions:
10428d7b3dSmrg *
11428d7b3dSmrg * The above copyright notice and this permission notice (including the next
12428d7b3dSmrg * paragraph) shall be included in all copies or substantial portions of the
13428d7b3dSmrg * Software.
14428d7b3dSmrg *
15428d7b3dSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16428d7b3dSmrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17428d7b3dSmrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18428d7b3dSmrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19428d7b3dSmrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20428d7b3dSmrg * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21428d7b3dSmrg * SOFTWARE.
22428d7b3dSmrg *
23428d7b3dSmrg * Authors:
24428d7b3dSmrg *    Xiang Haihao <haihao.xiang@intel.com>
25428d7b3dSmrg *
26428d7b3dSmrg */
27428d7b3dSmrg
28428d7b3dSmrg#ifndef _I915XVMC_H
29428d7b3dSmrg#define _I915XVMC_H
30428d7b3dSmrg
31428d7b3dSmrg#include "intel_xvmc_private.h"
32428d7b3dSmrg
33428d7b3dSmrg#define I915_SUBPIC_PALETTE_SIZE        16
34428d7b3dSmrg#define MAX_SUBCONTEXT_LEN              1024
35428d7b3dSmrg
36428d7b3dSmrg#define PCI_CHIP_I915_G                 0x2582
37428d7b3dSmrg#define PCI_CHIP_I915_GM                0x2592
38428d7b3dSmrg#define PCI_CHIP_I945_G                 0x2772
39428d7b3dSmrg#define PCI_CHIP_I945_GM                0x27A2
40428d7b3dSmrg#define PCI_CHIP_I945_GME               0x27AE
41428d7b3dSmrg#define PCI_CHIP_G33_G                  0x29C2
42428d7b3dSmrg#define PCI_CHIP_Q35_G                  0x29B2
43428d7b3dSmrg#define PCI_CHIP_Q33_G                  0x29D2
44428d7b3dSmrg
45428d7b3dSmrg#define CORRDATA_SIZE			128*GTT_PAGE_SIZE
46428d7b3dSmrg/*
47428d7b3dSmrg * i915XvMCContext:
48428d7b3dSmrg *	Private Context data referenced via the privData
49428d7b3dSmrg *      pointer in the XvMCContext structure.
50428d7b3dSmrg */
51428d7b3dSmrgtypedef struct _i915XvMCContext {
52428d7b3dSmrg	struct intel_xvmc_context comm;
53428d7b3dSmrg	unsigned int yStride;
54428d7b3dSmrg	unsigned int uvStride;
55428d7b3dSmrg	unsigned int use_phys_addr;
56428d7b3dSmrg
57428d7b3dSmrg	drm_intel_bo *sis_bo;
58428d7b3dSmrg	drm_intel_bo *msb_bo;
59428d7b3dSmrg	drm_intel_bo *ssb_bo;
60428d7b3dSmrg	drm_intel_bo *psp_bo;
61428d7b3dSmrg	drm_intel_bo *psc_bo;
62428d7b3dSmrg	drm_intel_bo *corrdata_bo;
63428d7b3dSmrg} i915XvMCContext;
64428d7b3dSmrg
65428d7b3dSmrg/*
66428d7b3dSmrg * i915XvMCSubpicture:
67428d7b3dSmrg *  Private data structure for each XvMCSubpicture. This
68428d7b3dSmrg *  structure is referenced by the privData pointer in the XvMCSubpicture
69428d7b3dSmrg *  structure.
70428d7b3dSmrg */
71428d7b3dSmrgtypedef struct _i915XvMCSubpicture {
72428d7b3dSmrg	unsigned int srfNo;
73428d7b3dSmrg	unsigned int pitch;
74428d7b3dSmrg	unsigned char palette[3][16];
75428d7b3dSmrg	intel_xvmc_drm_map_t srf;
76428d7b3dSmrg	i915XvMCContext *privContext;
77428d7b3dSmrg} i915XvMCSubpicture;
78428d7b3dSmrg
79428d7b3dSmrg/* Number of YUV buffers per surface */
80428d7b3dSmrg#define I830_MAX_BUFS 2
81428d7b3dSmrg
82428d7b3dSmrg#endif /* _I915XVMC_H */
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