1/**************************************************************************
2
3Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
4All Rights Reserved.
5
6Permission is hereby granted, free of charge, to any person obtaining a
7copy of this software and associated documentation files (the
8"Software"), to deal in the Software without restriction, including
9without limitation the rights to use, copy, modify, merge, publish,
10distribute, sub license, and/or sell copies of the Software, and to
11permit persons to whom the Software is furnished to do so, subject to
12the following conditions:
13
14The above copyright notice and this permission notice (including the
15next paragraph) shall be included in all copies or substantial portions
16of the Software.
17
18THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
22ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26**************************************************************************/
27
28/*
29 * Authors:
30 *   Keith Whitwell <keith@tungstengraphics.com>
31 *
32 */
33
34/*
35 * XXX So far, for GXxor this is about 40% of the speed of SW, but CPU
36 * utilisation falls from 95% to < 5%.
37 */
38
39#ifdef HAVE_CONFIG_H
40#include "config.h"
41#endif
42
43#include <errno.h>
44
45#include "xorg-server.h"
46#include "xf86.h"
47#include "i830.h"
48#include "i810_reg.h"
49#include "i830_debug.h"
50#include "i830_ring.h"
51#include "i915_drm.h"
52
53unsigned long
54intel_get_pixmap_offset(PixmapPtr pPix)
55{
56    ScreenPtr pScreen = pPix->drawable.pScreen;
57    ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
58    I830Ptr pI830 = I830PTR(pScrn);
59
60    return (unsigned long)pPix->devPrivate.ptr - (unsigned long)pI830->FbBase;
61}
62
63unsigned long
64intel_get_pixmap_pitch(PixmapPtr pPix)
65{
66    return (unsigned long)pPix->devKind;
67}
68
69int
70I830WaitLpRing(ScrnInfoPtr pScrn, int n, int timeout_millis)
71{
72   I830Ptr pI830 = I830PTR(pScrn);
73   I830RingBuffer *ring = &pI830->ring;
74   int iters = 0;
75   unsigned int start = 0;
76   unsigned int now = 0;
77   int last_head = 0;
78   unsigned int first = 0;
79
80   /* If your system hasn't moved the head pointer in 2 seconds, I'm going to
81    * call it crashed.
82    */
83   if (timeout_millis == 0)
84      timeout_millis = 2000;
85
86   if (I810_DEBUG & DEBUG_VERBOSE_ACCEL) {
87      ErrorF("I830WaitLpRing %d\n", n);
88      first = GetTimeInMillis();
89   }
90
91   while (ring->space < n) {
92      ring->head = INREG(LP_RING + RING_HEAD) & I830_HEAD_MASK;
93      ring->space = ring->head - (ring->tail + 8);
94
95      if (ring->space < 0)
96	 ring->space += ring->mem->size;
97
98      iters++;
99      now = GetTimeInMillis();
100      if (start == 0 || now < start || ring->head != last_head) {
101	 if (I810_DEBUG & DEBUG_VERBOSE_ACCEL)
102	    if (now > start)
103	       ErrorF("space: %d wanted %d\n", ring->space, n);
104	 start = now;
105	 last_head = ring->head;
106      } else if (now - start > timeout_millis) {
107	 ErrorF("Error in I830WaitLpRing(), timeout for %d seconds\n",
108		timeout_millis/1000);
109	 if (IS_I965G(pI830))
110	     i965_dump_error_state(pScrn);
111	 else
112	     i830_dump_error_state(pScrn);
113	 ErrorF("space: %d wanted %d\n", ring->space, n);
114	 pI830->uxa_driver = NULL;
115	 FatalError("lockup\n");
116      }
117
118      DELAY(10);
119   }
120
121   if (I810_DEBUG & DEBUG_VERBOSE_ACCEL) {
122      now = GetTimeInMillis();
123      if (now - first) {
124	 ErrorF("Elapsed %u ms\n", now - first);
125	 ErrorF("space: %d wanted %d\n", ring->space, n);
126      }
127   }
128
129   return iters;
130}
131
132void
133I830Sync(ScrnInfoPtr pScrn)
134{
135   I830Ptr pI830 = I830PTR(pScrn);
136
137   if (I810_DEBUG & (DEBUG_VERBOSE_ACCEL | DEBUG_VERBOSE_SYNC))
138      ErrorF("I830Sync\n");
139
140   if (!pScrn->vtSema || !pI830->batch_bo)
141       return;
142
143   I830EmitFlush(pScrn);
144
145   intel_batch_flush(pScrn, TRUE);
146   intel_batch_wait_last(pScrn);
147}
148
149void
150I830EmitFlush(ScrnInfoPtr pScrn)
151{
152   I830Ptr pI830 = I830PTR(pScrn);
153   int flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
154
155   if (IS_I965G(pI830))
156      flags = 0;
157
158   {
159       BEGIN_BATCH(1);
160       OUT_BATCH(MI_FLUSH | flags);
161       ADVANCE_BATCH();
162   }
163}
164
165
166#if (ALWAYS_SYNC || ALWAYS_FLUSH)
167void
168i830_debug_sync(ScrnInfoPtr scrn)
169{
170    if (ALWAYS_SYNC)
171	I830Sync(scrn);
172    else
173	intel_batch_flush(scrn, FALSE);
174}
175#endif
176
177/* The following function sets up the supported acceleration. Call it
178 * from the FbInit() function in the SVGA driver, or before ScreenInit
179 * in a monolithic server.
180 */
181Bool
182I830AccelInit(ScreenPtr pScreen)
183{
184    ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
185    I830Ptr pI830 = I830PTR(pScrn);
186
187    /* Limits are described in the BLT engine chapter under Graphics Data Size
188     * Limitations, and the descriptions of SURFACE_STATE, 3DSTATE_BUFFER_INFO,
189     * 3DSTATE_DRAWING_RECTANGLE, 3DSTATE_MAP_INFO, and 3DSTATE_MAP_INFO.
190     *
191     * i845 through i965 limits 2D rendering to 65536 lines and pitch of 32768.
192     *
193     * i965 limits 3D surface to (2*element size)-aligned offset if un-tiled.
194     * i965 limits 3D surface to 4kB-aligned offset if tiled.
195     * i965 limits 3D surfaces to w,h of ?,8192.
196     * i965 limits 3D surface to pitch of 1B - 128kB.
197     * i965 limits 3D surface pitch alignment to 1 or 2 times the element size.
198     * i965 limits 3D surface pitch alignment to 512B if tiled.
199     * i965 limits 3D destination drawing rect to w,h of 8192,8192.
200     *
201     * i915 limits 3D textures to 4B-aligned offset if un-tiled.
202     * i915 limits 3D textures to ~4kB-aligned offset if tiled.
203     * i915 limits 3D textures to width,height of 2048,2048.
204     * i915 limits 3D textures to pitch of 16B - 8kB, in dwords.
205     * i915 limits 3D destination to ~4kB-aligned offset if tiled.
206     * i915 limits 3D destination to pitch of 16B - 8kB, in dwords, if un-tiled.
207     * i915 limits 3D destination to pitch 64B-aligned if used with depth.
208     * i915 limits 3D destination to pitch of 512B - 8kB, in tiles, if tiled.
209     * i915 limits 3D destination to POT aligned pitch if tiled.
210     * i915 limits 3D destination drawing rect to w,h of 2048,2048.
211     *
212     * i845 limits 3D textures to 4B-aligned offset if un-tiled.
213     * i845 limits 3D textures to ~4kB-aligned offset if tiled.
214     * i845 limits 3D textures to width,height of 2048,2048.
215     * i845 limits 3D textures to pitch of 4B - 8kB, in dwords.
216     * i845 limits 3D destination to 4B-aligned offset if un-tiled.
217     * i845 limits 3D destination to ~4kB-aligned offset if tiled.
218     * i845 limits 3D destination to pitch of 8B - 8kB, in dwords.
219     * i845 limits 3D destination drawing rect to w,h of 2048,2048.
220     *
221     * For the tiled issues, the only tiled buffer we draw to should be
222     * the front, which will have an appropriate pitch/offset already set up,
223     * so UXA doesn't need to worry.
224     */
225    if (IS_I965G(pI830)) {
226	pI830->accel_pixmap_offset_alignment = 4 * 2;
227	pI830->accel_pixmap_pitch_alignment = 64;
228	pI830->accel_max_x = 8192;
229	pI830->accel_max_y = 8192;
230    } else {
231	pI830->accel_pixmap_offset_alignment = 4;
232	pI830->accel_pixmap_pitch_alignment = 64;
233	pI830->accel_max_x = 2048;
234	pI830->accel_max_y = 2048;
235    }
236
237    return i830_uxa_init(pScreen);
238}
239