1 /************************************************************************** 2 * 3 * Copyright 2005 Tungsten Graphics, Inc., Cedar Park, Texas. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28#ifndef BRW_STRUCTS_H 29#define BRW_STRUCTS_H 30 31/* Command packets: 32 */ 33struct header 34{ 35 unsigned int length:16; 36 unsigned int opcode:16; 37}; 38 39 40union header_union 41{ 42 struct header bits; 43 unsigned int dword; 44}; 45 46struct brw_3d_control 47{ 48 struct 49 { 50 unsigned int length:8; 51 unsigned int notify_enable:1; 52 unsigned int pad:3; 53 unsigned int wc_flush_enable:1; 54 unsigned int depth_stall_enable:1; 55 unsigned int operation:2; 56 unsigned int opcode:16; 57 } header; 58 59 struct 60 { 61 unsigned int pad:2; 62 unsigned int dest_addr_type:1; 63 unsigned int dest_addr:29; 64 } dest; 65 66 unsigned int dword2; 67 unsigned int dword3; 68}; 69 70 71struct brw_3d_primitive 72{ 73 struct 74 { 75 unsigned int length:8; 76 unsigned int pad:2; 77 unsigned int topology:5; 78 unsigned int indexed:1; 79 unsigned int opcode:16; 80 } header; 81 82 unsigned int verts_per_instance; 83 unsigned int start_vert_location; 84 unsigned int instance_count; 85 unsigned int start_instance_location; 86 unsigned int base_vert_location; 87}; 88 89/* These seem to be passed around as function args, so it works out 90 * better to keep them as #defines: 91 */ 92#define BRW_FLUSH_READ_CACHE 0x1 93#define BRW_FLUSH_STATE_CACHE 0x2 94#define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4 95#define BRW_FLUSH_SNAPSHOT_COUNTERS 0x8 96 97struct brw_mi_flush 98{ 99 unsigned int flags:4; 100 unsigned int pad:12; 101 unsigned int opcode:16; 102}; 103 104struct brw_vf_statistics 105{ 106 unsigned int statistics_enable:1; 107 unsigned int pad:15; 108 unsigned int opcode:16; 109}; 110 111 112 113struct brw_binding_table_pointers 114{ 115 struct header header; 116 unsigned int vs; 117 unsigned int gs; 118 unsigned int clp; 119 unsigned int sf; 120 unsigned int wm; 121}; 122 123 124struct brw_blend_constant_color 125{ 126 struct header header; 127 float blend_constant_color[4]; 128}; 129 130 131struct brw_depthbuffer 132{ 133 union header_union header; 134 135 union { 136 struct { 137 unsigned int pitch:18; 138 unsigned int format:3; 139 unsigned int pad:4; 140 unsigned int depth_offset_disable:1; 141 unsigned int tile_walk:1; 142 unsigned int tiled_surface:1; 143 unsigned int pad2:1; 144 unsigned int surface_type:3; 145 } bits; 146 unsigned int dword; 147 } dword1; 148 149 unsigned int dword2_base_addr; 150 151 union { 152 struct { 153 unsigned int pad:1; 154 unsigned int mipmap_layout:1; 155 unsigned int lod:4; 156 unsigned int width:13; 157 unsigned int height:13; 158 } bits; 159 unsigned int dword; 160 } dword3; 161 162 union { 163 struct { 164 unsigned int pad:12; 165 unsigned int min_array_element:9; 166 unsigned int depth:11; 167 } bits; 168 unsigned int dword; 169 } dword4; 170}; 171 172struct brw_drawrect 173{ 174 struct header header; 175 unsigned int xmin:16; 176 unsigned int ymin:16; 177 unsigned int xmax:16; 178 unsigned int ymax:16; 179 unsigned int xorg:16; 180 unsigned int yorg:16; 181}; 182 183 184 185 186struct brw_global_depth_offset_clamp 187{ 188 struct header header; 189 float depth_offset_clamp; 190}; 191 192struct brw_indexbuffer 193{ 194 union { 195 struct 196 { 197 unsigned int length:8; 198 unsigned int index_format:2; 199 unsigned int cut_index_enable:1; 200 unsigned int pad:5; 201 unsigned int opcode:16; 202 } bits; 203 unsigned int dword; 204 205 } header; 206 207 unsigned int buffer_start; 208 unsigned int buffer_end; 209}; 210 211 212struct brw_line_stipple 213{ 214 struct header header; 215 216 struct 217 { 218 unsigned int pattern:16; 219 unsigned int pad:16; 220 } bits0; 221 222 struct 223 { 224 unsigned int repeat_count:9; 225 unsigned int pad:7; 226 unsigned int inverse_repeat_count:16; 227 } bits1; 228}; 229 230 231struct brw_pipelined_state_pointers 232{ 233 struct header header; 234 235 struct { 236 unsigned int pad:5; 237 unsigned int offset:27; 238 } vs; 239 240 struct 241 { 242 unsigned int enable:1; 243 unsigned int pad:4; 244 unsigned int offset:27; 245 } gs; 246 247 struct 248 { 249 unsigned int enable:1; 250 unsigned int pad:4; 251 unsigned int offset:27; 252 } clp; 253 254 struct 255 { 256 unsigned int pad:5; 257 unsigned int offset:27; 258 } sf; 259 260 struct 261 { 262 unsigned int pad:5; 263 unsigned int offset:27; 264 } wm; 265 266 struct 267 { 268 unsigned int pad:5; 269 unsigned int offset:27; /* KW: check me! */ 270 } cc; 271}; 272 273 274struct brw_polygon_stipple_offset 275{ 276 struct header header; 277 278 struct { 279 unsigned int y_offset:5; 280 unsigned int pad:3; 281 unsigned int x_offset:5; 282 unsigned int pad0:19; 283 } bits0; 284}; 285 286 287 288struct brw_polygon_stipple 289{ 290 struct header header; 291 unsigned int stipple[32]; 292}; 293 294 295 296struct brw_pipeline_select 297{ 298 struct 299 { 300 unsigned int pipeline_select:1; 301 unsigned int pad:15; 302 unsigned int opcode:16; 303 } header; 304}; 305 306 307struct brw_pipe_control 308{ 309 struct 310 { 311 unsigned int length:8; 312 unsigned int notify_enable:1; 313 unsigned int pad:2; 314 unsigned int instruction_state_cache_flush_enable:1; 315 unsigned int write_cache_flush_enable:1; 316 unsigned int depth_stall_enable:1; 317 unsigned int post_sync_operation:2; 318 319 unsigned int opcode:16; 320 } header; 321 322 struct 323 { 324 unsigned int pad:2; 325 unsigned int dest_addr_type:1; 326 unsigned int dest_addr:29; 327 } bits1; 328 329 unsigned int data0; 330 unsigned int data1; 331}; 332 333 334struct brw_urb_fence 335{ 336 struct 337 { 338 unsigned int length:8; 339 unsigned int vs_realloc:1; 340 unsigned int gs_realloc:1; 341 unsigned int clp_realloc:1; 342 unsigned int sf_realloc:1; 343 unsigned int vfe_realloc:1; 344 unsigned int cs_realloc:1; 345 unsigned int pad:2; 346 unsigned int opcode:16; 347 } header; 348 349 struct 350 { 351 unsigned int vs_fence:10; 352 unsigned int gs_fence:10; 353 unsigned int clp_fence:10; 354 unsigned int pad:2; 355 } bits0; 356 357 struct 358 { 359 unsigned int sf_fence:10; 360 unsigned int vf_fence:10; 361 unsigned int cs_fence:10; 362 unsigned int pad:2; 363 } bits1; 364}; 365 366struct brw_constant_buffer_state /* previously brw_command_streamer */ 367{ 368 struct header header; 369 370 struct 371 { 372 unsigned int nr_urb_entries:3; 373 unsigned int pad:1; 374 unsigned int urb_entry_size:5; 375 unsigned int pad0:23; 376 } bits0; 377}; 378 379struct brw_constant_buffer 380{ 381 struct 382 { 383 unsigned int length:8; 384 unsigned int valid:1; 385 unsigned int pad:7; 386 unsigned int opcode:16; 387 } header; 388 389 struct 390 { 391 unsigned int buffer_length:6; 392 unsigned int buffer_address:26; 393 } bits0; 394}; 395 396struct brw_state_base_address 397{ 398 struct header header; 399 400 struct 401 { 402 unsigned int modify_enable:1; 403 unsigned int pad:4; 404 unsigned int general_state_address:27; 405 } bits0; 406 407 struct 408 { 409 unsigned int modify_enable:1; 410 unsigned int pad:4; 411 unsigned int surface_state_address:27; 412 } bits1; 413 414 struct 415 { 416 unsigned int modify_enable:1; 417 unsigned int pad:4; 418 unsigned int indirect_object_state_address:27; 419 } bits2; 420 421 struct 422 { 423 unsigned int modify_enable:1; 424 unsigned int pad:11; 425 unsigned int general_state_upper_bound:20; 426 } bits3; 427 428 struct 429 { 430 unsigned int modify_enable:1; 431 unsigned int pad:11; 432 unsigned int indirect_object_state_upper_bound:20; 433 } bits4; 434}; 435 436struct brw_state_prefetch 437{ 438 struct header header; 439 440 struct 441 { 442 unsigned int prefetch_count:3; 443 unsigned int pad:3; 444 unsigned int prefetch_pointer:26; 445 } bits0; 446}; 447 448struct brw_system_instruction_pointer 449{ 450 struct header header; 451 452 struct 453 { 454 unsigned int pad:4; 455 unsigned int system_instruction_pointer:28; 456 } bits0; 457}; 458 459 460 461 462/* State structs for the various fixed function units: 463 */ 464 465 466struct thread0 467{ 468 unsigned int pad0:1; 469 unsigned int grf_reg_count:3; 470 unsigned int pad1:2; 471 unsigned int kernel_start_pointer:26; 472}; 473 474struct thread1 475{ 476 unsigned int ext_halt_exception_enable:1; 477 unsigned int sw_exception_enable:1; 478 unsigned int mask_stack_exception_enable:1; 479 unsigned int timeout_exception_enable:1; 480 unsigned int illegal_op_exception_enable:1; 481 unsigned int pad0:3; 482 unsigned int depth_coef_urb_read_offset:6; /* WM only */ 483 unsigned int pad1:2; 484 unsigned int floating_point_mode:1; 485 unsigned int thread_priority:1; 486 unsigned int binding_table_entry_count:8; 487 unsigned int pad3:5; 488 unsigned int single_program_flow:1; 489}; 490 491struct thread2 492{ 493 unsigned int per_thread_scratch_space:4; 494 unsigned int pad0:6; 495 unsigned int scratch_space_base_pointer:22; 496}; 497 498 499struct thread3 500{ 501 unsigned int dispatch_grf_start_reg:4; 502 unsigned int urb_entry_read_offset:6; 503 unsigned int pad0:1; 504 unsigned int urb_entry_read_length:6; 505 unsigned int pad1:1; 506 unsigned int const_urb_entry_read_offset:6; 507 unsigned int pad2:1; 508 unsigned int const_urb_entry_read_length:6; 509 unsigned int pad3:1; 510}; 511 512 513 514struct brw_clip_unit_state 515{ 516 struct thread0 thread0; 517 struct thread1 thread1; 518 struct thread2 thread2; 519 struct thread3 thread3; 520 521 struct 522 { 523 unsigned int pad0:9; 524 unsigned int gs_output_stats:1; /* not always */ 525 unsigned int stats_enable:1; 526 unsigned int nr_urb_entries:7; 527 unsigned int pad1:1; 528 unsigned int urb_entry_allocation_size:5; 529 unsigned int pad2:1; 530 unsigned int max_threads:6; /* may be less */ 531 unsigned int pad3:1; 532 } thread4; 533 534 struct 535 { 536 unsigned int pad0:13; 537 unsigned int clip_mode:3; 538 unsigned int userclip_enable_flags:8; 539 unsigned int userclip_must_clip:1; 540 unsigned int pad1:1; 541 unsigned int guard_band_enable:1; 542 unsigned int viewport_z_clip_enable:1; 543 unsigned int viewport_xy_clip_enable:1; 544 unsigned int vertex_position_space:1; 545 unsigned int api_mode:1; 546 unsigned int pad2:1; 547 } clip5; 548 549 struct 550 { 551 unsigned int pad0:5; 552 unsigned int clipper_viewport_state_ptr:27; 553 } clip6; 554 555 556 float viewport_xmin; 557 float viewport_xmax; 558 float viewport_ymin; 559 float viewport_ymax; 560}; 561 562 563 564struct brw_cc_unit_state 565{ 566 struct 567 { 568 unsigned int pad0:3; 569 unsigned int bf_stencil_pass_depth_pass_op:3; 570 unsigned int bf_stencil_pass_depth_fail_op:3; 571 unsigned int bf_stencil_fail_op:3; 572 unsigned int bf_stencil_func:3; 573 unsigned int bf_stencil_enable:1; 574 unsigned int pad1:2; 575 unsigned int stencil_write_enable:1; 576 unsigned int stencil_pass_depth_pass_op:3; 577 unsigned int stencil_pass_depth_fail_op:3; 578 unsigned int stencil_fail_op:3; 579 unsigned int stencil_func:3; 580 unsigned int stencil_enable:1; 581 } cc0; 582 583 584 struct 585 { 586 unsigned int bf_stencil_ref:8; 587 unsigned int stencil_write_mask:8; 588 unsigned int stencil_test_mask:8; 589 unsigned int stencil_ref:8; 590 } cc1; 591 592 593 struct 594 { 595 unsigned int logicop_enable:1; 596 unsigned int pad0:10; 597 unsigned int depth_write_enable:1; 598 unsigned int depth_test_function:3; 599 unsigned int depth_test:1; 600 unsigned int bf_stencil_write_mask:8; 601 unsigned int bf_stencil_test_mask:8; 602 } cc2; 603 604 605 struct 606 { 607 unsigned int pad0:8; 608 unsigned int alpha_test_func:3; 609 unsigned int alpha_test:1; 610 unsigned int blend_enable:1; 611 unsigned int ia_blend_enable:1; 612 unsigned int pad1:1; 613 unsigned int alpha_test_format:1; 614 unsigned int pad2:16; 615 } cc3; 616 617 struct 618 { 619 unsigned int pad0:5; 620 unsigned int cc_viewport_state_offset:27; 621 } cc4; 622 623 struct 624 { 625 unsigned int pad0:2; 626 unsigned int ia_dest_blend_factor:5; 627 unsigned int ia_src_blend_factor:5; 628 unsigned int ia_blend_function:3; 629 unsigned int statistics_enable:1; 630 unsigned int logicop_func:4; 631 unsigned int pad1:11; 632 unsigned int dither_enable:1; 633 } cc5; 634 635 struct 636 { 637 unsigned int clamp_post_alpha_blend:1; 638 unsigned int clamp_pre_alpha_blend:1; 639 unsigned int clamp_range:2; 640 unsigned int pad0:11; 641 unsigned int y_dither_offset:2; 642 unsigned int x_dither_offset:2; 643 unsigned int dest_blend_factor:5; 644 unsigned int src_blend_factor:5; 645 unsigned int blend_function:3; 646 } cc6; 647 648 struct { 649 union { 650 float f; 651 unsigned char ub[4]; 652 } alpha_ref; 653 } cc7; 654}; 655 656 657 658struct brw_sf_unit_state 659{ 660 struct thread0 thread0; 661 struct { 662 unsigned int pad0:7; 663 unsigned int sw_exception_enable:1; 664 unsigned int pad1:3; 665 unsigned int mask_stack_exception_enable:1; 666 unsigned int pad2:1; 667 unsigned int illegal_op_exception_enable:1; 668 unsigned int pad3:2; 669 unsigned int floating_point_mode:1; 670 unsigned int thread_priority:1; 671 unsigned int binding_table_entry_count:8; 672 unsigned int pad4:5; 673 unsigned int single_program_flow:1; 674 } sf1; 675 676 struct thread2 thread2; 677 struct thread3 thread3; 678 679 struct 680 { 681 unsigned int pad0:10; 682 unsigned int stats_enable:1; 683 unsigned int nr_urb_entries:7; 684 unsigned int pad1:1; 685 unsigned int urb_entry_allocation_size:5; 686 unsigned int pad2:1; 687 unsigned int max_threads:6; 688 unsigned int pad3:1; 689 } thread4; 690 691 struct 692 { 693 unsigned int front_winding:1; 694 unsigned int viewport_transform:1; 695 unsigned int pad0:3; 696 unsigned int sf_viewport_state_offset:27; 697 } sf5; 698 699 struct 700 { 701 unsigned int pad0:9; 702 unsigned int dest_org_vbias:4; 703 unsigned int dest_org_hbias:4; 704 unsigned int scissor:1; 705 unsigned int disable_2x2_trifilter:1; 706 unsigned int disable_zero_pix_trifilter:1; 707 unsigned int point_rast_rule:2; 708 unsigned int line_endcap_aa_region_width:2; 709 unsigned int line_width:4; 710 unsigned int fast_scissor_disable:1; 711 unsigned int cull_mode:2; 712 unsigned int aa_enable:1; 713 } sf6; 714 715 struct 716 { 717 unsigned int point_size:11; 718 unsigned int use_point_size_state:1; 719 unsigned int subpixel_precision:1; 720 unsigned int sprite_point:1; 721 unsigned int pad0:11; 722 unsigned int trifan_pv:2; 723 unsigned int linestrip_pv:2; 724 unsigned int tristrip_pv:2; 725 unsigned int line_last_pixel_enable:1; 726 } sf7; 727 728}; 729 730 731struct brw_gs_unit_state 732{ 733 struct thread0 thread0; 734 struct thread1 thread1; 735 struct thread2 thread2; 736 struct thread3 thread3; 737 738 struct 739 { 740 unsigned int pad0:10; 741 unsigned int stats_enable:1; 742 unsigned int nr_urb_entries:7; 743 unsigned int pad1:1; 744 unsigned int urb_entry_allocation_size:5; 745 unsigned int pad2:1; 746 unsigned int max_threads:1; 747 unsigned int pad3:6; 748 } thread4; 749 750 struct 751 { 752 unsigned int sampler_count:3; 753 unsigned int pad0:2; 754 unsigned int sampler_state_pointer:27; 755 } gs5; 756 757 758 struct 759 { 760 unsigned int max_vp_index:4; 761 unsigned int pad0:26; 762 unsigned int reorder_enable:1; 763 unsigned int pad1:1; 764 } gs6; 765}; 766 767 768struct brw_vs_unit_state 769{ 770 struct thread0 thread0; 771 struct thread1 thread1; 772 struct thread2 thread2; 773 struct thread3 thread3; 774 775 struct 776 { 777 unsigned int pad0:10; 778 unsigned int stats_enable:1; 779 unsigned int nr_urb_entries:7; 780 unsigned int pad1:1; 781 unsigned int urb_entry_allocation_size:5; 782 unsigned int pad2:1; 783 unsigned int max_threads:4; 784 unsigned int pad3:3; 785 } thread4; 786 787 struct 788 { 789 unsigned int sampler_count:3; 790 unsigned int pad0:2; 791 unsigned int sampler_state_pointer:27; 792 } vs5; 793 794 struct 795 { 796 unsigned int vs_enable:1; 797 unsigned int vert_cache_disable:1; 798 unsigned int pad0:30; 799 } vs6; 800}; 801 802 803struct brw_wm_unit_state 804{ 805 struct thread0 thread0; 806 struct thread1 thread1; 807 struct thread2 thread2; 808 struct thread3 thread3; 809 810 struct { 811 unsigned int stats_enable:1; 812 unsigned int pad0:1; 813 unsigned int sampler_count:3; 814 unsigned int sampler_state_pointer:27; 815 } wm4; 816 817 struct 818 { 819 unsigned int enable_8_pix:1; 820 unsigned int enable_16_pix:1; 821 unsigned int enable_32_pix:1; 822 unsigned int pad0:7; 823 unsigned int legacy_global_depth_bias:1; 824 unsigned int line_stipple:1; 825 unsigned int depth_offset:1; 826 unsigned int polygon_stipple:1; 827 unsigned int line_aa_region_width:2; 828 unsigned int line_endcap_aa_region_width:2; 829 unsigned int early_depth_test:1; 830 unsigned int thread_dispatch_enable:1; 831 unsigned int program_uses_depth:1; 832 unsigned int program_computes_depth:1; 833 unsigned int program_uses_killpixel:1; 834 unsigned int legacy_line_rast: 1; 835 unsigned int transposed_urb_read:1; 836 unsigned int max_threads:7; 837 } wm5; 838 839 float global_depth_offset_constant; 840 float global_depth_offset_scale; 841 842 struct { 843 unsigned int pad0:1; 844 unsigned int grf_reg_count_1:3; 845 unsigned int pad1:2; 846 unsigned int kernel_start_pointer_1:26; 847 } wm8; 848 849 struct { 850 unsigned int pad0:1; 851 unsigned int grf_reg_count_2:3; 852 unsigned int pad1:2; 853 unsigned int kernel_start_pointer_2:26; 854 } wm9; 855 856 struct { 857 unsigned int pad0:1; 858 unsigned int grf_reg_count_3:3; 859 unsigned int pad1:2; 860 unsigned int kernel_start_pointer_3:26; 861 } wm10; 862}; 863 864struct brw_wm_unit_state_padded { 865 struct brw_wm_unit_state state; 866 char pad[64 - sizeof(struct brw_wm_unit_state)]; 867}; 868 869/* The hardware supports two different modes for border color. The 870 * default (OpenGL) mode uses floating-point color channels, while the 871 * legacy mode uses 4 bytes. 872 * 873 * More significantly, the legacy mode respects the components of the 874 * border color for channels not present in the source, (whereas the 875 * default mode will ignore the border color's alpha channel and use 876 * alpha==1 for an RGB source, for example). 877 * 878 * The legacy mode matches the semantics specified by the Render 879 * extension. 880 */ 881struct brw_sampler_default_border_color { 882 float color[4]; 883}; 884 885struct brw_sampler_legacy_border_color { 886 uint8_t color[4]; 887}; 888 889struct brw_sampler_state 890{ 891 892 struct 893 { 894 unsigned int shadow_function:3; 895 unsigned int lod_bias:11; 896 unsigned int min_filter:3; 897 unsigned int mag_filter:3; 898 unsigned int mip_filter:2; 899 unsigned int base_level:5; 900 unsigned int pad:1; 901 unsigned int lod_preclamp:1; 902 unsigned int border_color_mode:1; 903 unsigned int pad0:1; 904 unsigned int disable:1; 905 } ss0; 906 907 struct 908 { 909 unsigned int r_wrap_mode:3; 910 unsigned int t_wrap_mode:3; 911 unsigned int s_wrap_mode:3; 912 unsigned int pad:3; 913 unsigned int max_lod:10; 914 unsigned int min_lod:10; 915 } ss1; 916 917 918 struct 919 { 920 unsigned int pad:5; 921 unsigned int border_color_pointer:27; 922 } ss2; 923 924 struct 925 { 926 unsigned int pad:19; 927 unsigned int max_aniso:3; 928 unsigned int chroma_key_mode:1; 929 unsigned int chroma_key_index:2; 930 unsigned int chroma_key_enable:1; 931 unsigned int monochrome_filter_width:3; 932 unsigned int monochrome_filter_height:3; 933 } ss3; 934}; 935 936 937struct brw_clipper_viewport 938{ 939 float xmin; 940 float xmax; 941 float ymin; 942 float ymax; 943}; 944 945struct brw_cc_viewport 946{ 947 float min_depth; 948 float max_depth; 949}; 950 951struct brw_sf_viewport 952{ 953 struct { 954 float m00; 955 float m11; 956 float m22; 957 float m30; 958 float m31; 959 float m32; 960 } viewport; 961 962 struct { 963 short xmin; 964 short ymin; 965 short xmax; 966 short ymax; 967 } scissor; 968}; 969 970/* Documented in the subsystem/shared-functions/sampler chapter... 971 */ 972struct brw_surface_state 973{ 974 struct { 975 unsigned int cube_pos_z:1; 976 unsigned int cube_neg_z:1; 977 unsigned int cube_pos_y:1; 978 unsigned int cube_neg_y:1; 979 unsigned int cube_pos_x:1; 980 unsigned int cube_neg_x:1; 981 unsigned int pad:3; 982 unsigned int render_cache_read_mode:1; 983 unsigned int mipmap_layout_mode:1; 984 unsigned int vert_line_stride_ofs:1; 985 unsigned int vert_line_stride:1; 986 unsigned int color_blend:1; 987 unsigned int writedisable_blue:1; 988 unsigned int writedisable_green:1; 989 unsigned int writedisable_red:1; 990 unsigned int writedisable_alpha:1; 991 unsigned int surface_format:9; 992 unsigned int data_return_format:1; 993 unsigned int pad0:1; 994 unsigned int surface_type:3; 995 } ss0; 996 997 struct { 998 unsigned int base_addr; 999 } ss1; 1000 1001 struct { 1002 unsigned int render_target_rotation:2; 1003 unsigned int mip_count:4; 1004 unsigned int width:13; 1005 unsigned int height:13; 1006 } ss2; 1007 1008 struct { 1009 unsigned int tile_walk:1; 1010 unsigned int tiled_surface:1; 1011 unsigned int pad:1; 1012 unsigned int pitch:18; 1013 unsigned int depth:11; 1014 } ss3; 1015 1016 struct { 1017 unsigned int pad:19; 1018 unsigned int min_array_elt:9; 1019 unsigned int min_lod:4; 1020 } ss4; 1021 1022 struct { 1023 unsigned int pad:20; 1024 unsigned int y_offset:4; 1025 unsigned int pad2:1; 1026 unsigned int x_offset:7; 1027 } ss5; 1028}; 1029 1030 1031 1032struct brw_vertex_buffer_state 1033{ 1034 struct { 1035 unsigned int pitch:11; 1036 unsigned int pad:15; 1037 unsigned int access_type:1; 1038 unsigned int vb_index:5; 1039 } vb0; 1040 1041 unsigned int start_addr; 1042 unsigned int max_index; 1043#if 1 1044 unsigned int instance_data_step_rate; /* not included for sequential/random vertices? */ 1045#endif 1046}; 1047 1048#define BRW_VBP_MAX 17 1049 1050struct brw_vb_array_state { 1051 struct header header; 1052 struct brw_vertex_buffer_state vb[BRW_VBP_MAX]; 1053}; 1054 1055 1056struct brw_vertex_element_state 1057{ 1058 struct 1059 { 1060 unsigned int src_offset:11; 1061 unsigned int pad:5; 1062 unsigned int src_format:9; 1063 unsigned int pad0:1; 1064 unsigned int valid:1; 1065 unsigned int vertex_buffer_index:5; 1066 } ve0; 1067 1068 struct 1069 { 1070 unsigned int dst_offset:8; 1071 unsigned int pad:8; 1072 unsigned int vfcomponent3:4; 1073 unsigned int vfcomponent2:4; 1074 unsigned int vfcomponent1:4; 1075 unsigned int vfcomponent0:4; 1076 } ve1; 1077}; 1078 1079#define BRW_VEP_MAX 18 1080 1081struct brw_vertex_element_packet { 1082 struct header header; 1083 struct brw_vertex_element_state ve[BRW_VEP_MAX]; /* note: less than _TNL_ATTRIB_MAX */ 1084}; 1085 1086 1087struct brw_urb_immediate { 1088 unsigned int opcode:4; 1089 unsigned int offset:6; 1090 unsigned int swizzle_control:2; 1091 unsigned int pad:1; 1092 unsigned int allocate:1; 1093 unsigned int used:1; 1094 unsigned int complete:1; 1095 unsigned int response_length:4; 1096 unsigned int msg_length:4; 1097 unsigned int msg_target:4; 1098 unsigned int pad1:3; 1099 unsigned int end_of_thread:1; 1100}; 1101 1102/* Instruction format for the execution units: 1103 */ 1104 1105struct brw_instruction 1106{ 1107 struct 1108 { 1109 unsigned int opcode:7; 1110 unsigned int pad:1; 1111 unsigned int access_mode:1; 1112 unsigned int mask_control:1; 1113 unsigned int dependency_control:2; 1114 unsigned int compression_control:2; 1115 unsigned int thread_control:2; 1116 unsigned int predicate_control:4; 1117 unsigned int predicate_inverse:1; 1118 unsigned int execution_size:3; 1119 unsigned int destreg__conditonalmod:4; /* destreg - send, conditionalmod - others */ 1120 unsigned int pad0:2; 1121 unsigned int debug_control:1; 1122 unsigned int saturate:1; 1123 } header; 1124 1125 union { 1126 struct 1127 { 1128 unsigned int dest_reg_file:2; 1129 unsigned int dest_reg_type:3; 1130 unsigned int src0_reg_file:2; 1131 unsigned int src0_reg_type:3; 1132 unsigned int src1_reg_file:2; 1133 unsigned int src1_reg_type:3; 1134 unsigned int pad:1; 1135 unsigned int dest_subreg_nr:5; 1136 unsigned int dest_reg_nr:8; 1137 unsigned int dest_horiz_stride:2; 1138 unsigned int dest_address_mode:1; 1139 } da1; 1140 1141 struct 1142 { 1143 unsigned int dest_reg_file:2; 1144 unsigned int dest_reg_type:3; 1145 unsigned int src0_reg_file:2; 1146 unsigned int src0_reg_type:3; 1147 unsigned int pad:6; 1148 int dest_indirect_offset:10; /* offset against the deref'd address reg */ 1149 unsigned int dest_subreg_nr:3; /* subnr for the address reg a0.x */ 1150 unsigned int dest_horiz_stride:2; 1151 unsigned int dest_address_mode:1; 1152 } ia1; 1153 1154 struct 1155 { 1156 unsigned int dest_reg_file:2; 1157 unsigned int dest_reg_type:3; 1158 unsigned int src0_reg_file:2; 1159 unsigned int src0_reg_type:3; 1160 unsigned int src1_reg_file:2; 1161 unsigned int src1_reg_type:3; 1162 unsigned int pad0:1; 1163 unsigned int dest_writemask:4; 1164 unsigned int dest_subreg_nr:1; 1165 unsigned int dest_reg_nr:8; 1166 unsigned int pad1:2; 1167 unsigned int dest_address_mode:1; 1168 } da16; 1169 1170 struct 1171 { 1172 unsigned int dest_reg_file:2; 1173 unsigned int dest_reg_type:3; 1174 unsigned int src0_reg_file:2; 1175 unsigned int src0_reg_type:3; 1176 unsigned int pad0:6; 1177 unsigned int dest_writemask:4; 1178 int dest_indirect_offset:6; 1179 unsigned int dest_subreg_nr:3; 1180 unsigned int pad1:2; 1181 unsigned int dest_address_mode:1; 1182 } ia16; 1183 } bits1; 1184 1185 1186 union { 1187 struct 1188 { 1189 unsigned int src0_subreg_nr:5; 1190 unsigned int src0_reg_nr:8; 1191 unsigned int src0_abs:1; 1192 unsigned int src0_negate:1; 1193 unsigned int src0_address_mode:1; 1194 unsigned int src0_horiz_stride:2; 1195 unsigned int src0_width:3; 1196 unsigned int src0_vert_stride:4; 1197 unsigned int flag_reg_nr:1; 1198 unsigned int pad:6; 1199 } da1; 1200 1201 struct 1202 { 1203 int src0_indirect_offset:10; 1204 unsigned int src0_subreg_nr:3; 1205 unsigned int src0_abs:1; 1206 unsigned int src0_negate:1; 1207 unsigned int src0_address_mode:1; 1208 unsigned int src0_horiz_stride:2; 1209 unsigned int src0_width:3; 1210 unsigned int src0_vert_stride:4; 1211 unsigned int flag_reg_nr:1; 1212 unsigned int pad:6; 1213 } ia1; 1214 1215 struct 1216 { 1217 unsigned int src0_swz_x:2; 1218 unsigned int src0_swz_y:2; 1219 unsigned int src0_subreg_nr:1; 1220 unsigned int src0_reg_nr:8; 1221 unsigned int src0_abs:1; 1222 unsigned int src0_negate:1; 1223 unsigned int src0_address_mode:1; 1224 unsigned int src0_swz_z:2; 1225 unsigned int src0_swz_w:2; 1226 unsigned int pad0:1; 1227 unsigned int src0_vert_stride:4; 1228 unsigned int flag_reg_nr:1; 1229 unsigned int pad1:6; 1230 } da16; 1231 1232 struct 1233 { 1234 unsigned int src0_swz_x:2; 1235 unsigned int src0_swz_y:2; 1236 int src0_indirect_offset:6; 1237 unsigned int src0_subreg_nr:3; 1238 unsigned int src0_abs:1; 1239 unsigned int src0_negate:1; 1240 unsigned int src0_address_mode:1; 1241 unsigned int src0_swz_z:2; 1242 unsigned int src0_swz_w:2; 1243 unsigned int pad0:1; 1244 unsigned int src0_vert_stride:4; 1245 unsigned int flag_reg_nr:1; 1246 unsigned int pad1:6; 1247 } ia16; 1248 1249 } bits2; 1250 1251 union 1252 { 1253 struct 1254 { 1255 unsigned int src1_subreg_nr:5; 1256 unsigned int src1_reg_nr:8; 1257 unsigned int src1_abs:1; 1258 unsigned int src1_negate:1; 1259 unsigned int pad:1; 1260 unsigned int src1_horiz_stride:2; 1261 unsigned int src1_width:3; 1262 unsigned int src1_vert_stride:4; 1263 unsigned int pad0:7; 1264 } da1; 1265 1266 struct 1267 { 1268 unsigned int src1_swz_x:2; 1269 unsigned int src1_swz_y:2; 1270 unsigned int src1_subreg_nr:1; 1271 unsigned int src1_reg_nr:8; 1272 unsigned int src1_abs:1; 1273 unsigned int src1_negate:1; 1274 unsigned int pad0:1; 1275 unsigned int src1_swz_z:2; 1276 unsigned int src1_swz_w:2; 1277 unsigned int pad1:1; 1278 unsigned int src1_vert_stride:4; 1279 unsigned int pad2:7; 1280 } da16; 1281 1282 struct 1283 { 1284 int src1_indirect_offset:10; 1285 unsigned int src1_subreg_nr:3; 1286 unsigned int src1_abs:1; 1287 unsigned int src1_negate:1; 1288 unsigned int pad0:1; 1289 unsigned int src1_horiz_stride:2; 1290 unsigned int src1_width:3; 1291 unsigned int src1_vert_stride:4; 1292 unsigned int flag_reg_nr:1; 1293 unsigned int pad1:6; 1294 } ia1; 1295 1296 struct 1297 { 1298 unsigned int src1_swz_x:2; 1299 unsigned int src1_swz_y:2; 1300 int src1_indirect_offset:6; 1301 unsigned int src1_subreg_nr:3; 1302 unsigned int src1_abs:1; 1303 unsigned int src1_negate:1; 1304 unsigned int pad0:1; 1305 unsigned int src1_swz_z:2; 1306 unsigned int src1_swz_w:2; 1307 unsigned int pad1:1; 1308 unsigned int src1_vert_stride:4; 1309 unsigned int flag_reg_nr:1; 1310 unsigned int pad2:6; 1311 } ia16; 1312 1313 1314 struct 1315 { 1316 int jump_count:16; /* note: signed */ 1317 unsigned int pop_count:4; 1318 unsigned int pad0:12; 1319 } if_else; 1320 1321 struct { 1322 unsigned int function:4; 1323 unsigned int int_type:1; 1324 unsigned int precision:1; 1325 unsigned int saturate:1; 1326 unsigned int data_type:1; 1327 unsigned int pad0:8; 1328 unsigned int response_length:4; 1329 unsigned int msg_length:4; 1330 unsigned int msg_target:4; 1331 unsigned int pad1:3; 1332 unsigned int end_of_thread:1; 1333 } math; 1334 1335 struct { 1336 unsigned int binding_table_index:8; 1337 unsigned int sampler:4; 1338 unsigned int return_format:2; 1339 unsigned int msg_type:2; 1340 unsigned int response_length:4; 1341 unsigned int msg_length:4; 1342 unsigned int msg_target:4; 1343 unsigned int pad1:3; 1344 unsigned int end_of_thread:1; 1345 } sampler; 1346 1347 struct brw_urb_immediate urb; 1348 1349 struct { 1350 unsigned int binding_table_index:8; 1351 unsigned int msg_control:4; 1352 unsigned int msg_type:2; 1353 unsigned int target_cache:2; 1354 unsigned int response_length:4; 1355 unsigned int msg_length:4; 1356 unsigned int msg_target:4; 1357 unsigned int pad1:3; 1358 unsigned int end_of_thread:1; 1359 } dp_read; 1360 1361 struct { 1362 unsigned int binding_table_index:8; 1363 unsigned int msg_control:3; 1364 unsigned int pixel_scoreboard_clear:1; 1365 unsigned int msg_type:3; 1366 unsigned int send_commit_msg:1; 1367 unsigned int response_length:4; 1368 unsigned int msg_length:4; 1369 unsigned int msg_target:4; 1370 unsigned int pad1:3; 1371 unsigned int end_of_thread:1; 1372 } dp_write; 1373 1374 struct { 1375 unsigned int pad:16; 1376 unsigned int response_length:4; 1377 unsigned int msg_length:4; 1378 unsigned int msg_target:4; 1379 unsigned int pad1:3; 1380 unsigned int end_of_thread:1; 1381 } generic; 1382 1383 unsigned int ud; 1384 } bits3; 1385}; 1386 1387/* media pipeline */ 1388 1389struct brw_vfe_state { 1390 struct { 1391 unsigned int per_thread_scratch_space:4; 1392 unsigned int pad3:3; 1393 unsigned int extend_vfe_state_present:1; 1394 unsigned int pad2:2; 1395 unsigned int scratch_base:22; 1396 } vfe0; 1397 1398 struct { 1399 unsigned int debug_counter_control:2; 1400 unsigned int children_present:1; 1401 unsigned int vfe_mode:4; 1402 unsigned int pad2:2; 1403 unsigned int num_urb_entries:7; 1404 unsigned int urb_entry_alloc_size:9; 1405 unsigned int max_threads:7; 1406 } vfe1; 1407 1408 struct { 1409 unsigned int pad4:4; 1410 unsigned int interface_descriptor_base:28; 1411 } vfe2; 1412}; 1413 1414struct brw_vld_state { 1415 struct { 1416 unsigned int pad6:6; 1417 unsigned int scan_order:1; 1418 unsigned int intra_vlc_format:1; 1419 unsigned int quantizer_scale_type:1; 1420 unsigned int concealment_motion_vector:1; 1421 unsigned int frame_predict_frame_dct:1; 1422 unsigned int top_field_first:1; 1423 unsigned int picture_structure:2; 1424 unsigned int intra_dc_precision:2; 1425 unsigned int f_code_0_0:4; 1426 unsigned int f_code_0_1:4; 1427 unsigned int f_code_1_0:4; 1428 unsigned int f_code_1_1:4; 1429 } vld0; 1430 1431 struct { 1432 unsigned int pad2:9; 1433 unsigned int picture_coding_type:2; 1434 unsigned int pad:21; 1435 } vld1; 1436 1437 struct { 1438 unsigned int index_0:4; 1439 unsigned int index_1:4; 1440 unsigned int index_2:4; 1441 unsigned int index_3:4; 1442 unsigned int index_4:4; 1443 unsigned int index_5:4; 1444 unsigned int index_6:4; 1445 unsigned int index_7:4; 1446 } desc_remap_table0; 1447 1448 struct { 1449 unsigned int index_8:4; 1450 unsigned int index_9:4; 1451 unsigned int index_10:4; 1452 unsigned int index_11:4; 1453 unsigned int index_12:4; 1454 unsigned int index_13:4; 1455 unsigned int index_14:4; 1456 unsigned int index_15:4; 1457 } desc_remap_table1; 1458}; 1459 1460struct brw_interface_descriptor { 1461 struct { 1462 unsigned int grf_reg_blocks:4; 1463 unsigned int pad:2; 1464 unsigned int kernel_start_pointer:26; 1465 } desc0; 1466 1467 struct { 1468 unsigned int pad:7; 1469 unsigned int software_exception:1; 1470 unsigned int pad2:3; 1471 unsigned int maskstack_exception:1; 1472 unsigned int pad3:1; 1473 unsigned int illegal_opcode_exception:1; 1474 unsigned int pad4:2; 1475 unsigned int floating_point_mode:1; 1476 unsigned int thread_priority:1; 1477 unsigned int single_program_flow:1; 1478 unsigned int pad5:1; 1479 unsigned int const_urb_entry_read_offset:6; 1480 unsigned int const_urb_entry_read_len:6; 1481 } desc1; 1482 1483 struct { 1484 unsigned int pad:2; 1485 unsigned int sampler_count:3; 1486 unsigned int sampler_state_pointer:27; 1487 } desc2; 1488 1489 struct { 1490 unsigned int binding_table_entry_count:5; 1491 unsigned int binding_table_pointer:27; 1492 } desc3; 1493}; 1494 1495struct gen6_blend_state 1496{ 1497 struct { 1498 unsigned int dest_blend_factor:5; 1499 unsigned int source_blend_factor:5; 1500 unsigned int pad3:1; 1501 unsigned int blend_func:3; 1502 unsigned int pad2:1; 1503 unsigned int ia_dest_blend_factor:5; 1504 unsigned int ia_source_blend_factor:5; 1505 unsigned int pad1:1; 1506 unsigned int ia_blend_func:3; 1507 unsigned int pad0:1; 1508 unsigned int ia_blend_enable:1; 1509 unsigned int blend_enable:1; 1510 } blend0; 1511 1512 struct { 1513 unsigned int post_blend_clamp_enable:1; 1514 unsigned int pre_blend_clamp_enable:1; 1515 unsigned int clamp_range:2; 1516 unsigned int pad0:4; 1517 unsigned int x_dither_offset:2; 1518 unsigned int y_dither_offset:2; 1519 unsigned int dither_enable:1; 1520 unsigned int alpha_test_func:3; 1521 unsigned int alpha_test_enable:1; 1522 unsigned int pad1:1; 1523 unsigned int logic_op_func:4; 1524 unsigned int logic_op_enable:1; 1525 unsigned int pad2:1; 1526 unsigned int write_disable_b:1; 1527 unsigned int write_disable_g:1; 1528 unsigned int write_disable_r:1; 1529 unsigned int write_disable_a:1; 1530 unsigned int pad3:1; 1531 unsigned int alpha_to_coverage_dither:1; 1532 unsigned int alpha_to_one:1; 1533 unsigned int alpha_to_coverage:1; 1534 } blend1; 1535}; 1536 1537struct gen6_color_calc_state 1538{ 1539 struct { 1540 unsigned int alpha_test_format:1; 1541 unsigned int pad0:14; 1542 unsigned int round_disable:1; 1543 unsigned int bf_stencil_ref:8; 1544 unsigned int stencil_ref:8; 1545 } cc0; 1546 1547 union { 1548 float alpha_ref_f; 1549 struct { 1550 unsigned int ui:8; 1551 unsigned int pad0:24; 1552 } alpha_ref_fi; 1553 } cc1; 1554 1555 float constant_r; 1556 float constant_g; 1557 float constant_b; 1558 float constant_a; 1559}; 1560 1561struct gen6_depth_stencil_state 1562{ 1563 struct { 1564 unsigned int pad0:3; 1565 unsigned int bf_stencil_pass_depth_pass_op:3; 1566 unsigned int bf_stencil_pass_depth_fail_op:3; 1567 unsigned int bf_stencil_fail_op:3; 1568 unsigned int bf_stencil_func:3; 1569 unsigned int bf_stencil_enable:1; 1570 unsigned int pad1:2; 1571 unsigned int stencil_write_enable:1; 1572 unsigned int stencil_pass_depth_pass_op:3; 1573 unsigned int stencil_pass_depth_fail_op:3; 1574 unsigned int stencil_fail_op:3; 1575 unsigned int stencil_func:3; 1576 unsigned int stencil_enable:1; 1577 } ds0; 1578 1579 struct { 1580 unsigned int bf_stencil_write_mask:8; 1581 unsigned int bf_stencil_test_mask:8; 1582 unsigned int stencil_write_mask:8; 1583 unsigned int stencil_test_mask:8; 1584 } ds1; 1585 1586 struct { 1587 unsigned int pad0:26; 1588 unsigned int depth_write_enable:1; 1589 unsigned int depth_test_func:3; 1590 unsigned int pad1:1; 1591 unsigned int depth_test_enable:1; 1592 } ds2; 1593}; 1594 1595struct gen7_surface_state 1596{ 1597 struct { 1598 unsigned int cube_pos_z:1; 1599 unsigned int cube_neg_z:1; 1600 unsigned int cube_pos_y:1; 1601 unsigned int cube_neg_y:1; 1602 unsigned int cube_pos_x:1; 1603 unsigned int cube_neg_x:1; 1604 unsigned int pad2:2; 1605 unsigned int render_cache_read_write:1; 1606 unsigned int pad1:1; 1607 unsigned int surface_array_spacing:1; 1608 unsigned int vert_line_stride_ofs:1; 1609 unsigned int vert_line_stride:1; 1610 unsigned int tile_walk:1; 1611 unsigned int tiled_surface:1; 1612 unsigned int horizontal_alignment:1; 1613 unsigned int vertical_alignment:2; 1614 unsigned int surface_format:9; /**< BRW_SURFACEFORMAT_x */ 1615 unsigned int pad0:1; 1616 unsigned int is_array:1; 1617 unsigned int surface_type:3; /**< BRW_SURFACE_1D/2D/3D/CUBE */ 1618 } ss0; 1619 1620 struct { 1621 unsigned int base_addr; 1622 } ss1; 1623 1624 struct { 1625 unsigned int width:14; 1626 unsigned int pad1:2; 1627 unsigned int height:14; 1628 unsigned int pad0:2; 1629 } ss2; 1630 1631 struct { 1632 unsigned int pitch:18; 1633 unsigned int pad:3; 1634 unsigned int depth:11; 1635 } ss3; 1636 1637 struct { 1638 unsigned int multisample_position_palette_index:3; 1639 unsigned int num_multisamples:3; 1640 unsigned int multisampled_surface_storage_format:1; 1641 unsigned int render_target_view_extent:11; 1642 unsigned int min_array_elt:11; 1643 unsigned int rotation:2; 1644 unsigned int pad0:1; 1645 } ss4; 1646 1647 struct { 1648 unsigned int mip_count:4; 1649 unsigned int min_lod:4; 1650 unsigned int pad1:12; 1651 unsigned int y_offset:4; 1652 unsigned int pad0:1; 1653 unsigned int x_offset:7; 1654 } ss5; 1655 1656 struct { 1657 unsigned int pad; /* Multisample Control Surface stuff */ 1658 } ss6; 1659 1660 struct { 1661 unsigned int resource_min_lod:12; 1662 unsigned int pad0:4; 1663 unsigned int shader_chanel_select_a:3; 1664 unsigned int shader_chanel_select_b:3; 1665 unsigned int shader_chanel_select_g:3; 1666 unsigned int shader_chanel_select_r:3; 1667 unsigned int alpha_clear_color:1; 1668 unsigned int blue_clear_color:1; 1669 unsigned int green_clear_color:1; 1670 unsigned int red_clear_color:1; 1671 } ss7; 1672}; 1673 1674struct gen7_sampler_state 1675{ 1676 struct 1677 { 1678 unsigned int aniso_algorithm:1; 1679 unsigned int lod_bias:13; 1680 unsigned int min_filter:3; 1681 unsigned int mag_filter:3; 1682 unsigned int mip_filter:2; 1683 unsigned int base_level:5; 1684 unsigned int pad1:1; 1685 unsigned int lod_preclamp:1; 1686 unsigned int default_color_mode:1; 1687 unsigned int pad0:1; 1688 unsigned int disable:1; 1689 } ss0; 1690 1691 struct 1692 { 1693 unsigned int cube_control_mode:1; 1694 unsigned int shadow_function:3; 1695 unsigned int pad:4; 1696 unsigned int max_lod:12; 1697 unsigned int min_lod:12; 1698 } ss1; 1699 1700 struct 1701 { 1702 unsigned int pad:5; 1703 unsigned int default_color_pointer:27; 1704 } ss2; 1705 1706 struct 1707 { 1708 unsigned int r_wrap_mode:3; 1709 unsigned int t_wrap_mode:3; 1710 unsigned int s_wrap_mode:3; 1711 unsigned int pad:1; 1712 unsigned int non_normalized_coord:1; 1713 unsigned int trilinear_quality:2; 1714 unsigned int address_round:6; 1715 unsigned int max_aniso:3; 1716 unsigned int chroma_key_mode:1; 1717 unsigned int chroma_key_index:2; 1718 unsigned int chroma_key_enable:1; 1719 unsigned int pad0:6; 1720 } ss3; 1721}; 1722 1723#endif 1724