1/************************************************************************** 2 * 3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28#ifdef HAVE_CONFIG_H 29#include "config.h" 30#endif 31 32#include "xorg-server.h" 33#include "xf86.h" 34#include "intel.h" 35#include "intel_uxa.h" 36 37#include "i830_reg.h" 38 39void I830EmitInvarientState(ScrnInfoPtr scrn) 40{ 41 intel_screen_private *intel = intel_get_screen_private(scrn); 42 43 assert(intel->in_batch_atomic); 44 45 OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(0)); 46 OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(1)); 47 OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(2)); 48 OUT_BATCH(_3DSTATE_MAP_CUBE | MAP_UNIT(3)); 49 50 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD); 51 OUT_BATCH(0); 52 53 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD); 54 OUT_BATCH(0); 55 56 OUT_BATCH(_3DSTATE_DFLT_Z_CMD); 57 OUT_BATCH(0); 58 59 OUT_BATCH(_3DSTATE_FOG_MODE_CMD); 60 OUT_BATCH(FOGFUNC_ENABLE | 61 FOG_LINEAR_CONST | FOGSRC_INDEX_Z | ENABLE_FOG_DENSITY); 62 OUT_BATCH(0); 63 OUT_BATCH(0); 64 65 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD | 66 MAP_UNIT(0) | 67 DISABLE_TEX_STREAM_BUMP | 68 ENABLE_TEX_STREAM_COORD_SET | 69 TEX_STREAM_COORD_SET(0) | 70 ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(0)); 71 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD | 72 MAP_UNIT(1) | 73 DISABLE_TEX_STREAM_BUMP | 74 ENABLE_TEX_STREAM_COORD_SET | 75 TEX_STREAM_COORD_SET(1) | 76 ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(1)); 77 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD | 78 MAP_UNIT(2) | 79 DISABLE_TEX_STREAM_BUMP | 80 ENABLE_TEX_STREAM_COORD_SET | 81 TEX_STREAM_COORD_SET(2) | 82 ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(2)); 83 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD | 84 MAP_UNIT(3) | 85 DISABLE_TEX_STREAM_BUMP | 86 ENABLE_TEX_STREAM_COORD_SET | 87 TEX_STREAM_COORD_SET(3) | 88 ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(3)); 89 90 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM); 91 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(0)); 92 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM); 93 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(1)); 94 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM); 95 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(2)); 96 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM); 97 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(3)); 98 99 OUT_BATCH(_3DSTATE_RASTER_RULES_CMD | 100 ENABLE_POINT_RASTER_RULE | 101 OGL_POINT_RASTER_RULE | 102 ENABLE_LINE_STRIP_PROVOKE_VRTX | 103 ENABLE_TRI_FAN_PROVOKE_VRTX | 104 ENABLE_TRI_STRIP_PROVOKE_VRTX | 105 LINE_STRIP_PROVOKE_VRTX(1) | 106 TRI_FAN_PROVOKE_VRTX(2) | TRI_STRIP_PROVOKE_VRTX(2)); 107 108 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT); 109 110 OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD); 111 OUT_BATCH(0); 112 OUT_BATCH(0); 113 114 OUT_BATCH(_3DSTATE_VERTEX_TRANSFORM); 115 OUT_BATCH(DISABLE_VIEWPORT_TRANSFORM | DISABLE_PERSPECTIVE_DIVIDE); 116 117 OUT_BATCH(_3DSTATE_W_STATE_CMD); 118 OUT_BATCH(MAGIC_W_STATE_DWORD1); 119 OUT_BATCH(0x3f800000 /* 1.0 in IEEE float */ ); 120 121 OUT_BATCH(_3DSTATE_COLOR_FACTOR_CMD); 122 OUT_BATCH(0x80808080); /* .5 required in alpha for GL_DOT3_RGBA_EXT */ 123 124 OUT_BATCH(_3DSTATE_MAP_COORD_SETBIND_CMD); 125 OUT_BATCH(TEXBIND_SET3(TEXCOORDSRC_VTXSET_3) | 126 TEXBIND_SET2(TEXCOORDSRC_VTXSET_2) | 127 TEXBIND_SET1(TEXCOORDSRC_VTXSET_1) | 128 TEXBIND_SET0(TEXCOORDSRC_VTXSET_0)); 129 130 /* copy from mesa */ 131 OUT_BATCH(_3DSTATE_INDPT_ALPHA_BLEND_CMD | 132 DISABLE_INDPT_ALPHA_BLEND | 133 ENABLE_ALPHA_BLENDFUNC | ABLENDFUNC_ADD); 134 135 OUT_BATCH(_3DSTATE_FOG_COLOR_CMD | 136 FOG_COLOR_RED(0) | FOG_COLOR_GREEN(0) | FOG_COLOR_BLUE(0)); 137 138 OUT_BATCH(_3DSTATE_CONST_BLEND_COLOR_CMD); 139 OUT_BATCH(0); 140 141 OUT_BATCH(_3DSTATE_MODES_1_CMD | 142 ENABLE_COLR_BLND_FUNC | 143 BLENDFUNC_ADD | 144 ENABLE_SRC_BLND_FACTOR | 145 SRC_BLND_FACT(BLENDFACTOR_ONE) | 146 ENABLE_DST_BLND_FACTOR | DST_BLND_FACT(BLENDFACTOR_ZERO)); 147 OUT_BATCH(_3DSTATE_MODES_2_CMD | ENABLE_GLOBAL_DEPTH_BIAS | GLOBAL_DEPTH_BIAS(0) | ENABLE_ALPHA_TEST_FUNC | ALPHA_TEST_FUNC(0) | /* always */ 148 ALPHA_REF_VALUE(0)); 149 OUT_BATCH(_3DSTATE_MODES_3_CMD | 150 ENABLE_DEPTH_TEST_FUNC | 151 DEPTH_TEST_FUNC(0x2) | /* COMPAREFUNC_LESS */ 152 ENABLE_ALPHA_SHADE_MODE | 153 ALPHA_SHADE_MODE(SHADE_MODE_LINEAR) | 154 ENABLE_FOG_SHADE_MODE | 155 FOG_SHADE_MODE(SHADE_MODE_LINEAR) | 156 ENABLE_SPEC_SHADE_MODE | 157 SPEC_SHADE_MODE(SHADE_MODE_LINEAR) | 158 ENABLE_COLOR_SHADE_MODE | 159 COLOR_SHADE_MODE(SHADE_MODE_LINEAR) | 160 ENABLE_CULL_MODE | CULLMODE_NONE); 161 162 OUT_BATCH(_3DSTATE_MODES_4_CMD | 163 ENABLE_LOGIC_OP_FUNC | 164 LOGIC_OP_FUNC(LOGICOP_COPY) | 165 ENABLE_STENCIL_TEST_MASK | 166 STENCIL_TEST_MASK(0xff) | 167 ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff)); 168 169 OUT_BATCH(_3DSTATE_STENCIL_TEST_CMD | 170 ENABLE_STENCIL_PARMS | 171 STENCIL_FAIL_OP(0) | /* STENCILOP_KEEP */ 172 STENCIL_PASS_DEPTH_FAIL_OP(0) | /* STENCILOP_KEEP */ 173 STENCIL_PASS_DEPTH_PASS_OP(0) | /* STENCILOP_KEEP */ 174 ENABLE_STENCIL_TEST_FUNC | 175 STENCIL_TEST_FUNC(0) | /* COMPAREFUNC_ALWAYS */ 176 ENABLE_STENCIL_REF_VALUE | 177 STENCIL_REF_VALUE(0)); 178 179 OUT_BATCH(_3DSTATE_MODES_5_CMD | 180 FLUSH_TEXTURE_CACHE | 181 ENABLE_SPRITE_POINT_TEX | SPRITE_POINT_TEX_OFF | 182 ENABLE_FIXED_LINE_WIDTH | FIXED_LINE_WIDTH(0x2) | /* 1.0 */ 183 ENABLE_FIXED_POINT_WIDTH | FIXED_POINT_WIDTH(1)); 184 185 OUT_BATCH(_3DSTATE_ENABLES_1_CMD | 186 DISABLE_LOGIC_OP | 187 DISABLE_STENCIL_TEST | 188 DISABLE_DEPTH_BIAS | 189 DISABLE_SPEC_ADD | 190 DISABLE_FOG | 191 DISABLE_ALPHA_TEST | ENABLE_COLOR_BLEND | DISABLE_DEPTH_TEST); 192 OUT_BATCH(_3DSTATE_ENABLES_2_CMD | 193 DISABLE_STENCIL_WRITE | 194 ENABLE_TEX_CACHE | 195 DISABLE_DITHER | 196 ENABLE_COLOR_MASK | ENABLE_COLOR_WRITE | DISABLE_DEPTH_WRITE); 197 198 OUT_BATCH(_3DSTATE_STIPPLE); 199 200 /* Set default blend state */ 201 OUT_BATCH(_3DSTATE_MAP_BLEND_OP_CMD(0) | 202 TEXPIPE_COLOR | 203 ENABLE_TEXOUTPUT_WRT_SEL | 204 TEXOP_OUTPUT_CURRENT | 205 DISABLE_TEX_CNTRL_STAGE | 206 TEXOP_SCALE_1X | 207 TEXOP_MODIFY_PARMS | TEXOP_LAST_STAGE | TEXBLENDOP_ARG1); 208 OUT_BATCH(_3DSTATE_MAP_BLEND_OP_CMD(0) | 209 TEXPIPE_ALPHA | 210 ENABLE_TEXOUTPUT_WRT_SEL | 211 TEXOP_OUTPUT_CURRENT | 212 TEXOP_SCALE_1X | TEXOP_MODIFY_PARMS | TEXBLENDOP_ARG1); 213 OUT_BATCH(_3DSTATE_MAP_BLEND_ARG_CMD(0) | 214 TEXPIPE_COLOR | 215 TEXBLEND_ARG1 | 216 TEXBLENDARG_MODIFY_PARMS | TEXBLENDARG_DIFFUSE); 217 OUT_BATCH(_3DSTATE_MAP_BLEND_ARG_CMD(0) | 218 TEXPIPE_ALPHA | 219 TEXBLEND_ARG1 | 220 TEXBLENDARG_MODIFY_PARMS | TEXBLENDARG_DIFFUSE); 221 222 OUT_BATCH(_3DSTATE_AA_CMD | 223 AA_LINE_ECAAR_WIDTH_ENABLE | 224 AA_LINE_ECAAR_WIDTH_1_0 | 225 AA_LINE_REGION_WIDTH_ENABLE | 226 AA_LINE_REGION_WIDTH_1_0 | AA_LINE_DISABLE); 227} 228