intel.h revision 03b705cf
1/************************************************************************** 2 3Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. 4Copyright © 2002 David Dawes 5 6All Rights Reserved. 7 8Permission is hereby granted, free of charge, to any person obtaining a 9copy of this software and associated documentation files (the 10"Software"), to deal in the Software without restriction, including 11without limitation the rights to use, copy, modify, merge, publish, 12distribute, sub license, and/or sell copies of the Software, and to 13permit persons to whom the Software is furnished to do so, subject to 14the following conditions: 15 16The above copyright notice and this permission notice (including the 17next paragraph) shall be included in all copies or substantial portions 18of the Software. 19 20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 24ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28**************************************************************************/ 29 30/* 31 * Authors: 32 * Keith Whitwell <keith@tungstengraphics.com> 33 * David Dawes <dawes@xfree86.org> 34 * 35 */ 36 37#ifdef HAVE_CONFIG_H 38#include "config.h" 39#endif 40 41#if 0 42#define I830DEBUG 43#endif 44 45#include <stdint.h> 46 47#ifndef REMAP_RESERVED 48#define REMAP_RESERVED 0 49#endif 50 51#ifndef _I830_H_ 52#define _I830_H_ 53 54#include "xf86_OSproc.h" 55#include "compiler.h" 56#include "xf86Pci.h" 57#include "xf86Cursor.h" 58#include "xf86xv.h" 59#include "xf86Crtc.h" 60#include "xf86RandR12.h" 61 62#include "xorg-server.h" 63#include <pciaccess.h> 64 65#define _XF86DRI_SERVER_ 66#include "dri2.h" 67#include "intel_bufmgr.h" 68#include "i915_drm.h" 69 70#include "intel_driver.h" 71#include "intel_options.h" 72#include "intel_list.h" 73#include "compat-api.h" 74 75#if HAVE_UDEV 76#include <libudev.h> 77#endif 78 79/* remain compatible to xorg-server 1.6 */ 80#ifndef MONITOR_EDID_COMPLETE_RAWDATA 81#define MONITOR_EDID_COMPLETE_RAWDATA EDID_COMPLETE_RAWDATA 82#endif 83 84#if XF86_CRTC_VERSION >= 5 85#define INTEL_PIXMAP_SHARING 1 86#endif 87 88struct intel_pixmap { 89 dri_bo *bo; 90 91 struct list batch; 92 93 uint16_t stride; 94 uint8_t tiling; 95 int8_t busy :2; 96 uint8_t dirty :1; 97 uint8_t offscreen :1; 98 uint8_t pinned :3; 99#define PIN_SCANOUT 0x1 100#define PIN_DRI 0x2 101#define PIN_GLAMOR 0x4 102}; 103 104#if HAS_DEVPRIVATEKEYREC 105extern DevPrivateKeyRec uxa_pixmap_index; 106#else 107extern int uxa_pixmap_index; 108#endif 109 110static inline struct intel_pixmap *intel_get_pixmap_private(PixmapPtr pixmap) 111{ 112#if HAS_DEVPRIVATEKEYREC 113 return dixGetPrivate(&pixmap->devPrivates, &uxa_pixmap_index); 114#else 115 return dixLookupPrivate(&pixmap->devPrivates, &uxa_pixmap_index); 116#endif 117} 118 119static inline Bool intel_pixmap_is_busy(struct intel_pixmap *priv) 120{ 121 if (priv->busy == -1) 122 priv->busy = drm_intel_bo_busy(priv->bo); 123 return priv->busy; 124} 125 126static inline void intel_set_pixmap_private(PixmapPtr pixmap, struct intel_pixmap *intel) 127{ 128 dixSetPrivate(&pixmap->devPrivates, &uxa_pixmap_index, intel); 129} 130 131static inline Bool intel_pixmap_is_dirty(PixmapPtr pixmap) 132{ 133 return pixmap && intel_get_pixmap_private(pixmap)->dirty; 134} 135 136static inline Bool intel_pixmap_tiled(PixmapPtr pixmap) 137{ 138 return intel_get_pixmap_private(pixmap)->tiling != I915_TILING_NONE; 139} 140 141dri_bo *intel_get_pixmap_bo(PixmapPtr pixmap); 142void intel_set_pixmap_bo(PixmapPtr pixmap, dri_bo * bo); 143 144#include "common.h" 145 146#define PITCH_NONE 0 147 148/** enumeration of 3d consumers so some can maintain invariant state. */ 149enum last_3d { 150 LAST_3D_OTHER, 151 LAST_3D_VIDEO, 152 LAST_3D_RENDER, 153 LAST_3D_ROTATION 154}; 155 156enum dri_type { 157 DRI_DISABLED, 158 DRI_NONE, 159 DRI_DRI2 160}; 161 162typedef struct intel_screen_private { 163 ScrnInfoPtr scrn; 164 int cpp; 165 166#define RENDER_BATCH I915_EXEC_RENDER 167#define BLT_BATCH I915_EXEC_BLT 168 unsigned int current_batch; 169 170 void *modes; 171 drm_intel_bo *front_buffer, *back_buffer; 172 PixmapPtr back_pixmap; 173 unsigned int back_name; 174 long front_pitch, front_tiling; 175 176 dri_bufmgr *bufmgr; 177 178 uint32_t batch_ptr[4096]; 179 /** Byte offset in batch_ptr for the next dword to be emitted. */ 180 unsigned int batch_used; 181 /** Position in batch_ptr at the start of the current BEGIN_BATCH */ 182 unsigned int batch_emit_start; 183 /** Number of bytes to be emitted in the current BEGIN_BATCH. */ 184 uint32_t batch_emitting; 185 dri_bo *batch_bo, *last_batch_bo[2]; 186 /** Whether we're in a section of code that can't tolerate flushing */ 187 Bool in_batch_atomic; 188 /** Ending batch_used that was verified by intel_start_batch_atomic() */ 189 int batch_atomic_limit; 190 struct list batch_pixmaps; 191 drm_intel_bo *wa_scratch_bo; 192 OsTimerPtr cache_expire; 193 194 /* For Xvideo */ 195 Bool use_overlay; 196#ifdef INTEL_XVMC 197 /* For XvMC */ 198 Bool XvMCEnabled; 199#endif 200 201 CreateScreenResourcesProcPtr CreateScreenResources; 202 203 Bool shadow_present; 204 205 unsigned int tiling; 206#define INTEL_TILING_FB 0x1 207#define INTEL_TILING_2D 0x2 208#define INTEL_TILING_3D 0x4 209#define INTEL_TILING_ALL (~0) 210 211 Bool swapbuffers_wait; 212 Bool has_relaxed_fencing; 213 214 int Chipset; 215 EntityInfoPtr pEnt; 216 struct pci_device *PciInfo; 217 const struct intel_device_info *info; 218 219 unsigned int BR[20]; 220 221 CloseScreenProcPtr CloseScreen; 222 223 void (*context_switch) (struct intel_screen_private *intel, 224 int new_mode); 225 void (*vertex_flush) (struct intel_screen_private *intel); 226 void (*batch_flush) (struct intel_screen_private *intel); 227 void (*batch_commit_notify) (struct intel_screen_private *intel); 228 229 struct _UxaDriver *uxa_driver; 230 int uxa_flags; 231 Bool need_sync; 232 int accel_pixmap_offset_alignment; 233 int accel_max_x; 234 int accel_max_y; 235 int max_bo_size; 236 int max_gtt_map_size; 237 int max_tiling_size; 238 239 Bool XvDisabled; /* Xv disabled in PreInit. */ 240 Bool XvEnabled; /* Xv enabled for this generation. */ 241 Bool XvPreferOverlay; 242 243 int colorKey; 244 XF86VideoAdaptorPtr adaptor; 245 ScreenBlockHandlerProcPtr BlockHandler; 246 Bool overlayOn; 247 248 struct { 249 drm_intel_bo *gen4_vs_bo; 250 drm_intel_bo *gen4_sf_bo; 251 drm_intel_bo *gen4_wm_packed_bo; 252 drm_intel_bo *gen4_wm_planar_bo; 253 drm_intel_bo *gen4_cc_bo; 254 drm_intel_bo *gen4_cc_vp_bo; 255 drm_intel_bo *gen4_sampler_bo; 256 drm_intel_bo *gen4_sip_kernel_bo; 257 drm_intel_bo *wm_prog_packed_bo; 258 drm_intel_bo *wm_prog_planar_bo; 259 drm_intel_bo *gen6_blend_bo; 260 drm_intel_bo *gen6_depth_stencil_bo; 261 } video; 262 263 /* Render accel state */ 264 float scale_units[2][2]; 265 /** Transform pointers for src/mask, or NULL if identity */ 266 PictTransform *transform[2]; 267 268 PixmapPtr render_source, render_mask, render_dest; 269 PicturePtr render_source_picture, render_mask_picture, render_dest_picture; 270 Bool needs_3d_invariant; 271 Bool needs_render_state_emit; 272 Bool needs_render_vertex_emit; 273 274 /* i830 render accel state */ 275 uint32_t render_dest_format; 276 uint32_t cblend, ablend, s8_blendctl; 277 278 /* i915 render accel state */ 279 PixmapPtr texture[2]; 280 uint32_t mapstate[6]; 281 uint32_t samplerstate[6]; 282 283 struct { 284 int op; 285 uint32_t dst_format; 286 } i915_render_state; 287 288 struct { 289 int num_sf_outputs; 290 int drawrect; 291 uint32_t blend; 292 dri_bo *samplers; 293 dri_bo *kernel; 294 } gen6_render_state; 295 296 uint32_t prim_offset; 297 void (*prim_emit)(struct intel_screen_private *intel, 298 int srcX, int srcY, 299 int maskX, int maskY, 300 int dstX, int dstY, 301 int w, int h); 302 int floats_per_vertex; 303 int last_floats_per_vertex; 304 uint16_t vertex_offset; 305 uint16_t vertex_count; 306 uint16_t vertex_index; 307 uint16_t vertex_used; 308 uint32_t vertex_id; 309 float vertex_ptr[4*1024]; 310 dri_bo *vertex_bo; 311 312 uint8_t surface_data[16*1024]; 313 uint16_t surface_used; 314 uint16_t surface_table; 315 uint32_t surface_reloc; 316 dri_bo *surface_bo; 317 318 /* 965 render acceleration state */ 319 struct gen4_render_state *gen4_render_state; 320 321 enum dri_type directRenderingType; /* DRI enabled this generation. */ 322 323 Bool directRenderingOpen; 324 int drmSubFD; 325 char *deviceName; 326 327 Bool use_pageflipping; 328 Bool use_triple_buffer; 329 Bool force_fallback; 330 Bool has_kernel_flush; 331 Bool needs_flush; 332 333 struct _DRI2FrameEvent *pending_flip[2]; 334 335 /* Broken-out options. */ 336 OptionInfoPtr Options; 337 338 /* Driver phase/state information */ 339 Bool suspended; 340 341 enum last_3d last_3d; 342 343 /** 344 * User option to print acceleration fallback info to the server log. 345 */ 346 Bool fallback_debug; 347 unsigned debug_flush; 348#if HAVE_UDEV 349 struct udev_monitor *uevent_monitor; 350 InputHandlerProc uevent_handler; 351#endif 352 Bool has_prime_vmap_flush; 353} intel_screen_private; 354 355#define INTEL_INFO(intel) ((intel)->info) 356#define IS_GENx(intel, X) (INTEL_INFO(intel)->gen >= 8*(X) && INTEL_INFO(intel)->gen < 8*((X)+1)) 357#define IS_GEN1(intel) IS_GENx(intel, 1) 358#define IS_GEN2(intel) IS_GENx(intel, 2) 359#define IS_GEN3(intel) IS_GENx(intel, 3) 360#define IS_GEN4(intel) IS_GENx(intel, 4) 361#define IS_GEN5(intel) IS_GENx(intel, 5) 362#define IS_GEN6(intel) IS_GENx(intel, 6) 363#define IS_GEN7(intel) IS_GENx(intel, 7) 364#define IS_HSW(intel) (INTEL_INFO(intel)->gen == 075) 365 366/* Some chips have specific errata (or limits) that we need to workaround. */ 367#define IS_I830(intel) ((intel)->PciInfo->device_id == PCI_CHIP_I830_M) 368#define IS_845G(intel) ((intel)->PciInfo->device_id == PCI_CHIP_845_G) 369#define IS_I865G(intel) ((intel)->PciInfo->device_id == PCI_CHIP_I865_G) 370 371#define IS_I915G(pI810) ((intel)->PciInfo->device_id == PCI_CHIP_I915_G || (intel)->PciInfo->device_id == PCI_CHIP_E7221_G) 372#define IS_I915GM(pI810) ((intel)->PciInfo->device_id == PCI_CHIP_I915_GM) 373 374#define IS_965_Q(pI810) ((intel)->PciInfo->device_id == PCI_CHIP_I965_Q) 375 376/* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */ 377#define SUPPORTS_YTILING(pI810) (INTEL_INFO(intel)->gen >= 040) 378#define HAS_BLT(pI810) (INTEL_INFO(intel)->gen >= 060) 379 380#ifndef I915_PARAM_HAS_PRIME_VMAP_FLUSH 381#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 382#endif 383 384enum { 385 DEBUG_FLUSH_BATCHES = 0x1, 386 DEBUG_FLUSH_CACHES = 0x2, 387 DEBUG_FLUSH_WAIT = 0x4, 388}; 389 390extern Bool intel_mode_pre_init(ScrnInfoPtr pScrn, int fd, int cpp); 391extern void intel_mode_init(struct intel_screen_private *intel); 392extern void intel_mode_disable_unused_functions(ScrnInfoPtr scrn); 393extern void intel_mode_remove_fb(intel_screen_private *intel); 394extern void intel_mode_close(intel_screen_private *intel); 395extern void intel_mode_fini(intel_screen_private *intel); 396 397extern int intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, xf86CrtcPtr crtc); 398extern int intel_crtc_id(xf86CrtcPtr crtc); 399extern int intel_output_dpms_status(xf86OutputPtr output); 400extern void intel_copy_fb(ScrnInfoPtr scrn); 401 402enum DRI2FrameEventType { 403 DRI2_SWAP, 404 DRI2_SWAP_CHAIN, 405 DRI2_FLIP, 406 DRI2_WAITMSC, 407}; 408 409#if XORG_VERSION_CURRENT <= XORG_VERSION_NUMERIC(1,7,99,3,0) 410typedef void (*DRI2SwapEventPtr)(ClientPtr client, void *data, int type, 411 CARD64 ust, CARD64 msc, CARD64 sbc); 412#endif 413 414typedef struct _DRI2FrameEvent { 415 struct intel_screen_private *intel; 416 417 XID drawable_id; 418 ClientPtr client; 419 enum DRI2FrameEventType type; 420 int frame; 421 int pipe; 422 423 struct list drawable_resource, client_resource; 424 425 /* for swaps & flips only */ 426 DRI2SwapEventPtr event_complete; 427 void *event_data; 428 DRI2BufferPtr front; 429 DRI2BufferPtr back; 430 431 struct _DRI2FrameEvent *chain; 432} DRI2FrameEventRec, *DRI2FrameEventPtr; 433 434extern Bool intel_do_pageflip(intel_screen_private *intel, 435 dri_bo *new_front, 436 DRI2FrameEventPtr flip_info, int ref_crtc_hw_id); 437 438static inline intel_screen_private * 439intel_get_screen_private(ScrnInfoPtr scrn) 440{ 441 return (intel_screen_private *)(scrn->driverPrivate); 442} 443 444#ifndef ARRAY_SIZE 445#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) 446#endif 447 448#ifndef ALIGN 449#define ALIGN(i,m) (((i) + (m) - 1) & ~((m) - 1)) 450#endif 451 452#ifndef MIN 453#define MIN(a,b) ((a) < (b) ? (a) : (b)) 454#endif 455 456static inline unsigned long intel_pixmap_pitch(PixmapPtr pixmap) 457{ 458 return (unsigned long)pixmap->devKind; 459} 460 461/* Batchbuffer support macros and functions */ 462#include "intel_batchbuffer.h" 463 464/* I830 specific functions */ 465extern void IntelEmitInvarientState(ScrnInfoPtr scrn); 466extern void I830EmitInvarientState(ScrnInfoPtr scrn); 467extern void I915EmitInvarientState(ScrnInfoPtr scrn); 468 469extern void I830EmitFlush(ScrnInfoPtr scrn); 470 471extern void I830InitVideo(ScreenPtr pScreen); 472extern xf86CrtcPtr intel_covering_crtc(ScrnInfoPtr scrn, BoxPtr box, 473 xf86CrtcPtr desired, BoxPtr crtc_box_ret); 474 475Bool I830DRI2ScreenInit(ScreenPtr pScreen); 476void I830DRI2CloseScreen(ScreenPtr pScreen); 477void I830DRI2FrameEventHandler(unsigned int frame, unsigned int tv_sec, 478 unsigned int tv_usec, DRI2FrameEventPtr flip_info); 479void I830DRI2FlipEventHandler(unsigned int frame, unsigned int tv_sec, 480 unsigned int tv_usec, DRI2FrameEventPtr flip_info); 481 482extern Bool intel_crtc_on(xf86CrtcPtr crtc); 483int intel_crtc_to_pipe(xf86CrtcPtr crtc); 484 485/* intel_memory.c */ 486unsigned long intel_get_fence_size(intel_screen_private *intel, unsigned long size); 487unsigned long intel_get_fence_pitch(intel_screen_private *intel, unsigned long pitch, 488 uint32_t tiling_mode); 489 490drm_intel_bo *intel_allocate_framebuffer(ScrnInfoPtr scrn, 491 int w, int h, int cpp, 492 unsigned long *pitch, 493 uint32_t *tiling); 494 495/* i830_render.c */ 496Bool i830_check_composite(int op, 497 PicturePtr sourcec, PicturePtr mask, PicturePtr dest, 498 int width, int height); 499Bool i830_check_composite_target(PixmapPtr pixmap); 500Bool i830_check_composite_texture(ScreenPtr screen, PicturePtr picture); 501Bool i830_prepare_composite(int op, PicturePtr sourcec, PicturePtr mask, 502 PicturePtr dest, PixmapPtr sourcecPixmap, 503 PixmapPtr maskPixmap, PixmapPtr destPixmap); 504void i830_composite(PixmapPtr dest, int srcX, int srcY, 505 int maskX, int maskY, int dstX, int dstY, int w, int h); 506void i830_vertex_flush(intel_screen_private *intel); 507 508/* i915_render.c */ 509Bool i915_check_composite(int op, 510 PicturePtr sourcec, PicturePtr mask, PicturePtr dest, 511 int width, int height); 512Bool i915_check_composite_target(PixmapPtr pixmap); 513Bool i915_check_composite_texture(ScreenPtr screen, PicturePtr picture); 514Bool i915_prepare_composite(int op, PicturePtr sourcec, PicturePtr mask, 515 PicturePtr dest, PixmapPtr sourcecPixmap, 516 PixmapPtr maskPixmap, PixmapPtr destPixmap); 517void i915_composite(PixmapPtr dest, int srcX, int srcY, 518 int maskX, int maskY, int dstX, int dstY, int w, int h); 519void i915_vertex_flush(intel_screen_private *intel); 520void i915_batch_commit_notify(intel_screen_private *intel); 521void i830_batch_commit_notify(intel_screen_private *intel); 522/* i965_render.c */ 523unsigned int gen4_render_state_size(ScrnInfoPtr scrn); 524void gen4_render_state_init(ScrnInfoPtr scrn); 525void gen4_render_state_cleanup(ScrnInfoPtr scrn); 526Bool i965_check_composite(int op, 527 PicturePtr sourcec, PicturePtr mask, PicturePtr dest, 528 int width, int height); 529Bool i965_check_composite_texture(ScreenPtr screen, PicturePtr picture); 530Bool i965_prepare_composite(int op, PicturePtr sourcec, PicturePtr mask, 531 PicturePtr dest, PixmapPtr sourcecPixmap, 532 PixmapPtr maskPixmap, PixmapPtr destPixmap); 533void i965_composite(PixmapPtr dest, int srcX, int srcY, 534 int maskX, int maskY, int dstX, int dstY, int w, int h); 535 536void i965_vertex_flush(intel_screen_private *intel); 537void i965_batch_flush(intel_screen_private *intel); 538void i965_batch_commit_notify(intel_screen_private *intel); 539 540/* i965_3d.c */ 541void gen6_upload_invariant_states(intel_screen_private *intel); 542void gen6_upload_viewport_state_pointers(intel_screen_private *intel, 543 drm_intel_bo *cc_vp_bo); 544void gen7_upload_viewport_state_pointers(intel_screen_private *intel, 545 drm_intel_bo *cc_vp_bo); 546void gen6_upload_urb(intel_screen_private *intel); 547void gen7_upload_urb(intel_screen_private *intel); 548void gen6_upload_cc_state_pointers(intel_screen_private *intel, 549 drm_intel_bo *blend_bo, drm_intel_bo *cc_bo, 550 drm_intel_bo *depth_stencil_bo, 551 uint32_t blend_offset); 552void gen7_upload_cc_state_pointers(intel_screen_private *intel, 553 drm_intel_bo *blend_bo, drm_intel_bo *cc_bo, 554 drm_intel_bo *depth_stencil_bo, 555 uint32_t blend_offset); 556void gen6_upload_sampler_state_pointers(intel_screen_private *intel, 557 drm_intel_bo *sampler_bo); 558void gen7_upload_sampler_state_pointers(intel_screen_private *intel, 559 drm_intel_bo *sampler_bo); 560void gen7_upload_bypass_states(intel_screen_private *intel); 561void gen6_upload_gs_state(intel_screen_private *intel); 562void gen6_upload_vs_state(intel_screen_private *intel); 563void gen6_upload_clip_state(intel_screen_private *intel); 564void gen6_upload_sf_state(intel_screen_private *intel, int num_sf_outputs, int read_offset); 565void gen7_upload_sf_state(intel_screen_private *intel, int num_sf_outputs, int read_offset); 566void gen6_upload_binding_table(intel_screen_private *intel, uint32_t ps_binding_table_offset); 567void gen7_upload_binding_table(intel_screen_private *intel, uint32_t ps_binding_table_offset); 568void gen6_upload_depth_buffer_state(intel_screen_private *intel); 569void gen7_upload_depth_buffer_state(intel_screen_private *intel); 570 571Bool intel_transform_is_affine(PictTransformPtr t); 572Bool 573intel_get_transformed_coordinates(int x, int y, PictTransformPtr transform, 574 float *x_out, float *y_out); 575 576Bool 577intel_get_transformed_coordinates_3d(int x, int y, PictTransformPtr transform, 578 float *x_out, float *y_out, float *z_out); 579 580static inline void 581intel_debug_fallback(ScrnInfoPtr scrn, const char *format, ...) _X_ATTRIBUTE_PRINTF(2, 3); 582 583static inline void 584intel_debug_fallback(ScrnInfoPtr scrn, const char *format, ...) 585{ 586 intel_screen_private *intel = intel_get_screen_private(scrn); 587 va_list ap; 588 589 va_start(ap, format); 590 if (intel->fallback_debug) { 591 xf86DrvMsg(scrn->scrnIndex, X_INFO, "fallback: "); 592 LogVMessageVerb(X_INFO, 1, format, ap); 593 } 594 va_end(ap); 595} 596 597static inline Bool 598intel_check_pitch_2d(PixmapPtr pixmap) 599{ 600 uint32_t pitch = intel_pixmap_pitch(pixmap); 601 if (pitch > KB(32)) { 602 ScrnInfoPtr scrn = xf86ScreenToScrn(pixmap->drawable.pScreen); 603 intel_debug_fallback(scrn, "pitch exceeds 2d limit 32K\n"); 604 return FALSE; 605 } 606 return TRUE; 607} 608 609/* For pre-965 chip only, as they have 8KB limit for 3D */ 610static inline Bool 611intel_check_pitch_3d(PixmapPtr pixmap) 612{ 613 uint32_t pitch = intel_pixmap_pitch(pixmap); 614 if (pitch > KB(8)) { 615 ScrnInfoPtr scrn = xf86ScreenToScrn(pixmap->drawable.pScreen); 616 intel_debug_fallback(scrn, "pitch exceeds 3d limit 8K\n"); 617 return FALSE; 618 } 619 return TRUE; 620} 621 622/** 623 * Little wrapper around drm_intel_bo_reloc to return the initial value you 624 * should stuff into the relocation entry. 625 * 626 * If only we'd done this before settling on the library API. 627 */ 628static inline uint32_t 629intel_emit_reloc(drm_intel_bo * bo, uint32_t offset, 630 drm_intel_bo * target_bo, uint32_t target_offset, 631 uint32_t read_domains, uint32_t write_domain) 632{ 633 drm_intel_bo_emit_reloc(bo, offset, target_bo, target_offset, 634 read_domains, write_domain); 635 636 return target_bo->offset + target_offset; 637} 638 639static inline drm_intel_bo *intel_bo_alloc_for_data(intel_screen_private *intel, 640 const void *data, 641 unsigned int size, 642 const char *name) 643{ 644 drm_intel_bo *bo; 645 int ret; 646 647 bo = drm_intel_bo_alloc(intel->bufmgr, name, size, 4096); 648 assert(bo); 649 650 ret = drm_intel_bo_subdata(bo, 0, size, data); 651 assert(ret == 0); 652 653 return bo; 654 (void)ret; 655} 656 657void intel_debug_flush(ScrnInfoPtr scrn); 658 659static inline PixmapPtr get_drawable_pixmap(DrawablePtr drawable) 660{ 661 ScreenPtr screen = drawable->pScreen; 662 663 if (drawable->type == DRAWABLE_PIXMAP) 664 return (PixmapPtr) drawable; 665 else 666 return screen->GetWindowPixmap((WindowPtr) drawable); 667} 668 669static inline Bool pixmap_is_scanout(PixmapPtr pixmap) 670{ 671 ScreenPtr screen = pixmap->drawable.pScreen; 672 673 return pixmap == screen->GetScreenPixmap(screen); 674} 675 676Bool intel_uxa_init(ScreenPtr pScreen); 677Bool intel_uxa_create_screen_resources(ScreenPtr pScreen); 678void intel_uxa_block_handler(intel_screen_private *intel); 679Bool intel_get_aperture_space(ScrnInfoPtr scrn, drm_intel_bo ** bo_table, 680 int num_bos); 681 682static inline Bool intel_pixmap_is_offscreen(PixmapPtr pixmap) 683{ 684 struct intel_pixmap *priv = intel_get_pixmap_private(pixmap); 685 return priv && priv->offscreen; 686} 687 688#endif /* _I830_H_ */ 689