1fe5e51b7Smrg#ifndef _MGA_MACROS_H_ 2fe5e51b7Smrg#define _MGA_MACROS_H_ 3fe5e51b7Smrg 4fe5e51b7Smrg#ifdef XSERVER_LIBPCIACCESS 5fe5e51b7Smrg#define MGA_IO_ADDRESS(p) (p)->PciInfo->regions[(p)->io_bar].base_addr 6fe5e51b7Smrg#define VENDOR_ID(p) (p)->vendor_id 7fe5e51b7Smrg#define DEVICE_ID(p) (p)->device_id 8fe5e51b7Smrg#define SUBSYS_ID(p) (p)->subdevice_id 9fe5e51b7Smrg#define CHIP_REVISION(p) (p)->revision 10fe5e51b7Smrg#else 11fe5e51b7Smrg#define MGA_IO_ADDRESS(p) (p)->IOAddress 12fe5e51b7Smrg#define VENDOR_ID(p) (p)->vendor 13fe5e51b7Smrg#define DEVICE_ID(p) (p)->chipType 14fe5e51b7Smrg#define SUBSYS_ID(p) (p)->subsysCard 15fe5e51b7Smrg#define CHIP_REVISION(p) (p)->chipRev 16fe5e51b7Smrg#endif 17fe5e51b7Smrg 18fe5e51b7Smrg#define RGBEQUAL(c) (!((((c) >> 8) ^ (c)) & 0xffff)) 19fe5e51b7Smrg 200bb88ba4Smrg#ifdef MGADRI 21fe5e51b7Smrg#define MGA_SYNC_XTAG 0x275f4200 22fe5e51b7Smrg 23fe5e51b7Smrg#define MGABUSYWAIT() do { \ 24fe5e51b7SmrgOUTREG(MGAREG_DWGSYNC, MGA_SYNC_XTAG); \ 25fe5e51b7Smrgwhile(INREG(MGAREG_DWGSYNC) != MGA_SYNC_XTAG) ; \ 26fe5e51b7Smrg}while(0); 27fe5e51b7Smrg 28fe5e51b7Smrg#endif 29fe5e51b7Smrg 30fe5e51b7Smrg#define MGAISBUSY() (INREG8(MGAREG_Status + 2) & 0x01) 31fe5e51b7Smrg 32fe5e51b7Smrg#define WAITFIFO(cnt) \ 33fe5e51b7Smrg if(!pMga->UsePCIRetry) {\ 34fe5e51b7Smrg register int n = cnt; \ 35fe5e51b7Smrg if(n > pMga->FifoSize) n = pMga->FifoSize; \ 36fe5e51b7Smrg while(pMga->fifoCount < (n))\ 37fe5e51b7Smrg pMga->fifoCount = INREG8(MGAREG_FIFOSTATUS);\ 38fe5e51b7Smrg pMga->fifoCount -= n;\ 39fe5e51b7Smrg } 40fe5e51b7Smrg 41fe5e51b7Smrg#define XYADDRESS(x,y) \ 42fe5e51b7Smrg ((y) * pMga->CurrentLayout.displayWidth + (x) + pMga->YDstOrg) 43fe5e51b7Smrg 44fe5e51b7Smrg#define MAKEDMAINDEX(index) ((((index) >> 2) & 0x7f) | (((index) >> 6) & 0x80)) 45fe5e51b7Smrg 46fe5e51b7Smrg#define DMAINDICES(one,two,three,four) \ 47fe5e51b7Smrg ( MAKEDMAINDEX(one) | \ 48fe5e51b7Smrg (MAKEDMAINDEX(two) << 8) | \ 49fe5e51b7Smrg (MAKEDMAINDEX(three) << 16) | \ 50fe5e51b7Smrg (MAKEDMAINDEX(four) << 24) ) 51fe5e51b7Smrg 52fe5e51b7Smrg#define SET_PLANEMASK_REPLICATED(mask, rep_mask, bpp) \ 53fe5e51b7Smrg do { \ 54fe5e51b7Smrg if( (bpp != 24) \ 55fe5e51b7Smrg && !(pMga->AccelFlags & MGA_NO_PLANEMASK) \ 56fe5e51b7Smrg && ((mask) != pMga->PlaneMask)) { \ 57fe5e51b7Smrg pMga->PlaneMask = (mask); \ 58fe5e51b7Smrg OUTREG(MGAREG_PLNWT,(rep_mask)); \ 59fe5e51b7Smrg } \ 60fe5e51b7Smrg } while( 0 ) 61fe5e51b7Smrg 62fe5e51b7Smrg#define DISABLE_CLIP() { \ 63fe5e51b7Smrg pMga->AccelFlags &= ~CLIPPER_ON; \ 64fe5e51b7Smrg WAITFIFO(1); \ 65fe5e51b7Smrg OUTREG(MGAREG_CXBNDRY, 0xFFFF0000); } 66fe5e51b7Smrg 670bb88ba4Smrg#ifdef MGADRI 68fe5e51b7Smrg#define CHECK_DMA_QUIESCENT(pMGA, pScrn) { \ 69fe5e51b7Smrg if (!pMGA->haveQuiescense) { \ 70fe5e51b7Smrg pMGA->GetQuiescence( pScrn ); \ 71fe5e51b7Smrg } \ 72fe5e51b7Smrg} 73fe5e51b7Smrg#else 74fe5e51b7Smrg#define CHECK_DMA_QUIESCENT(pMGA, pScrn) 75fe5e51b7Smrg#endif 76fe5e51b7Smrg 77fe5e51b7Smrg#define MGA_NOT_HAL(x) { x; } 78fe5e51b7Smrg 79fe5e51b7Smrg#define MGAISGx50(x) ((x)->is_Gx50) 80fe5e51b7Smrg 81fe5e51b7Smrg#define MGA_DH_NEEDS_HAL(x) (((x)->Chipset == PCI_CHIP_MGAG400) && \ 82fe5e51b7Smrg ((x)->ChipRev < 0x80)) 83fe5e51b7Smrg 84fe5e51b7Smrg#endif /* _MGA_MACROS_H_ */ 85