1fe5e51b7Smrg/*
2fe5e51b7Smrg * Copyright 2000 Gareth Hughes
3fe5e51b7Smrg * All Rights Reserved.
4fe5e51b7Smrg *
5fe5e51b7Smrg * Permission is hereby granted, free of charge, to any person obtaining a
6fe5e51b7Smrg * copy of this software and associated documentation files (the "Software"),
7fe5e51b7Smrg * to deal in the Software without restriction, including without limitation
8fe5e51b7Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9fe5e51b7Smrg * and/or sell copies of the Software, and to permit persons to whom the
10fe5e51b7Smrg * Software is furnished to do so, subject to the following conditions:
11fe5e51b7Smrg *
12fe5e51b7Smrg * The above copyright notice and this permission notice (including the next
13fe5e51b7Smrg * paragraph) shall be included in all copies or substantial portions of the
14fe5e51b7Smrg * Software.
15fe5e51b7Smrg *
16fe5e51b7Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17fe5e51b7Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18fe5e51b7Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19fe5e51b7Smrg * GARETH HUGHES BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
20fe5e51b7Smrg * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21fe5e51b7Smrg * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22fe5e51b7Smrg *
23fe5e51b7Smrg * Authors:
24fe5e51b7Smrg *   Gareth Hughes <gareth@valinux.com>
25fe5e51b7Smrg */
26fe5e51b7Smrg
27fe5e51b7Smrg#ifndef __MGA_SAREA_H__
28fe5e51b7Smrg#define __MGA_SAREA_H__
29fe5e51b7Smrg
30fe5e51b7Smrg/* WARNING: If you change any of these defines, make sure to change
31fe5e51b7Smrg * the kernel include file as well (mga_drm.h)
32fe5e51b7Smrg */
33fe5e51b7Smrg#ifndef __MGA_SAREA_DEFINES__
34fe5e51b7Smrg#define __MGA_SAREA_DEFINES__
35fe5e51b7Smrg
36fe5e51b7Smrg/* WARP pipe flags
37fe5e51b7Smrg */
38fe5e51b7Smrg#define MGA_F			0x1		/* fog */
39fe5e51b7Smrg#define MGA_A			0x2		/* alpha */
40fe5e51b7Smrg#define MGA_S			0x4		/* specular */
41fe5e51b7Smrg#define MGA_T2			0x8		/* multitexture */
42fe5e51b7Smrg
43fe5e51b7Smrg#define MGA_WARP_TGZ		0
44fe5e51b7Smrg#define MGA_WARP_TGZF		(MGA_F)
45fe5e51b7Smrg#define MGA_WARP_TGZA		(MGA_A)
46fe5e51b7Smrg#define MGA_WARP_TGZAF		(MGA_F|MGA_A)
47fe5e51b7Smrg#define MGA_WARP_TGZS		(MGA_S)
48fe5e51b7Smrg#define MGA_WARP_TGZSF		(MGA_S|MGA_F)
49fe5e51b7Smrg#define MGA_WARP_TGZSA		(MGA_S|MGA_A)
50fe5e51b7Smrg#define MGA_WARP_TGZSAF		(MGA_S|MGA_F|MGA_A)
51fe5e51b7Smrg#define MGA_WARP_T2GZ		(MGA_T2)
52fe5e51b7Smrg#define MGA_WARP_T2GZF		(MGA_T2|MGA_F)
53fe5e51b7Smrg#define MGA_WARP_T2GZA		(MGA_T2|MGA_A)
54fe5e51b7Smrg#define MGA_WARP_T2GZAF		(MGA_T2|MGA_A|MGA_F)
55fe5e51b7Smrg#define MGA_WARP_T2GZS		(MGA_T2|MGA_S)
56fe5e51b7Smrg#define MGA_WARP_T2GZSF		(MGA_T2|MGA_S|MGA_F)
57fe5e51b7Smrg#define MGA_WARP_T2GZSA		(MGA_T2|MGA_S|MGA_A)
58fe5e51b7Smrg#define MGA_WARP_T2GZSAF	(MGA_T2|MGA_S|MGA_F|MGA_A)
59fe5e51b7Smrg
60fe5e51b7Smrg#define MGA_MAX_G200_PIPES	8		/* no multitex */
61fe5e51b7Smrg#define MGA_MAX_G400_PIPES	16
62fe5e51b7Smrg#define MGA_MAX_WARP_PIPES	MGA_MAX_G400_PIPES
63fe5e51b7Smrg#define MGA_WARP_UCODE_SIZE	32768		/* in bytes */
64fe5e51b7Smrg
65fe5e51b7Smrg#define MGA_CARD_TYPE_G200	1
66fe5e51b7Smrg#define MGA_CARD_TYPE_G400	2
67fe5e51b7Smrg
68fe5e51b7Smrg
69fe5e51b7Smrg#define MGA_FRONT		0x1
70fe5e51b7Smrg#define MGA_BACK		0x2
71fe5e51b7Smrg#define MGA_DEPTH		0x4
72fe5e51b7Smrg
73fe5e51b7Smrg/* What needs to be changed for the current vertex dma buffer?
74fe5e51b7Smrg */
75fe5e51b7Smrg#define MGA_UPLOAD_CONTEXT	0x1
76fe5e51b7Smrg#define MGA_UPLOAD_TEX0		0x2
77fe5e51b7Smrg#define MGA_UPLOAD_TEX1		0x4
78fe5e51b7Smrg#define MGA_UPLOAD_PIPE		0x8
79fe5e51b7Smrg#define MGA_UPLOAD_TEX0IMAGE	0x10
80fe5e51b7Smrg#define MGA_UPLOAD_TEX1IMAGE	0x20
81fe5e51b7Smrg#define MGA_UPLOAD_2D		0x40
82fe5e51b7Smrg#define MGA_WAIT_AGE		0x80 /* handled client-side */
83fe5e51b7Smrg#define MGA_UPLOAD_CLIPRECTS	0x100 /* handled client-side */
84fe5e51b7Smrg#if 0
85fe5e51b7Smrg#define MGA_DMA_FLUSH		0x200 /* set when someone gets the lock
86fe5e51b7Smrg					 quiescent */
87fe5e51b7Smrg#endif
88fe5e51b7Smrg
89fe5e51b7Smrg/* 32 buffers of 64k each, total 1 meg.
90fe5e51b7Smrg */
91fe5e51b7Smrg#define MGA_BUFFER_SIZE		(1 << 16)
92fe5e51b7Smrg#define MGA_NUM_BUFFERS		128
93fe5e51b7Smrg
94fe5e51b7Smrg/* Keep these small for testing.
95fe5e51b7Smrg */
96fe5e51b7Smrg#define MGA_NR_SAREA_CLIPRECTS	8
97fe5e51b7Smrg
981e423a8fSmrg/* 2 heaps (1 for card, 1 for agp), each divided into up to 128
99fe5e51b7Smrg * regions, subject to a minimum region size of (1<<16) == 64k.
100fe5e51b7Smrg *
101fe5e51b7Smrg * Clients may subdivide regions internally, but when sharing between
102fe5e51b7Smrg * clients, the region size is the minimum granularity.
103fe5e51b7Smrg */
104fe5e51b7Smrg
105fe5e51b7Smrg#define MGA_CARD_HEAP			0
106fe5e51b7Smrg#define MGA_AGP_HEAP			1
107fe5e51b7Smrg#define MGA_NR_TEX_HEAPS		2
108fe5e51b7Smrg#define MGA_NR_TEX_REGIONS		16
109fe5e51b7Smrg#define MGA_LOG_MIN_TEX_REGION_SIZE	16
110fe5e51b7Smrg
111fe5e51b7Smrg#endif /* __MGA_SAREA_DEFINES__ */
112fe5e51b7Smrg
113fe5e51b7Smrg
114fe5e51b7Smrg/* Setup registers for 3D context
115fe5e51b7Smrg */
116fe5e51b7Smrgtypedef struct {
117fe5e51b7Smrg   unsigned int dstorg;
118fe5e51b7Smrg   unsigned int maccess;
119fe5e51b7Smrg   unsigned int plnwt;
120fe5e51b7Smrg   unsigned int dwgctl;
121fe5e51b7Smrg   unsigned int alphactrl;
122fe5e51b7Smrg   unsigned int fogcolor;
123fe5e51b7Smrg   unsigned int wflag;
124fe5e51b7Smrg   unsigned int tdualstage0;
125fe5e51b7Smrg   unsigned int tdualstage1;
126fe5e51b7Smrg   unsigned int fcol;
127fe5e51b7Smrg   unsigned int stencil;
128fe5e51b7Smrg   unsigned int stencilctl;
129fe5e51b7Smrg} mga_context_regs_t;
130fe5e51b7Smrg
131fe5e51b7Smrg/* Setup registers for 2D, X server
132fe5e51b7Smrg */
133fe5e51b7Smrgtypedef struct {
134fe5e51b7Smrg   unsigned int pitch;
135fe5e51b7Smrg} mga_server_regs_t;
136fe5e51b7Smrg
137fe5e51b7Smrg/* Setup registers for each texture unit
138fe5e51b7Smrg */
139fe5e51b7Smrgtypedef struct {
140fe5e51b7Smrg   unsigned int texctl;
141fe5e51b7Smrg   unsigned int texctl2;
142fe5e51b7Smrg   unsigned int texfilter;
143fe5e51b7Smrg   unsigned int texbordercol;
144fe5e51b7Smrg   unsigned int texorg;
145fe5e51b7Smrg   unsigned int texwidth;
146fe5e51b7Smrg   unsigned int texheight;
147fe5e51b7Smrg   unsigned int texorg1;
148fe5e51b7Smrg   unsigned int texorg2;
149fe5e51b7Smrg   unsigned int texorg3;
150fe5e51b7Smrg   unsigned int texorg4;
151fe5e51b7Smrg} mga_texture_regs_t;
152fe5e51b7Smrg
153fe5e51b7Smrg/* General ageing mechanism
154fe5e51b7Smrg */
155fe5e51b7Smrgtypedef struct {
156fe5e51b7Smrg	unsigned int head;		/* Position of head pointer          */
157fe5e51b7Smrg	unsigned int wrap;		/* Primary DMA wrap count            */
158fe5e51b7Smrg} mga_age_t;
159fe5e51b7Smrg
160fe5e51b7Smrg
161fe5e51b7Smrg/* WARNING: Do not change the SAREA structure without changing the kernel
162fe5e51b7Smrg * as well.
163fe5e51b7Smrg */
164fe5e51b7Smrgtypedef struct {
165fe5e51b7Smrg   /* The channel for communication of state information to the kernel
166fe5e51b7Smrg    * on firing a vertex dma buffer.
167fe5e51b7Smrg    */
168fe5e51b7Smrg   mga_context_regs_t ContextState;
169fe5e51b7Smrg   mga_server_regs_t ServerState;
170fe5e51b7Smrg   mga_texture_regs_t TexState[2];
171fe5e51b7Smrg   unsigned int WarpPipe;
172fe5e51b7Smrg   unsigned int dirty;
173fe5e51b7Smrg   unsigned int vertsize;
174fe5e51b7Smrg
175fe5e51b7Smrg   /* The current cliprects, or a subset thereof.
176fe5e51b7Smrg    */
177fe5e51b7Smrg   drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS];
178fe5e51b7Smrg   unsigned int nbox;
179fe5e51b7Smrg
180fe5e51b7Smrg   /* Information about the most recently used 3d drawable.  The
181fe5e51b7Smrg    * client fills in the req_* fields, the server fills in the
182fe5e51b7Smrg    * exported_ fields and puts the cliprects into boxes, above.
183fe5e51b7Smrg    *
184fe5e51b7Smrg    * The client clears the exported_drawable field before
185fe5e51b7Smrg    * clobbering the boxes data.
186fe5e51b7Smrg    */
187fe5e51b7Smrg   unsigned int req_drawable;       /* the X drawable id */
188fe5e51b7Smrg   unsigned int req_draw_buffer;    /* MGA_FRONT or MGA_BACK */
189fe5e51b7Smrg
190fe5e51b7Smrg   unsigned int exported_drawable;
191fe5e51b7Smrg   unsigned int exported_index;
192fe5e51b7Smrg   unsigned int exported_stamp;
193fe5e51b7Smrg   unsigned int exported_buffers;
194fe5e51b7Smrg   unsigned int exported_nfront;	/* FIXME: verify signedness... */
195fe5e51b7Smrg   unsigned int exported_nback;
196fe5e51b7Smrg   int exported_back_x, exported_front_x, exported_w;
197fe5e51b7Smrg   int exported_back_y, exported_front_y, exported_h;
198fe5e51b7Smrg   drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS];
199fe5e51b7Smrg
200fe5e51b7Smrg   /* Counters for aging textures and for client-side throttling.
201fe5e51b7Smrg    */
202fe5e51b7Smrg   unsigned int status[4];
203fe5e51b7Smrg   unsigned int last_wrap;
204fe5e51b7Smrg
205fe5e51b7Smrg   mga_age_t last_frame;
206fe5e51b7Smrg   unsigned int last_enqueue;       /* last time a buffer was enqueued */
207fe5e51b7Smrg   unsigned int last_dispatch;      /* age of the most recently dispatched buffer */
208fe5e51b7Smrg   unsigned int last_quiescent;     /*  */
209fe5e51b7Smrg
210fe5e51b7Smrg   /* LRU lists for texture memory in agp space and on the card.
211fe5e51b7Smrg    */
212fe5e51b7Smrg   drmTextureRegion texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS+1];
213fe5e51b7Smrg   unsigned int texAge[MGA_NR_TEX_HEAPS];
214fe5e51b7Smrg
215fe5e51b7Smrg   /* Last context that uploaded statel
216fe5e51b7Smrg    */
217fe5e51b7Smrg   int ctxOwner;
218fe5e51b7Smrg} MGASAREAPrivRec, *MGASAREAPrivPtr;
219fe5e51b7Smrg
220fe5e51b7Smrg#endif
221