171d7fec4Smrg/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nsc/gfx/vid_1200.c,v 1.2 2003/01/14 09:34:34 alanh Exp $ */
271d7fec4Smrg/*
371d7fec4Smrg * $Workfile: vid_1200.c $
471d7fec4Smrg *
571d7fec4Smrg * This file contains routines to control the SC1200 video overlay hardware.
671d7fec4Smrg *
771d7fec4Smrg * NSC_LIC_ALTERNATIVE_PREAMBLE
871d7fec4Smrg *
971d7fec4Smrg * Revision 1.0
1071d7fec4Smrg *
1171d7fec4Smrg * National Semiconductor Alternative GPL-BSD License
1271d7fec4Smrg *
1371d7fec4Smrg * National Semiconductor Corporation licenses this software
1471d7fec4Smrg * ("Software"):
1571d7fec4Smrg *
1671d7fec4Smrg *      Durango
1771d7fec4Smrg *
1871d7fec4Smrg * under one of the two following licenses, depending on how the
1971d7fec4Smrg * Software is received by the Licensee.
2071d7fec4Smrg *
2171d7fec4Smrg * If this Software is received as part of the Linux Framebuffer or
2271d7fec4Smrg * other GPL licensed software, then the GPL license designated
2371d7fec4Smrg * NSC_LIC_GPL applies to this Software; in all other circumstances
2471d7fec4Smrg * then the BSD-style license designated NSC_LIC_BSD shall apply.
2571d7fec4Smrg *
2671d7fec4Smrg * END_NSC_LIC_ALTERNATIVE_PREAMBLE */
2771d7fec4Smrg
2871d7fec4Smrg/* NSC_LIC_BSD
2971d7fec4Smrg *
3071d7fec4Smrg * National Semiconductor Corporation Open Source License for Durango
3171d7fec4Smrg *
3271d7fec4Smrg * (BSD License with Export Notice)
3371d7fec4Smrg *
3471d7fec4Smrg * Copyright (c) 1999-2001
3571d7fec4Smrg * National Semiconductor Corporation.
3671d7fec4Smrg * All rights reserved.
3771d7fec4Smrg *
3871d7fec4Smrg * Redistribution and use in source and binary forms, with or without
3971d7fec4Smrg * modification, are permitted provided that the following conditions
4071d7fec4Smrg * are met:
4171d7fec4Smrg *
4271d7fec4Smrg *   * Redistributions of source code must retain the above copyright
4371d7fec4Smrg *     notice, this list of conditions and the following disclaimer.
4471d7fec4Smrg *
4571d7fec4Smrg *   * Redistributions in binary form must reproduce the above
4671d7fec4Smrg *     copyright notice, this list of conditions and the following
4771d7fec4Smrg *     disclaimer in the documentation and/or other materials provided
4871d7fec4Smrg *     with the distribution.
4971d7fec4Smrg *
5071d7fec4Smrg *   * Neither the name of the National Semiconductor Corporation nor
5171d7fec4Smrg *     the names of its contributors may be used to endorse or promote
5271d7fec4Smrg *     products derived from this software without specific prior
5371d7fec4Smrg *     written permission.
5471d7fec4Smrg *
5571d7fec4Smrg * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
5671d7fec4Smrg * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
5771d7fec4Smrg * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
5871d7fec4Smrg * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
5971d7fec4Smrg * NATIONAL SEMICONDUCTOR CORPORATION OR CONTRIBUTORS BE LIABLE FOR ANY
6071d7fec4Smrg * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
6171d7fec4Smrg * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
6271d7fec4Smrg * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
6371d7fec4Smrg * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
6471d7fec4Smrg * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE,
6571d7fec4Smrg * INTELLECTUAL PROPERTY INFRINGEMENT, OR OTHERWISE) ARISING IN ANY WAY
6671d7fec4Smrg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
6771d7fec4Smrg * OF SUCH DAMAGE.
6871d7fec4Smrg *
6971d7fec4Smrg * EXPORT LAWS: THIS LICENSE ADDS NO RESTRICTIONS TO THE EXPORT LAWS OF
7071d7fec4Smrg * YOUR JURISDICTION. It is licensee's responsibility to comply with
7171d7fec4Smrg * any export regulations applicable in licensee's jurisdiction. Under
7271d7fec4Smrg * CURRENT (2001) U.S. export regulations this software
7371d7fec4Smrg * is eligible for export from the U.S. and can be downloaded by or
7471d7fec4Smrg * otherwise exported or reexported worldwide EXCEPT to U.S. embargoed
7571d7fec4Smrg * destinations which include Cuba, Iraq, Libya, North Korea, Iran,
7671d7fec4Smrg * Syria, Sudan, Afghanistan and any other country to which the U.S.
7771d7fec4Smrg * has embargoed goods and services.
7871d7fec4Smrg *
7971d7fec4Smrg * END_NSC_LIC_BSD */
8071d7fec4Smrg
8171d7fec4Smrg/* NSC_LIC_GPL
8271d7fec4Smrg *
8371d7fec4Smrg * National Semiconductor Corporation Gnu General Public License for Durango
8471d7fec4Smrg *
8571d7fec4Smrg * (GPL License with Export Notice)
8671d7fec4Smrg *
8771d7fec4Smrg * Copyright (c) 1999-2001
8871d7fec4Smrg * National Semiconductor Corporation.
8971d7fec4Smrg * All rights reserved.
9071d7fec4Smrg *
9171d7fec4Smrg * Redistribution and use in source and binary forms, with or without
9271d7fec4Smrg * modification, are permitted under the terms of the GNU General
9371d7fec4Smrg * Public License as published by the Free Software Foundation; either
9471d7fec4Smrg * version 2 of the License, or (at your option) any later version
9571d7fec4Smrg *
9671d7fec4Smrg * In addition to the terms of the GNU General Public License, neither
9771d7fec4Smrg * the name of the National Semiconductor Corporation nor the names of
9871d7fec4Smrg * its contributors may be used to endorse or promote products derived
9971d7fec4Smrg * from this software without specific prior written permission.
10071d7fec4Smrg *
10171d7fec4Smrg * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
10271d7fec4Smrg * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
10371d7fec4Smrg * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
10471d7fec4Smrg * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
10571d7fec4Smrg * NATIONAL SEMICONDUCTOR CORPORATION OR CONTRIBUTORS BE LIABLE FOR ANY
10671d7fec4Smrg * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
10771d7fec4Smrg * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
10871d7fec4Smrg * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
10971d7fec4Smrg * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
11071d7fec4Smrg * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE,
11171d7fec4Smrg * INTELLECTUAL PROPERTY INFRINGEMENT, OR OTHERWISE) ARISING IN ANY WAY
11271d7fec4Smrg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
11371d7fec4Smrg * OF SUCH DAMAGE. See the GNU General Public License for more details.
11471d7fec4Smrg *
11571d7fec4Smrg * EXPORT LAWS: THIS LICENSE ADDS NO RESTRICTIONS TO THE EXPORT LAWS OF
11671d7fec4Smrg * YOUR JURISDICTION. It is licensee's responsibility to comply with
11771d7fec4Smrg * any export regulations applicable in licensee's jurisdiction. Under
11871d7fec4Smrg * CURRENT (2001) U.S. export regulations this software
11971d7fec4Smrg * is eligible for export from the U.S. and can be downloaded by or
12071d7fec4Smrg * otherwise exported or reexported worldwide EXCEPT to U.S. embargoed
12171d7fec4Smrg * destinations which include Cuba, Iraq, Libya, North Korea, Iran,
12271d7fec4Smrg * Syria, Sudan, Afghanistan and any other country to which the U.S.
12371d7fec4Smrg * has embargoed goods and services.
12471d7fec4Smrg *
12571d7fec4Smrg * You should have received a copy of the GNU General Public License
12671d7fec4Smrg * along with this file; if not, write to the Free Software Foundation,
12771d7fec4Smrg * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
12871d7fec4Smrg *
12971d7fec4Smrg * END_NSC_LIC_GPL */
13071d7fec4Smrg
13171d7fec4Smrg/*----------------------------------------------------------------------------
13271d7fec4Smrg * SC1200 PLL TABLE
13371d7fec4Smrg *----------------------------------------------------------------------------
13471d7fec4Smrg */
13571d7fec4Smrg
13671d7fec4Smrgtypedef struct tagSC1200PLL
13771d7fec4Smrg{
13871d7fec4Smrg   long frequency;			/* 16.16 fixed point frequency */
13971d7fec4Smrg   unsigned long clock_select;		/* clock select register (0x2C) */
14071d7fec4Smrg}
14171d7fec4SmrgSC1200PLL;
14271d7fec4Smrg
14371d7fec4SmrgSC1200PLL gfx_sc1200_clock_table[] = {
14471d7fec4Smrg   {(25L << 16) | ((1750L * 65536L) / 10000L), 0x0070E00C},	/* 25.1750 (sc=24.9231) */
14571d7fec4Smrg   {(27L << 16) | ((0000L * 65536L) / 10000L), 0x00300100},	/* 27.0000 */
14671d7fec4Smrg   {(28L << 16) | ((3220L * 65536L) / 10000L), 0x0070EC0C},	/* 28.3220 (SC=27.000) */
14771d7fec4Smrg   {(31L << 16) | ((5000L * 65536L) / 10000L), 0x00500D02},	/* 31.5000 */
14871d7fec4Smrg   {(36L << 16) | ((0000L * 65536L) / 10000L), 0x00500F02},	/* 36.0000 */
14971d7fec4Smrg   {(37L << 16) | ((5000L * 65536L) / 10000L), 0x0050B108},	/* 37.5000 */
15071d7fec4Smrg   {(40L << 16) | ((0000L * 65536L) / 10000L), 0x0050D20D},	/* 40.0000 */
15171d7fec4Smrg   {(44L << 16) | ((9000L * 65536L) / 10000L), 0x0050DC0D},	/* 44.9000 */
15271d7fec4Smrg   {(49L << 16) | ((5000L * 65536L) / 10000L), 0x00501502},	/* 49.5000 */
15371d7fec4Smrg   {(50L << 16) | ((0000L * 65536L) / 10000L), 0x0050A404},	/* 50.0000 */
15471d7fec4Smrg   {(50L << 16) | ((3500L * 65536L) / 10000L), 0x0050E00C},	/* 50.3500 */
15571d7fec4Smrg   {(54L << 16) | ((0000L * 65536L) / 10000L), 0x00300300},	/* 54.0000 */
15671d7fec4Smrg   {(56L << 16) | ((3916L * 65536L) / 10000L), 0x0050F40D},	/* 56.3916 */
15771d7fec4Smrg   {(56L << 16) | ((6440L * 65536L) / 10000L), 0x0050EC0C},	/* 56.6440 */
15871d7fec4Smrg   {(59L << 16) | ((0000L * 65536L) / 10000L), 0x0030A207},	/* 59.0000 */
15971d7fec4Smrg   {(63L << 16) | ((0000L * 65536L) / 10000L), 0x00300D02},	/* 63.0000 */
16071d7fec4Smrg   {(65L << 16) | ((0000L * 65536L) / 10000L), 0x0030CC0F},	/* 65.0000 */
16171d7fec4Smrg   {(67L << 16) | ((5000L * 65536L) / 10000L), 0x00300400},	/* 67.5000 */
16271d7fec4Smrg   {(70L << 16) | ((8000L * 65536L) / 10000L), 0x00301403},	/* 70.8000 */
16371d7fec4Smrg   {(72L << 16) | ((0000L * 65536L) / 10000L), 0x00300F02},	/* 72.0000 */
16471d7fec4Smrg   {(75L << 16) | ((0000L * 65536L) / 10000L), 0x0030B108},	/* 75.0000 */
16571d7fec4Smrg   {(78L << 16) | ((7500L * 65536L) / 10000L), 0x0030A205},	/* 78.7500 */
16671d7fec4Smrg   {(80L << 16) | ((0000L * 65536L) / 10000L), 0x0030D20D},	/* 80.0000 */
16771d7fec4Smrg   {(87L << 16) | ((2728L * 65536L) / 10000L), 0x0030E00E},	/* 87.2728 */
16871d7fec4Smrg   {(89L << 16) | ((8000L * 65536L) / 10000L), 0x0030DC0D},	/* 89.8000 */
16971d7fec4Smrg   {(94L << 16) | ((5000L * 65536L) / 10000L), 0x00300600},	/* 99.0000 */
17071d7fec4Smrg   {(99L << 16) | ((0000L * 65536L) / 10000L), 0x00301502},	/* 99.0000 */
17171d7fec4Smrg   {(100L << 16) | ((0000L * 65536L) / 10000L), 0x0030A404},	/* 100.00 */
17271d7fec4Smrg   {(108L << 16) | ((0000L * 65536L) / 10000L), 0x00100300},	/* 108.00 */
17371d7fec4Smrg   {(112L << 16) | ((5000L * 65536L) / 10000L), 0x00301802},	/* 108.00 */
17471d7fec4Smrg   {(130L << 16) | ((0000L * 65536L) / 10000L), 0x0010CC0F},	/* 130.00 */
17571d7fec4Smrg   {(135L << 16) | ((0000L * 65536L) / 10000L), 0x00100400},	/* 135.00 */
17671d7fec4Smrg   {(157L << 16) | ((5000L * 65536L) / 10000L), 0x0010A205},	/* 157.50 */
17771d7fec4Smrg   {(162L << 16) | ((0000L * 65536L) / 10000L), 0x00100500},	/* 162.00 */
17871d7fec4Smrg   {(175L << 16) | ((0000L * 65536L) / 10000L), 0x0010E00E},	/* 175.50 */
17971d7fec4Smrg   {(189L << 16) | ((0000L * 65536L) / 10000L), 0x00100600},	/* 189.00 */
18071d7fec4Smrg   {(202L << 16) | ((0000L * 65536L) / 10000L), 0x0010EF0E},	/* 202.50 */
18171d7fec4Smrg   {(232L << 16) | ((0000L * 65536L) / 10000L), 0x0010AA04},	/* 232.50 */
18271d7fec4Smrg
18371d7fec4Smrg   /* Precomputed inidces in the hardware */
18471d7fec4Smrg   {0x0018EC4D, 0x000F0000},		/*  24.923052 */
18571d7fec4Smrg   {0x00192CCC, 0x00000000},		/*  25.1750 */
18671d7fec4Smrg   {0x001B0000, 0x00300100},		/*  27.0000 */
18771d7fec4Smrg   {0x001F8000, 0x00010000},		/*  31.5000 */
18871d7fec4Smrg   {0x00240000, 0x00020000},		/*  36.0000 */
18971d7fec4Smrg   {0x00280000, 0x00030000},		/*  40.0000 */
19071d7fec4Smrg   {0x00318000, 0x00050000},		/*  49.5000 */
19171d7fec4Smrg   {0x00320000, 0x00040000},		/*  50.0000 */
19271d7fec4Smrg   {0x00384000, 0x00060000},		/*  56.2500 */
19371d7fec4Smrg   {0x00410000, 0x00080000},		/*  65.0000 */
19471d7fec4Smrg   {0x004E8000, 0x000A0000},		/*  78.5000 */
19571d7fec4Smrg   {0x005E8000, 0x000B0000},		/*  94.5000 */
19671d7fec4Smrg   {0x006C0000, 0x000C0000},		/* 108.0000 */
19771d7fec4Smrg   {0x00870000, 0x000D0000},		/* 135.0000 */
19871d7fec4Smrg};
19971d7fec4Smrg
20071d7fec4Smrg#define NUM_SC1200_FREQUENCIES sizeof(gfx_sc1200_clock_table)/sizeof(SC1200PLL)
20171d7fec4Smrg
20271d7fec4Smrgint sc1200_set_video_enable(int enable);
20371d7fec4Smrgint sc1200_set_video_format(unsigned long format);
20471d7fec4Smrgint sc1200_set_video_size(unsigned short width, unsigned short height);
20571d7fec4Smrgint sc1200_set_video_yuv_pitch(unsigned long ypitch, unsigned long uvpitch);
20671d7fec4Smrgint sc1200_set_video_offset(unsigned long offset);
20771d7fec4Smrgint sc1200_set_video_yuv_offsets(unsigned long yoffset, unsigned long uoffset,
20871d7fec4Smrg				 unsigned long voffset);
20971d7fec4Smrgint sc1200_set_video_window(short x, short y, unsigned short w,
21071d7fec4Smrg			    unsigned short h);
21171d7fec4Smrgint sc1200_set_video_left_crop(unsigned short x);
21271d7fec4Smrgint sc1200_set_video_upscale(unsigned short srcw, unsigned short srch,
21371d7fec4Smrg			     unsigned short dstw, unsigned short dsth);
21471d7fec4Smrgint sc1200_set_video_scale(unsigned short srcw, unsigned short srch,
21571d7fec4Smrg			   unsigned short dstw, unsigned short dsth);
21671d7fec4Smrgint sc1200_set_video_vertical_downscale(unsigned short srch,
21771d7fec4Smrg					unsigned short dsth);
21871d7fec4Smrgvoid sc1200_set_video_vertical_downscale_enable(int enable);
21971d7fec4Smrgint sc1200_set_video_downscale_config(unsigned short type, unsigned short m);
22071d7fec4Smrgint sc1200_set_video_color_key(unsigned long key, unsigned long mask,
22171d7fec4Smrg			       int bluescreen);
22271d7fec4Smrgint sc1200_set_video_filter(int xfilter, int yfilter);
22371d7fec4Smrgint sc1200_set_video_palette(unsigned long *palette);
22471d7fec4Smrgint sc1200_set_video_palette_entry(unsigned long index, unsigned long color);
22571d7fec4Smrgint sc1200_set_video_downscale_coefficients(unsigned short coef1,
22671d7fec4Smrg					    unsigned short coef2,
22771d7fec4Smrg					    unsigned short coef3,
22871d7fec4Smrg					    unsigned short coef4);
22971d7fec4Smrgint sc1200_set_video_downscale_enable(int enable);
23071d7fec4Smrgint sc1200_set_video_source(VideoSourceType source);
23171d7fec4Smrgint sc1200_set_vbi_source(VbiSourceType source);
23271d7fec4Smrgint sc1200_set_vbi_lines(unsigned long even, unsigned long odd);
23371d7fec4Smrgint sc1200_set_vbi_total(unsigned long even, unsigned long odd);
23471d7fec4Smrgint sc1200_set_video_interlaced(int enable);
23571d7fec4Smrgint sc1200_set_color_space_YUV(int enable);
23671d7fec4Smrgint sc1200_set_vertical_scaler_offset(char offset);
23771d7fec4Smrgint sc1200_set_top_line_in_odd(int enable);
23871d7fec4Smrgint sc1200_set_genlock_delay(unsigned long delay);
23971d7fec4Smrgint sc1200_set_genlock_enable(int flags);
24071d7fec4Smrgint sc1200_set_video_cursor(unsigned long key, unsigned long mask,
24171d7fec4Smrg			    unsigned short select_color2,
24271d7fec4Smrg			    unsigned long color1, unsigned long color2);
24371d7fec4Smrgint sc1200_set_video_cursor_enable(int enable);
24471d7fec4Smrgint sc1200_set_video_request(short x, short y);
24571d7fec4Smrg
24671d7fec4Smrgint sc1200_select_alpha_region(int region);
24771d7fec4Smrgint sc1200_set_alpha_enable(int enable);
24871d7fec4Smrgint sc1200_set_alpha_window(short x, short y,
24971d7fec4Smrg			    unsigned short width, unsigned short height);
25071d7fec4Smrgint sc1200_set_alpha_value(unsigned char alpha, char delta);
25171d7fec4Smrgint sc1200_set_alpha_priority(int priority);
25271d7fec4Smrgint sc1200_set_alpha_color(unsigned long color);
25371d7fec4Smrgint sc1200_set_alpha_color_enable(int enable);
25471d7fec4Smrgint sc1200_set_no_ck_outside_alpha(int enable);
25571d7fec4Smrgint sc1200_disable_softvga(void);
25671d7fec4Smrgint sc1200_enable_softvga(void);
25771d7fec4Smrgint sc1200_set_macrovision_enable(int enable);
25871d7fec4Smrgvoid sc1200_reset_video(void);
25971d7fec4Smrgint sc1200_set_display_control(int sync_polarities);
26071d7fec4Smrgvoid sc1200_set_clock_frequency(unsigned long frequency);
26171d7fec4Smrgint sc1200_set_screen_enable(int enable);
26271d7fec4Smrgint sc1200_set_crt_enable(int enable);
26371d7fec4Smrg
26471d7fec4Smrg/* READ ROUTINES IN GFX_VID.C */
26571d7fec4Smrg
26671d7fec4Smrgint sc1200_get_video_enable(void);
26771d7fec4Smrgint sc1200_get_video_format(void);
26871d7fec4Smrgunsigned long sc1200_get_video_src_size(void);
26971d7fec4Smrgunsigned long sc1200_get_video_line_size(void);
27071d7fec4Smrgunsigned long sc1200_get_video_xclip(void);
27171d7fec4Smrgunsigned long sc1200_get_video_offset(void);
27271d7fec4Smrgvoid sc1200_get_video_yuv_offsets(unsigned long *yoffset,
27371d7fec4Smrg				  unsigned long *uoffset,
27471d7fec4Smrg				  unsigned long *voffset);
27571d7fec4Smrgvoid sc1200_get_video_yuv_pitch(unsigned long *ypitch,
27671d7fec4Smrg				unsigned long *uvpitch);
27771d7fec4Smrgunsigned long sc1200_get_video_upscale(void);
27871d7fec4Smrgunsigned long sc1200_get_video_scale(void);
27971d7fec4Smrgunsigned long sc1200_get_video_downscale_delta(void);
28071d7fec4Smrgint sc1200_get_video_vertical_downscale_enable(void);
28171d7fec4Smrgint sc1200_get_video_downscale_config(unsigned short *type,
28271d7fec4Smrg				      unsigned short *m);
28371d7fec4Smrgvoid sc1200_get_video_downscale_coefficients(unsigned short *coef1,
28471d7fec4Smrg					     unsigned short *coef2,
28571d7fec4Smrg					     unsigned short *coef3,
28671d7fec4Smrg					     unsigned short *coef4);
28771d7fec4Smrgvoid sc1200_get_video_downscale_enable(int *enable);
28871d7fec4Smrgunsigned long sc1200_get_video_dst_size(void);
28971d7fec4Smrgunsigned long sc1200_get_video_position(void);
29071d7fec4Smrgunsigned long sc1200_get_video_color_key(void);
29171d7fec4Smrgunsigned long sc1200_get_video_color_key_mask(void);
29271d7fec4Smrgint sc1200_get_video_palette_entry(unsigned long index,
29371d7fec4Smrg				   unsigned long *palette);
29471d7fec4Smrgint sc1200_get_video_color_key_src(void);
29571d7fec4Smrgint sc1200_get_video_filter(void);
29671d7fec4Smrgint sc1200_get_video_request(short *x, short *y);
29771d7fec4Smrgint sc1200_get_video_source(VideoSourceType * source);
29871d7fec4Smrgint sc1200_get_vbi_source(VbiSourceType * source);
29971d7fec4Smrgunsigned long sc1200_get_vbi_lines(int odd);
30071d7fec4Smrgunsigned long sc1200_get_vbi_total(int odd);
30171d7fec4Smrgint sc1200_get_video_interlaced(void);
30271d7fec4Smrgint sc1200_get_color_space_YUV(void);
30371d7fec4Smrgint sc1200_get_vertical_scaler_offset(char *offset);
30471d7fec4Smrgunsigned long sc1200_get_genlock_delay(void);
30571d7fec4Smrgint sc1200_get_genlock_enable(void);
30671d7fec4Smrgint sc1200_get_video_cursor(unsigned long *key, unsigned long *mask,
30771d7fec4Smrg			    unsigned short *select_color2,
30871d7fec4Smrg			    unsigned long *color1, unsigned short *color2);
30971d7fec4Smrgunsigned long sc1200_read_crc(void);
31071d7fec4Smrgunsigned long sc1200_read_crc32(void);
31171d7fec4Smrgunsigned long sc1200_read_window_crc(int source, unsigned short x,
31271d7fec4Smrg				     unsigned short y, unsigned short width,
31371d7fec4Smrg				     unsigned short height, int crc32);
31471d7fec4Smrgint sc1200_get_macrovision_enable(void);
31571d7fec4Smrg
31671d7fec4Smrgvoid sc1200_get_alpha_enable(int *enable);
31771d7fec4Smrgvoid sc1200_get_alpha_size(unsigned short *x, unsigned short *y,
31871d7fec4Smrg			   unsigned short *width, unsigned short *height);
31971d7fec4Smrgvoid sc1200_get_alpha_value(unsigned char *alpha, char *delta);
32071d7fec4Smrgvoid sc1200_get_alpha_priority(int *priority);
32171d7fec4Smrgvoid sc1200_get_alpha_color(unsigned long *color);
32271d7fec4Smrgunsigned long sc1200_get_clock_frequency(void);
32371d7fec4Smrgint sc1200_get_vsa2_softvga_enable(void);
32471d7fec4Smrgint sc1200_get_sync_polarities(void);
32571d7fec4Smrg
32671d7fec4Smrg/*---------------------------------------------------------------------------
32771d7fec4Smrg * gfx_reset_video (PRIVATE ROUTINE: NOT PART OF DURANGO API)
32871d7fec4Smrg *
32971d7fec4Smrg * This routine is used to disable all components of video overlay before
33071d7fec4Smrg * performing a mode switch.
33171d7fec4Smrg *---------------------------------------------------------------------------
33271d7fec4Smrg */
33371d7fec4Smrg#if GFX_VIDEO_DYNAMIC
33471d7fec4Smrgvoid
33571d7fec4Smrgsc1200_reset_video(void)
33671d7fec4Smrg#else
33771d7fec4Smrgvoid
33871d7fec4Smrggfx_reset_video(void)
33971d7fec4Smrg#endif
34071d7fec4Smrg{
34171d7fec4Smrg   int i;
34271d7fec4Smrg
34371d7fec4Smrg   gfx_set_video_enable(0);
34471d7fec4Smrg
34571d7fec4Smrg   /* SET WINDOW 0 AFTER RESET */
34671d7fec4Smrg
34771d7fec4Smrg   for (i = 2; i >= 0; i--) {
34871d7fec4Smrg      gfx_select_alpha_region(i);
34971d7fec4Smrg      gfx_set_alpha_enable(0);
35071d7fec4Smrg      gfx_set_alpha_color_enable(0);
35171d7fec4Smrg   }
35271d7fec4Smrg}
35371d7fec4Smrg
35471d7fec4Smrg/*-----------------------------------------------------------------------------
35571d7fec4Smrg * gfx_set_display_control (PRIVATE ROUTINE: NOT PART OF DURANGO API)
35671d7fec4Smrg *
35771d7fec4Smrg * This routine configures the display output.
35871d7fec4Smrg *
35971d7fec4Smrg * "sync_polarities" is used to set the polarities of the sync pulses according
36071d7fec4Smrg * to the following mask:
36171d7fec4Smrg *
36271d7fec4Smrg *     Bit 0: If set to 1, negative horizontal polarity is programmed,
36371d7fec4Smrg *            otherwise positive horizontal polarity is programmed.
36471d7fec4Smrg *     Bit 1: If set to 1, negative vertical polarity is programmed,
36571d7fec4Smrg *            otherwise positive vertical polarity is programmed.
36671d7fec4Smrg *
36771d7fec4Smrg *-----------------------------------------------------------------------------
36871d7fec4Smrg */
36971d7fec4Smrg#if GFX_VIDEO_DYNAMIC
37071d7fec4Smrgint
37171d7fec4Smrgsc1200_set_display_control(int sync_polarities)
37271d7fec4Smrg#else
37371d7fec4Smrgint
37471d7fec4Smrggfx_set_display_control(int sync_polarities)
37571d7fec4Smrg#endif
37671d7fec4Smrg{
37771d7fec4Smrg   unsigned long dcfg;
37871d7fec4Smrg
37971d7fec4Smrg   /* CONFIGURE DISPLAY OUTPUT FROM VIDEO PROCESSOR */
38071d7fec4Smrg
38171d7fec4Smrg   dcfg = READ_VID32(SC1200_DISPLAY_CONFIG);
38271d7fec4Smrg   dcfg &= ~(SC1200_DCFG_CRT_SYNC_SKW_MASK | SC1200_DCFG_PWR_SEQ_DLY_MASK |
38371d7fec4Smrg	     SC1200_DCFG_CRT_HSYNC_POL | SC1200_DCFG_CRT_VSYNC_POL |
38471d7fec4Smrg	     SC1200_DCFG_FP_PWR_EN | SC1200_DCFG_FP_DATA_EN);
38571d7fec4Smrg
38671d7fec4Smrg   dcfg |= (SC1200_DCFG_CRT_SYNC_SKW_INIT |
38771d7fec4Smrg	    SC1200_DCFG_PWR_SEQ_DLY_INIT | SC1200_DCFG_GV_PAL_BYP);
38871d7fec4Smrg
38971d7fec4Smrg   if (PanelEnable)
39071d7fec4Smrg      dcfg |= SC1200_DCFG_FP_PWR_EN;
39171d7fec4Smrg
39271d7fec4Smrg   /* SET APPROPRIATE SYNC POLARITIES */
39371d7fec4Smrg
39471d7fec4Smrg   if (sync_polarities & 0x1)
39571d7fec4Smrg      dcfg |= SC1200_DCFG_CRT_HSYNC_POL;
39671d7fec4Smrg   if (sync_polarities & 0x2)
39771d7fec4Smrg      dcfg |= SC1200_DCFG_CRT_VSYNC_POL;
39871d7fec4Smrg
39971d7fec4Smrg   WRITE_VID32(SC1200_DISPLAY_CONFIG, dcfg);
40071d7fec4Smrg
40171d7fec4Smrg   return (0);
40271d7fec4Smrg}
40371d7fec4Smrg
40471d7fec4Smrg/*---------------------------------------------------------------------------
40571d7fec4Smrg * gfx_set_clock_frequency
40671d7fec4Smrg *
40771d7fec4Smrg * This routine sets the clock frequency, specified as a 16.16 fixed point
40871d7fec4Smrg * value (0x00318000 = 49.5 MHz).  It will set the closest frequency found
40971d7fec4Smrg * in the lookup table.
41071d7fec4Smrg *---------------------------------------------------------------------------
41171d7fec4Smrg */
41271d7fec4Smrg#if GFX_VIDEO_DYNAMIC
41371d7fec4Smrgvoid
41471d7fec4Smrgsc1200_set_clock_frequency(unsigned long frequency)
41571d7fec4Smrg#else
41671d7fec4Smrgvoid
41771d7fec4Smrggfx_set_clock_frequency(unsigned long frequency)
41871d7fec4Smrg#endif
41971d7fec4Smrg{
42071d7fec4Smrg   unsigned int index;
42171d7fec4Smrg   unsigned long value, pll;
42271d7fec4Smrg   long min, diff;
42371d7fec4Smrg
42471d7fec4Smrg   /* FIND THE REGISTER VALUES FOR THE DESIRED FREQUENCY */
42571d7fec4Smrg   /* Search the table for the closest frequency (16.16 format). */
42671d7fec4Smrg
42771d7fec4Smrg   value = gfx_sc1200_clock_table[0].clock_select;
42871d7fec4Smrg   min = (long)gfx_sc1200_clock_table[0].frequency - frequency;
42971d7fec4Smrg   if (min < 0L)
43071d7fec4Smrg      min = -min;
43171d7fec4Smrg   for (index = 1; index < NUM_SC1200_FREQUENCIES; index++) {
43271d7fec4Smrg      diff = (long)gfx_sc1200_clock_table[index].frequency - frequency;
43371d7fec4Smrg      if (diff < 0L)
43471d7fec4Smrg	 diff = -diff;
43571d7fec4Smrg      if (diff < min) {
43671d7fec4Smrg	 min = diff;
43771d7fec4Smrg	 value = gfx_sc1200_clock_table[index].clock_select;
43871d7fec4Smrg      }
43971d7fec4Smrg   }
44071d7fec4Smrg
44171d7fec4Smrg   /* SET THE DOT CLOCK REGISTER */
44271d7fec4Smrg
44371d7fec4Smrg   pll = READ_VID32(SC1200_VID_MISC);
44471d7fec4Smrg   WRITE_VID32(SC1200_VID_MISC, pll | SC1200_PLL_POWER_NORMAL);
44571d7fec4Smrg   WRITE_VID32(SC1200_VID_CLOCK_SELECT, value);
44671d7fec4Smrg   return;
44771d7fec4Smrg}
44871d7fec4Smrg
44971d7fec4Smrg/*---------------------------------------------------------------------------
45071d7fec4Smrg * gfx_set_screen_enable (PRIVATE ROUTINE - NOT PART OF API)
45171d7fec4Smrg *
45271d7fec4Smrg * This routine enables or disables the graphics display logic of the video processor.
45371d7fec4Smrg *---------------------------------------------------------------------------
45471d7fec4Smrg */
45571d7fec4Smrg#if GFX_VIDEO_DYNAMIC
45671d7fec4Smrgint
45771d7fec4Smrgsc1200_set_screen_enable(int enable)
45871d7fec4Smrg#else
45971d7fec4Smrgint
46071d7fec4Smrggfx_set_screen_enable(int enable)
46171d7fec4Smrg#endif
46271d7fec4Smrg{
46371d7fec4Smrg   unsigned long config;
46471d7fec4Smrg
46571d7fec4Smrg   config = READ_VID32(SC1200_DISPLAY_CONFIG);
46671d7fec4Smrg   if (enable)
46771d7fec4Smrg      WRITE_VID32(SC1200_DISPLAY_CONFIG, config | SC1200_DCFG_DIS_EN);
46871d7fec4Smrg   else
46971d7fec4Smrg      WRITE_VID32(SC1200_DISPLAY_CONFIG, config & ~SC1200_DCFG_DIS_EN);
47071d7fec4Smrg   return (GFX_STATUS_OK);
47171d7fec4Smrg}
47271d7fec4Smrg
47371d7fec4Smrg/*---------------------------------------------------------------------------
47471d7fec4Smrg * gfx_set_crt_enable
47571d7fec4Smrg *
47671d7fec4Smrg * This routine enables or disables the CRT output from the video processor.
47771d7fec4Smrg *---------------------------------------------------------------------------
47871d7fec4Smrg */
47971d7fec4Smrg#if GFX_VIDEO_DYNAMIC
48071d7fec4Smrgint
48171d7fec4Smrgsc1200_set_crt_enable(int enable)
48271d7fec4Smrg#else
48371d7fec4Smrgint
48471d7fec4Smrggfx_set_crt_enable(int enable)
48571d7fec4Smrg#endif
48671d7fec4Smrg{
48771d7fec4Smrg   unsigned long config, misc;
48871d7fec4Smrg
48971d7fec4Smrg   config = READ_VID32(SC1200_DISPLAY_CONFIG);
49071d7fec4Smrg   misc = READ_VID32(SC1200_VID_MISC);
49171d7fec4Smrg
49271d7fec4Smrg   /*
49371d7fec4Smrg    *  IMPORTANT: For all modes do NOT disable the graphics display logic
49471d7fec4Smrg    *  because it might be needed for TV
49571d7fec4Smrg    */
49671d7fec4Smrg
49771d7fec4Smrg   switch (enable) {
49871d7fec4Smrg   case CRT_DISABLE:			/* HSync:Off VSync:Off */
49971d7fec4Smrg      WRITE_VID32(SC1200_DISPLAY_CONFIG, config & ~(SC1200_DCFG_HSYNC_EN
50071d7fec4Smrg						    | SC1200_DCFG_VSYNC_EN
50171d7fec4Smrg						    | SC1200_DCFG_DAC_BL_EN));
50271d7fec4Smrg      WRITE_VID32(SC1200_VID_MISC, misc | SC1200_DAC_POWER_DOWN);
50371d7fec4Smrg      break;
50471d7fec4Smrg   case CRT_ENABLE:			/* Enable CRT display, including display logic */
50571d7fec4Smrg      WRITE_VID32(SC1200_DISPLAY_CONFIG, config | SC1200_DCFG_HSYNC_EN
50671d7fec4Smrg		  | SC1200_DCFG_VSYNC_EN | SC1200_DCFG_DAC_BL_EN);
50771d7fec4Smrg      WRITE_VID32(SC1200_VID_MISC, misc & ~SC1200_DAC_POWER_DOWN);
50871d7fec4Smrg
50971d7fec4Smrg      /* ENABLE GRAPHICS DISPLAY LOGIC */
51071d7fec4Smrg      gfx_set_screen_enable(1);
51171d7fec4Smrg      break;
51271d7fec4Smrg   case CRT_STANDBY:			/* HSync:Off VSync:On */
51371d7fec4Smrg      WRITE_VID32(SC1200_DISPLAY_CONFIG, (config & ~(SC1200_DCFG_HSYNC_EN
51471d7fec4Smrg						     | SC1200_DCFG_DAC_BL_EN))
51571d7fec4Smrg		  | SC1200_DCFG_VSYNC_EN);
51671d7fec4Smrg      WRITE_VID32(SC1200_VID_MISC, misc | SC1200_DAC_POWER_DOWN);
51771d7fec4Smrg      break;
51871d7fec4Smrg   case CRT_SUSPEND:			/* HSync:On VSync:Off */
51971d7fec4Smrg      WRITE_VID32(SC1200_DISPLAY_CONFIG, (config & ~(SC1200_DCFG_VSYNC_EN
52071d7fec4Smrg						     | SC1200_DCFG_DAC_BL_EN))
52171d7fec4Smrg		  | SC1200_DCFG_HSYNC_EN);
52271d7fec4Smrg      WRITE_VID32(SC1200_VID_MISC, misc | SC1200_DAC_POWER_DOWN);
52371d7fec4Smrg      break;
52471d7fec4Smrg   default:
52571d7fec4Smrg      return GFX_STATUS_BAD_PARAMETER;
52671d7fec4Smrg   }
52771d7fec4Smrg   return (GFX_STATUS_OK);
52871d7fec4Smrg}
52971d7fec4Smrg
53071d7fec4Smrg/*-----------------------------------------------------------------------------
53171d7fec4Smrg * gfx_set_video_enable
53271d7fec4Smrg *
53371d7fec4Smrg * This routine enables or disables the video overlay functionality.
53471d7fec4Smrg *-----------------------------------------------------------------------------
53571d7fec4Smrg */
53671d7fec4Smrg#if GFX_VIDEO_DYNAMIC
53771d7fec4Smrgint
53871d7fec4Smrgsc1200_set_video_enable(int enable)
53971d7fec4Smrg#else
54071d7fec4Smrgint
54171d7fec4Smrggfx_set_video_enable(int enable)
54271d7fec4Smrg#endif
54371d7fec4Smrg{
54471d7fec4Smrg   unsigned long vcfg;
54571d7fec4Smrg
54671d7fec4Smrg   /* WAIT FOR VERTICAL BLANK TO START */
54771d7fec4Smrg   /* Otherwise a glitch can be observed. */
54871d7fec4Smrg
54971d7fec4Smrg   if (gfx_test_timing_active()) {
55071d7fec4Smrg      if (!gfx_test_vertical_active()) {
55171d7fec4Smrg	 while (!gfx_test_vertical_active()) ;
55271d7fec4Smrg      }
55371d7fec4Smrg      while (gfx_test_vertical_active()) ;
55471d7fec4Smrg   }
55571d7fec4Smrg
55671d7fec4Smrg   vcfg = READ_VID32(SC1200_VIDEO_CONFIG);
55771d7fec4Smrg   if (enable) {
55871d7fec4Smrg      /* ENABLE VIDEO OVERLAY FROM DISPLAY CONTROLLER */
55971d7fec4Smrg      /* Use private routine to abstract the display controller. */
56071d7fec4Smrg
56171d7fec4Smrg      gfx_set_display_video_enable(1);
56271d7fec4Smrg
56371d7fec4Smrg      /* ENABLE SC1200 VIDEO OVERLAY */
56471d7fec4Smrg
56571d7fec4Smrg      vcfg |= SC1200_VCFG_VID_EN;
56671d7fec4Smrg      WRITE_VID32(SC1200_VIDEO_CONFIG, vcfg);
56771d7fec4Smrg   } else {
56871d7fec4Smrg      /* DISABLE SC1200 VIDEO OVERLAY */
56971d7fec4Smrg
57071d7fec4Smrg      vcfg &= ~SC1200_VCFG_VID_EN;
57171d7fec4Smrg      WRITE_VID32(SC1200_VIDEO_CONFIG, vcfg);
57271d7fec4Smrg
57371d7fec4Smrg      /* DISABLE VIDEO OVERLAY FROM DISPLAY CONTROLLER */
57471d7fec4Smrg      /* Use private routine to abstract the display controller. */
57571d7fec4Smrg
57671d7fec4Smrg      gfx_set_display_video_enable(0);
57771d7fec4Smrg   }
57871d7fec4Smrg   return (0);
57971d7fec4Smrg}
58071d7fec4Smrg
58171d7fec4Smrg/*-----------------------------------------------------------------------------
58271d7fec4Smrg * gfx_set_video_format
58371d7fec4Smrg *
58471d7fec4Smrg * Sets input video format type, to one of the YUV formats or to RGB.
58571d7fec4Smrg *-----------------------------------------------------------------------------
58671d7fec4Smrg */
58771d7fec4Smrg#if GFX_VIDEO_DYNAMIC
58871d7fec4Smrgint
58971d7fec4Smrgsc1200_set_video_format(unsigned long format)
59071d7fec4Smrg#else
59171d7fec4Smrgint
59271d7fec4Smrggfx_set_video_format(unsigned long format)
59371d7fec4Smrg#endif
59471d7fec4Smrg{
59571d7fec4Smrg   unsigned long ctrl, vcfg = 0;
59671d7fec4Smrg
59771d7fec4Smrg   /* SET THE SC1200 VIDEO INPUT FORMAT */
59871d7fec4Smrg
59971d7fec4Smrg   vcfg = READ_VID32(SC1200_VIDEO_CONFIG);
60071d7fec4Smrg   ctrl = READ_VID32(SC1200_VID_ALPHA_CONTROL);
60171d7fec4Smrg   ctrl &= ~(SC1200_VIDEO_INPUT_IS_RGB);
60271d7fec4Smrg   vcfg &= ~(SC1200_VCFG_VID_INP_FORMAT | SC1200_VCFG_4_2_0_MODE);
60371d7fec4Smrg   switch (format) {
60471d7fec4Smrg   case VIDEO_FORMAT_UYVY:
60571d7fec4Smrg      vcfg |= SC1200_VCFG_UYVY_FORMAT;
60671d7fec4Smrg      break;
60771d7fec4Smrg   case VIDEO_FORMAT_YUYV:
60871d7fec4Smrg      vcfg |= SC1200_VCFG_YUYV_FORMAT;
60971d7fec4Smrg      break;
61071d7fec4Smrg   case VIDEO_FORMAT_Y2YU:
61171d7fec4Smrg      vcfg |= SC1200_VCFG_Y2YU_FORMAT;
61271d7fec4Smrg      break;
61371d7fec4Smrg   case VIDEO_FORMAT_YVYU:
61471d7fec4Smrg      vcfg |= SC1200_VCFG_YVYU_FORMAT;
61571d7fec4Smrg      break;
61671d7fec4Smrg   case VIDEO_FORMAT_Y0Y1Y2Y3:
61771d7fec4Smrg      vcfg |= SC1200_VCFG_UYVY_FORMAT;
61871d7fec4Smrg      vcfg |= SC1200_VCFG_4_2_0_MODE;
61971d7fec4Smrg      break;
62071d7fec4Smrg   case VIDEO_FORMAT_Y3Y2Y1Y0:
62171d7fec4Smrg      vcfg |= SC1200_VCFG_Y2YU_FORMAT;
62271d7fec4Smrg      vcfg |= SC1200_VCFG_4_2_0_MODE;
62371d7fec4Smrg      break;
62471d7fec4Smrg   case VIDEO_FORMAT_Y1Y0Y3Y2:
62571d7fec4Smrg      vcfg |= SC1200_VCFG_YUYV_FORMAT;
62671d7fec4Smrg      vcfg |= SC1200_VCFG_4_2_0_MODE;
62771d7fec4Smrg      break;
62871d7fec4Smrg   case VIDEO_FORMAT_Y1Y2Y3Y0:
62971d7fec4Smrg      vcfg |= SC1200_VCFG_YVYU_FORMAT;
63071d7fec4Smrg      vcfg |= SC1200_VCFG_4_2_0_MODE;
63171d7fec4Smrg      break;
63271d7fec4Smrg   case VIDEO_FORMAT_RGB:
63371d7fec4Smrg      ctrl |= SC1200_VIDEO_INPUT_IS_RGB;
63471d7fec4Smrg      vcfg |= SC1200_VCFG_UYVY_FORMAT;
63571d7fec4Smrg      break;
63671d7fec4Smrg   case VIDEO_FORMAT_P2M_P2L_P1M_P1L:
63771d7fec4Smrg      ctrl |= SC1200_VIDEO_INPUT_IS_RGB;
63871d7fec4Smrg      vcfg |= SC1200_VCFG_Y2YU_FORMAT;
63971d7fec4Smrg      break;
64071d7fec4Smrg   case VIDEO_FORMAT_P1M_P1L_P2M_P2L:
64171d7fec4Smrg      ctrl |= SC1200_VIDEO_INPUT_IS_RGB;
64271d7fec4Smrg      vcfg |= SC1200_VCFG_YUYV_FORMAT;
64371d7fec4Smrg      break;
64471d7fec4Smrg   case VIDEO_FORMAT_P1M_P2L_P2M_P1L:
64571d7fec4Smrg      ctrl |= SC1200_VIDEO_INPUT_IS_RGB;
64671d7fec4Smrg      vcfg |= SC1200_VCFG_YVYU_FORMAT;
64771d7fec4Smrg      break;
64871d7fec4Smrg   default:
64971d7fec4Smrg      return GFX_STATUS_BAD_PARAMETER;
65071d7fec4Smrg   }
65171d7fec4Smrg
65271d7fec4Smrg   /* ALWAYS DISABLE GRAPHICS CSC */
65371d7fec4Smrg   /* This is enabled in the function gfx_set_color_space_YUV for */
65471d7fec4Smrg   /* YUV blending on TV.                                         */
65571d7fec4Smrg
65671d7fec4Smrg   ctrl &= ~SC1200_CSC_GFX_RGB_TO_YUV;
65771d7fec4Smrg
65871d7fec4Smrg   if (ctrl & SC1200_VIDEO_INPUT_IS_RGB)
65971d7fec4Smrg      ctrl &= ~SC1200_CSC_VIDEO_YUV_TO_RGB;
66071d7fec4Smrg   else
66171d7fec4Smrg      ctrl |= SC1200_CSC_VIDEO_YUV_TO_RGB;
66271d7fec4Smrg
66371d7fec4Smrg   WRITE_VID32(SC1200_VIDEO_CONFIG, vcfg);
66471d7fec4Smrg   WRITE_VID32(SC1200_VID_ALPHA_CONTROL, ctrl);
66571d7fec4Smrg
66671d7fec4Smrg   return (0);
66771d7fec4Smrg}
66871d7fec4Smrg
66971d7fec4Smrg/*-----------------------------------------------------------------------------
67071d7fec4Smrg * gfx_set_video_size
67171d7fec4Smrg *
67271d7fec4Smrg * This routine specifies the size of the source data.  It is used only
67371d7fec4Smrg * to determine how much data to transfer per frame, and is not used to
67471d7fec4Smrg * calculate the scaling value (that is handled by a separate routine).
67571d7fec4Smrg *-----------------------------------------------------------------------------
67671d7fec4Smrg */
67771d7fec4Smrg#if GFX_VIDEO_DYNAMIC
67871d7fec4Smrgint
67971d7fec4Smrgsc1200_set_video_size(unsigned short width, unsigned short height)
68071d7fec4Smrg#else
68171d7fec4Smrgint
68271d7fec4Smrggfx_set_video_size(unsigned short width, unsigned short height)
68371d7fec4Smrg#endif
68471d7fec4Smrg{
68571d7fec4Smrg   unsigned long size, vcfg;
68671d7fec4Smrg
68771d7fec4Smrg   /* SET THE SC1200 VIDEO LINE SIZE */
68871d7fec4Smrg
68971d7fec4Smrg   vcfg = READ_VID32(SC1200_VIDEO_CONFIG);
69071d7fec4Smrg   vcfg &= ~(SC1200_VCFG_LINE_SIZE_LOWER_MASK | SC1200_VCFG_LINE_SIZE_UPPER);
69171d7fec4Smrg   size = (width >> 1);
69271d7fec4Smrg   vcfg |= (size & 0x00FF) << 8;
69371d7fec4Smrg   if (size & 0x0100)
69471d7fec4Smrg      vcfg |= SC1200_VCFG_LINE_SIZE_UPPER;
69571d7fec4Smrg   WRITE_VID32(SC1200_VIDEO_CONFIG, vcfg);
69671d7fec4Smrg
69771d7fec4Smrg   /* SET TOTAL VIDEO BUFFER SIZE IN DISPLAY CONTROLLER */
69871d7fec4Smrg   /* Use private routine to abstract the display controller. */
69971d7fec4Smrg
70071d7fec4Smrg   /* Add 1 line to bypass issue #803 */
70171d7fec4Smrg   gfx_set_display_video_size(width, (unsigned short)(height + 2));
70271d7fec4Smrg   return (0);
70371d7fec4Smrg}
70471d7fec4Smrg
70571d7fec4Smrg/*-----------------------------------------------------------------------------
70671d7fec4Smrg * gfx_set_video_offset
70771d7fec4Smrg *
70871d7fec4Smrg * This routine sets the starting offset for the video buffer when only
70971d7fec4Smrg * one offset needs to be specified.
71071d7fec4Smrg *-----------------------------------------------------------------------------
71171d7fec4Smrg */
71271d7fec4Smrg#if GFX_VIDEO_DYNAMIC
71371d7fec4Smrgint
71471d7fec4Smrgsc1200_set_video_offset(unsigned long offset)
71571d7fec4Smrg#else
71671d7fec4Smrgint
71771d7fec4Smrggfx_set_video_offset(unsigned long offset)
71871d7fec4Smrg#endif
71971d7fec4Smrg{
72071d7fec4Smrg   /* SAVE VALUE FOR FUTURE CLIPPING OF THE TOP OF THE VIDEO WINDOW */
72171d7fec4Smrg
72271d7fec4Smrg   gfx_vid_offset = offset;
72371d7fec4Smrg
72471d7fec4Smrg   /* SET VIDEO BUFFER OFFSET IN DISPLAY CONTROLLER */
72571d7fec4Smrg   /* Use private routine to abstract the display controller. */
72671d7fec4Smrg
72771d7fec4Smrg   gfx_set_display_video_offset(offset);
72871d7fec4Smrg   return (0);
72971d7fec4Smrg}
73071d7fec4Smrg
73171d7fec4Smrg/*---------------------------------------------------------------------------
73271d7fec4Smrg * gfx_set_video_upscale
73371d7fec4Smrg *
73471d7fec4Smrg * This routine sets the scale factor for the video overlay window.  The
73571d7fec4Smrg * size of the source and destination regions are specified in pixels.
73671d7fec4Smrg *---------------------------------------------------------------------------
73771d7fec4Smrg */
73871d7fec4Smrg#if GFX_VIDEO_DYNAMIC
73971d7fec4Smrgint
74071d7fec4Smrgsc1200_set_video_upscale(unsigned short srcw, unsigned short srch,
74171d7fec4Smrg			 unsigned short dstw, unsigned short dsth)
74271d7fec4Smrg#else
74371d7fec4Smrgint
74471d7fec4Smrggfx_set_video_upscale(unsigned short srcw, unsigned short srch,
74571d7fec4Smrg		      unsigned short dstw, unsigned short dsth)
74671d7fec4Smrg#endif
74771d7fec4Smrg{
74871d7fec4Smrg   unsigned long xscale, yscale;
74971d7fec4Smrg
75071d7fec4Smrg   /* SAVE PARAMETERS (unless don't-care zero destination arguments are used) */
75171d7fec4Smrg   /* These are needed for clipping the video window later. */
75271d7fec4Smrg
75371d7fec4Smrg   if (dstw != 0) {
75471d7fec4Smrg      gfx_vid_srcw = srcw;
75571d7fec4Smrg      gfx_vid_dstw = dstw;
75671d7fec4Smrg   }
75771d7fec4Smrg   if (dsth != 0) {
75871d7fec4Smrg      gfx_vid_srch = srch;
75971d7fec4Smrg      gfx_vid_dsth = dsth;
76071d7fec4Smrg   }
76171d7fec4Smrg
76271d7fec4Smrg   /* CALCULATE SC1200 SCALE FACTORS */
76371d7fec4Smrg
76471d7fec4Smrg   if (dstw == 0)
76571d7fec4Smrg      xscale = READ_VID32(SC1200_VIDEO_UPSCALE) & 0xffff;	/* keep previous if don't-care argument */
76671d7fec4Smrg   else if (dstw <= srcw)
76771d7fec4Smrg      xscale = 0x2000l;			/* horizontal downscaling is currently done in a separate function */
76871d7fec4Smrg   else if ((srcw == 1) || (dstw == 1))
76971d7fec4Smrg      return GFX_STATUS_BAD_PARAMETER;
77071d7fec4Smrg   else
77171d7fec4Smrg      xscale = (0x2000l * (srcw - 1l)) / (dstw - 1l);
77271d7fec4Smrg
77371d7fec4Smrg   if (dsth == 0)
77471d7fec4Smrg      yscale = (READ_VID32(SC1200_VIDEO_UPSCALE) & 0xffff0000) >> 16;	/* keep previous if don't-care argument */
77571d7fec4Smrg   else if (dsth <= srch)
77671d7fec4Smrg      yscale = 0x2000l;			/* No vertical downscaling in SC1200 so force to 1x if attempted */
77771d7fec4Smrg   else if ((srch == 1) || (dsth == 1))
77871d7fec4Smrg      return GFX_STATUS_BAD_PARAMETER;
77971d7fec4Smrg   else
78071d7fec4Smrg      yscale = (0x2000l * (srch - 1l)) / (dsth - 1l);
78171d7fec4Smrg
78271d7fec4Smrg   WRITE_VID32(SC1200_VIDEO_UPSCALE, (yscale << 16) | xscale);
78371d7fec4Smrg
78471d7fec4Smrg   /* CALL ROUTINE TO UPDATE WINDOW POSITION */
78571d7fec4Smrg   /* This is required because the scale values effect the number of */
78671d7fec4Smrg   /* source data pixels that need to be clipped, as well as the */
78771d7fec4Smrg   /* amount of data that needs to be transferred. */
78871d7fec4Smrg
78971d7fec4Smrg   gfx_set_video_window(gfx_vid_xpos, gfx_vid_ypos, gfx_vid_width,
79071d7fec4Smrg			gfx_vid_height);
79171d7fec4Smrg   return (0);
79271d7fec4Smrg}
79371d7fec4Smrg
79471d7fec4Smrg/*---------------------------------------------------------------------------
79571d7fec4Smrg * gfx_set_video_scale
79671d7fec4Smrg *
79771d7fec4Smrg * This routine sets the scale factor for the video overlay window.  The
79871d7fec4Smrg * size of the source and destination regions are specified in pixels.
79971d7fec4Smrg *---------------------------------------------------------------------------
80071d7fec4Smrg */
80171d7fec4Smrg#if GFX_VIDEO_DYNAMIC
80271d7fec4Smrgint
80371d7fec4Smrgsc1200_set_video_scale(unsigned short srcw, unsigned short srch,
80471d7fec4Smrg		       unsigned short dstw, unsigned short dsth)
80571d7fec4Smrg#else
80671d7fec4Smrgint
80771d7fec4Smrggfx_set_video_scale(unsigned short srcw, unsigned short srch,
80871d7fec4Smrg		    unsigned short dstw, unsigned short dsth)
80971d7fec4Smrg#endif
81071d7fec4Smrg{
81171d7fec4Smrg   return gfx_set_video_upscale(srcw, srch, dstw, dsth);
81271d7fec4Smrg}
81371d7fec4Smrg
81471d7fec4Smrg/*---------------------------------------------------------------------------
81571d7fec4Smrg * gfx_set_video_downscale_config
81671d7fec4Smrg *
81771d7fec4Smrg * This routine sets the downscale type and factor for the video overlay window.
81871d7fec4Smrg * Note: No downscaling support for RGB565 and YUV420 video formats.
81971d7fec4Smrg *---------------------------------------------------------------------------
82071d7fec4Smrg */
82171d7fec4Smrg#if GFX_VIDEO_DYNAMIC
82271d7fec4Smrgint
82371d7fec4Smrgsc1200_set_video_downscale_config(unsigned short type, unsigned short m)
82471d7fec4Smrg#else
82571d7fec4Smrgint
82671d7fec4Smrggfx_set_video_downscale_config(unsigned short type, unsigned short m)
82771d7fec4Smrg#endif
82871d7fec4Smrg{
82971d7fec4Smrg   unsigned long downscale;
83071d7fec4Smrg
83171d7fec4Smrg   if ((m < 1) || (m > 16))
83271d7fec4Smrg      return GFX_STATUS_BAD_PARAMETER;
83371d7fec4Smrg
83471d7fec4Smrg   downscale = READ_VID32(SC1200_VIDEO_DOWNSCALER_CONTROL);
83571d7fec4Smrg   downscale &=
83671d7fec4Smrg	 ~(SC1200_VIDEO_DOWNSCALE_FACTOR_MASK |
83771d7fec4Smrg	   SC1200_VIDEO_DOWNSCALE_TYPE_MASK);
83871d7fec4Smrg   downscale |= ((m - 1l) << SC1200_VIDEO_DOWNSCALE_FACTOR_POS);
83971d7fec4Smrg   switch (type) {
84071d7fec4Smrg   case VIDEO_DOWNSCALE_KEEP_1_OF:
84171d7fec4Smrg      downscale |= SC1200_VIDEO_DOWNSCALE_TYPE_A;
84271d7fec4Smrg      break;
84371d7fec4Smrg   case VIDEO_DOWNSCALE_DROP_1_OF:
84471d7fec4Smrg      downscale |= SC1200_VIDEO_DOWNSCALE_TYPE_B;
84571d7fec4Smrg      break;
84671d7fec4Smrg   default:
84771d7fec4Smrg      return GFX_STATUS_BAD_PARAMETER;
84871d7fec4Smrg   }
84971d7fec4Smrg   WRITE_VID32(SC1200_VIDEO_DOWNSCALER_CONTROL, downscale);
85071d7fec4Smrg   return (0);
85171d7fec4Smrg}
85271d7fec4Smrg
85371d7fec4Smrg/*---------------------------------------------------------------------------
85471d7fec4Smrg * gfx_set_video_downscale_coefficients
85571d7fec4Smrg *
85671d7fec4Smrg * This routine sets the downscale filter coefficients.
85771d7fec4Smrg *---------------------------------------------------------------------------
85871d7fec4Smrg */
85971d7fec4Smrg#if GFX_VIDEO_DYNAMIC
86071d7fec4Smrgint
86171d7fec4Smrgsc1200_set_video_downscale_coefficients(unsigned short coef1,
86271d7fec4Smrg					unsigned short coef2,
86371d7fec4Smrg					unsigned short coef3,
86471d7fec4Smrg					unsigned short coef4)
86571d7fec4Smrg#else
86671d7fec4Smrgint
86771d7fec4Smrggfx_set_video_downscale_coefficients(unsigned short coef1,
86871d7fec4Smrg				     unsigned short coef2,
86971d7fec4Smrg				     unsigned short coef3,
87071d7fec4Smrg				     unsigned short coef4)
87171d7fec4Smrg#endif
87271d7fec4Smrg{
87371d7fec4Smrg   if ((coef1 + coef2 + coef3 + coef4) != 16)
87471d7fec4Smrg      return GFX_STATUS_BAD_PARAMETER;
87571d7fec4Smrg
87671d7fec4Smrg   WRITE_VID32(SC1200_VIDEO_DOWNSCALER_COEFFICIENTS,
87771d7fec4Smrg	       ((unsigned long)coef1 << SC1200_VIDEO_DOWNSCALER_COEF1_POS) |
87871d7fec4Smrg	       ((unsigned long)coef2 << SC1200_VIDEO_DOWNSCALER_COEF2_POS) |
87971d7fec4Smrg	       ((unsigned long)coef3 << SC1200_VIDEO_DOWNSCALER_COEF3_POS) |
88071d7fec4Smrg	       ((unsigned long)coef4 << SC1200_VIDEO_DOWNSCALER_COEF4_POS));
88171d7fec4Smrg   return (0);
88271d7fec4Smrg}
88371d7fec4Smrg
88471d7fec4Smrg/*---------------------------------------------------------------------------
88571d7fec4Smrg * gfx_set_video_downscale_enable
88671d7fec4Smrg *
88771d7fec4Smrg * This routine enables or disables downscaling for the video overlay window.
88871d7fec4Smrg *---------------------------------------------------------------------------
88971d7fec4Smrg */
89071d7fec4Smrg#if GFX_VIDEO_DYNAMIC
89171d7fec4Smrgint
89271d7fec4Smrgsc1200_set_video_downscale_enable(int enable)
89371d7fec4Smrg#else
89471d7fec4Smrgint
89571d7fec4Smrggfx_set_video_downscale_enable(int enable)
89671d7fec4Smrg#endif
89771d7fec4Smrg{
89871d7fec4Smrg   unsigned long downscale;
89971d7fec4Smrg
90071d7fec4Smrg   downscale = READ_VID32(SC1200_VIDEO_DOWNSCALER_CONTROL);
90171d7fec4Smrg   downscale &= ~SC1200_VIDEO_DOWNSCALE_ENABLE;
90271d7fec4Smrg   if (enable)
90371d7fec4Smrg      downscale |= SC1200_VIDEO_DOWNSCALE_ENABLE;
90471d7fec4Smrg   WRITE_VID32(SC1200_VIDEO_DOWNSCALER_CONTROL, downscale);
90571d7fec4Smrg   return (0);
90671d7fec4Smrg}
90771d7fec4Smrg
90871d7fec4Smrg/*---------------------------------------------------------------------------
90971d7fec4Smrg * gfx_set_video_window
91071d7fec4Smrg *
91171d7fec4Smrg * This routine sets the position and size of the video overlay window.  The
91271d7fec4Smrg * y position is specified in screen relative coordinates, and may be negative.
91371d7fec4Smrg * The size of destination region is specified in pixels.  The line size
91471d7fec4Smrg * indicates the number of bytes of source data per scanline.
91571d7fec4Smrg * For the effect of negative x values, call the function
91671d7fec4Smrg * gfx_set_video_left_crop().
91771d7fec4Smrg *---------------------------------------------------------------------------
91871d7fec4Smrg */
91971d7fec4Smrg#if GFX_VIDEO_DYNAMIC
92071d7fec4Smrgint
92171d7fec4Smrgsc1200_set_video_window(short x, short y, unsigned short w, unsigned short h)
92271d7fec4Smrg#else
92371d7fec4Smrgint
92471d7fec4Smrggfx_set_video_window(short x, short y, unsigned short w, unsigned short h)
92571d7fec4Smrg#endif
92671d7fec4Smrg{
92771d7fec4Smrg   unsigned long control;
92871d7fec4Smrg   unsigned long hadjust, vadjust;
92971d7fec4Smrg   unsigned long xstart, ystart, xend, yend;
93071d7fec4Smrg
93171d7fec4Smrg   /* For left cropping call the function gfx_set_video_left_crop() */
93271d7fec4Smrg
93371d7fec4Smrg   if (x < 0)
93471d7fec4Smrg      return GFX_STATUS_BAD_PARAMETER;
93571d7fec4Smrg
93671d7fec4Smrg   /* SAVE PARAMETERS */
93771d7fec4Smrg   /* These are needed to call this routine if the scale value changes. */
93871d7fec4Smrg   /* In the case of SC1200 they are also needed for restoring when video is re-enabled */
93971d7fec4Smrg
94071d7fec4Smrg   gfx_vid_xpos = x;
94171d7fec4Smrg   gfx_vid_ypos = y;
94271d7fec4Smrg   gfx_vid_width = w;
94371d7fec4Smrg   gfx_vid_height = h;
94471d7fec4Smrg
94571d7fec4Smrg   /* GET ADJUSTMENT VALUES */
94671d7fec4Smrg   /* Use routines to abstract version of display controller. */
94771d7fec4Smrg
94871d7fec4Smrg   hadjust = gfx_get_htotal() - gfx_get_hsync_end() - 14l;
94971d7fec4Smrg   vadjust = gfx_get_vtotal() - gfx_get_vsync_end() + 1l;
95071d7fec4Smrg
95171d7fec4Smrg   /* HORIZONTAL START */
95271d7fec4Smrg
95371d7fec4Smrg   xstart = (unsigned long)x + hadjust;
95471d7fec4Smrg
95571d7fec4Smrg   /* HORIZONTAL END */
95671d7fec4Smrg   /* End positions in register are non-inclusive (one more than the actual end) */
95771d7fec4Smrg
95871d7fec4Smrg   if ((x + w) < gfx_get_hactive())
95971d7fec4Smrg      xend = (unsigned long)x + (unsigned long)w + hadjust;
96071d7fec4Smrg   else					/* right clipping needed */
96171d7fec4Smrg      xend = (unsigned long)gfx_get_hactive() + hadjust;
96271d7fec4Smrg
96371d7fec4Smrg   /* VERTICAL START */
96471d7fec4Smrg
96571d7fec4Smrg   ystart = (unsigned long)y + vadjust;
96671d7fec4Smrg
96771d7fec4Smrg   /* VERTICAL END */
96871d7fec4Smrg
96971d7fec4Smrg   if ((y + h) < gfx_get_vactive())
97071d7fec4Smrg      yend = (unsigned long)y + (unsigned long)h + vadjust;
97171d7fec4Smrg   else					/* bottom clipping needed */
97271d7fec4Smrg      yend = (unsigned long)gfx_get_vactive() + vadjust;
97371d7fec4Smrg
97471d7fec4Smrg   /* SET VIDEO LINE INVERT BIT */
97571d7fec4Smrg
97671d7fec4Smrg   control = READ_VID32(SC1200_VID_ALPHA_CONTROL);
97771d7fec4Smrg   if (y & 0x1)
97871d7fec4Smrg      WRITE_VID32(SC1200_VID_ALPHA_CONTROL,
97971d7fec4Smrg		  control | SC1200_VIDEO_LINE_OFFSET_ODD);
98071d7fec4Smrg   else
98171d7fec4Smrg      WRITE_VID32(SC1200_VID_ALPHA_CONTROL,
98271d7fec4Smrg		  control & ~SC1200_VIDEO_LINE_OFFSET_ODD);
98371d7fec4Smrg
98471d7fec4Smrg   /* SET VIDEO POSITION */
98571d7fec4Smrg
98671d7fec4Smrg   WRITE_VID32(SC1200_VIDEO_X_POS, (xend << 16) | xstart);
98771d7fec4Smrg   WRITE_VID32(SC1200_VIDEO_Y_POS, (yend << 16) | ystart);
98871d7fec4Smrg
98971d7fec4Smrg   return (0);
99071d7fec4Smrg}
99171d7fec4Smrg
99271d7fec4Smrg/*---------------------------------------------------------------------------
99371d7fec4Smrg * gfx_set_video_left_crop
99471d7fec4Smrg *
99571d7fec4Smrg * This routine sets the number of pixels which will be cropped from the
99671d7fec4Smrg * beginning of each video line. The video window will begin to display only
99771d7fec4Smrg * from the pixel following the cropped pixels, and the cropped pixels
99871d7fec4Smrg * will be ignored.
99971d7fec4Smrg *---------------------------------------------------------------------------
100071d7fec4Smrg */
100171d7fec4Smrg#if GFX_VIDEO_DYNAMIC
100271d7fec4Smrgint
100371d7fec4Smrgsc1200_set_video_left_crop(unsigned short x)
100471d7fec4Smrg#else
100571d7fec4Smrgint
100671d7fec4Smrggfx_set_video_left_crop(unsigned short x)
100771d7fec4Smrg#endif
100871d7fec4Smrg{
100971d7fec4Smrg   unsigned long vcfg, initread;
101071d7fec4Smrg
101171d7fec4Smrg   /* CLIPPING ON LEFT */
101271d7fec4Smrg   /* Adjust initial read for scale, checking for divide by zero */
101371d7fec4Smrg
101471d7fec4Smrg   if (gfx_vid_dstw)
101571d7fec4Smrg      initread = (unsigned long)x *gfx_vid_srcw / gfx_vid_dstw;
101671d7fec4Smrg
101771d7fec4Smrg   else
101871d7fec4Smrg      initread = 0l;
101971d7fec4Smrg
102071d7fec4Smrg   /* SET INITIAL READ ADDRESS */
102171d7fec4Smrg
102271d7fec4Smrg   vcfg = READ_VID32(SC1200_VIDEO_CONFIG);
102371d7fec4Smrg   vcfg &= ~SC1200_VCFG_INIT_READ_MASK;
102471d7fec4Smrg   vcfg |= (initread << 15) & SC1200_VCFG_INIT_READ_MASK;
102571d7fec4Smrg   WRITE_VID32(SC1200_VIDEO_CONFIG, vcfg);
102671d7fec4Smrg   return (0);
102771d7fec4Smrg}
102871d7fec4Smrg
102971d7fec4Smrg/*---------------------------------------------------------------------------
103071d7fec4Smrg * gfx_set_video_color_key
103171d7fec4Smrg *
103271d7fec4Smrg * This routine specifies the color key value and mask for the video overlay
103371d7fec4Smrg * hardware. To disable color key, the color and mask should both be set to
103471d7fec4Smrg * zero. The hardware uses the color key in the following equation:
103571d7fec4Smrg *
103671d7fec4Smrg * ((source data) & (color key mask)) == ((color key) & (color key mask))
103771d7fec4Smrg *
103871d7fec4Smrg * If "graphics" is set to TRUE, the source data is graphics, and color key
103971d7fec4Smrg * is an RGB value. If "graphics" is set to FALSE, the source data is the video,
104071d7fec4Smrg * and color key is a YUV value.
104171d7fec4Smrg *---------------------------------------------------------------------------
104271d7fec4Smrg */
104371d7fec4Smrg#if GFX_VIDEO_DYNAMIC
104471d7fec4Smrgint
104571d7fec4Smrgsc1200_set_video_color_key(unsigned long key, unsigned long mask,
104671d7fec4Smrg			   int graphics)
104771d7fec4Smrg#else
104871d7fec4Smrgint
104971d7fec4Smrggfx_set_video_color_key(unsigned long key, unsigned long mask, int graphics)
105071d7fec4Smrg#endif
105171d7fec4Smrg{
105271d7fec4Smrg   unsigned long dcfg = 0;
105371d7fec4Smrg
105471d7fec4Smrg   /* SET SC1200 COLOR KEY VALUE */
105571d7fec4Smrg
105671d7fec4Smrg   WRITE_VID32(SC1200_VIDEO_COLOR_KEY, key);
105771d7fec4Smrg   WRITE_VID32(SC1200_VIDEO_COLOR_MASK, mask);
105871d7fec4Smrg
105971d7fec4Smrg   /* SELECT GRAPHICS OR VIDEO DATA TO COMPARE TO THE COLOR KEY */
106071d7fec4Smrg
106171d7fec4Smrg   dcfg = READ_VID32(SC1200_DISPLAY_CONFIG);
106271d7fec4Smrg   if (graphics & 0x01)
106371d7fec4Smrg      dcfg &= ~SC1200_DCFG_VG_CK;
106471d7fec4Smrg   else
106571d7fec4Smrg      dcfg |= SC1200_DCFG_VG_CK;
106671d7fec4Smrg   WRITE_VID32(SC1200_DISPLAY_CONFIG, dcfg);
106771d7fec4Smrg   return (0);
106871d7fec4Smrg}
106971d7fec4Smrg
107071d7fec4Smrg/*---------------------------------------------------------------------------
107171d7fec4Smrg * gfx_set_video_filter
107271d7fec4Smrg *
107371d7fec4Smrg * This routine enables or disables the video overlay filters.
107471d7fec4Smrg *---------------------------------------------------------------------------
107571d7fec4Smrg */
107671d7fec4Smrg#if GFX_VIDEO_DYNAMIC
107771d7fec4Smrgint
107871d7fec4Smrgsc1200_set_video_filter(int xfilter, int yfilter)
107971d7fec4Smrg#else
108071d7fec4Smrgint
108171d7fec4Smrggfx_set_video_filter(int xfilter, int yfilter)
108271d7fec4Smrg#endif
108371d7fec4Smrg{
108471d7fec4Smrg   unsigned long vcfg = 0;
108571d7fec4Smrg
108671d7fec4Smrg   /* ENABLE OR DISABLE SC1200 VIDEO OVERLAY FILTERS */
108771d7fec4Smrg
108871d7fec4Smrg   vcfg = READ_VID32(SC1200_VIDEO_CONFIG);
108971d7fec4Smrg   vcfg &= ~(SC1200_VCFG_X_FILTER_EN | SC1200_VCFG_Y_FILTER_EN);
109071d7fec4Smrg   if (xfilter)
109171d7fec4Smrg      vcfg |= SC1200_VCFG_X_FILTER_EN;
109271d7fec4Smrg   if (yfilter)
109371d7fec4Smrg      vcfg |= SC1200_VCFG_Y_FILTER_EN;
109471d7fec4Smrg   WRITE_VID32(SC1200_VIDEO_CONFIG, vcfg);
109571d7fec4Smrg   return (0);
109671d7fec4Smrg}
109771d7fec4Smrg
109871d7fec4Smrg/*---------------------------------------------------------------------------
109971d7fec4Smrg * gfx_set_video_palette
110071d7fec4Smrg *
110171d7fec4Smrg * This routine loads the video hardware palette.  If a NULL pointer is
110271d7fec4Smrg * specified, the palette is bypassed (for SC1200, this means loading the
110371d7fec4Smrg * palette with identity values).
110471d7fec4Smrg *---------------------------------------------------------------------------
110571d7fec4Smrg */
110671d7fec4Smrg#if GFX_VIDEO_DYNAMIC
110771d7fec4Smrgint
110871d7fec4Smrgsc1200_set_video_palette(unsigned long *palette)
110971d7fec4Smrg#else
111071d7fec4Smrgint
111171d7fec4Smrggfx_set_video_palette(unsigned long *palette)
111271d7fec4Smrg#endif
111371d7fec4Smrg{
111471d7fec4Smrg   unsigned long i, entry;
111571d7fec4Smrg
111671d7fec4Smrg   /* WAIT FOR VERTICAL BLANK TO END */
111771d7fec4Smrg   /* Otherwise palette will not be written properly. */
111871d7fec4Smrg
111971d7fec4Smrg   if (gfx_test_timing_active()) {
112071d7fec4Smrg      if (gfx_test_vertical_active()) {
112171d7fec4Smrg	 while (gfx_test_vertical_active()) ;
112271d7fec4Smrg      }
112371d7fec4Smrg      while (!gfx_test_vertical_active()) ;
112471d7fec4Smrg   }
112571d7fec4Smrg
112671d7fec4Smrg   /* LOAD SC1200 VIDEO PALETTE */
112771d7fec4Smrg
112871d7fec4Smrg   WRITE_VID32(SC1200_PALETTE_ADDRESS, 0);
112971d7fec4Smrg   for (i = 0; i < 256; i++) {
113071d7fec4Smrg      if (palette)
113171d7fec4Smrg	 entry = palette[i];
113271d7fec4Smrg      else
113371d7fec4Smrg	 entry = (i << 8) | (i << 16) | (i << 24);
113471d7fec4Smrg      WRITE_VID32(SC1200_PALETTE_DATA, entry);
113571d7fec4Smrg   }
113671d7fec4Smrg   return (0);
113771d7fec4Smrg}
113871d7fec4Smrg
113971d7fec4Smrg/*---------------------------------------------------------------------------
114071d7fec4Smrg * gfx_set_video_palette_entry
114171d7fec4Smrg *
114271d7fec4Smrg * This routine loads a single entry of the video hardware palette.
114371d7fec4Smrg *---------------------------------------------------------------------------
114471d7fec4Smrg */
114571d7fec4Smrg#if GFX_VIDEO_DYNAMIC
114671d7fec4Smrgint
114771d7fec4Smrgsc1200_set_video_palette_entry(unsigned long index, unsigned long palette)
114871d7fec4Smrg#else
114971d7fec4Smrgint
115071d7fec4Smrggfx_set_video_palette_entry(unsigned long index, unsigned long palette)
115171d7fec4Smrg#endif
115271d7fec4Smrg{
115371d7fec4Smrg   if (index > 0xFF)
115471d7fec4Smrg      return GFX_STATUS_BAD_PARAMETER;
115571d7fec4Smrg
115671d7fec4Smrg   /* WAIT FOR VERTICAL BLANK TO END */
115771d7fec4Smrg   /* Otherwise palette will not be written properly. */
115871d7fec4Smrg
115971d7fec4Smrg   if (gfx_test_timing_active()) {
116071d7fec4Smrg      if (gfx_test_vertical_active()) {
116171d7fec4Smrg	 while (gfx_test_vertical_active()) ;
116271d7fec4Smrg      }
116371d7fec4Smrg      while (!gfx_test_vertical_active()) ;
116471d7fec4Smrg   }
116571d7fec4Smrg
116671d7fec4Smrg   /* SET A SINGLE ENTRY */
116771d7fec4Smrg
116871d7fec4Smrg   WRITE_VID32(SC1200_PALETTE_ADDRESS, index);
116971d7fec4Smrg   WRITE_VID32(SC1200_PALETTE_DATA, palette);
117071d7fec4Smrg
117171d7fec4Smrg   return (0);
117271d7fec4Smrg}
117371d7fec4Smrg
117471d7fec4Smrg/*---------------------------------------------------------------------------
117571d7fec4Smrg * gfx_set_video_request()
117671d7fec4Smrg *
117771d7fec4Smrg * This routine sets the horizontal (pixel) and vertical (line) video request
117871d7fec4Smrg * values.
117971d7fec4Smrg *---------------------------------------------------------------------------
118071d7fec4Smrg */
118171d7fec4Smrg#if GFX_VIDEO_DYNAMIC
118271d7fec4Smrgint
118371d7fec4Smrgsc1200_set_video_request(short x, short y)
118471d7fec4Smrg#else
118571d7fec4Smrgint
118671d7fec4Smrggfx_set_video_request(short x, short y)
118771d7fec4Smrg#endif
118871d7fec4Smrg{
118971d7fec4Smrg   /* SET SC1200 VIDEO REQUEST */
119071d7fec4Smrg
119171d7fec4Smrg   x += gfx_get_htotal() - gfx_get_hsync_end() - 2;
119271d7fec4Smrg   y += gfx_get_vtotal() - gfx_get_vsync_end() + 1;
119371d7fec4Smrg
119471d7fec4Smrg   if ((x < 0) || (x > SC1200_VIDEO_REQUEST_MASK) ||
119571d7fec4Smrg       (y < 0) || (y > SC1200_VIDEO_REQUEST_MASK))
119671d7fec4Smrg      return GFX_STATUS_BAD_PARAMETER;
119771d7fec4Smrg
119871d7fec4Smrg   WRITE_VID32(SC1200_VIDEO_REQUEST,
119971d7fec4Smrg	       ((unsigned long)x << SC1200_VIDEO_X_REQUEST_POS) |
120071d7fec4Smrg	       ((unsigned long)y << SC1200_VIDEO_Y_REQUEST_POS));
120171d7fec4Smrg   return (0);
120271d7fec4Smrg}
120371d7fec4Smrg
120471d7fec4Smrg/*---------------------------------------------------------------------------
120571d7fec4Smrg * gfx_set_video_source()
120671d7fec4Smrg *
120771d7fec4Smrg * This routine sets the video source to either memory or Direct VIP.
120871d7fec4Smrg *---------------------------------------------------------------------------
120971d7fec4Smrg */
121071d7fec4Smrg#if GFX_VIDEO_DYNAMIC
121171d7fec4Smrgint
121271d7fec4Smrgsc1200_set_video_source(VideoSourceType source)
121371d7fec4Smrg#else
121471d7fec4Smrgint
121571d7fec4Smrggfx_set_video_source(VideoSourceType source)
121671d7fec4Smrg#endif
121771d7fec4Smrg{
121871d7fec4Smrg   unsigned long display_mode;
121971d7fec4Smrg
122071d7fec4Smrg   display_mode = READ_VID32(SC1200_VIDEO_DISPLAY_MODE);
122171d7fec4Smrg
122271d7fec4Smrg   /* SET SC1200 VIDEO SOURCE */
122371d7fec4Smrg   switch (source) {
122471d7fec4Smrg   case VIDEO_SOURCE_MEMORY:
122571d7fec4Smrg      WRITE_VID32(SC1200_VIDEO_DISPLAY_MODE,
122671d7fec4Smrg		  (display_mode & ~SC1200_VIDEO_SOURCE_MASK) |
122771d7fec4Smrg		  SC1200_VIDEO_SOURCE_GX1);
122871d7fec4Smrg      break;
122971d7fec4Smrg   case VIDEO_SOURCE_DVIP:
123071d7fec4Smrg      WRITE_VID32(SC1200_VIDEO_DISPLAY_MODE,
123171d7fec4Smrg		  (display_mode & ~SC1200_VIDEO_SOURCE_MASK) |
123271d7fec4Smrg		  SC1200_VIDEO_SOURCE_DVIP);
123371d7fec4Smrg      break;
123471d7fec4Smrg   default:
123571d7fec4Smrg      return GFX_STATUS_BAD_PARAMETER;
123671d7fec4Smrg   }
123771d7fec4Smrg   return (0);
123871d7fec4Smrg}
123971d7fec4Smrg
124071d7fec4Smrg/*---------------------------------------------------------------------------
124171d7fec4Smrg * gfx_set_vbi_source()
124271d7fec4Smrg *
124371d7fec4Smrg * This routine sets the vbi source to either memory or Direct VIP.
124471d7fec4Smrg *---------------------------------------------------------------------------
124571d7fec4Smrg */
124671d7fec4Smrg#if GFX_VIDEO_DYNAMIC
124771d7fec4Smrgint
124871d7fec4Smrgsc1200_set_vbi_source(VbiSourceType source)
124971d7fec4Smrg#else
125071d7fec4Smrgint
125171d7fec4Smrggfx_set_vbi_source(VbiSourceType source)
125271d7fec4Smrg#endif
125371d7fec4Smrg{
125471d7fec4Smrg   unsigned long display_mode;
125571d7fec4Smrg
125671d7fec4Smrg   display_mode = READ_VID32(SC1200_VIDEO_DISPLAY_MODE);
125771d7fec4Smrg
125871d7fec4Smrg   /* SET SC1200 VBI SOURCE */
125971d7fec4Smrg   switch (source) {
126071d7fec4Smrg   case VBI_SOURCE_MEMORY:
126171d7fec4Smrg      WRITE_VID32(SC1200_VIDEO_DISPLAY_MODE,
126271d7fec4Smrg		  (display_mode & ~SC1200_VBI_SOURCE_MASK) |
126371d7fec4Smrg		  SC1200_VBI_SOURCE_GX1);
126471d7fec4Smrg      break;
126571d7fec4Smrg   case VBI_SOURCE_DVIP:
126671d7fec4Smrg      WRITE_VID32(SC1200_VIDEO_DISPLAY_MODE,
126771d7fec4Smrg		  (display_mode & ~SC1200_VBI_SOURCE_MASK) |
126871d7fec4Smrg		  SC1200_VBI_SOURCE_DVIP);
126971d7fec4Smrg      break;
127071d7fec4Smrg   default:
127171d7fec4Smrg      return GFX_STATUS_BAD_PARAMETER;
127271d7fec4Smrg   }
127371d7fec4Smrg   return (0);
127471d7fec4Smrg}
127571d7fec4Smrg
127671d7fec4Smrg/*---------------------------------------------------------------------------
127771d7fec4Smrg * gfx_set_vbi_lines()
127871d7fec4Smrg *
127971d7fec4Smrg * This routine sets the VBI lines to pass to the TV encoder.
128071d7fec4Smrg *---------------------------------------------------------------------------
128171d7fec4Smrg */
128271d7fec4Smrg#if GFX_VIDEO_DYNAMIC
128371d7fec4Smrgint
128471d7fec4Smrgsc1200_set_vbi_lines(unsigned long even, unsigned long odd)
128571d7fec4Smrg#else
128671d7fec4Smrgint
128771d7fec4Smrggfx_set_vbi_lines(unsigned long even, unsigned long odd)
128871d7fec4Smrg#endif
128971d7fec4Smrg{
129071d7fec4Smrg   /* SET SC1200 VBI LINES */
129171d7fec4Smrg   WRITE_VID32(SC1200_VIDEO_EVEN_VBI_LINE_ENABLE,
129271d7fec4Smrg	       even & SC1200_VIDEO_VBI_LINE_ENABLE_MASK);
129371d7fec4Smrg   WRITE_VID32(SC1200_VIDEO_ODD_VBI_LINE_ENABLE,
129471d7fec4Smrg	       odd & SC1200_VIDEO_VBI_LINE_ENABLE_MASK);
129571d7fec4Smrg   return (0);
129671d7fec4Smrg}
129771d7fec4Smrg
129871d7fec4Smrg/*---------------------------------------------------------------------------
129971d7fec4Smrg * gfx_set_vbi_total()
130071d7fec4Smrg *
130171d7fec4Smrg * This routine sets the total number of VBI bytes for each field.
130271d7fec4Smrg * The total is needed when both VBI and active video are received from memory.
130371d7fec4Smrg *---------------------------------------------------------------------------
130471d7fec4Smrg */
130571d7fec4Smrg#if GFX_VIDEO_DYNAMIC
130671d7fec4Smrgint
130771d7fec4Smrgsc1200_set_vbi_total(unsigned long even, unsigned long odd)
130871d7fec4Smrg#else
130971d7fec4Smrgint
131071d7fec4Smrggfx_set_vbi_total(unsigned long even, unsigned long odd)
131171d7fec4Smrg#endif
131271d7fec4Smrg{
131371d7fec4Smrg   /* SET SC1200 VBI TOTAL */
131471d7fec4Smrg   WRITE_VID32(SC1200_VIDEO_EVEN_VBI_TOTAL_COUNT,
131571d7fec4Smrg	       even & SC1200_VIDEO_VBI_TOTAL_COUNT_MASK);
131671d7fec4Smrg   WRITE_VID32(SC1200_VIDEO_ODD_VBI_TOTAL_COUNT,
131771d7fec4Smrg	       odd & SC1200_VIDEO_VBI_TOTAL_COUNT_MASK);
131871d7fec4Smrg   return (0);
131971d7fec4Smrg}
132071d7fec4Smrg
132171d7fec4Smrg/*---------------------------------------------------------------------------
132271d7fec4Smrg * gfx_set_video_interlaced()
132371d7fec4Smrg *
132471d7fec4Smrg * This routine configures the video processor video overlay mode to be
132571d7fec4Smrg * interlaced YUV.
132671d7fec4Smrg *---------------------------------------------------------------------------
132771d7fec4Smrg */
132871d7fec4Smrg#if GFX_VIDEO_DYNAMIC
132971d7fec4Smrgint
133071d7fec4Smrgsc1200_set_video_interlaced(int enable)
133171d7fec4Smrg#else
133271d7fec4Smrgint
133371d7fec4Smrggfx_set_video_interlaced(int enable)
133471d7fec4Smrg#endif
133571d7fec4Smrg{
133671d7fec4Smrg   unsigned long control;
133771d7fec4Smrg
133871d7fec4Smrg   control = READ_VID32(SC1200_VID_ALPHA_CONTROL);
133971d7fec4Smrg   /* SET INTERLACED VIDEO */
134071d7fec4Smrg   if (enable)
134171d7fec4Smrg      WRITE_VID32(SC1200_VID_ALPHA_CONTROL,
134271d7fec4Smrg		  control | SC1200_VIDEO_IS_INTERLACED);
134371d7fec4Smrg   else
134471d7fec4Smrg      WRITE_VID32(SC1200_VID_ALPHA_CONTROL,
134571d7fec4Smrg		  control & ~SC1200_VIDEO_IS_INTERLACED);
134671d7fec4Smrg   return (0);
134771d7fec4Smrg}
134871d7fec4Smrg
134971d7fec4Smrg/*---------------------------------------------------------------------------
135071d7fec4Smrg * gfx_set_color_space_YUV()
135171d7fec4Smrg *
135271d7fec4Smrg * This routine configures the video processor to process graphics and video
135371d7fec4Smrg * in either YUV or RGB color space. The mode should be set to tune image
135471d7fec4Smrg * quality.
135571d7fec4Smrg * Setting "enable" to TRUE improves image quality on TV,
135671d7fec4Smrg * but in this mode colors on CRT will not be correct.
135771d7fec4Smrg *---------------------------------------------------------------------------
135871d7fec4Smrg */
135971d7fec4Smrg#if GFX_VIDEO_DYNAMIC
136071d7fec4Smrgint
136171d7fec4Smrgsc1200_set_color_space_YUV(int enable)
136271d7fec4Smrg#else
136371d7fec4Smrgint
136471d7fec4Smrggfx_set_color_space_YUV(int enable)
136571d7fec4Smrg#endif
136671d7fec4Smrg{
136771d7fec4Smrg   unsigned long control;
136871d7fec4Smrg
136971d7fec4Smrg   control = READ_VID32(SC1200_VID_ALPHA_CONTROL);
137071d7fec4Smrg
137171d7fec4Smrg   /* SET SC1200 VIDEO COLOR SPACE TO YUV OR RGB */
137271d7fec4Smrg
137371d7fec4Smrg   if (enable) {
137471d7fec4Smrg      /* ENABLE YUV BLENDING */
137571d7fec4Smrg      /* YUV blending cannot be enabled in RGB video formats */
137671d7fec4Smrg
137771d7fec4Smrg      control |= SC1200_CSC_GFX_RGB_TO_YUV;	/* Convert graphics to YUV */
137871d7fec4Smrg      control &= ~SC1200_CSC_VIDEO_YUV_TO_RGB;	/* Leave video in YUV      */
137971d7fec4Smrg
138071d7fec4Smrg      if (control & SC1200_VIDEO_INPUT_IS_RGB)
138171d7fec4Smrg	 return (GFX_STATUS_UNSUPPORTED);	/* Can't convert video from RGB to YUV */
138271d7fec4Smrg   } else {
138371d7fec4Smrg      /* RGB BLENDING */
138471d7fec4Smrg
138571d7fec4Smrg      control &= ~SC1200_CSC_GFX_RGB_TO_YUV;	/* Leave graphics in RGB */
138671d7fec4Smrg      if (control & SC1200_VIDEO_INPUT_IS_RGB)
138771d7fec4Smrg	 control &= ~SC1200_CSC_VIDEO_YUV_TO_RGB;	/* Leave video in RGB */
138871d7fec4Smrg      else
138971d7fec4Smrg	 control |= SC1200_CSC_VIDEO_YUV_TO_RGB;	/* Convert video to RGB */
139071d7fec4Smrg   }
139171d7fec4Smrg   WRITE_VID32(SC1200_VID_ALPHA_CONTROL, control);
139271d7fec4Smrg   return (0);
139371d7fec4Smrg}
139471d7fec4Smrg
139571d7fec4Smrg/*---------------------------------------------------------------------------
139671d7fec4Smrg * gfx_set_vertical_scaler_offset()
139771d7fec4Smrg *
139871d7fec4Smrg * This routine sets the value by which the odd frame is shifted with respect
139971d7fec4Smrg * to the even frame. This is useful for de-interlacing in Bob method, by
140071d7fec4Smrg * setting the shift value to be one line.
140171d7fec4Smrg * If offset is 0, no shifting occurs.
140271d7fec4Smrg *---------------------------------------------------------------------------
140371d7fec4Smrg */
140471d7fec4Smrg#if GFX_VIDEO_DYNAMIC
140571d7fec4Smrgint
140671d7fec4Smrgsc1200_set_vertical_scaler_offset(char offset)
140771d7fec4Smrg#else
140871d7fec4Smrgint
140971d7fec4Smrggfx_set_vertical_scaler_offset(char offset)
141071d7fec4Smrg#endif
141171d7fec4Smrg{
141271d7fec4Smrg   unsigned long control;
141371d7fec4Smrg
141471d7fec4Smrg   control = READ_VID32(SC1200_VID_ALPHA_CONTROL);
141571d7fec4Smrg   if (offset == 1) {
141671d7fec4Smrg      control &= ~SC1200_VERTICAL_SCALER_SHIFT_MASK;	/* Clear shifting value */
141771d7fec4Smrg      control |= SC1200_VERTICAL_SCALER_SHIFT_INIT;	/* Set shifting value */
141871d7fec4Smrg      control |= SC1200_VERTICAL_SCALER_SHIFT_EN;	/* Enable odd frame shifting */
141971d7fec4Smrg   } else if (offset == 0) {
142071d7fec4Smrg      control &= ~SC1200_VERTICAL_SCALER_SHIFT_EN;	/* No shifting occurs */
142171d7fec4Smrg      control &= ~SC1200_VERTICAL_SCALER_SHIFT_MASK;	/* Clear shifting value */
142271d7fec4Smrg   } else
142371d7fec4Smrg      return (GFX_STATUS_BAD_PARAMETER);	/* TODO: how to program other values ? */
142471d7fec4Smrg   WRITE_VID32(SC1200_VID_ALPHA_CONTROL, control);
142571d7fec4Smrg   return (0);
142671d7fec4Smrg}
142771d7fec4Smrg
142871d7fec4Smrg/*---------------------------------------------------------------------------
142971d7fec4Smrg * gfx_set_top_line_in_odd()
143071d7fec4Smrg *
143171d7fec4Smrg * This routine sets the field in which the top line of input video resides.
143271d7fec4Smrg * If enable is "0", this is the even field (default). [not to be confused
143371d7fec4Smrg * with the odd field being the top field on TV].
143471d7fec4Smrg * If enable is "1", this is the odd field.
143571d7fec4Smrg * Use enable "1" for input devices whose field indication is reversed from
143671d7fec4Smrg * normal, i.e. an indication of "odd" field is given for even field data,
143771d7fec4Smrg * and vice versa.
143871d7fec4Smrg * This setting affects the video processor only when it is in either interlaced
143971d7fec4Smrg * or Bob (scaler offset active) modes.
144071d7fec4Smrg  *---------------------------------------------------------------------------
144171d7fec4Smrg */
144271d7fec4Smrg#if GFX_VIDEO_DYNAMIC
144371d7fec4Smrgint
144471d7fec4Smrgsc1200_set_top_line_in_odd(int enable)
144571d7fec4Smrg#else
144671d7fec4Smrgint
144771d7fec4Smrggfx_set_top_line_in_odd(int enable)
144871d7fec4Smrg#endif
144971d7fec4Smrg{
145071d7fec4Smrg   unsigned long control;
145171d7fec4Smrg
145271d7fec4Smrg   control = READ_VID32(SC1200_VID_ALPHA_CONTROL);
145371d7fec4Smrg   if (enable)
145471d7fec4Smrg      control |= SC1200_TOP_LINE_IN_ODD;	/* Set shifting value */
145571d7fec4Smrg   else
145671d7fec4Smrg      control &= ~SC1200_TOP_LINE_IN_ODD;	/* No shifting occurs */
145771d7fec4Smrg   WRITE_VID32(SC1200_VID_ALPHA_CONTROL, control);
145871d7fec4Smrg   return (0);
145971d7fec4Smrg}
146071d7fec4Smrg
146171d7fec4Smrg/*---------------------------------------------------------------------------
146271d7fec4Smrg * gfx_set_genlock_delay()
146371d7fec4Smrg *
146471d7fec4Smrg * This routine sets the delay between VIP VSYNC and display controller VSYNC.
146571d7fec4Smrg * The delay is in 27 MHz clocks.
146671d7fec4Smrg *---------------------------------------------------------------------------
146771d7fec4Smrg */
146871d7fec4Smrg#if GFX_VIDEO_DYNAMIC
146971d7fec4Smrgint
147071d7fec4Smrgsc1200_set_genlock_delay(unsigned long delay)
147171d7fec4Smrg#else
147271d7fec4Smrgint
147371d7fec4Smrggfx_set_genlock_delay(unsigned long delay)
147471d7fec4Smrg#endif
147571d7fec4Smrg{
147671d7fec4Smrg   /* SET SC1200 GENLOCK DELAY */
147771d7fec4Smrg   WRITE_VID32(SC1200_GENLOCK_DELAY, delay & SC1200_GENLOCK_DELAY_MASK);
147871d7fec4Smrg   return (0);
147971d7fec4Smrg}
148071d7fec4Smrg
148171d7fec4Smrg/*---------------------------------------------------------------------------
148271d7fec4Smrg * gfx_set_genlock_enable()
148371d7fec4Smrg *
148471d7fec4Smrg * This routine sets and configures the genlock according to the flags parameter.
148571d7fec4Smrg * Flags value of 0 disables genlock and resets its configuration.
148671d7fec4Smrg *---------------------------------------------------------------------------
148771d7fec4Smrg */
148871d7fec4Smrg#if GFX_VIDEO_DYNAMIC
148971d7fec4Smrgint
149071d7fec4Smrgsc1200_set_genlock_enable(int flags)
149171d7fec4Smrg#else
149271d7fec4Smrgint
149371d7fec4Smrggfx_set_genlock_enable(int flags)
149471d7fec4Smrg#endif
149571d7fec4Smrg{
149671d7fec4Smrg   unsigned long genlock = 0;
149771d7fec4Smrg
149871d7fec4Smrg   if (flags) {
149971d7fec4Smrg      /* SET SC1200 GENLOCK CONFIGURATION */
150071d7fec4Smrg      if (flags & GENLOCK_SINGLE)
150171d7fec4Smrg	 genlock |= SC1200_GENLOCK_SINGLE_ENABLE;
150271d7fec4Smrg      if (flags & GENLOCK_FIELD_SYNC)
150371d7fec4Smrg	 genlock |= SC1200_GENLOCK_FIELD_SYNC_ENABLE;
150471d7fec4Smrg      if (flags & GENLOCK_CONTINUOUS)
150571d7fec4Smrg	 genlock |= SC1200_GENLOCK_CONTINUOUS_ENABLE;
150671d7fec4Smrg      if (flags & GENLOCK_SYNCED_EDGE_FALLING)
150771d7fec4Smrg	 genlock |= SC1200_GENLOCK_GX_VSYNC_FALLING_EDGE;
150871d7fec4Smrg      if (flags & GENLOCK_SYNCING_EDGE_FALLING)
150971d7fec4Smrg	 genlock |= SC1200_GENLOCK_VIP_VSYNC_FALLING_EDGE;
151071d7fec4Smrg      if (flags & GENLOCK_TIMEOUT)
151171d7fec4Smrg	 genlock |= SC1200_GENLOCK_TIMEOUT_ENABLE;
151271d7fec4Smrg      if (flags & GENLOCK_TVENC_RESET_EVEN_FIELD)
151371d7fec4Smrg	 genlock |= SC1200_GENLOCK_TVENC_RESET_EVEN_FIELD;
151471d7fec4Smrg      if (flags & GENLOCK_TVENC_RESET_BEFORE_DELAY)
151571d7fec4Smrg	 genlock |= SC1200_GENLOCK_TVENC_RESET_BEFORE_DELAY;
151671d7fec4Smrg      if (flags & GENLOCK_TVENC_RESET)
151771d7fec4Smrg	 genlock |= SC1200_GENLOCK_TVENC_RESET_ENABLE;
151871d7fec4Smrg      if (flags & GENLOCK_SYNC_TO_TVENC)
151971d7fec4Smrg	 genlock |= SC1200_GENLOCK_SYNC_TO_TVENC;
152071d7fec4Smrg   }
152171d7fec4Smrg   WRITE_VID32(SC1200_GENLOCK, genlock);
152271d7fec4Smrg   return (0);
152371d7fec4Smrg}
152471d7fec4Smrg
152571d7fec4Smrg/*---------------------------------------------------------------------------
152671d7fec4Smrg * gfx_set_video_cursor()
152771d7fec4Smrg *
152871d7fec4Smrg * This routine configures the video hardware cursor.
152971d7fec4Smrg * If the "mask"ed bits in the graphics pixel match "key", then either "color1"
153071d7fec4Smrg * or "color2" will be used for this pixel, according to the value of bit
153171d7fec4Smrg * number "select_color2" of the graphics pixel.
153271d7fec4Smrg *
153371d7fec4Smrg * key - 24 bit RGB value
153471d7fec4Smrg * mask - 24 bit mask
153571d7fec4Smrg * color1, color2 - RGB or YUV, depending on the current color space conversion
153671d7fec4Smrg * select_color2 - value between 0 to 23
153771d7fec4Smrg *
153871d7fec4Smrg * To disable match, a "mask" and "key" value of 0xffffff should be set,
153971d7fec4Smrg * because the graphics pixels incoming to the video processor have maximum 16
154071d7fec4Smrg * bits set (0xF8FCF8).
154171d7fec4Smrg *
154271d7fec4Smrg * This feature is useful for disabling alpha blending of the cursor.
154371d7fec4Smrg * Otherwise cursor image would be blurred (or completely invisible if video
154471d7fec4Smrg * alpha is maximum value).
154571d7fec4Smrg * Note: the cursor pixel replacements take place both inside and outside the
154671d7fec4Smrg * video overlay window.
154771d7fec4Smrg *---------------------------------------------------------------------------
154871d7fec4Smrg */
154971d7fec4Smrg#if GFX_VIDEO_DYNAMIC
155071d7fec4Smrgint
155171d7fec4Smrgsc1200_set_video_cursor(unsigned long key, unsigned long mask,
155271d7fec4Smrg			unsigned short select_color2, unsigned long color1,
155371d7fec4Smrg			unsigned long color2)
155471d7fec4Smrg#else
155571d7fec4Smrgint
155671d7fec4Smrggfx_set_video_cursor(unsigned long key, unsigned long mask,
155771d7fec4Smrg		     unsigned short select_color2, unsigned long color1,
155871d7fec4Smrg		     unsigned long color2)
155971d7fec4Smrg#endif
156071d7fec4Smrg{
156171d7fec4Smrg   if (select_color2 > SC1200_CURSOR_COLOR_BITS)
156271d7fec4Smrg      return GFX_STATUS_BAD_PARAMETER;
156371d7fec4Smrg   key = (key & SC1200_COLOR_MASK) | ((unsigned long)select_color2 <<
156471d7fec4Smrg				      SC1200_CURSOR_COLOR_KEY_OFFSET_POS);
156571d7fec4Smrg   WRITE_VID32(SC1200_CURSOR_COLOR_KEY, key);
156671d7fec4Smrg   WRITE_VID32(SC1200_CURSOR_COLOR_MASK, mask);
156771d7fec4Smrg   WRITE_VID32(SC1200_CURSOR_COLOR_1, color1);
156871d7fec4Smrg   WRITE_VID32(SC1200_CURSOR_COLOR_2, color2);
156971d7fec4Smrg   return (0);
157071d7fec4Smrg}
157171d7fec4Smrg
157271d7fec4Smrg/*---------------------------------------------------------------------------
157371d7fec4Smrg * gfx_set_alpha_enable
157471d7fec4Smrg *
157571d7fec4Smrg * This routine enables or disables the currently selected alpha region.
157671d7fec4Smrg *---------------------------------------------------------------------------
157771d7fec4Smrg */
157871d7fec4Smrg#if GFX_VIDEO_DYNAMIC
157971d7fec4Smrgint
158071d7fec4Smrgsc1200_set_alpha_enable(int enable)
158171d7fec4Smrg#else
158271d7fec4Smrgint
158371d7fec4Smrggfx_set_alpha_enable(int enable)
158471d7fec4Smrg#endif
158571d7fec4Smrg{
158671d7fec4Smrg   unsigned long address = 0, value = 0;
158771d7fec4Smrg
158871d7fec4Smrg   if (gfx_alpha_select > 2)
158971d7fec4Smrg      return (GFX_STATUS_UNSUPPORTED);
159071d7fec4Smrg   address = SC1200_ALPHA_CONTROL_1 + ((unsigned long)gfx_alpha_select << 4);
159171d7fec4Smrg   value = READ_VID32(address);
159271d7fec4Smrg   if (enable)
159371d7fec4Smrg      value |= (SC1200_ACTRL_WIN_ENABLE | SC1200_ACTRL_LOAD_ALPHA);
159471d7fec4Smrg   else
159571d7fec4Smrg      value &= ~(SC1200_ACTRL_WIN_ENABLE);
159671d7fec4Smrg   WRITE_VID32(address, value);
159771d7fec4Smrg   return (GFX_STATUS_OK);
159871d7fec4Smrg}
159971d7fec4Smrg
160071d7fec4Smrg/*---------------------------------------------------------------------------
160171d7fec4Smrg * gfx_set_alpha_window
160271d7fec4Smrg *
160371d7fec4Smrg * This routine sets the size of the currently selected alpha region.
160471d7fec4Smrg * Note: "x" and "y" are signed to enable using negative values needed for
160571d7fec4Smrg * implementing workarounds of hardware issues.
160671d7fec4Smrg *---------------------------------------------------------------------------
160771d7fec4Smrg */
160871d7fec4Smrg#if GFX_VIDEO_DYNAMIC
160971d7fec4Smrgint
161071d7fec4Smrgsc1200_set_alpha_window(short x, short y,
161171d7fec4Smrg			unsigned short width, unsigned short height)
161271d7fec4Smrg#else
161371d7fec4Smrgint
161471d7fec4Smrggfx_set_alpha_window(short x, short y,
161571d7fec4Smrg		     unsigned short width, unsigned short height)
161671d7fec4Smrg#endif
161771d7fec4Smrg{
161871d7fec4Smrg   unsigned long address = 0;
161971d7fec4Smrg
162071d7fec4Smrg   /* CHECK FOR CLIPPING */
162171d7fec4Smrg
162271d7fec4Smrg   if ((x + width) > gfx_get_hactive())
162371d7fec4Smrg      width = gfx_get_hactive() - x;
162471d7fec4Smrg   if ((y + height) > gfx_get_vactive())
162571d7fec4Smrg      height = gfx_get_vactive() - y;
162671d7fec4Smrg
162771d7fec4Smrg   /* ADJUST POSITIONS */
162871d7fec4Smrg
162971d7fec4Smrg   x += gfx_get_htotal() - gfx_get_hsync_end() - 2;
163071d7fec4Smrg   y += gfx_get_vtotal() - gfx_get_vsync_end() + 1;
163171d7fec4Smrg
163271d7fec4Smrg   if (gfx_alpha_select > 2)
163371d7fec4Smrg      return (GFX_STATUS_UNSUPPORTED);
163471d7fec4Smrg   address = SC1200_ALPHA_XPOS_1 + ((unsigned long)gfx_alpha_select << 4);
163571d7fec4Smrg
163671d7fec4Smrg   /* End positions in register are non-inclusive (one more than the actual end) */
163771d7fec4Smrg
163871d7fec4Smrg   WRITE_VID32(address, (unsigned long)x |
163971d7fec4Smrg	       ((unsigned long)(x + width) << 16));
164071d7fec4Smrg   WRITE_VID32(address + 4l, (unsigned long)y |
164171d7fec4Smrg	       ((unsigned long)(y + height) << 16));
164271d7fec4Smrg   return (GFX_STATUS_OK);
164371d7fec4Smrg}
164471d7fec4Smrg
164571d7fec4Smrg/*---------------------------------------------------------------------------
164671d7fec4Smrg * gfx_set_alpha_value
164771d7fec4Smrg *
164871d7fec4Smrg * This routine sets the alpha value for the currently selected alpha
164971d7fec4Smrg * region.  It also specifies an increment/decrement value for fading.
165071d7fec4Smrg *---------------------------------------------------------------------------
165171d7fec4Smrg */
165271d7fec4Smrg#if GFX_VIDEO_DYNAMIC
165371d7fec4Smrgint
165471d7fec4Smrgsc1200_set_alpha_value(unsigned char alpha, char delta)
165571d7fec4Smrg#else
165671d7fec4Smrgint
165771d7fec4Smrggfx_set_alpha_value(unsigned char alpha, char delta)
165871d7fec4Smrg#endif
165971d7fec4Smrg{
166071d7fec4Smrg   unsigned long address = 0, value = 0;
166171d7fec4Smrg   unsigned char new_value = 0;
166271d7fec4Smrg   int loop = 1;
166371d7fec4Smrg
166471d7fec4Smrg   if (gfx_alpha_select > 2)
166571d7fec4Smrg      return (GFX_STATUS_UNSUPPORTED);
166671d7fec4Smrg   address = SC1200_ALPHA_CONTROL_1 + ((unsigned long)gfx_alpha_select << 4);
166771d7fec4Smrg   value = READ_VID32(address);
166871d7fec4Smrg   value &= SC1200_ACTRL_WIN_ENABLE;	/* keep only enable bit */
166971d7fec4Smrg   value |= (unsigned long)alpha;
167071d7fec4Smrg   value |= (((unsigned long)delta) & 0xff) << 8;
167171d7fec4Smrg   value |= SC1200_ACTRL_LOAD_ALPHA;
167271d7fec4Smrg   WRITE_VID32(address, value);
167371d7fec4Smrg
167471d7fec4Smrg   /* WORKAROUND FOR ISSUE #1187 */
167571d7fec4Smrg   /* Need to verify that the alpha operation succeeded */
167671d7fec4Smrg
167771d7fec4Smrg   while (1) {
167871d7fec4Smrg      /* WAIT FOR VERTICAL BLANK TO END */
167971d7fec4Smrg      if (gfx_test_timing_active()) {
168071d7fec4Smrg	 if (gfx_test_vertical_active())
168171d7fec4Smrg	    while (gfx_test_vertical_active()) ;
168271d7fec4Smrg	 while (!gfx_test_vertical_active()) ;
168371d7fec4Smrg      }
168471d7fec4Smrg      new_value =
168571d7fec4Smrg	    (unsigned
168671d7fec4Smrg	     char)((READ_VID32(SC1200_ALPHA_WATCH) >> (gfx_alpha_select << 3))
168771d7fec4Smrg		   & 0xff);
168871d7fec4Smrg      if (new_value == alpha)
168971d7fec4Smrg	 return GFX_STATUS_OK;
169071d7fec4Smrg      if (++loop > 10)
169171d7fec4Smrg	 return GFX_STATUS_ERROR;
169271d7fec4Smrg      WRITE_VID32(address, value);
169371d7fec4Smrg   }
169471d7fec4Smrg}
169571d7fec4Smrg
169671d7fec4Smrg/*---------------------------------------------------------------------------
169771d7fec4Smrg * gfx_set_alpha_priority
169871d7fec4Smrg *
169971d7fec4Smrg * This routine sets the priority of the currently selected alpha region.
170071d7fec4Smrg * A higher value indicates a higher priority.
170171d7fec4Smrg * Note: Priority of enabled alpha windows must be different.
170271d7fec4Smrg *---------------------------------------------------------------------------
170371d7fec4Smrg */
170471d7fec4Smrg#if GFX_VIDEO_DYNAMIC
170571d7fec4Smrgint
170671d7fec4Smrgsc1200_set_alpha_priority(int priority)
170771d7fec4Smrg#else
170871d7fec4Smrgint
170971d7fec4Smrggfx_set_alpha_priority(int priority)
171071d7fec4Smrg#endif
171171d7fec4Smrg{
171271d7fec4Smrg   unsigned long pos = 0, value = 0;
171371d7fec4Smrg
171471d7fec4Smrg   if (priority > 3)
171571d7fec4Smrg      return (GFX_STATUS_BAD_PARAMETER);
171671d7fec4Smrg   if (gfx_alpha_select > 2)
171771d7fec4Smrg      return (GFX_STATUS_UNSUPPORTED);
171871d7fec4Smrg   value = READ_VID32(SC1200_VID_ALPHA_CONTROL);
171971d7fec4Smrg   pos = 16 + (gfx_alpha_select << 1);
172071d7fec4Smrg   value &= ~(0x03l << pos);
172171d7fec4Smrg   value |= (unsigned long)priority << pos;
172271d7fec4Smrg   WRITE_VID32(SC1200_VID_ALPHA_CONTROL, value);
172371d7fec4Smrg   return (GFX_STATUS_OK);
172471d7fec4Smrg}
172571d7fec4Smrg
172671d7fec4Smrg/*---------------------------------------------------------------------------
172771d7fec4Smrg * gfx_set_alpha_color
172871d7fec4Smrg *
172971d7fec4Smrg * This routine sets the color to be displayed inside the currently selected
173071d7fec4Smrg * alpha window when there is a color key match (when the alpha color
173171d7fec4Smrg * mechanism is enabled).
173271d7fec4Smrg * "color" is a 24 bit RGB value (for RGB blending) or YUV value (for YUV blending).
173371d7fec4Smrg * In Interlaced YUV blending mode, Y/2 value should be used.
173471d7fec4Smrg *---------------------------------------------------------------------------
173571d7fec4Smrg */
173671d7fec4Smrg#if GFX_VIDEO_DYNAMIC
173771d7fec4Smrgint
173871d7fec4Smrgsc1200_set_alpha_color(unsigned long color)
173971d7fec4Smrg#else
174071d7fec4Smrgint
174171d7fec4Smrggfx_set_alpha_color(unsigned long color)
174271d7fec4Smrg#endif
174371d7fec4Smrg{
174471d7fec4Smrg   unsigned long address = 0;
174571d7fec4Smrg
174671d7fec4Smrg   if (gfx_alpha_select > 2)
174771d7fec4Smrg      return (GFX_STATUS_UNSUPPORTED);
174871d7fec4Smrg   address = SC1200_ALPHA_COLOR_1 + ((unsigned long)gfx_alpha_select << 4);
174971d7fec4Smrg
175071d7fec4Smrg   /* ONLY 24 VALID BITS */
175171d7fec4Smrg   color &= 0xffffffl;
175271d7fec4Smrg
175371d7fec4Smrg   /* KEEP UPPER BYTE UNCHANGED */
175471d7fec4Smrg   WRITE_VID32(address, (color | (READ_VID32(address) & ~0xffffffl)));
175571d7fec4Smrg   return (GFX_STATUS_OK);
175671d7fec4Smrg}
175771d7fec4Smrg
175871d7fec4Smrg/*---------------------------------------------------------------------------
175971d7fec4Smrg * gfx_set_alpha_color_enable
176071d7fec4Smrg *
176171d7fec4Smrg * Enable or disable the color mechanism in the alpha window.
176271d7fec4Smrg *---------------------------------------------------------------------------
176371d7fec4Smrg */
176471d7fec4Smrg#if GFX_VIDEO_DYNAMIC
176571d7fec4Smrgint
176671d7fec4Smrgsc1200_set_alpha_color_enable(int enable)
176771d7fec4Smrg#else
176871d7fec4Smrgint
176971d7fec4Smrggfx_set_alpha_color_enable(int enable)
177071d7fec4Smrg#endif
177171d7fec4Smrg{
177271d7fec4Smrg   unsigned long color;
177371d7fec4Smrg   unsigned long address = 0;
177471d7fec4Smrg
177571d7fec4Smrg   if (gfx_alpha_select > 2)
177671d7fec4Smrg      return (GFX_STATUS_UNSUPPORTED);
177771d7fec4Smrg   address = SC1200_ALPHA_COLOR_1 + ((unsigned long)gfx_alpha_select << 4);
177871d7fec4Smrg   color = READ_VID32(address);
177971d7fec4Smrg   if (enable)
178071d7fec4Smrg      color |= SC1200_ALPHA_COLOR_ENABLE;
178171d7fec4Smrg   else
178271d7fec4Smrg      color &= ~SC1200_ALPHA_COLOR_ENABLE;
178371d7fec4Smrg   WRITE_VID32(address, color);
178471d7fec4Smrg   return (GFX_STATUS_OK);
178571d7fec4Smrg}
178671d7fec4Smrg
178771d7fec4Smrg/*---------------------------------------------------------------------------
178871d7fec4Smrg * gfx_set_no_ck_outside_alpha
178971d7fec4Smrg *
179071d7fec4Smrg * This function affects where inside the video window color key or chroma
179171d7fec4Smrg * key comparison is done:
179271d7fec4Smrg * If enable is TRUE, color/chroma key comparison is performed only inside
179371d7fec4Smrg * the enabled alpha windows. Outside the (enabled) alpha windows, only video
179471d7fec4Smrg * is displayed if color key is used, and only graphics is displayed if chroma
179571d7fec4Smrg * key is used.
179671d7fec4Smrg * If enable is FALSE, color/chroma key comparison is performed in all the
179771d7fec4Smrg * video window area.
179871d7fec4Smrg *---------------------------------------------------------------------------
179971d7fec4Smrg */
180071d7fec4Smrg#if GFX_VIDEO_DYNAMIC
180171d7fec4Smrgint
180271d7fec4Smrgsc1200_set_no_ck_outside_alpha(int enable)
180371d7fec4Smrg#else
180471d7fec4Smrgint
180571d7fec4Smrggfx_set_no_ck_outside_alpha(int enable)
180671d7fec4Smrg#endif
180771d7fec4Smrg{
180871d7fec4Smrg   unsigned long value;
180971d7fec4Smrg
181071d7fec4Smrg   value = READ_VID32(SC1200_VID_ALPHA_CONTROL);
181171d7fec4Smrg   if (enable)
181271d7fec4Smrg      WRITE_VID32(SC1200_VID_ALPHA_CONTROL,
181371d7fec4Smrg		  value | SC1200_NO_CK_OUTSIDE_ALPHA);
181471d7fec4Smrg   else
181571d7fec4Smrg      WRITE_VID32(SC1200_VID_ALPHA_CONTROL,
181671d7fec4Smrg		  value & ~SC1200_NO_CK_OUTSIDE_ALPHA);
181771d7fec4Smrg   return (0);
181871d7fec4Smrg}
181971d7fec4Smrg
182071d7fec4Smrg/*---------------------------------------------------------------------------
182171d7fec4Smrg * gfx_set_macrovision_enable
182271d7fec4Smrg *
182371d7fec4Smrg * This routine enables or disables macrovision on the tv encoder output.
182471d7fec4Smrg *---------------------------------------------------------------------------
182571d7fec4Smrg */
182671d7fec4Smrg#if GFX_VIDEO_DYNAMIC
182771d7fec4Smrgint
182871d7fec4Smrgsc1200_set_macrovision_enable(int enable)
182971d7fec4Smrg#else
183071d7fec4Smrgint
183171d7fec4Smrggfx_set_macrovision_enable(int enable)
183271d7fec4Smrg#endif
183371d7fec4Smrg{
183471d7fec4Smrg   if (enable)
183571d7fec4Smrg      WRITE_VID32(SC1200_TVENC_MV_CONTROL, SC1200_TVENC_MV_ENABLE);
183671d7fec4Smrg   else
183771d7fec4Smrg      WRITE_VID32(SC1200_TVENC_MV_CONTROL, 0);
183871d7fec4Smrg   return (GFX_STATUS_OK);
183971d7fec4Smrg}
184071d7fec4Smrg
184171d7fec4Smrg#define SC1200_VIDEO_PCI_44 0x80009444
184271d7fec4Smrg
184371d7fec4Smrg/*---------------------------------------------------------------------------
184471d7fec4Smrg * gfx_disable_softvga
184571d7fec4Smrg *
184671d7fec4Smrg * Disables SoftVga. This function is only valid with VSA2, Returns 1 if
184771d7fec4Smrg * SoftVga can be disabled; 0 if not.
184871d7fec4Smrg *---------------------------------------------------------------------------
184971d7fec4Smrg */
185071d7fec4Smrg#if GFX_VIDEO_DYNAMIC
185171d7fec4Smrgint
185271d7fec4Smrgsc1200_disable_softvga(void)
185371d7fec4Smrg#else
185471d7fec4Smrgint
185571d7fec4Smrggfx_disable_softvga(void)
185671d7fec4Smrg#endif
185771d7fec4Smrg{
185871d7fec4Smrg   unsigned long reg_val;
185971d7fec4Smrg
186071d7fec4Smrg   /* get the current value */
186171d7fec4Smrg   reg_val = gfx_pci_config_read(SC1200_VIDEO_PCI_44);
186271d7fec4Smrg   /* setting video PCI register 44 bit 0 to 1 disables SoftVga */
186371d7fec4Smrg   reg_val |= 0x1;
186471d7fec4Smrg   gfx_pci_config_write(SC1200_VIDEO_PCI_44, reg_val);
186571d7fec4Smrg
186671d7fec4Smrg   /* see if we set the bit and return the appropriate value */
186771d7fec4Smrg   reg_val = gfx_pci_config_read(SC1200_VIDEO_PCI_44);
186871d7fec4Smrg   if ((reg_val & 0x1) == 0x1)
186971d7fec4Smrg      return (1);
187071d7fec4Smrg   else
187171d7fec4Smrg      return (0);
187271d7fec4Smrg}
187371d7fec4Smrg
187471d7fec4Smrg/*---------------------------------------------------------------------------
187571d7fec4Smrg * gfx_enable_softvga
187671d7fec4Smrg *
187771d7fec4Smrg * Enables SoftVga. This function is only valid with VSA2, Returns 1 if
187871d7fec4Smrg * SoftVga can be enbled; 0 if not.
187971d7fec4Smrg *---------------------------------------------------------------------------
188071d7fec4Smrg */
188171d7fec4Smrg#if GFX_VIDEO_DYNAMIC
188271d7fec4Smrgint
188371d7fec4Smrgsc1200_enable_softvga(void)
188471d7fec4Smrg#else
188571d7fec4Smrgint
188671d7fec4Smrggfx_enable_softvga(void)
188771d7fec4Smrg#endif
188871d7fec4Smrg{
188971d7fec4Smrg   unsigned long reg_val;
189071d7fec4Smrg
189171d7fec4Smrg   /* get the current value */
189271d7fec4Smrg   reg_val = gfx_pci_config_read(SC1200_VIDEO_PCI_44);
189371d7fec4Smrg   /* clearing video PCI register 44 bit 0 enables SoftVga */
189471d7fec4Smrg   gfx_pci_config_write(SC1200_VIDEO_PCI_44, reg_val & 0xfffffffel);
189571d7fec4Smrg
189671d7fec4Smrg   /* see if we cleared the bit and return the appropriate value */
189771d7fec4Smrg   reg_val = gfx_pci_config_read(SC1200_VIDEO_PCI_44);
189871d7fec4Smrg   if ((reg_val & 0x1) == 0)
189971d7fec4Smrg      return (1);
190071d7fec4Smrg   else
190171d7fec4Smrg      return (0);
190271d7fec4Smrg}
190371d7fec4Smrg
190471d7fec4Smrg/*---------------------------------------------------------------------------
190571d7fec4Smrg * gfx_get_clock_frequency
190671d7fec4Smrg *
190771d7fec4Smrg * This routine returns the current clock frequency in 16.16 format.
190871d7fec4Smrg * It reads the current register value and finds the match in the table.
190971d7fec4Smrg * If no match is found, this routine returns 0.
191071d7fec4Smrg *---------------------------------------------------------------------------
191171d7fec4Smrg */
191271d7fec4Smrg#if GFX_VIDEO_DYNAMIC
191371d7fec4Smrgunsigned long
191471d7fec4Smrgsc1200_get_clock_frequency(void)
191571d7fec4Smrg#else
191671d7fec4Smrgunsigned long
191771d7fec4Smrggfx_get_clock_frequency(void)
191871d7fec4Smrg#endif
191971d7fec4Smrg{
192071d7fec4Smrg   unsigned int index;
192171d7fec4Smrg   unsigned long value, mask;
192271d7fec4Smrg
192371d7fec4Smrg   mask = 0x007FFF0F;
192471d7fec4Smrg   value = READ_VID32(SC1200_VID_CLOCK_SELECT) & mask;
192571d7fec4Smrg   for (index = 0; index < NUM_SC1200_FREQUENCIES; index++) {
192671d7fec4Smrg      if ((gfx_sc1200_clock_table[index].clock_select & mask) == value)
192771d7fec4Smrg	 return (gfx_sc1200_clock_table[index].frequency);
192871d7fec4Smrg   }
192971d7fec4Smrg   return (0);
193071d7fec4Smrg}
193171d7fec4Smrg
193271d7fec4Smrg/*************************************************************/
193371d7fec4Smrg/*  READ ROUTINES  |  INCLUDED FOR DIAGNOSTIC PURPOSES ONLY  */
193471d7fec4Smrg/*************************************************************/
193571d7fec4Smrg
193671d7fec4Smrg#if GFX_READ_ROUTINES
193771d7fec4Smrg
193871d7fec4Smrg/*---------------------------------------------------------------------------
193971d7fec4Smrg * gfx_get_vsa2_softvga_enable
194071d7fec4Smrg *
194171d7fec4Smrg * This function returns the enable status of SoftVGA.  It is valid
194271d7fec4Smrg * only if VSAII is present.
194371d7fec4Smrg *---------------------------------------------------------------------------
194471d7fec4Smrg */
194571d7fec4Smrg#if GFX_VIDEO_DYNAMIC
194671d7fec4Smrgint
194771d7fec4Smrgsc1200_get_vsa2_softvga_enable(void)
194871d7fec4Smrg#else
194971d7fec4Smrgint
195071d7fec4Smrggfx_get_vsa2_softvga_enable(void)
195171d7fec4Smrg#endif
195271d7fec4Smrg{
195371d7fec4Smrg   unsigned long reg_val;
195471d7fec4Smrg
195571d7fec4Smrg   reg_val = gfx_pci_config_read(SC1200_VIDEO_PCI_44);
195671d7fec4Smrg   if ((reg_val & 0x1) == 0)
195771d7fec4Smrg      return (1);
195871d7fec4Smrg   else
195971d7fec4Smrg      return (0);
196071d7fec4Smrg
196171d7fec4Smrg}
196271d7fec4Smrg
196371d7fec4Smrg/*---------------------------------------------------------------------------
196471d7fec4Smrg * gfx_get_sync_polarities
196571d7fec4Smrg *
196671d7fec4Smrg * This routine returns the polarities of the sync pulses:
196771d7fec4Smrg *     Bit 0: Set if negative horizontal polarity.
196871d7fec4Smrg *     Bit 1: Set if negative vertical polarity.
196971d7fec4Smrg *---------------------------------------------------------------------------
197071d7fec4Smrg */
197171d7fec4Smrg#if GFX_VIDEO_DYNAMIC
197271d7fec4Smrgint
197371d7fec4Smrgsc1200_get_sync_polarities(void)
197471d7fec4Smrg#else
197571d7fec4Smrgint
197671d7fec4Smrggfx_get_sync_polarities(void)
197771d7fec4Smrg#endif
197871d7fec4Smrg{
197971d7fec4Smrg   int polarities = 0;
198071d7fec4Smrg
198171d7fec4Smrg   if (READ_VID32(SC1200_DISPLAY_CONFIG) & SC1200_DCFG_CRT_HSYNC_POL)
198271d7fec4Smrg      polarities |= 1;
198371d7fec4Smrg   if (READ_VID32(SC1200_DISPLAY_CONFIG) & SC1200_DCFG_CRT_VSYNC_POL)
198471d7fec4Smrg      polarities |= 2;
198571d7fec4Smrg   return (polarities);
198671d7fec4Smrg}
198771d7fec4Smrg
198871d7fec4Smrg/*---------------------------------------------------------------------------
198971d7fec4Smrg * gfx_get_video_palette_entry
199071d7fec4Smrg *
199171d7fec4Smrg * This routine returns a single palette entry.
199271d7fec4Smrg *---------------------------------------------------------------------------
199371d7fec4Smrg */
199471d7fec4Smrg#if GFX_VIDEO_DYNAMIC
199571d7fec4Smrgint
199671d7fec4Smrgsc1200_get_video_palette_entry(unsigned long index, unsigned long *palette)
199771d7fec4Smrg#else
199871d7fec4Smrgint
199971d7fec4Smrggfx_get_video_palette_entry(unsigned long index, unsigned long *palette)
200071d7fec4Smrg#endif
200171d7fec4Smrg{
200271d7fec4Smrg   if (index > 0xFF)
200371d7fec4Smrg      return GFX_STATUS_BAD_PARAMETER;
200471d7fec4Smrg
200571d7fec4Smrg   /* READ A SINGLE ENTRY */
200671d7fec4Smrg
200771d7fec4Smrg   WRITE_VID32(SC1200_PALETTE_ADDRESS, index);
200871d7fec4Smrg   *palette = READ_VID32(SC1200_PALETTE_DATA);
200971d7fec4Smrg
201071d7fec4Smrg   return (GFX_STATUS_OK);
201171d7fec4Smrg}
201271d7fec4Smrg
201371d7fec4Smrg/*-----------------------------------------------------------------------------
201471d7fec4Smrg * gfx_get_video_enable
201571d7fec4Smrg *
201671d7fec4Smrg * This routine returns the value "one" if video overlay is currently enabled,
201771d7fec4Smrg * otherwise it returns the value "zero".
201871d7fec4Smrg *-----------------------------------------------------------------------------
201971d7fec4Smrg */
202071d7fec4Smrg#if GFX_VIDEO_DYNAMIC
202171d7fec4Smrgint
202271d7fec4Smrgsc1200_get_video_enable(void)
202371d7fec4Smrg#else
202471d7fec4Smrgint
202571d7fec4Smrggfx_get_video_enable(void)
202671d7fec4Smrg#endif
202771d7fec4Smrg{
202871d7fec4Smrg   if (READ_VID32(SC1200_VIDEO_CONFIG) & SC1200_VCFG_VID_EN)
202971d7fec4Smrg      return (1);
203071d7fec4Smrg   return (0);
203171d7fec4Smrg}
203271d7fec4Smrg
203371d7fec4Smrg/*-----------------------------------------------------------------------------
203471d7fec4Smrg * gfx_get_video_format
203571d7fec4Smrg *
203671d7fec4Smrg * This routine returns the current video overlay format.
203771d7fec4Smrg *-----------------------------------------------------------------------------
203871d7fec4Smrg */
203971d7fec4Smrg#if GFX_VIDEO_DYNAMIC
204071d7fec4Smrgint
204171d7fec4Smrgsc1200_get_video_format(void)
204271d7fec4Smrg#else
204371d7fec4Smrgint
204471d7fec4Smrggfx_get_video_format(void)
204571d7fec4Smrg#endif
204671d7fec4Smrg{
204771d7fec4Smrg   unsigned long ctrl, vcfg;
204871d7fec4Smrg
204971d7fec4Smrg   ctrl = READ_VID32(SC1200_VID_ALPHA_CONTROL);
205071d7fec4Smrg   vcfg = READ_VID32(SC1200_VIDEO_CONFIG);
205171d7fec4Smrg
205271d7fec4Smrg   if (ctrl & SC1200_VIDEO_INPUT_IS_RGB) {
205371d7fec4Smrg      switch (vcfg & SC1200_VCFG_VID_INP_FORMAT) {
205471d7fec4Smrg      case SC1200_VCFG_UYVY_FORMAT:
205571d7fec4Smrg	 return VIDEO_FORMAT_RGB;
205671d7fec4Smrg      case SC1200_VCFG_Y2YU_FORMAT:
205771d7fec4Smrg	 return VIDEO_FORMAT_P2M_P2L_P1M_P1L;
205871d7fec4Smrg      case SC1200_VCFG_YUYV_FORMAT:
205971d7fec4Smrg	 return VIDEO_FORMAT_P1M_P1L_P2M_P2L;
206071d7fec4Smrg      case SC1200_VCFG_YVYU_FORMAT:
206171d7fec4Smrg	 return VIDEO_FORMAT_P1M_P2L_P2M_P1L;
206271d7fec4Smrg      }
206371d7fec4Smrg   }
206471d7fec4Smrg
206571d7fec4Smrg   if (vcfg & SC1200_VCFG_4_2_0_MODE) {
206671d7fec4Smrg      switch (vcfg & SC1200_VCFG_VID_INP_FORMAT) {
206771d7fec4Smrg      case SC1200_VCFG_UYVY_FORMAT:
206871d7fec4Smrg	 return VIDEO_FORMAT_Y0Y1Y2Y3;
206971d7fec4Smrg      case SC1200_VCFG_Y2YU_FORMAT:
207071d7fec4Smrg	 return VIDEO_FORMAT_Y3Y2Y1Y0;
207171d7fec4Smrg      case SC1200_VCFG_YUYV_FORMAT:
207271d7fec4Smrg	 return VIDEO_FORMAT_Y1Y0Y3Y2;
207371d7fec4Smrg      case SC1200_VCFG_YVYU_FORMAT:
207471d7fec4Smrg	 return VIDEO_FORMAT_Y1Y2Y3Y0;
207571d7fec4Smrg      }
207671d7fec4Smrg   } else {
207771d7fec4Smrg      switch (vcfg & SC1200_VCFG_VID_INP_FORMAT) {
207871d7fec4Smrg      case SC1200_VCFG_UYVY_FORMAT:
207971d7fec4Smrg	 return VIDEO_FORMAT_UYVY;
208071d7fec4Smrg      case SC1200_VCFG_Y2YU_FORMAT:
208171d7fec4Smrg	 return VIDEO_FORMAT_Y2YU;
208271d7fec4Smrg      case SC1200_VCFG_YUYV_FORMAT:
208371d7fec4Smrg	 return VIDEO_FORMAT_YUYV;
208471d7fec4Smrg      case SC1200_VCFG_YVYU_FORMAT:
208571d7fec4Smrg	 return VIDEO_FORMAT_YVYU;
208671d7fec4Smrg      }
208771d7fec4Smrg   }
208871d7fec4Smrg   return (GFX_STATUS_ERROR);
208971d7fec4Smrg}
209071d7fec4Smrg
209171d7fec4Smrg/*-----------------------------------------------------------------------------
209271d7fec4Smrg * gfx_get_video_src_size
209371d7fec4Smrg *
209471d7fec4Smrg * This routine returns the size of the source video overlay buffer.  The
209571d7fec4Smrg * return value is (height << 16) | width.
209671d7fec4Smrg *-----------------------------------------------------------------------------
209771d7fec4Smrg */
209871d7fec4Smrg#if GFX_VIDEO_DYNAMIC
209971d7fec4Smrgunsigned long
210071d7fec4Smrgsc1200_get_video_src_size(void)
210171d7fec4Smrg#else
210271d7fec4Smrgunsigned long
210371d7fec4Smrggfx_get_video_src_size(void)
210471d7fec4Smrg#endif
210571d7fec4Smrg{
210671d7fec4Smrg   unsigned long width = 0, height = 0;
210771d7fec4Smrg
210871d7fec4Smrg   /* DETERMINE SOURCE WIDTH FROM THE SC1200 VIDEO LINE SIZE */
210971d7fec4Smrg
211071d7fec4Smrg   width = (READ_VID32(SC1200_VIDEO_CONFIG) >> 7) & 0x000001FE;
211171d7fec4Smrg   if (READ_VID32(SC1200_VIDEO_CONFIG) & SC1200_VCFG_LINE_SIZE_UPPER)
211271d7fec4Smrg      width += 512l;
211371d7fec4Smrg
211471d7fec4Smrg   if (width) {
211571d7fec4Smrg      /* DETERMINE HEIGHT BY DIVIDING TOTAL SIZE BY WIDTH */
211671d7fec4Smrg      /* Get total size from display controller - abtracted. */
211771d7fec4Smrg
211871d7fec4Smrg      height = gfx_get_display_video_size() / (width << 1);
211971d7fec4Smrg   }
212071d7fec4Smrg   return ((height << 16) | width);
212171d7fec4Smrg}
212271d7fec4Smrg
212371d7fec4Smrg/*-----------------------------------------------------------------------------
212471d7fec4Smrg * gfx_get_video_line_size
212571d7fec4Smrg *
212671d7fec4Smrg * This routine returns the line size of the source video overlay buffer, in
212771d7fec4Smrg * pixels.
212871d7fec4Smrg *-----------------------------------------------------------------------------
212971d7fec4Smrg */
213071d7fec4Smrg#if GFX_VIDEO_DYNAMIC
213171d7fec4Smrgunsigned long
213271d7fec4Smrgsc1200_get_video_line_size(void)
213371d7fec4Smrg#else
213471d7fec4Smrgunsigned long
213571d7fec4Smrggfx_get_video_line_size(void)
213671d7fec4Smrg#endif
213771d7fec4Smrg{
213871d7fec4Smrg   unsigned long width = 0;
213971d7fec4Smrg
214071d7fec4Smrg   /* DETERMINE SOURCE WIDTH FROM THE SC1200 VIDEO LINE SIZE */
214171d7fec4Smrg
214271d7fec4Smrg   width = (READ_VID32(SC1200_VIDEO_CONFIG) >> 7) & 0x000001FE;
214371d7fec4Smrg   if (READ_VID32(SC1200_VIDEO_CONFIG) & SC1200_VCFG_LINE_SIZE_UPPER)
214471d7fec4Smrg      width += 512l;
214571d7fec4Smrg   return (width);
214671d7fec4Smrg}
214771d7fec4Smrg
214871d7fec4Smrg/*-----------------------------------------------------------------------------
214971d7fec4Smrg * gfx_get_video_xclip
215071d7fec4Smrg *
215171d7fec4Smrg * This routine returns the number of bytes clipped on the left side of a
215271d7fec4Smrg * video overlay line (skipped at beginning).
215371d7fec4Smrg *-----------------------------------------------------------------------------
215471d7fec4Smrg */
215571d7fec4Smrg#if GFX_VIDEO_DYNAMIC
215671d7fec4Smrgunsigned long
215771d7fec4Smrgsc1200_get_video_xclip(void)
215871d7fec4Smrg#else
215971d7fec4Smrgunsigned long
216071d7fec4Smrggfx_get_video_xclip(void)
216171d7fec4Smrg#endif
216271d7fec4Smrg{
216371d7fec4Smrg   unsigned long clip = 0;
216471d7fec4Smrg
216571d7fec4Smrg   /* DETERMINE SOURCE WIDTH FROM THE SC1200 VIDEO LINE SIZE */
216671d7fec4Smrg
216771d7fec4Smrg   clip = (READ_VID32(SC1200_VIDEO_CONFIG) >> 14) & 0x000007FC;
216871d7fec4Smrg   return (clip);
216971d7fec4Smrg}
217071d7fec4Smrg
217171d7fec4Smrg/*-----------------------------------------------------------------------------
217271d7fec4Smrg * gfx_get_video_offset
217371d7fec4Smrg *
217471d7fec4Smrg * This routine returns the current offset for the video overlay buffer.
217571d7fec4Smrg *-----------------------------------------------------------------------------
217671d7fec4Smrg */
217771d7fec4Smrg#if GFX_VIDEO_DYNAMIC
217871d7fec4Smrgunsigned long
217971d7fec4Smrgsc1200_get_video_offset(void)
218071d7fec4Smrg#else
218171d7fec4Smrgunsigned long
218271d7fec4Smrggfx_get_video_offset(void)
218371d7fec4Smrg#endif
218471d7fec4Smrg{
218571d7fec4Smrg   return (gfx_get_display_video_offset());
218671d7fec4Smrg}
218771d7fec4Smrg
218871d7fec4Smrg/*---------------------------------------------------------------------------
218971d7fec4Smrg * gfx_get_video_upscale
219071d7fec4Smrg *
219171d7fec4Smrg * This routine returns the scale factor for the video overlay window.
219271d7fec4Smrg *---------------------------------------------------------------------------
219371d7fec4Smrg */
219471d7fec4Smrg#if GFX_VIDEO_DYNAMIC
219571d7fec4Smrgunsigned long
219671d7fec4Smrgsc1200_get_video_upscale(void)
219771d7fec4Smrg#else
219871d7fec4Smrgunsigned long
219971d7fec4Smrggfx_get_video_upscale(void)
220071d7fec4Smrg#endif
220171d7fec4Smrg{
220271d7fec4Smrg   return (READ_VID32(SC1200_VIDEO_UPSCALE));
220371d7fec4Smrg}
220471d7fec4Smrg
220571d7fec4Smrg/*---------------------------------------------------------------------------
220671d7fec4Smrg * gfx_get_video_scale
220771d7fec4Smrg *
220871d7fec4Smrg * This routine returns the scale factor for the video overlay window.
220971d7fec4Smrg *---------------------------------------------------------------------------
221071d7fec4Smrg */
221171d7fec4Smrg#if GFX_VIDEO_DYNAMIC
221271d7fec4Smrgunsigned long
221371d7fec4Smrgsc1200_get_video_scale(void)
221471d7fec4Smrg#else
221571d7fec4Smrgunsigned long
221671d7fec4Smrggfx_get_video_scale(void)
221771d7fec4Smrg#endif
221871d7fec4Smrg{
221971d7fec4Smrg   return gfx_get_video_upscale();
222071d7fec4Smrg}
222171d7fec4Smrg
222271d7fec4Smrg/*---------------------------------------------------------------------------
222371d7fec4Smrg * gfx_get_video_downscale_config
222471d7fec4Smrg *
222571d7fec4Smrg * This routine returns the current type and value of video downscaling.
222671d7fec4Smrg *---------------------------------------------------------------------------
222771d7fec4Smrg */
222871d7fec4Smrg#if GFX_VIDEO_DYNAMIC
222971d7fec4Smrgint
223071d7fec4Smrgsc1200_get_video_downscale_config(unsigned short *type, unsigned short *m)
223171d7fec4Smrg#else
223271d7fec4Smrgint
223371d7fec4Smrggfx_get_video_downscale_config(unsigned short *type, unsigned short *m)
223471d7fec4Smrg#endif
223571d7fec4Smrg{
223671d7fec4Smrg   unsigned long downscale;
223771d7fec4Smrg
223871d7fec4Smrg   downscale = READ_VID32(SC1200_VIDEO_DOWNSCALER_CONTROL);
223971d7fec4Smrg   *m = (unsigned short)((downscale & SC1200_VIDEO_DOWNSCALE_FACTOR_MASK) >>
224071d7fec4Smrg			 SC1200_VIDEO_DOWNSCALE_FACTOR_POS) + 1;
224171d7fec4Smrg
224271d7fec4Smrg   switch (downscale & SC1200_VIDEO_DOWNSCALE_TYPE_MASK) {
224371d7fec4Smrg   case SC1200_VIDEO_DOWNSCALE_TYPE_A:
224471d7fec4Smrg      *type = VIDEO_DOWNSCALE_KEEP_1_OF;
224571d7fec4Smrg      break;
224671d7fec4Smrg   case SC1200_VIDEO_DOWNSCALE_TYPE_B:
224771d7fec4Smrg      *type = VIDEO_DOWNSCALE_DROP_1_OF;
224871d7fec4Smrg      break;
224971d7fec4Smrg   default:
225071d7fec4Smrg      return GFX_STATUS_ERROR;
225171d7fec4Smrg      break;
225271d7fec4Smrg   }
225371d7fec4Smrg   return (0);
225471d7fec4Smrg}
225571d7fec4Smrg
225671d7fec4Smrg/*---------------------------------------------------------------------------
225771d7fec4Smrg * gfx_get_video_downscale_coefficients
225871d7fec4Smrg *
225971d7fec4Smrg * This routine returns the current video downscaling coefficients.
226071d7fec4Smrg *---------------------------------------------------------------------------
226171d7fec4Smrg */
226271d7fec4Smrg#if GFX_VIDEO_DYNAMIC
226371d7fec4Smrgvoid
226471d7fec4Smrgsc1200_get_video_downscale_coefficients(unsigned short *coef1,
226571d7fec4Smrg					unsigned short *coef2,
226671d7fec4Smrg					unsigned short *coef3,
226771d7fec4Smrg					unsigned short *coef4)
226871d7fec4Smrg#else
226971d7fec4Smrgvoid
227071d7fec4Smrggfx_get_video_downscale_coefficients(unsigned short *coef1,
227171d7fec4Smrg				     unsigned short *coef2,
227271d7fec4Smrg				     unsigned short *coef3,
227371d7fec4Smrg				     unsigned short *coef4)
227471d7fec4Smrg#endif
227571d7fec4Smrg{
227671d7fec4Smrg   unsigned long coef;
227771d7fec4Smrg
227871d7fec4Smrg   coef = READ_VID32(SC1200_VIDEO_DOWNSCALER_COEFFICIENTS);
227971d7fec4Smrg   *coef1 =
228071d7fec4Smrg	 (unsigned short)((coef >> SC1200_VIDEO_DOWNSCALER_COEF1_POS) &
228171d7fec4Smrg			  SC1200_VIDEO_DOWNSCALER_COEF_MASK);
228271d7fec4Smrg   *coef2 =
228371d7fec4Smrg	 (unsigned short)((coef >> SC1200_VIDEO_DOWNSCALER_COEF2_POS) &
228471d7fec4Smrg			  SC1200_VIDEO_DOWNSCALER_COEF_MASK);
228571d7fec4Smrg   *coef3 =
228671d7fec4Smrg	 (unsigned short)((coef >> SC1200_VIDEO_DOWNSCALER_COEF3_POS) &
228771d7fec4Smrg			  SC1200_VIDEO_DOWNSCALER_COEF_MASK);
228871d7fec4Smrg   *coef4 =
228971d7fec4Smrg	 (unsigned short)((coef >> SC1200_VIDEO_DOWNSCALER_COEF4_POS) &
229071d7fec4Smrg			  SC1200_VIDEO_DOWNSCALER_COEF_MASK);
229171d7fec4Smrg   return;
229271d7fec4Smrg}
229371d7fec4Smrg
229471d7fec4Smrg/*---------------------------------------------------------------------------
229571d7fec4Smrg * gfx_get_video_downscale_enable
229671d7fec4Smrg *
229771d7fec4Smrg * This routine returns 1 if video downscaling is currently enabled,
229871d7fec4Smrg * or 0 if it is currently disabled.
229971d7fec4Smrg *---------------------------------------------------------------------------
230071d7fec4Smrg */
230171d7fec4Smrg#if GFX_VIDEO_DYNAMIC
230271d7fec4Smrgvoid
230371d7fec4Smrgsc1200_get_video_downscale_enable(int *enable)
230471d7fec4Smrg#else
230571d7fec4Smrgvoid
230671d7fec4Smrggfx_get_video_downscale_enable(int *enable)
230771d7fec4Smrg#endif
230871d7fec4Smrg{
230971d7fec4Smrg   if (READ_VID32(SC1200_VIDEO_DOWNSCALER_CONTROL) &
231071d7fec4Smrg       SC1200_VIDEO_DOWNSCALE_ENABLE)
231171d7fec4Smrg      *enable = 1;
231271d7fec4Smrg   else
231371d7fec4Smrg      *enable = 0;
231471d7fec4Smrg   return;
231571d7fec4Smrg}
231671d7fec4Smrg
231771d7fec4Smrg/*---------------------------------------------------------------------------
231871d7fec4Smrg * gfx_get_video_dst_size
231971d7fec4Smrg *
232071d7fec4Smrg * This routine returns the size of the displayed video overlay window.
232171d7fec4Smrg *---------------------------------------------------------------------------
232271d7fec4Smrg */
232371d7fec4Smrg#if GFX_VIDEO_DYNAMIC
232471d7fec4Smrgunsigned long
232571d7fec4Smrgsc1200_get_video_dst_size(void)
232671d7fec4Smrg#else
232771d7fec4Smrgunsigned long
232871d7fec4Smrggfx_get_video_dst_size(void)
232971d7fec4Smrg#endif
233071d7fec4Smrg{
233171d7fec4Smrg   unsigned long xsize, ysize;
233271d7fec4Smrg
233371d7fec4Smrg   xsize = READ_VID32(SC1200_VIDEO_X_POS);
233471d7fec4Smrg   xsize = ((xsize >> 16) & 0x7FF) - (xsize & 0x7FF);
233571d7fec4Smrg   ysize = READ_VID32(SC1200_VIDEO_Y_POS);
233671d7fec4Smrg   ysize = ((ysize >> 16) & 0x7FF) - (ysize & 0x7FF);
233771d7fec4Smrg   return ((ysize << 16) | xsize);
233871d7fec4Smrg}
233971d7fec4Smrg
234071d7fec4Smrg/*---------------------------------------------------------------------------
234171d7fec4Smrg * gfx_get_video_position
234271d7fec4Smrg *
234371d7fec4Smrg * This routine returns the position of the video overlay window.  The
234471d7fec4Smrg * return value is (ypos << 16) | xpos.
234571d7fec4Smrg *---------------------------------------------------------------------------
234671d7fec4Smrg */
234771d7fec4Smrg#if GFX_VIDEO_DYNAMIC
234871d7fec4Smrgunsigned long
234971d7fec4Smrgsc1200_get_video_position(void)
235071d7fec4Smrg#else
235171d7fec4Smrgunsigned long
235271d7fec4Smrggfx_get_video_position(void)
235371d7fec4Smrg#endif
235471d7fec4Smrg{
235571d7fec4Smrg   unsigned long hadjust, vadjust;
235671d7fec4Smrg   unsigned long xpos, ypos;
235771d7fec4Smrg
235871d7fec4Smrg   /* READ HARDWARE POSITION */
235971d7fec4Smrg
236071d7fec4Smrg   xpos = READ_VID32(SC1200_VIDEO_X_POS) & 0x000007FF;
236171d7fec4Smrg   ypos = READ_VID32(SC1200_VIDEO_Y_POS) & 0x000007FF;
236271d7fec4Smrg
236371d7fec4Smrg   /* GET ADJUSTMENT VALUES */
236471d7fec4Smrg   /* Use routines to abstract version of display controller. */
236571d7fec4Smrg
236671d7fec4Smrg   hadjust =
236771d7fec4Smrg	 (unsigned long)gfx_get_htotal() -
236871d7fec4Smrg	 (unsigned long)gfx_get_hsync_end() - 14l;
236971d7fec4Smrg   vadjust =
237071d7fec4Smrg	 (unsigned long)gfx_get_vtotal() -
237171d7fec4Smrg	 (unsigned long)gfx_get_vsync_end() + 1l;
237271d7fec4Smrg   xpos -= hadjust;
237371d7fec4Smrg   ypos -= vadjust;
237471d7fec4Smrg   return ((ypos << 16) | (xpos & 0x0000FFFF));
237571d7fec4Smrg}
237671d7fec4Smrg
237771d7fec4Smrg/*---------------------------------------------------------------------------
237871d7fec4Smrg * gfx_get_video_color_key
237971d7fec4Smrg *
238071d7fec4Smrg * This routine returns the current video color key value.
238171d7fec4Smrg *---------------------------------------------------------------------------
238271d7fec4Smrg */
238371d7fec4Smrg#if GFX_VIDEO_DYNAMIC
238471d7fec4Smrgunsigned long
238571d7fec4Smrgsc1200_get_video_color_key(void)
238671d7fec4Smrg#else
238771d7fec4Smrgunsigned long
238871d7fec4Smrggfx_get_video_color_key(void)
238971d7fec4Smrg#endif
239071d7fec4Smrg{
239171d7fec4Smrg   return (READ_VID32(SC1200_VIDEO_COLOR_KEY));
239271d7fec4Smrg}
239371d7fec4Smrg
239471d7fec4Smrg/*---------------------------------------------------------------------------
239571d7fec4Smrg * gfx_get_video_color_key_mask
239671d7fec4Smrg *
239771d7fec4Smrg * This routine returns the current video color mask value.
239871d7fec4Smrg *---------------------------------------------------------------------------
239971d7fec4Smrg */
240071d7fec4Smrg#if GFX_VIDEO_DYNAMIC
240171d7fec4Smrgunsigned long
240271d7fec4Smrgsc1200_get_video_color_key_mask(void)
240371d7fec4Smrg#else
240471d7fec4Smrgunsigned long
240571d7fec4Smrggfx_get_video_color_key_mask(void)
240671d7fec4Smrg#endif
240771d7fec4Smrg{
240871d7fec4Smrg   return (READ_VID32(SC1200_VIDEO_COLOR_MASK));
240971d7fec4Smrg}
241071d7fec4Smrg
241171d7fec4Smrg/*---------------------------------------------------------------------------
241271d7fec4Smrg * gfx_get_video_color_key_src
241371d7fec4Smrg *
241471d7fec4Smrg * This routine returns 0 for video data compare, 1 for graphics data.
241571d7fec4Smrg *---------------------------------------------------------------------------
241671d7fec4Smrg */
241771d7fec4Smrg#if GFX_VIDEO_DYNAMIC
241871d7fec4Smrgint
241971d7fec4Smrgsc1200_get_video_color_key_src(void)
242071d7fec4Smrg#else
242171d7fec4Smrgint
242271d7fec4Smrggfx_get_video_color_key_src(void)
242371d7fec4Smrg#endif
242471d7fec4Smrg{
242571d7fec4Smrg   if (READ_VID32(SC1200_DISPLAY_CONFIG) & SC1200_DCFG_VG_CK)
242671d7fec4Smrg      return (0);
242771d7fec4Smrg   return (1);
242871d7fec4Smrg}
242971d7fec4Smrg
243071d7fec4Smrg/*---------------------------------------------------------------------------
243171d7fec4Smrg * gfx_get_video_filter
243271d7fec4Smrg *
243371d7fec4Smrg * This routine returns if the filters are currently enabled.
243471d7fec4Smrg *---------------------------------------------------------------------------
243571d7fec4Smrg */
243671d7fec4Smrg#if GFX_VIDEO_DYNAMIC
243771d7fec4Smrgint
243871d7fec4Smrgsc1200_get_video_filter(void)
243971d7fec4Smrg#else
244071d7fec4Smrgint
244171d7fec4Smrggfx_get_video_filter(void)
244271d7fec4Smrg#endif
244371d7fec4Smrg{
244471d7fec4Smrg   int retval = 0;
244571d7fec4Smrg
244671d7fec4Smrg   if (READ_VID32(SC1200_VIDEO_CONFIG) & SC1200_VCFG_X_FILTER_EN)
244771d7fec4Smrg      retval |= 1;
244871d7fec4Smrg   if (READ_VID32(SC1200_VIDEO_CONFIG) & SC1200_VCFG_Y_FILTER_EN)
244971d7fec4Smrg      retval |= 2;
245071d7fec4Smrg   return (retval);
245171d7fec4Smrg}
245271d7fec4Smrg
245371d7fec4Smrg/*---------------------------------------------------------------------------
245471d7fec4Smrg * gfx_get_video_request
245571d7fec4Smrg *
245671d7fec4Smrg * This routine returns the horizontal (pixel) and vertical (lines) video
245771d7fec4Smrg * request values.
245871d7fec4Smrg *---------------------------------------------------------------------------
245971d7fec4Smrg */
246071d7fec4Smrg#if GFX_VIDEO_DYNAMIC
246171d7fec4Smrgint
246271d7fec4Smrgsc1200_get_video_request(short *x, short *y)
246371d7fec4Smrg#else
246471d7fec4Smrgint
246571d7fec4Smrggfx_get_video_request(short *x, short *y)
246671d7fec4Smrg#endif
246771d7fec4Smrg{
246871d7fec4Smrg   int request = 0;
246971d7fec4Smrg
247071d7fec4Smrg   request = (int)(READ_VID32(SC1200_VIDEO_REQUEST));
247171d7fec4Smrg   *x = (request >> SC1200_VIDEO_X_REQUEST_POS) & SC1200_VIDEO_REQUEST_MASK;
247271d7fec4Smrg   *y = (request >> SC1200_VIDEO_Y_REQUEST_POS) & SC1200_VIDEO_REQUEST_MASK;
247371d7fec4Smrg
247471d7fec4Smrg   *x -= gfx_get_htotal() - gfx_get_hsync_end() - 2;
247571d7fec4Smrg   *y -= gfx_get_vtotal() - gfx_get_vsync_end() + 1;
247671d7fec4Smrg
247771d7fec4Smrg   return (0);
247871d7fec4Smrg}
247971d7fec4Smrg
248071d7fec4Smrg/*---------------------------------------------------------------------------
248171d7fec4Smrg * gfx_get_video_source
248271d7fec4Smrg *
248371d7fec4Smrg * This routine returns the current video source.
248471d7fec4Smrg *---------------------------------------------------------------------------
248571d7fec4Smrg */
248671d7fec4Smrg#if GFX_VIDEO_DYNAMIC
248771d7fec4Smrgint
248871d7fec4Smrgsc1200_get_video_source(VideoSourceType * source)
248971d7fec4Smrg#else
249071d7fec4Smrgint
249171d7fec4Smrggfx_get_video_source(VideoSourceType * source)
249271d7fec4Smrg#endif
249371d7fec4Smrg{
249471d7fec4Smrg   switch (READ_VID32(SC1200_VIDEO_DISPLAY_MODE) & SC1200_VIDEO_SOURCE_MASK) {
249571d7fec4Smrg   case SC1200_VIDEO_SOURCE_GX1:
249671d7fec4Smrg      *source = VIDEO_SOURCE_MEMORY;
249771d7fec4Smrg      break;
249871d7fec4Smrg   case SC1200_VIDEO_SOURCE_DVIP:
249971d7fec4Smrg      *source = VIDEO_SOURCE_DVIP;
250071d7fec4Smrg      break;
250171d7fec4Smrg   default:
250271d7fec4Smrg      return GFX_STATUS_ERROR;
250371d7fec4Smrg   }
250471d7fec4Smrg   return (0);
250571d7fec4Smrg}
250671d7fec4Smrg
250771d7fec4Smrg/*---------------------------------------------------------------------------
250871d7fec4Smrg * gfx_get_vbi_source
250971d7fec4Smrg *
251071d7fec4Smrg * This routine returns the current vbi source.
251171d7fec4Smrg *---------------------------------------------------------------------------
251271d7fec4Smrg */
251371d7fec4Smrg#if GFX_VIDEO_DYNAMIC
251471d7fec4Smrgint
251571d7fec4Smrgsc1200_get_vbi_source(VbiSourceType * source)
251671d7fec4Smrg#else
251771d7fec4Smrgint
251871d7fec4Smrggfx_get_vbi_source(VbiSourceType * source)
251971d7fec4Smrg#endif
252071d7fec4Smrg{
252171d7fec4Smrg   switch (READ_VID32(SC1200_VIDEO_DISPLAY_MODE) & SC1200_VBI_SOURCE_MASK) {
252271d7fec4Smrg   case SC1200_VBI_SOURCE_GX1:
252371d7fec4Smrg      *source = VBI_SOURCE_MEMORY;
252471d7fec4Smrg      break;
252571d7fec4Smrg   case SC1200_VBI_SOURCE_DVIP:
252671d7fec4Smrg      *source = VBI_SOURCE_DVIP;
252771d7fec4Smrg      break;
252871d7fec4Smrg   default:
252971d7fec4Smrg      return GFX_STATUS_ERROR;
253071d7fec4Smrg   }
253171d7fec4Smrg   return (0);
253271d7fec4Smrg}
253371d7fec4Smrg
253471d7fec4Smrg/*---------------------------------------------------------------------------
253571d7fec4Smrg * gfx_get_vbi_lines
253671d7fec4Smrg *
253771d7fec4Smrg * This routine returns the VBI lines which are sent to the TV encoder.
253871d7fec4Smrg *---------------------------------------------------------------------------
253971d7fec4Smrg */
254071d7fec4Smrg#if GFX_VIDEO_DYNAMIC
254171d7fec4Smrgunsigned long
254271d7fec4Smrgsc1200_get_vbi_lines(int odd)
254371d7fec4Smrg#else
254471d7fec4Smrgunsigned long
254571d7fec4Smrggfx_get_vbi_lines(int odd)
254671d7fec4Smrg#endif
254771d7fec4Smrg{
254871d7fec4Smrg   if (odd)
254971d7fec4Smrg      return (READ_VID32(SC1200_VIDEO_ODD_VBI_LINE_ENABLE) &
255071d7fec4Smrg	      SC1200_VIDEO_VBI_LINE_ENABLE_MASK);
255171d7fec4Smrg   return (READ_VID32(SC1200_VIDEO_EVEN_VBI_LINE_ENABLE) &
255271d7fec4Smrg	   SC1200_VIDEO_VBI_LINE_ENABLE_MASK);
255371d7fec4Smrg}
255471d7fec4Smrg
255571d7fec4Smrg/*---------------------------------------------------------------------------
255671d7fec4Smrg * gfx_get_vbi_total
255771d7fec4Smrg *
255871d7fec4Smrg * This routine returns the total number of VBI bytes in the field.
255971d7fec4Smrg *---------------------------------------------------------------------------
256071d7fec4Smrg */
256171d7fec4Smrg#if GFX_VIDEO_DYNAMIC
256271d7fec4Smrgunsigned long
256371d7fec4Smrgsc1200_get_vbi_total(int odd)
256471d7fec4Smrg#else
256571d7fec4Smrgunsigned long
256671d7fec4Smrggfx_get_vbi_total(int odd)
256771d7fec4Smrg#endif
256871d7fec4Smrg{
256971d7fec4Smrg   if (odd)
257071d7fec4Smrg      return (READ_VID32(SC1200_VIDEO_ODD_VBI_TOTAL_COUNT) &
257171d7fec4Smrg	      SC1200_VIDEO_VBI_TOTAL_COUNT_MASK);
257271d7fec4Smrg   return (READ_VID32(SC1200_VIDEO_EVEN_VBI_TOTAL_COUNT) &
257371d7fec4Smrg	   SC1200_VIDEO_VBI_TOTAL_COUNT_MASK);
257471d7fec4Smrg}
257571d7fec4Smrg
257671d7fec4Smrg/*---------------------------------------------------------------------------
257771d7fec4Smrg * gfx_get_video_interlaced()
257871d7fec4Smrg *
257971d7fec4Smrg * This routine returns "1" if input video is currently in interlaced mode.
258071d7fec4Smrg * "0" otherwise.
258171d7fec4Smrg *---------------------------------------------------------------------------
258271d7fec4Smrg */
258371d7fec4Smrg#if GFX_VIDEO_DYNAMIC
258471d7fec4Smrgint
258571d7fec4Smrgsc1200_get_video_interlaced(void)
258671d7fec4Smrg#else
258771d7fec4Smrgint
258871d7fec4Smrggfx_get_video_interlaced(void)
258971d7fec4Smrg#endif
259071d7fec4Smrg{
259171d7fec4Smrg   if (READ_VID32(SC1200_VID_ALPHA_CONTROL) & SC1200_VIDEO_IS_INTERLACED)
259271d7fec4Smrg      return (1);
259371d7fec4Smrg   else
259471d7fec4Smrg      return (0);
259571d7fec4Smrg}
259671d7fec4Smrg
259771d7fec4Smrg/*---------------------------------------------------------------------------
259871d7fec4Smrg * gfx_get_color_space_YUV()
259971d7fec4Smrg *
260071d7fec4Smrg * This routine returns "1" if video processor color space mode is currently
260171d7fec4Smrg * YUV. "0" otherwise.
260271d7fec4Smrg *---------------------------------------------------------------------------
260371d7fec4Smrg */
260471d7fec4Smrg#if GFX_VIDEO_DYNAMIC
260571d7fec4Smrgint
260671d7fec4Smrgsc1200_get_color_space_YUV(void)
260771d7fec4Smrg#else
260871d7fec4Smrgint
260971d7fec4Smrggfx_get_color_space_YUV(void)
261071d7fec4Smrg#endif
261171d7fec4Smrg{
261271d7fec4Smrg   unsigned long control;
261371d7fec4Smrg
261471d7fec4Smrg   control = READ_VID32(SC1200_VID_ALPHA_CONTROL);
261571d7fec4Smrg
261671d7fec4Smrg   /* IS SC1200 VIDEO COLOR SPACE RGB OR CONVERTED TO RGB */
261771d7fec4Smrg   if ((control & SC1200_VIDEO_INPUT_IS_RGB)
261871d7fec4Smrg       || (control & SC1200_CSC_VIDEO_YUV_TO_RGB))
261971d7fec4Smrg      return (0);
262071d7fec4Smrg   else
262171d7fec4Smrg      return (1);
262271d7fec4Smrg}
262371d7fec4Smrg
262471d7fec4Smrg/*---------------------------------------------------------------------------
262571d7fec4Smrg * gfx_get_vertical_scaler_offset()
262671d7fec4Smrg *
262771d7fec4Smrg * This routine sets "offset" to the value by which odd frames are shifted,
262871d7fec4Smrg * if insert is enabled, and to 0 if no shifting occurs.
262971d7fec4Smrg *---------------------------------------------------------------------------
263071d7fec4Smrg */
263171d7fec4Smrg#if GFX_VIDEO_DYNAMIC
263271d7fec4Smrgint
263371d7fec4Smrgsc1200_get_vertical_scaler_offset(char *offset)
263471d7fec4Smrg#else
263571d7fec4Smrgint
263671d7fec4Smrggfx_get_vertical_scaler_offset(char *offset)
263771d7fec4Smrg#endif
263871d7fec4Smrg{
263971d7fec4Smrg   unsigned long control;
264071d7fec4Smrg
264171d7fec4Smrg   control = READ_VID32(SC1200_VID_ALPHA_CONTROL);
264271d7fec4Smrg   if (control & SC1200_VERTICAL_SCALER_SHIFT_EN) {
264371d7fec4Smrg      if ((control & SC1200_VERTICAL_SCALER_SHIFT_MASK) ==
264471d7fec4Smrg	  SC1200_VERTICAL_SCALER_SHIFT_INIT)
264571d7fec4Smrg	 *offset = 1;
264671d7fec4Smrg      else
264771d7fec4Smrg	 return GFX_STATUS_ERROR;	/* TODO: find the interpretation of other values */
264871d7fec4Smrg   } else
264971d7fec4Smrg      *offset = 0;
265071d7fec4Smrg   return (0);
265171d7fec4Smrg}
265271d7fec4Smrg
265371d7fec4Smrg/*---------------------------------------------------------------------------
265471d7fec4Smrg * gfx_get_genlock_delay
265571d7fec4Smrg *
265671d7fec4Smrg * This routine returns the genlock delay in 27 MHz clocks.
265771d7fec4Smrg *---------------------------------------------------------------------------
265871d7fec4Smrg */
265971d7fec4Smrg#if GFX_VIDEO_DYNAMIC
266071d7fec4Smrgunsigned long
266171d7fec4Smrgsc1200_get_genlock_delay(void)
266271d7fec4Smrg#else
266371d7fec4Smrgunsigned long
266471d7fec4Smrggfx_get_genlock_delay(void)
266571d7fec4Smrg#endif
266671d7fec4Smrg{
266771d7fec4Smrg   return (READ_VID32(SC1200_GENLOCK_DELAY) & SC1200_GENLOCK_DELAY_MASK);
266871d7fec4Smrg}
266971d7fec4Smrg
267071d7fec4Smrg/*---------------------------------------------------------------------------
267171d7fec4Smrg * gfx_get_genlock_enable
267271d7fec4Smrg *
267371d7fec4Smrg * This routine returns "1" if genlock is currently enabled, "0" otherwise.
267471d7fec4Smrg *---------------------------------------------------------------------------
267571d7fec4Smrg */
267671d7fec4Smrg#if GFX_VIDEO_DYNAMIC
267771d7fec4Smrgint
267871d7fec4Smrgsc1200_get_genlock_enable(void)
267971d7fec4Smrg#else
268071d7fec4Smrgint
268171d7fec4Smrggfx_get_genlock_enable(void)
268271d7fec4Smrg#endif
268371d7fec4Smrg{
268471d7fec4Smrg   if (READ_VID32(SC1200_GENLOCK) &
268571d7fec4Smrg       (SC1200_GENLOCK_SINGLE_ENABLE | SC1200_GENLOCK_CONTINUOUS_ENABLE))
268671d7fec4Smrg      return (1);
268771d7fec4Smrg   else
268871d7fec4Smrg      return (0);
268971d7fec4Smrg}
269071d7fec4Smrg
269171d7fec4Smrg/*---------------------------------------------------------------------------
269271d7fec4Smrg * gfx_get_video_cursor()
269371d7fec4Smrg *
269471d7fec4Smrg * This routine configures the video hardware cursor.
269571d7fec4Smrg * If the "mask"ed bits in the graphics pixel match "key", then either "color1"
269671d7fec4Smrg * or "color2" will be used for this pixel, according to the value of the bit
269771d7fec4Smrg * in offset "select_color2".
269871d7fec4Smrg *---------------------------------------------------------------------------
269971d7fec4Smrg */
270071d7fec4Smrg#if GFX_VIDEO_DYNAMIC
270171d7fec4Smrgint
270271d7fec4Smrgsc1200_get_video_cursor(unsigned long *key, unsigned long *mask,
270371d7fec4Smrg			unsigned short *select_color2, unsigned long *color1,
270471d7fec4Smrg			unsigned short *color2)
270571d7fec4Smrg#else
270671d7fec4Smrgint
270771d7fec4Smrggfx_get_video_cursor(unsigned long *key, unsigned long *mask,
270871d7fec4Smrg		     unsigned short *select_color2, unsigned long *color1,
270971d7fec4Smrg		     unsigned short *color2)
271071d7fec4Smrg#endif
271171d7fec4Smrg{
271271d7fec4Smrg   *select_color2 =
271371d7fec4Smrg	 (unsigned short)(READ_VID32(SC1200_CURSOR_COLOR_KEY) >>
271471d7fec4Smrg			  SC1200_CURSOR_COLOR_KEY_OFFSET_POS);
271571d7fec4Smrg   *key = READ_VID32(SC1200_CURSOR_COLOR_KEY) & SC1200_COLOR_MASK;
271671d7fec4Smrg   *mask = READ_VID32(SC1200_CURSOR_COLOR_MASK) & SC1200_COLOR_MASK;
271771d7fec4Smrg   *color1 = READ_VID32(SC1200_CURSOR_COLOR_1) & SC1200_COLOR_MASK;
271871d7fec4Smrg   *color2 =
271971d7fec4Smrg	 (unsigned short)(READ_VID32(SC1200_CURSOR_COLOR_2) &
272071d7fec4Smrg			  SC1200_COLOR_MASK);
272171d7fec4Smrg   return (0);
272271d7fec4Smrg}
272371d7fec4Smrg
272471d7fec4Smrg/*---------------------------------------------------------------------------
272571d7fec4Smrg * gfx_read_crc
272671d7fec4Smrg *
272771d7fec4Smrg * This routine returns the hardware CRC value, which is used for automated
272871d7fec4Smrg * testing.  The value is like a checksum, but will change if pixels move
272971d7fec4Smrg * locations.
273071d7fec4Smrg *---------------------------------------------------------------------------
273171d7fec4Smrg */
273271d7fec4Smrg#if GFX_VIDEO_DYNAMIC
273371d7fec4Smrgunsigned long
273471d7fec4Smrgsc1200_read_crc(void)
273571d7fec4Smrg#else
273671d7fec4Smrgunsigned long
273771d7fec4Smrggfx_read_crc(void)
273871d7fec4Smrg#endif
273971d7fec4Smrg{
274071d7fec4Smrg   unsigned long crc = 0xFFFFFFFF;
274171d7fec4Smrg
274271d7fec4Smrg   if (gfx_test_timing_active()) {
274371d7fec4Smrg      /* WAIT UNTIL ACTIVE DISPLAY */
274471d7fec4Smrg
274571d7fec4Smrg      while (!gfx_test_vertical_active()) ;
274671d7fec4Smrg
274771d7fec4Smrg      /* RESET CRC DURING ACTIVE DISPLAY */
274871d7fec4Smrg
274971d7fec4Smrg      WRITE_VID32(SC1200_VID_CRC, 0);
275071d7fec4Smrg      WRITE_VID32(SC1200_VID_CRC, 1);
275171d7fec4Smrg
275271d7fec4Smrg      /* WAIT UNTIL NOT ACTIVE, THEN ACTIVE, NOT ACTIVE, THEN ACTIVE */
275371d7fec4Smrg
275471d7fec4Smrg      while (gfx_test_vertical_active()) ;
275571d7fec4Smrg      while (!gfx_test_vertical_active()) ;
275671d7fec4Smrg      while (gfx_test_vertical_active()) ;
275771d7fec4Smrg      while (!gfx_test_vertical_active()) ;
275871d7fec4Smrg      crc = READ_VID32(SC1200_VID_CRC) >> 8;
275971d7fec4Smrg   }
276071d7fec4Smrg   return (crc);
276171d7fec4Smrg}
276271d7fec4Smrg
276371d7fec4Smrg/*-----------------------------------------------------------------------------
276471d7fec4Smrg * gfx_get_macrovision_enable
276571d7fec4Smrg *
276671d7fec4Smrg * This routine returns the value "one" if macrovision currently enabled in the
276771d7fec4Smrg * TV encoder, otherwise it returns the value "zero".
276871d7fec4Smrg *-----------------------------------------------------------------------------
276971d7fec4Smrg */
277071d7fec4Smrg#if GFX_VIDEO_DYNAMIC
277171d7fec4Smrgint
277271d7fec4Smrgsc1200_get_macrovision_enable(void)
277371d7fec4Smrg#else
277471d7fec4Smrgint
277571d7fec4Smrggfx_get_macrovision_enable(void)
277671d7fec4Smrg#endif
277771d7fec4Smrg{
277871d7fec4Smrg   if (READ_VID32(SC1200_TVENC_MV_CONTROL) == SC1200_TVENC_MV_ENABLE)
277971d7fec4Smrg      return (1);
278071d7fec4Smrg   return (0);
278171d7fec4Smrg}
278271d7fec4Smrg
278371d7fec4Smrg/*---------------------------------------------------------------------------
278471d7fec4Smrg * gfx_get_alpha_enable
278571d7fec4Smrg *
278671d7fec4Smrg * This routine returns 1 if the selected alpha window is currently
278771d7fec4Smrg * enabled, or 0 if it is currently disabled.
278871d7fec4Smrg *---------------------------------------------------------------------------
278971d7fec4Smrg */
279071d7fec4Smrg#if GFX_VIDEO_DYNAMIC
279171d7fec4Smrgvoid
279271d7fec4Smrgsc1200_get_alpha_enable(int *enable)
279371d7fec4Smrg#else
279471d7fec4Smrgvoid
279571d7fec4Smrggfx_get_alpha_enable(int *enable)
279671d7fec4Smrg#endif
279771d7fec4Smrg{
279871d7fec4Smrg   unsigned long value = 0;
279971d7fec4Smrg
280071d7fec4Smrg   *enable = 0;
280171d7fec4Smrg   if (gfx_alpha_select <= 2) {
280271d7fec4Smrg      value =
280371d7fec4Smrg	    READ_VID32(SC1200_ALPHA_CONTROL_1 +
280471d7fec4Smrg		       ((unsigned long)gfx_alpha_select << 4));
280571d7fec4Smrg      if (value & SC1200_ACTRL_WIN_ENABLE)
280671d7fec4Smrg	 *enable = 1;
280771d7fec4Smrg   }
280871d7fec4Smrg   return;
280971d7fec4Smrg}
281071d7fec4Smrg
281171d7fec4Smrg/*---------------------------------------------------------------------------
281271d7fec4Smrg * gfx_get_alpha_size
281371d7fec4Smrg *
281471d7fec4Smrg * This routine returns the size of the currently selected alpha region.
281571d7fec4Smrg *---------------------------------------------------------------------------
281671d7fec4Smrg */
281771d7fec4Smrg#if GFX_VIDEO_DYNAMIC
281871d7fec4Smrgvoid
281971d7fec4Smrgsc1200_get_alpha_size(unsigned short *x, unsigned short *y,
282071d7fec4Smrg		      unsigned short *width, unsigned short *height)
282171d7fec4Smrg#else
282271d7fec4Smrgvoid
282371d7fec4Smrggfx_get_alpha_size(unsigned short *x, unsigned short *y,
282471d7fec4Smrg		   unsigned short *width, unsigned short *height)
282571d7fec4Smrg#endif
282671d7fec4Smrg{
282771d7fec4Smrg   unsigned long value = 0;
282871d7fec4Smrg
282971d7fec4Smrg   *x = 0;
283071d7fec4Smrg   *y = 0;
283171d7fec4Smrg   *width = 0;
283271d7fec4Smrg   *height = 0;
283371d7fec4Smrg   if (gfx_alpha_select <= 2) {
283471d7fec4Smrg      value =
283571d7fec4Smrg	    READ_VID32(SC1200_ALPHA_XPOS_1 +
283671d7fec4Smrg		       ((unsigned long)gfx_alpha_select << 4));
283771d7fec4Smrg      *x = (unsigned short)(value & 0x000007FF);
283871d7fec4Smrg      *width = (unsigned short)((value >> 16) & 0x000007FF) - *x;
283971d7fec4Smrg      value =
284071d7fec4Smrg	    READ_VID32(SC1200_ALPHA_YPOS_1 +
284171d7fec4Smrg		       ((unsigned long)gfx_alpha_select << 4));
284271d7fec4Smrg      *y = (unsigned short)(value & 0x000007FF);
284371d7fec4Smrg      *height = (unsigned short)((value >> 16) & 0x000007FF) - *y;
284471d7fec4Smrg   }
284571d7fec4Smrg   *x -= gfx_get_htotal() - gfx_get_hsync_end() - 2;
284671d7fec4Smrg   *y -= gfx_get_vtotal() - gfx_get_vsync_end() + 1;
284771d7fec4Smrg   return;
284871d7fec4Smrg}
284971d7fec4Smrg
285071d7fec4Smrg/*---------------------------------------------------------------------------
285171d7fec4Smrg * gfx_get_alpha_value
285271d7fec4Smrg *
285371d7fec4Smrg * This routine returns the alpha value and increment/decrement value of
285471d7fec4Smrg * the currently selected alpha region.
285571d7fec4Smrg *---------------------------------------------------------------------------
285671d7fec4Smrg */
285771d7fec4Smrg#if GFX_VIDEO_DYNAMIC
285871d7fec4Smrgvoid
285971d7fec4Smrgsc1200_get_alpha_value(unsigned char *alpha, char *delta)
286071d7fec4Smrg#else
286171d7fec4Smrgvoid
286271d7fec4Smrggfx_get_alpha_value(unsigned char *alpha, char *delta)
286371d7fec4Smrg#endif
286471d7fec4Smrg{
286571d7fec4Smrg   unsigned long value = 0;
286671d7fec4Smrg
286771d7fec4Smrg   *alpha = 0;
286871d7fec4Smrg   *delta = 0;
286971d7fec4Smrg   if (gfx_alpha_select <= 2) {
287071d7fec4Smrg      value =
287171d7fec4Smrg	    READ_VID32(SC1200_ALPHA_CONTROL_1 +
287271d7fec4Smrg		       ((unsigned long)gfx_alpha_select << 4));
287371d7fec4Smrg      *alpha = (unsigned char)(value & 0x00FF);
287471d7fec4Smrg      *delta = (char)((value >> 8) & 0x00FF);
287571d7fec4Smrg   }
287671d7fec4Smrg   return;
287771d7fec4Smrg}
287871d7fec4Smrg
287971d7fec4Smrg/*---------------------------------------------------------------------------
288071d7fec4Smrg * gfx_get_alpha_priority
288171d7fec4Smrg *
288271d7fec4Smrg * This routine returns the priority of the currently selected alpha region.
288371d7fec4Smrg *---------------------------------------------------------------------------
288471d7fec4Smrg */
288571d7fec4Smrg#if GFX_VIDEO_DYNAMIC
288671d7fec4Smrgvoid
288771d7fec4Smrgsc1200_get_alpha_priority(int *priority)
288871d7fec4Smrg#else
288971d7fec4Smrgvoid
289071d7fec4Smrggfx_get_alpha_priority(int *priority)
289171d7fec4Smrg#endif
289271d7fec4Smrg{
289371d7fec4Smrg   unsigned long pos = 0, value = 0;
289471d7fec4Smrg
289571d7fec4Smrg   *priority = 0;
289671d7fec4Smrg   if (gfx_alpha_select <= 2) {
289771d7fec4Smrg      value = READ_VID32(SC1200_VID_ALPHA_CONTROL);
289871d7fec4Smrg      pos = 16 + (gfx_alpha_select << 1);
289971d7fec4Smrg      *priority = (int)((value >> pos) & 3);
290071d7fec4Smrg   }
290171d7fec4Smrg   return;
290271d7fec4Smrg}
290371d7fec4Smrg
290471d7fec4Smrg/*---------------------------------------------------------------------------
290571d7fec4Smrg * gfx_get_alpha_color
290671d7fec4Smrg *
290771d7fec4Smrg * This routine returns the color register value for the currently selected
290871d7fec4Smrg * alpha region.  Bit 24 is set if the color register is enabled.
290971d7fec4Smrg *---------------------------------------------------------------------------
291071d7fec4Smrg */
291171d7fec4Smrg#if GFX_VIDEO_DYNAMIC
291271d7fec4Smrgvoid
291371d7fec4Smrgsc1200_get_alpha_color(unsigned long *color)
291471d7fec4Smrg#else
291571d7fec4Smrgvoid
291671d7fec4Smrggfx_get_alpha_color(unsigned long *color)
291771d7fec4Smrg#endif
291871d7fec4Smrg{
291971d7fec4Smrg   *color = 0;
292071d7fec4Smrg   if (gfx_alpha_select <= 2) {
292171d7fec4Smrg      *color =
292271d7fec4Smrg	    READ_VID32(SC1200_ALPHA_COLOR_1 +
292371d7fec4Smrg		       ((unsigned long)gfx_alpha_select << 4));
292471d7fec4Smrg   }
292571d7fec4Smrg   return;
292671d7fec4Smrg}
292771d7fec4Smrg
292871d7fec4Smrg#endif /* GFX_READ_ROUTINES */
292971d7fec4Smrg
293071d7fec4Smrg/* END OF FILE */
2931