171d7fec4Smrg/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nsc/gfx/vip_1200.c,v 1.1 2002/12/10 15:12:27 alanh Exp $ */
271d7fec4Smrg/*
371d7fec4Smrg * $Workfile: vip_1200.c $
471d7fec4Smrg *
571d7fec4Smrg * This file contains routines to control the SC1200 video input port (VIP) hardware.
671d7fec4Smrg *
771d7fec4Smrg * NSC_LIC_ALTERNATIVE_PREAMBLE
871d7fec4Smrg *
971d7fec4Smrg * Revision 1.0
1071d7fec4Smrg *
1171d7fec4Smrg * National Semiconductor Alternative GPL-BSD License
1271d7fec4Smrg *
1371d7fec4Smrg * National Semiconductor Corporation licenses this software
1471d7fec4Smrg * ("Software"):
1571d7fec4Smrg *
1671d7fec4Smrg *      Durango
1771d7fec4Smrg *
1871d7fec4Smrg * under one of the two following licenses, depending on how the
1971d7fec4Smrg * Software is received by the Licensee.
2071d7fec4Smrg *
2171d7fec4Smrg * If this Software is received as part of the Linux Framebuffer or
2271d7fec4Smrg * other GPL licensed software, then the GPL license designated
2371d7fec4Smrg * NSC_LIC_GPL applies to this Software; in all other circumstances
2471d7fec4Smrg * then the BSD-style license designated NSC_LIC_BSD shall apply.
2571d7fec4Smrg *
2671d7fec4Smrg * END_NSC_LIC_ALTERNATIVE_PREAMBLE */
2771d7fec4Smrg
2871d7fec4Smrg/* NSC_LIC_BSD
2971d7fec4Smrg *
3071d7fec4Smrg * National Semiconductor Corporation Open Source License for Durango
3171d7fec4Smrg *
3271d7fec4Smrg * (BSD License with Export Notice)
3371d7fec4Smrg *
3471d7fec4Smrg * Copyright (c) 1999-2001
3571d7fec4Smrg * National Semiconductor Corporation.
3671d7fec4Smrg * All rights reserved.
3771d7fec4Smrg *
3871d7fec4Smrg * Redistribution and use in source and binary forms, with or without
3971d7fec4Smrg * modification, are permitted provided that the following conditions
4071d7fec4Smrg * are met:
4171d7fec4Smrg *
4271d7fec4Smrg *   * Redistributions of source code must retain the above copyright
4371d7fec4Smrg *     notice, this list of conditions and the following disclaimer.
4471d7fec4Smrg *
4571d7fec4Smrg *   * Redistributions in binary form must reproduce the above
4671d7fec4Smrg *     copyright notice, this list of conditions and the following
4771d7fec4Smrg *     disclaimer in the documentation and/or other materials provided
4871d7fec4Smrg *     with the distribution.
4971d7fec4Smrg *
5071d7fec4Smrg *   * Neither the name of the National Semiconductor Corporation nor
5171d7fec4Smrg *     the names of its contributors may be used to endorse or promote
5271d7fec4Smrg *     products derived from this software without specific prior
5371d7fec4Smrg *     written permission.
5471d7fec4Smrg *
5571d7fec4Smrg * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
5671d7fec4Smrg * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
5771d7fec4Smrg * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
5871d7fec4Smrg * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
5971d7fec4Smrg * NATIONAL SEMICONDUCTOR CORPORATION OR CONTRIBUTORS BE LIABLE FOR ANY
6071d7fec4Smrg * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
6171d7fec4Smrg * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
6271d7fec4Smrg * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
6371d7fec4Smrg * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
6471d7fec4Smrg * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE,
6571d7fec4Smrg * INTELLECTUAL PROPERTY INFRINGEMENT, OR OTHERWISE) ARISING IN ANY WAY
6671d7fec4Smrg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
6771d7fec4Smrg * OF SUCH DAMAGE.
6871d7fec4Smrg *
6971d7fec4Smrg * EXPORT LAWS: THIS LICENSE ADDS NO RESTRICTIONS TO THE EXPORT LAWS OF
7071d7fec4Smrg * YOUR JURISDICTION. It is licensee's responsibility to comply with
7171d7fec4Smrg * any export regulations applicable in licensee's jurisdiction. Under
7271d7fec4Smrg * CURRENT (2001) U.S. export regulations this software
7371d7fec4Smrg * is eligible for export from the U.S. and can be downloaded by or
7471d7fec4Smrg * otherwise exported or reexported worldwide EXCEPT to U.S. embargoed
7571d7fec4Smrg * destinations which include Cuba, Iraq, Libya, North Korea, Iran,
7671d7fec4Smrg * Syria, Sudan, Afghanistan and any other country to which the U.S.
7771d7fec4Smrg * has embargoed goods and services.
7871d7fec4Smrg *
7971d7fec4Smrg * END_NSC_LIC_BSD */
8071d7fec4Smrg
8171d7fec4Smrg/* NSC_LIC_GPL
8271d7fec4Smrg *
8371d7fec4Smrg * National Semiconductor Corporation Gnu General Public License for Durango
8471d7fec4Smrg *
8571d7fec4Smrg * (GPL License with Export Notice)
8671d7fec4Smrg *
8771d7fec4Smrg * Copyright (c) 1999-2001
8871d7fec4Smrg * National Semiconductor Corporation.
8971d7fec4Smrg * All rights reserved.
9071d7fec4Smrg *
9171d7fec4Smrg * Redistribution and use in source and binary forms, with or without
9271d7fec4Smrg * modification, are permitted under the terms of the GNU General
9371d7fec4Smrg * Public License as published by the Free Software Foundation; either
9471d7fec4Smrg * version 2 of the License, or (at your option) any later version
9571d7fec4Smrg *
9671d7fec4Smrg * In addition to the terms of the GNU General Public License, neither
9771d7fec4Smrg * the name of the National Semiconductor Corporation nor the names of
9871d7fec4Smrg * its contributors may be used to endorse or promote products derived
9971d7fec4Smrg * from this software without specific prior written permission.
10071d7fec4Smrg *
10171d7fec4Smrg * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
10271d7fec4Smrg * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
10371d7fec4Smrg * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
10471d7fec4Smrg * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
10571d7fec4Smrg * NATIONAL SEMICONDUCTOR CORPORATION OR CONTRIBUTORS BE LIABLE FOR ANY
10671d7fec4Smrg * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
10771d7fec4Smrg * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
10871d7fec4Smrg * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
10971d7fec4Smrg * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
11071d7fec4Smrg * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE,
11171d7fec4Smrg * INTELLECTUAL PROPERTY INFRINGEMENT, OR OTHERWISE) ARISING IN ANY WAY
11271d7fec4Smrg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
11371d7fec4Smrg * OF SUCH DAMAGE. See the GNU General Public License for more details.
11471d7fec4Smrg *
11571d7fec4Smrg * EXPORT LAWS: THIS LICENSE ADDS NO RESTRICTIONS TO THE EXPORT LAWS OF
11671d7fec4Smrg * YOUR JURISDICTION. It is licensee's responsibility to comply with
11771d7fec4Smrg * any export regulations applicable in licensee's jurisdiction. Under
11871d7fec4Smrg * CURRENT (2001) U.S. export regulations this software
11971d7fec4Smrg * is eligible for export from the U.S. and can be downloaded by or
12071d7fec4Smrg * otherwise exported or reexported worldwide EXCEPT to U.S. embargoed
12171d7fec4Smrg * destinations which include Cuba, Iraq, Libya, North Korea, Iran,
12271d7fec4Smrg * Syria, Sudan, Afghanistan and any other country to which the U.S.
12371d7fec4Smrg * has embargoed goods and services.
12471d7fec4Smrg *
12571d7fec4Smrg * You should have received a copy of the GNU General Public License
12671d7fec4Smrg * along with this file; if not, write to the Free Software Foundation,
12771d7fec4Smrg * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
12871d7fec4Smrg *
12971d7fec4Smrg * END_NSC_LIC_GPL */
13071d7fec4Smrg
13171d7fec4Smrgint sc1200_set_vip_enable(int enable);
13271d7fec4Smrgint sc1200_set_vip_capture_run_mode(int mode);
13371d7fec4Smrgint sc1200_set_vip_base(unsigned long even, unsigned long odd);
13471d7fec4Smrgint sc1200_set_vip_pitch(unsigned long pitch);
13571d7fec4Smrgint sc1200_set_vip_mode(int mode);
13671d7fec4Smrgint sc1200_set_vbi_enable(int enable);
13771d7fec4Smrgint sc1200_set_vbi_mode(int mode);
13871d7fec4Smrgint sc1200_set_vbi_base(unsigned long even, unsigned long odd);
13971d7fec4Smrgint sc1200_set_vbi_pitch(unsigned long pitch);
14071d7fec4Smrgint sc1200_set_vbi_direct(unsigned long even_lines, unsigned long odd_lines);
14171d7fec4Smrgint sc1200_set_vbi_interrupt(int enable);
14271d7fec4Smrgint sc1200_set_vip_bus_request_threshold_high(int enable);
14371d7fec4Smrgint sc1200_set_vip_last_line(int last_line);
14471d7fec4Smrgint sc1200_test_vip_odd_field(void);
14571d7fec4Smrgint sc1200_test_vip_bases_updated(void);
14671d7fec4Smrgint sc1200_test_vip_fifo_overflow(void);
14771d7fec4Smrgint sc1200_get_vip_line(void);
14871d7fec4Smrg
14971d7fec4Smrg/* READ ROUTINES IN GFX_VIP.C */
15071d7fec4Smrg
15171d7fec4Smrgint sc1200_get_vip_enable(void);
15271d7fec4Smrgunsigned long sc1200_get_vip_base(int odd);
15371d7fec4Smrgunsigned long sc1200_get_vip_pitch(void);
15471d7fec4Smrgint sc1200_get_vip_mode(void);
15571d7fec4Smrgint sc1200_get_vbi_enable(void);
15671d7fec4Smrgint sc1200_get_vbi_mode(void);
15771d7fec4Smrgunsigned long sc1200_get_vbi_base(int odd);
15871d7fec4Smrgunsigned long sc1200_get_vbi_pitch(void);
15971d7fec4Smrgunsigned long sc1200_get_vbi_direct(int odd);
16071d7fec4Smrgint sc1200_get_vbi_interrupt(void);
16171d7fec4Smrgint sc1200_get_vip_bus_request_threshold_high(void);
16271d7fec4Smrg
16371d7fec4Smrg/*-----------------------------------------------------------------------------
16471d7fec4Smrg * gfx_set_vip_enable
16571d7fec4Smrg *
16671d7fec4Smrg * This routine enables or disables the writes to memory from the video port.
16771d7fec4Smrg *-----------------------------------------------------------------------------
16871d7fec4Smrg */
16971d7fec4Smrg#if GFX_VIP_DYNAMIC
17071d7fec4Smrgint
17171d7fec4Smrgsc1200_set_vip_enable(int enable)
17271d7fec4Smrg#else
17371d7fec4Smrgint
17471d7fec4Smrggfx_set_vip_enable(int enable)
17571d7fec4Smrg#endif
17671d7fec4Smrg{
17771d7fec4Smrg   unsigned long value;
17871d7fec4Smrg
17971d7fec4Smrg   value = READ_VIP32(SC1200_VIP_CONTROL);
18071d7fec4Smrg   if (enable)
18171d7fec4Smrg      value |= SC1200_VIP_DATA_CAPTURE_EN;
18271d7fec4Smrg   else
18371d7fec4Smrg      value &= ~SC1200_VIP_DATA_CAPTURE_EN;
18471d7fec4Smrg   WRITE_VIP32(SC1200_VIP_CONTROL, value);
18571d7fec4Smrg   return (0);
18671d7fec4Smrg}
18771d7fec4Smrg
18871d7fec4Smrg/*-----------------------------------------------------------------------------
18971d7fec4Smrg * gfx_set_vip_capture_run_mode
19071d7fec4Smrg *
19171d7fec4Smrg * This routine selects VIP capture run mode.
19271d7fec4Smrg *-----------------------------------------------------------------------------
19371d7fec4Smrg */
19471d7fec4Smrg#if GFX_VIP_DYNAMIC
19571d7fec4Smrgint
19671d7fec4Smrgsc1200_set_vip_capture_run_mode(int mode)
19771d7fec4Smrg#else
19871d7fec4Smrgint
19971d7fec4Smrggfx_set_vip_capture_run_mode(int mode)
20071d7fec4Smrg#endif
20171d7fec4Smrg{
20271d7fec4Smrg   unsigned long value;
20371d7fec4Smrg
20471d7fec4Smrg   value = READ_VIP32(SC1200_VIP_CONTROL);
20571d7fec4Smrg   value &= ~SC1200_CAPTURE_RUN_MODE_MASK;
20671d7fec4Smrg   switch (mode) {
20771d7fec4Smrg   case VIP_CAPTURE_STOP_LINE:
20871d7fec4Smrg      value |= SC1200_CAPTURE_RUN_MODE_STOP_LINE;
20971d7fec4Smrg      break;
21071d7fec4Smrg   case VIP_CAPTURE_STOP_FIELD:
21171d7fec4Smrg      value |= SC1200_CAPTURE_RUN_MODE_STOP_FIELD;
21271d7fec4Smrg      break;
21371d7fec4Smrg   case VIP_CAPTURE_START_FIELD:
21471d7fec4Smrg      value |= SC1200_CAPTURE_RUN_MODE_START;
21571d7fec4Smrg      break;
21671d7fec4Smrg   default:
21771d7fec4Smrg      return GFX_STATUS_BAD_PARAMETER;
21871d7fec4Smrg   }
21971d7fec4Smrg   WRITE_VIP32(SC1200_VIP_CONTROL, value);
22071d7fec4Smrg   return (0);
22171d7fec4Smrg}
22271d7fec4Smrg
22371d7fec4Smrg/*-----------------------------------------------------------------------------
22471d7fec4Smrg * gfx_set_vip_base
22571d7fec4Smrg *
22671d7fec4Smrg * This routine sets the odd and even base address values for the VIP memory
22771d7fec4Smrg * buffer.
22871d7fec4Smrg *-----------------------------------------------------------------------------
22971d7fec4Smrg */
23071d7fec4Smrg#if GFX_VIP_DYNAMIC
23171d7fec4Smrgint
23271d7fec4Smrgsc1200_set_vip_base(unsigned long even, unsigned long odd)
23371d7fec4Smrg#else
23471d7fec4Smrgint
23571d7fec4Smrggfx_set_vip_base(unsigned long even, unsigned long odd)
23671d7fec4Smrg#endif
23771d7fec4Smrg{
23871d7fec4Smrg   /* TRUE OFFSET IS SPECIFIED, NEED TO SET BIT 23 FOR HARDWARE */
23971d7fec4Smrg
24071d7fec4Smrg   if (even)
24171d7fec4Smrg      WRITE_VIP32(SC1200_VIP_EVEN_BASE, even + (unsigned long)gfx_phys_fbptr);
24271d7fec4Smrg   if (odd)
24371d7fec4Smrg      WRITE_VIP32(SC1200_VIP_ODD_BASE, odd + (unsigned long)gfx_phys_fbptr);
24471d7fec4Smrg   return (0);
24571d7fec4Smrg}
24671d7fec4Smrg
24771d7fec4Smrg/*-----------------------------------------------------------------------------
24871d7fec4Smrg * gfx_set_vip_pitch
24971d7fec4Smrg *
25071d7fec4Smrg * This routine sets the number of bytes between scanlines for the VIP data.
25171d7fec4Smrg *-----------------------------------------------------------------------------
25271d7fec4Smrg */
25371d7fec4Smrg#if GFX_VIP_DYNAMIC
25471d7fec4Smrgint
25571d7fec4Smrgsc1200_set_vip_pitch(unsigned long pitch)
25671d7fec4Smrg#else
25771d7fec4Smrgint
25871d7fec4Smrggfx_set_vip_pitch(unsigned long pitch)
25971d7fec4Smrg#endif
26071d7fec4Smrg{
26171d7fec4Smrg   WRITE_VIP32(SC1200_VIP_PITCH, pitch & SC1200_VIP_PITCH_MASK);
26271d7fec4Smrg   return (0);
26371d7fec4Smrg}
26471d7fec4Smrg
26571d7fec4Smrg/*-----------------------------------------------------------------------------
26671d7fec4Smrg * gfx_set_vip_mode
26771d7fec4Smrg *
26871d7fec4Smrg * This routine sets the VIP operating mode.
26971d7fec4Smrg *-----------------------------------------------------------------------------
27071d7fec4Smrg */
27171d7fec4Smrg#if GFX_VIP_DYNAMIC
27271d7fec4Smrgint
27371d7fec4Smrgsc1200_set_vip_mode(int mode)
27471d7fec4Smrg#else
27571d7fec4Smrgint
27671d7fec4Smrggfx_set_vip_mode(int mode)
27771d7fec4Smrg#endif
27871d7fec4Smrg{
27971d7fec4Smrg   unsigned long config;
28071d7fec4Smrg
28171d7fec4Smrg   config = READ_VIP32(SC1200_VIP_CONFIG);
28271d7fec4Smrg   config &= ~SC1200_VIP_MODE_MASK;
28371d7fec4Smrg   switch (mode) {
28471d7fec4Smrg   case VIP_MODE_C:
28571d7fec4Smrg      WRITE_VIP32(SC1200_VIP_CONFIG, config | SC1200_VIP_MODE_C);
28671d7fec4Smrg      break;
28771d7fec4Smrg   default:
28871d7fec4Smrg      return GFX_STATUS_BAD_PARAMETER;
28971d7fec4Smrg   }
29071d7fec4Smrg   return (0);
29171d7fec4Smrg}
29271d7fec4Smrg
29371d7fec4Smrg/*-----------------------------------------------------------------------------
29471d7fec4Smrg * gfx_set_vbi_enable
29571d7fec4Smrg *
29671d7fec4Smrg * This routine enables or disables the VBI data capture.
29771d7fec4Smrg *-----------------------------------------------------------------------------
29871d7fec4Smrg */
29971d7fec4Smrg#if GFX_VIP_DYNAMIC
30071d7fec4Smrgint
30171d7fec4Smrgsc1200_set_vbi_enable(int enable)
30271d7fec4Smrg#else
30371d7fec4Smrgint
30471d7fec4Smrggfx_set_vbi_enable(int enable)
30571d7fec4Smrg#endif
30671d7fec4Smrg{
30771d7fec4Smrg   unsigned long value;
30871d7fec4Smrg
30971d7fec4Smrg   value = READ_VIP32(SC1200_VIP_CONTROL);
31071d7fec4Smrg   if (enable)
31171d7fec4Smrg      value |= SC1200_VIP_VBI_CAPTURE_EN;
31271d7fec4Smrg   else
31371d7fec4Smrg      value &= ~SC1200_VIP_VBI_CAPTURE_EN;
31471d7fec4Smrg   WRITE_VIP32(SC1200_VIP_CONTROL, value);
31571d7fec4Smrg   return (0);
31671d7fec4Smrg}
31771d7fec4Smrg
31871d7fec4Smrg/*-----------------------------------------------------------------------------
31971d7fec4Smrg * gfx_set_vbi_mode
32071d7fec4Smrg *
32171d7fec4Smrg * This routine sets the VBI data types captured to memory.
32271d7fec4Smrg * It receives a mask of all enabled types.
32371d7fec4Smrg *-----------------------------------------------------------------------------
32471d7fec4Smrg */
32571d7fec4Smrg#if GFX_VIP_DYNAMIC
32671d7fec4Smrgint
32771d7fec4Smrgsc1200_set_vbi_mode(int mode)
32871d7fec4Smrg#else
32971d7fec4Smrgint
33071d7fec4Smrggfx_set_vbi_mode(int mode)
33171d7fec4Smrg#endif
33271d7fec4Smrg{
33371d7fec4Smrg   unsigned long config;
33471d7fec4Smrg
33571d7fec4Smrg   config = READ_VIP32(SC1200_VIP_CONFIG);
33671d7fec4Smrg   config &=
33771d7fec4Smrg	 ~(SC1200_VBI_ANCILLARY_TO_MEMORY | SC1200_VBI_TASK_A_TO_MEMORY |
33871d7fec4Smrg	   SC1200_VBI_TASK_B_TO_MEMORY);
33971d7fec4Smrg
34071d7fec4Smrg   if (mode & VBI_ANCILLARY)
34171d7fec4Smrg      config |= SC1200_VBI_ANCILLARY_TO_MEMORY;
34271d7fec4Smrg   if (mode & VBI_TASK_A)
34371d7fec4Smrg      config |= SC1200_VBI_TASK_A_TO_MEMORY;
34471d7fec4Smrg   if (mode & VBI_TASK_B)
34571d7fec4Smrg      config |= SC1200_VBI_TASK_B_TO_MEMORY;
34671d7fec4Smrg   WRITE_VIP32(SC1200_VIP_CONFIG, config);
34771d7fec4Smrg   return (0);
34871d7fec4Smrg}
34971d7fec4Smrg
35071d7fec4Smrg/*-----------------------------------------------------------------------------
35171d7fec4Smrg * gfx_set_vbi_base
35271d7fec4Smrg *
35371d7fec4Smrg * This routine sets the odd and even base address values for VBI capture.
35471d7fec4Smrg *
35571d7fec4Smrg * "even" and "odd" should contain 16-byte aligned physical addresses.
35671d7fec4Smrg *-----------------------------------------------------------------------------
35771d7fec4Smrg */
35871d7fec4Smrg#if GFX_VIP_DYNAMIC
35971d7fec4Smrgint
36071d7fec4Smrgsc1200_set_vbi_base(unsigned long even, unsigned long odd)
36171d7fec4Smrg#else
36271d7fec4Smrgint
36371d7fec4Smrggfx_set_vbi_base(unsigned long even, unsigned long odd)
36471d7fec4Smrg#endif
36571d7fec4Smrg{
36671d7fec4Smrg   /* VIP HW REQUIRES THAT BASE ADDRESSES BE 16-BYTE ALIGNED */
36771d7fec4Smrg
36871d7fec4Smrg   if (even)
36971d7fec4Smrg      WRITE_VIP32(SC1200_VBI_EVEN_BASE, even & ~0xf);
37071d7fec4Smrg   if (odd)
37171d7fec4Smrg      WRITE_VIP32(SC1200_VBI_ODD_BASE, odd & ~0xf);
37271d7fec4Smrg
37371d7fec4Smrg   return (0);
37471d7fec4Smrg}
37571d7fec4Smrg
37671d7fec4Smrg/*-----------------------------------------------------------------------------
37771d7fec4Smrg * gfx_set_vbi_pitch
37871d7fec4Smrg *
37971d7fec4Smrg * This routine sets the number of bytes between scanlines for VBI capture.
38071d7fec4Smrg *-----------------------------------------------------------------------------
38171d7fec4Smrg */
38271d7fec4Smrg#if GFX_VIP_DYNAMIC
38371d7fec4Smrgint
38471d7fec4Smrgsc1200_set_vbi_pitch(unsigned long pitch)
38571d7fec4Smrg#else
38671d7fec4Smrgint
38771d7fec4Smrggfx_set_vbi_pitch(unsigned long pitch)
38871d7fec4Smrg#endif
38971d7fec4Smrg{
39071d7fec4Smrg   WRITE_VIP32(SC1200_VBI_PITCH, pitch & SC1200_VBI_PITCH_MASK);
39171d7fec4Smrg   return (0);
39271d7fec4Smrg}
39371d7fec4Smrg
39471d7fec4Smrg/*-----------------------------------------------------------------------------
39571d7fec4Smrg * gfx_set_vbi_direct
39671d7fec4Smrg *
39771d7fec4Smrg * This routine sets the VBI lines to be passed to the Direct VIP.
39871d7fec4Smrg *-----------------------------------------------------------------------------
39971d7fec4Smrg */
40071d7fec4Smrg#if GFX_VIP_DYNAMIC
40171d7fec4Smrgint
40271d7fec4Smrgsc1200_set_vbi_direct(unsigned long even_lines, unsigned long odd_lines)
40371d7fec4Smrg#else
40471d7fec4Smrgint
40571d7fec4Smrggfx_set_vbi_direct(unsigned long even_lines, unsigned long odd_lines)
40671d7fec4Smrg#endif
40771d7fec4Smrg{
40871d7fec4Smrg   WRITE_VIP32(SC1200_EVEN_DIRECT_VBI_LINE_ENABLE,
40971d7fec4Smrg	       even_lines & SC1200_DIRECT_VBI_LINE_ENABLE_MASK);
41071d7fec4Smrg   WRITE_VIP32(SC1200_ODD_DIRECT_VBI_LINE_ENABLE,
41171d7fec4Smrg	       odd_lines & SC1200_DIRECT_VBI_LINE_ENABLE_MASK);
41271d7fec4Smrg   return (0);
41371d7fec4Smrg}
41471d7fec4Smrg
41571d7fec4Smrg/*-----------------------------------------------------------------------------
41671d7fec4Smrg * gfx_set_vbi_interrupt
41771d7fec4Smrg *
41871d7fec4Smrg * This routine enables or disables the VBI field interrupt.
41971d7fec4Smrg *-----------------------------------------------------------------------------
42071d7fec4Smrg */
42171d7fec4Smrg#if GFX_VIP_DYNAMIC
42271d7fec4Smrgint
42371d7fec4Smrgsc1200_set_vbi_interrupt(int enable)
42471d7fec4Smrg#else
42571d7fec4Smrgint
42671d7fec4Smrggfx_set_vbi_interrupt(int enable)
42771d7fec4Smrg#endif
42871d7fec4Smrg{
42971d7fec4Smrg   unsigned long value;
43071d7fec4Smrg
43171d7fec4Smrg   value = READ_VIP32(SC1200_VIP_CONTROL);
43271d7fec4Smrg   if (enable)
43371d7fec4Smrg      value |= SC1200_VIP_VBI_FIELD_INTERRUPT_EN;
43471d7fec4Smrg   else
43571d7fec4Smrg      value &= ~SC1200_VIP_VBI_FIELD_INTERRUPT_EN;
43671d7fec4Smrg   WRITE_VIP32(SC1200_VIP_CONTROL, value);
43771d7fec4Smrg   return (0);
43871d7fec4Smrg}
43971d7fec4Smrg
44071d7fec4Smrg/*-----------------------------------------------------------------------------
44171d7fec4Smrg * gfx_set_vip_bus_request_threshold_high
44271d7fec4Smrg *
44371d7fec4Smrg * This routine sets the VIP FIFO bus request threshold.
44471d7fec4Smrg * If enable is TRUE, VIP FIFO will be set to issue a bus request when it filled with 64 bytes.
44571d7fec4Smrg * If enable is FALSE, VIP FIFO will be set to issue a bus request when it filled with 32 bytes.
44671d7fec4Smrg *-----------------------------------------------------------------------------
44771d7fec4Smrg */
44871d7fec4Smrg#if GFX_VIP_DYNAMIC
44971d7fec4Smrgint
45071d7fec4Smrgsc1200_set_vip_bus_request_threshold_high(int enable)
45171d7fec4Smrg#else
45271d7fec4Smrgint
45371d7fec4Smrggfx_set_vip_bus_request_threshold_high(int enable)
45471d7fec4Smrg#endif
45571d7fec4Smrg{
45671d7fec4Smrg   unsigned long value;
45771d7fec4Smrg
45871d7fec4Smrg   value = READ_VIP32(SC1200_VIP_CONFIG);
45971d7fec4Smrg   if (enable)
46071d7fec4Smrg      value &= ~SC1200_VIP_BUS_REQUEST_THRESHOLD;
46171d7fec4Smrg   else
46271d7fec4Smrg      value |= SC1200_VIP_BUS_REQUEST_THRESHOLD;
46371d7fec4Smrg   WRITE_VIP32(SC1200_VIP_CONFIG, value);
46471d7fec4Smrg   return (0);
46571d7fec4Smrg}
46671d7fec4Smrg
46771d7fec4Smrg/*-----------------------------------------------------------------------------
46871d7fec4Smrg * gfx_set_vip_last_line
46971d7fec4Smrg *
47071d7fec4Smrg * This routine sets the maximum number of lines captured in each field.
47171d7fec4Smrg *-----------------------------------------------------------------------------
47271d7fec4Smrg */
47371d7fec4Smrg#if GFX_VIP_DYNAMIC
47471d7fec4Smrgint
47571d7fec4Smrgsc1200_set_vip_last_line(int last_line)
47671d7fec4Smrg#else
47771d7fec4Smrgint
47871d7fec4Smrggfx_set_vip_last_line(int last_line)
47971d7fec4Smrg#endif
48071d7fec4Smrg{
48171d7fec4Smrg   unsigned long value;
48271d7fec4Smrg
48371d7fec4Smrg   /* This feature is implemented in Rev C1 */
48471d7fec4Smrg   if (gfx_chip_revision < SC1200_REV_C1)
48571d7fec4Smrg      return (GFX_STATUS_OK);
48671d7fec4Smrg
48771d7fec4Smrg   value = READ_VIP32(SC1200_VIP_LINE_TARGET);
48871d7fec4Smrg   value &= ~SC1200_VIP_LAST_LINE_MASK;
48971d7fec4Smrg   value |= ((last_line & 0x3FF) << 16);
49071d7fec4Smrg   WRITE_VIP32(SC1200_VIP_LINE_TARGET, value);
49171d7fec4Smrg   return (GFX_STATUS_OK);
49271d7fec4Smrg}
49371d7fec4Smrg
49471d7fec4Smrg/*-----------------------------------------------------------------------------
49571d7fec4Smrg * gfx_test_vip_odd_field
49671d7fec4Smrg *
49771d7fec4Smrg * This routine returns 1 if the current VIP field is odd. Otherwise returns 0.
49871d7fec4Smrg *-----------------------------------------------------------------------------
49971d7fec4Smrg */
50071d7fec4Smrg#if GFX_VIP_DYNAMIC
50171d7fec4Smrgint
50271d7fec4Smrgsc1200_test_vip_odd_field(void)
50371d7fec4Smrg#else
50471d7fec4Smrgint
50571d7fec4Smrggfx_test_vip_odd_field(void)
50671d7fec4Smrg#endif
50771d7fec4Smrg{
50871d7fec4Smrg   if (READ_VIP32(SC1200_VIP_STATUS) & SC1200_VIP_CURRENT_FIELD_ODD)
50971d7fec4Smrg      return (1);
51071d7fec4Smrg   else
51171d7fec4Smrg      return (0);
51271d7fec4Smrg}
51371d7fec4Smrg
51471d7fec4Smrg/*-----------------------------------------------------------------------------
51571d7fec4Smrg * gfx_test_vip_bases_updated
51671d7fec4Smrg *
51771d7fec4Smrg * This routine returns 1 if all of the VIP base registers have been updated,
51871d7fec4Smrg * i.e. there is no base register which has been written with a new address,
51971d7fec4Smrg * that VIP has not already captured or started capturing into the new address.
52071d7fec4Smrg *-----------------------------------------------------------------------------
52171d7fec4Smrg */
52271d7fec4Smrg#if GFX_VIP_DYNAMIC
52371d7fec4Smrgint
52471d7fec4Smrgsc1200_test_vip_bases_updated(void)
52571d7fec4Smrg#else
52671d7fec4Smrgint
52771d7fec4Smrggfx_test_vip_bases_updated(void)
52871d7fec4Smrg#endif
52971d7fec4Smrg{
53071d7fec4Smrg   if (READ_VIP32(SC1200_VIP_STATUS) & SC1200_VIP_BASE_NOT_UPDATED)
53171d7fec4Smrg      return (0);
53271d7fec4Smrg   else
53371d7fec4Smrg      return (1);
53471d7fec4Smrg}
53571d7fec4Smrg
53671d7fec4Smrg/*-----------------------------------------------------------------------------
53771d7fec4Smrg * gfx_test_vip_fifo_overflow
53871d7fec4Smrg *
53971d7fec4Smrg * This routine returns 1 if an overflow occurred on the FIFO between the VIP
54071d7fec4Smrg * and the fast X-bus, 0 otherwise.
54171d7fec4Smrg * If an overflow occurred, the overflow status indication is reset.
54271d7fec4Smrg *-----------------------------------------------------------------------------
54371d7fec4Smrg */
54471d7fec4Smrg#if GFX_VIP_DYNAMIC
54571d7fec4Smrgint
54671d7fec4Smrgsc1200_test_vip_fifo_overflow(void)
54771d7fec4Smrg#else
54871d7fec4Smrgint
54971d7fec4Smrggfx_test_vip_fifo_overflow(void)
55071d7fec4Smrg#endif
55171d7fec4Smrg{
55271d7fec4Smrg   if (READ_VIP32(SC1200_VIP_STATUS) & SC1200_VIP_FIFO_OVERFLOW) {
55371d7fec4Smrg      /* Bits in vip status register are either read only or reset by writing 1 */
55471d7fec4Smrg      WRITE_VIP32(SC1200_VIP_STATUS, SC1200_VIP_FIFO_OVERFLOW);
55571d7fec4Smrg      return (1);
55671d7fec4Smrg   } else {
55771d7fec4Smrg      return (0);
55871d7fec4Smrg   }
55971d7fec4Smrg}
56071d7fec4Smrg
56171d7fec4Smrg/*-----------------------------------------------------------------------------
56271d7fec4Smrg * gfx_get_vip_line
56371d7fec4Smrg *
56471d7fec4Smrg * This routine returns the number of the current video line being
56571d7fec4Smrg * received by the VIP interface.
56671d7fec4Smrg *-----------------------------------------------------------------------------
56771d7fec4Smrg */
56871d7fec4Smrg#if GFX_VIP_DYNAMIC
56971d7fec4Smrgint
57071d7fec4Smrgsc1200_get_vip_line(void)
57171d7fec4Smrg#else
57271d7fec4Smrgint
57371d7fec4Smrggfx_get_vip_line(void)
57471d7fec4Smrg#endif
57571d7fec4Smrg{
57671d7fec4Smrg   return (int)(READ_VIP32(SC1200_VIP_CURRENT_LINE) &
57771d7fec4Smrg		SC1200_VIP_CURRENT_LINE_MASK);
57871d7fec4Smrg}
57971d7fec4Smrg
58071d7fec4Smrg/*-----------------------------------------------------------------------------
58171d7fec4Smrg * gfx_get_vip_base
58271d7fec4Smrg *-----------------------------------------------------------------------------
58371d7fec4Smrg */
58471d7fec4Smrg#if GFX_VIP_DYNAMIC
58571d7fec4Smrgunsigned long
58671d7fec4Smrgsc1200_get_vip_base(int odd)
58771d7fec4Smrg#else
58871d7fec4Smrgunsigned long
58971d7fec4Smrggfx_get_vip_base(int odd)
59071d7fec4Smrg#endif
59171d7fec4Smrg{
59271d7fec4Smrg   /* MASK BIT 23 AND ABOVE TO MAKE IT A TRUE OFFSET */
59371d7fec4Smrg
59471d7fec4Smrg   if (odd)
59571d7fec4Smrg      return (READ_VIP32(SC1200_VIP_ODD_BASE));
59671d7fec4Smrg   return (READ_VIP32(SC1200_VIP_EVEN_BASE));
59771d7fec4Smrg}
59871d7fec4Smrg
59971d7fec4Smrg/*-----------------------------------------------------------------------------
60071d7fec4Smrg * gfx_get_vbi_pitch
60171d7fec4Smrg *-----------------------------------------------------------------------------
60271d7fec4Smrg */
60371d7fec4Smrg#if GFX_VIP_DYNAMIC
60471d7fec4Smrgunsigned long
60571d7fec4Smrgsc1200_get_vbi_pitch(void)
60671d7fec4Smrg#else
60771d7fec4Smrgunsigned long
60871d7fec4Smrggfx_get_vbi_pitch(void)
60971d7fec4Smrg#endif
61071d7fec4Smrg{
61171d7fec4Smrg   return (READ_VIP32(SC1200_VBI_PITCH) & SC1200_VBI_PITCH_MASK);
61271d7fec4Smrg}
61371d7fec4Smrg
61471d7fec4Smrg/*************************************************************/
61571d7fec4Smrg/*  READ ROUTINES  |  INCLUDED FOR DIAGNOSTIC PURPOSES ONLY  */
61671d7fec4Smrg/*************************************************************/
61771d7fec4Smrg
61871d7fec4Smrg#if GFX_READ_ROUTINES
61971d7fec4Smrg
62071d7fec4Smrg/*-----------------------------------------------------------------------------
62171d7fec4Smrg * gfx_get_vip_enable
62271d7fec4Smrg *-----------------------------------------------------------------------------
62371d7fec4Smrg */
62471d7fec4Smrg#if GFX_VIP_DYNAMIC
62571d7fec4Smrgint
62671d7fec4Smrgsc1200_get_vip_enable(void)
62771d7fec4Smrg#else
62871d7fec4Smrgint
62971d7fec4Smrggfx_get_vip_enable(void)
63071d7fec4Smrg#endif
63171d7fec4Smrg{
63271d7fec4Smrg   if (READ_VIP32(SC1200_VIP_CONTROL) & SC1200_VIP_DATA_CAPTURE_EN)
63371d7fec4Smrg      return (1);
63471d7fec4Smrg   return (0);
63571d7fec4Smrg}
63671d7fec4Smrg
63771d7fec4Smrg/*-----------------------------------------------------------------------------
63871d7fec4Smrg * gfx_get_vip_pitch
63971d7fec4Smrg *-----------------------------------------------------------------------------
64071d7fec4Smrg */
64171d7fec4Smrg#if GFX_VIP_DYNAMIC
64271d7fec4Smrgunsigned long
64371d7fec4Smrgsc1200_get_vip_pitch(void)
64471d7fec4Smrg#else
64571d7fec4Smrgunsigned long
64671d7fec4Smrggfx_get_vip_pitch(void)
64771d7fec4Smrg#endif
64871d7fec4Smrg{
64971d7fec4Smrg   return (READ_VIP32(SC1200_VIP_PITCH) & SC1200_VIP_PITCH_MASK);
65071d7fec4Smrg}
65171d7fec4Smrg
65271d7fec4Smrg/*-----------------------------------------------------------------------------
65371d7fec4Smrg * gfx_get_vip_mode
65471d7fec4Smrg *-----------------------------------------------------------------------------
65571d7fec4Smrg */
65671d7fec4Smrg#if GFX_VIP_DYNAMIC
65771d7fec4Smrgint
65871d7fec4Smrgsc1200_get_vip_mode(void)
65971d7fec4Smrg#else
66071d7fec4Smrgint
66171d7fec4Smrggfx_get_vip_mode(void)
66271d7fec4Smrg#endif
66371d7fec4Smrg{
66471d7fec4Smrg   switch (READ_VIP32(SC1200_VIP_CONFIG) & SC1200_VIP_MODE_MASK) {
66571d7fec4Smrg   case SC1200_VIP_MODE_C:
66671d7fec4Smrg      return VIP_MODE_C;
66771d7fec4Smrg   default:
66871d7fec4Smrg      return (0);
66971d7fec4Smrg   }
67071d7fec4Smrg}
67171d7fec4Smrg
67271d7fec4Smrg/*-----------------------------------------------------------------------------
67371d7fec4Smrg * gfx_get_vbi_enable
67471d7fec4Smrg *-----------------------------------------------------------------------------
67571d7fec4Smrg */
67671d7fec4Smrg#if GFX_VIP_DYNAMIC
67771d7fec4Smrgint
67871d7fec4Smrgsc1200_get_vbi_enable(void)
67971d7fec4Smrg#else
68071d7fec4Smrgint
68171d7fec4Smrggfx_get_vbi_enable(void)
68271d7fec4Smrg#endif
68371d7fec4Smrg{
68471d7fec4Smrg   if (READ_VIP32(SC1200_VIP_CONTROL) & SC1200_VIP_VBI_CAPTURE_EN)
68571d7fec4Smrg      return (1);
68671d7fec4Smrg   return (0);
68771d7fec4Smrg}
68871d7fec4Smrg
68971d7fec4Smrg/*-----------------------------------------------------------------------------
69071d7fec4Smrg * gfx_get_vbi_mode
69171d7fec4Smrg *-----------------------------------------------------------------------------
69271d7fec4Smrg */
69371d7fec4Smrg#if GFX_VIP_DYNAMIC
69471d7fec4Smrgint
69571d7fec4Smrgsc1200_get_vbi_mode(void)
69671d7fec4Smrg#else
69771d7fec4Smrgint
69871d7fec4Smrggfx_get_vbi_mode(void)
69971d7fec4Smrg#endif
70071d7fec4Smrg{
70171d7fec4Smrg   int config;
70271d7fec4Smrg   int mode = 0;
70371d7fec4Smrg
70471d7fec4Smrg   config =
70571d7fec4Smrg	 (int)(READ_VIP32(SC1200_VIP_CONFIG) &
70671d7fec4Smrg	       (SC1200_VBI_ANCILLARY_TO_MEMORY | SC1200_VBI_TASK_A_TO_MEMORY |
70771d7fec4Smrg		SC1200_VBI_TASK_B_TO_MEMORY));
70871d7fec4Smrg   if (config & SC1200_VBI_ANCILLARY_TO_MEMORY)
70971d7fec4Smrg      mode |= VBI_ANCILLARY;
71071d7fec4Smrg   if (config & SC1200_VBI_TASK_A_TO_MEMORY)
71171d7fec4Smrg      mode |= VBI_TASK_A;
71271d7fec4Smrg   if (config & SC1200_VBI_TASK_B_TO_MEMORY)
71371d7fec4Smrg      mode |= VBI_TASK_B;
71471d7fec4Smrg   return mode;
71571d7fec4Smrg}
71671d7fec4Smrg
71771d7fec4Smrg/*-----------------------------------------------------------------------------
71871d7fec4Smrg * gfx_get_vbi_base
71971d7fec4Smrg *-----------------------------------------------------------------------------
72071d7fec4Smrg */
72171d7fec4Smrg#if GFX_VIP_DYNAMIC
72271d7fec4Smrgunsigned long
72371d7fec4Smrgsc1200_get_vbi_base(int odd)
72471d7fec4Smrg#else
72571d7fec4Smrgunsigned long
72671d7fec4Smrggfx_get_vbi_base(int odd)
72771d7fec4Smrg#endif
72871d7fec4Smrg{
72971d7fec4Smrg   /* MASK BIT 23 AND ABOVE TO MAKE IT A TRUE OFFSET */
73071d7fec4Smrg
73171d7fec4Smrg   if (odd)
73271d7fec4Smrg      return (READ_VIP32(SC1200_VBI_ODD_BASE));
73371d7fec4Smrg   return (READ_VIP32(SC1200_VBI_EVEN_BASE));
73471d7fec4Smrg}
73571d7fec4Smrg
73671d7fec4Smrg/*-----------------------------------------------------------------------------
73771d7fec4Smrg * gfx_get_vbi_direct
73871d7fec4Smrg *-----------------------------------------------------------------------------
73971d7fec4Smrg */
74071d7fec4Smrg#if GFX_VIP_DYNAMIC
74171d7fec4Smrgunsigned long
74271d7fec4Smrgsc1200_get_vbi_direct(int odd)
74371d7fec4Smrg#else
74471d7fec4Smrgunsigned long
74571d7fec4Smrggfx_get_vbi_direct(int odd)
74671d7fec4Smrg#endif
74771d7fec4Smrg{
74871d7fec4Smrg   /* MASK BIT 23 AND ABOVE TO MAKE IT A TRUE OFFSET */
74971d7fec4Smrg
75071d7fec4Smrg   if (odd)
75171d7fec4Smrg      return (READ_VIP32(SC1200_ODD_DIRECT_VBI_LINE_ENABLE) &
75271d7fec4Smrg	      SC1200_DIRECT_VBI_LINE_ENABLE_MASK);
75371d7fec4Smrg   return (READ_VIP32(SC1200_EVEN_DIRECT_VBI_LINE_ENABLE) &
75471d7fec4Smrg	   SC1200_DIRECT_VBI_LINE_ENABLE_MASK);
75571d7fec4Smrg}
75671d7fec4Smrg
75771d7fec4Smrg/*-----------------------------------------------------------------------------
75871d7fec4Smrg * gfx_get_vbi_interrupt
75971d7fec4Smrg *-----------------------------------------------------------------------------
76071d7fec4Smrg */
76171d7fec4Smrg#if GFX_VIP_DYNAMIC
76271d7fec4Smrgint
76371d7fec4Smrgsc1200_get_vbi_interrupt(void)
76471d7fec4Smrg#else
76571d7fec4Smrgint
76671d7fec4Smrggfx_get_vbi_interrupt(void)
76771d7fec4Smrg#endif
76871d7fec4Smrg{
76971d7fec4Smrg   if (READ_VIP32(SC1200_VIP_CONTROL) & SC1200_VIP_VBI_FIELD_INTERRUPT_EN)
77071d7fec4Smrg      return (1);
77171d7fec4Smrg   return (0);
77271d7fec4Smrg}
77371d7fec4Smrg
77471d7fec4Smrg/*-----------------------------------------------------------------------------
77571d7fec4Smrg * gfx_get_vip_bus_request_threshold_high
77671d7fec4Smrg *-----------------------------------------------------------------------------
77771d7fec4Smrg */
77871d7fec4Smrg#if GFX_VIP_DYNAMIC
77971d7fec4Smrgint
78071d7fec4Smrgsc1200_get_vip_bus_request_threshold_high(void)
78171d7fec4Smrg#else
78271d7fec4Smrgint
78371d7fec4Smrggfx_get_vip_bus_request_threshold_high(void)
78471d7fec4Smrg#endif
78571d7fec4Smrg{
78671d7fec4Smrg   if (READ_VIP32(SC1200_VIP_CONFIG) & SC1200_VIP_BUS_REQUEST_THRESHOLD)
78771d7fec4Smrg      return (1);
78871d7fec4Smrg   return (0);
78971d7fec4Smrg}
79071d7fec4Smrg
79171d7fec4Smrg#endif /* GFX_READ_ROUTINES */
79271d7fec4Smrg
79371d7fec4Smrg/* END OF FILE */
794