171d7fec4Smrg/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nsc/gfx/vip_1400.c,v 1.1 2002/12/10 15:12:28 alanh Exp $ */ 271d7fec4Smrg/*----------------------------------------------------------------------------- 371d7fec4Smrg * VIP_1400.C 471d7fec4Smrg * 571d7fec4Smrg * Version 2.0 - February 21, 2000. 671d7fec4Smrg * 771d7fec4Smrg * This file routines to control the SC1400 video input port (VIP) hardware. 871d7fec4Smrg * 971d7fec4Smrg * History: 1071d7fec4Smrg * Versions 0.1 through 2.0 by Brian Falardeau. 1171d7fec4Smrg * 1271d7fec4Smrg * Copyright (c) 1999-2000 National Semiconductor. 1371d7fec4Smrg *----------------------------------------------------------------------------- 1471d7fec4Smrg */ 1571d7fec4Smrg 1671d7fec4Smrg/*----------------------------------------------------------------------------- 1771d7fec4Smrg * gfx_set_vip_enable 1871d7fec4Smrg * 1971d7fec4Smrg * This routine enables or disables the writes to memory from the video port. 2071d7fec4Smrg *----------------------------------------------------------------------------- 2171d7fec4Smrg */ 2271d7fec4Smrg#if GFX_VIDEO_DYNAMIC 2371d7fec4Smrgint 2471d7fec4Smrgsc1400_set_vip_enable(int enable) 2571d7fec4Smrg#else 2671d7fec4Smrgint 2771d7fec4Smrggfx_set_vip_enable(int enable) 2871d7fec4Smrg#endif 2971d7fec4Smrg{ 3071d7fec4Smrg unsigned long mcr, value; 3171d7fec4Smrg 3271d7fec4Smrg value = READ_VIP32(SC1400_VIP_CONTROL); 3371d7fec4Smrg 3471d7fec4Smrg if (enable) { 3571d7fec4Smrg /* CONFIGURE MCR FOR VIDEO INPUT MODE */ 3671d7fec4Smrg 3771d7fec4Smrg mcr = IND(SC1400_CB_BASE_ADDR + SC1400_CB_MISC_CONFIG); 3871d7fec4Smrg mcr |= (SC1400_MCR_VPOUT_CK_SELECT | SC1400_MCR_VPOUT_CK_SOURCE); 3971d7fec4Smrg mcr &= ~SC1400_MCR_VPOUT_MODE; 4071d7fec4Smrg mcr |= SC1400_MCR_VPIN_CCIR656; 4171d7fec4Smrg mcr &= ~SC1400_MCR_GENLOCK_CONTINUE; 4271d7fec4Smrg OUTD(SC1400_CB_BASE_ADDR + SC1400_CB_MISC_CONFIG, mcr); 4371d7fec4Smrg 4471d7fec4Smrg /* ENABLE CAPTURE */ 4571d7fec4Smrg /* Hardcode config values for now. */ 4671d7fec4Smrg 4771d7fec4Smrg WRITE_VIP32(SC1400_VIP_CONFIG, 0x30012); 4871d7fec4Smrg value |= 0x103; 4971d7fec4Smrg } else { 5071d7fec4Smrg value &= ~(0x102); 5171d7fec4Smrg } 5271d7fec4Smrg 5371d7fec4Smrg WRITE_VIP32(SC1400_VIP_CONTROL, value); 5471d7fec4Smrg return (0); 5571d7fec4Smrg} 5671d7fec4Smrg 5771d7fec4Smrg/*----------------------------------------------------------------------------- 5871d7fec4Smrg * gfx_set_vip_base 5971d7fec4Smrg * 6071d7fec4Smrg * This routine sets the odd and even base address values for the VIP memory 6171d7fec4Smrg * buffer. 6271d7fec4Smrg *----------------------------------------------------------------------------- 6371d7fec4Smrg */ 6471d7fec4Smrg#if GFX_VIDEO_DYNAMIC 6571d7fec4Smrgint 6671d7fec4Smrgsc1400_set_vip_base(unsigned long even, unsigned long odd) 6771d7fec4Smrg#else 6871d7fec4Smrgint 6971d7fec4Smrggfx_set_vip_base(unsigned long even, unsigned long odd) 7071d7fec4Smrg#endif 7171d7fec4Smrg{ 7271d7fec4Smrg // TRUE OFFSET IS SPECIFIED, NEED TO SET BIT 23 FOR HARDWARE 7371d7fec4Smrg 7471d7fec4Smrg WRITE_VIP32(SC1400_VIP_EVEN_BASE, even | 0x00800000); 7571d7fec4Smrg WRITE_VIP32(SC1400_VIP_ODD_BASE, odd | 0x00800000); 7671d7fec4Smrg return (0); 7771d7fec4Smrg} 7871d7fec4Smrg 7971d7fec4Smrg/*----------------------------------------------------------------------------- 8071d7fec4Smrg * gfx_set_vip_pitch 8171d7fec4Smrg * 8271d7fec4Smrg * This routine sets the number of bytes between scanlines for the VIP data. 8371d7fec4Smrg *----------------------------------------------------------------------------- 8471d7fec4Smrg */ 8571d7fec4Smrg#if GFX_VIDEO_DYNAMIC 8671d7fec4Smrgint 8771d7fec4Smrgsc1400_set_vip_pitch(unsigned long pitch) 8871d7fec4Smrg#else 8971d7fec4Smrgint 9071d7fec4Smrggfx_set_vip_pitch(unsigned long pitch) 9171d7fec4Smrg#endif 9271d7fec4Smrg{ 9371d7fec4Smrg WRITE_VIP32(SC1400_VIP_PITCH, pitch & 0x0000FFFC); 9471d7fec4Smrg return (0); 9571d7fec4Smrg} 9671d7fec4Smrg 9771d7fec4Smrg/*----------------------------------------------------------------------------- 9871d7fec4Smrg * gfx_set_vbi_enable 9971d7fec4Smrg * 10071d7fec4Smrg * This routine enables or disables the VBI data capture. 10171d7fec4Smrg *----------------------------------------------------------------------------- 10271d7fec4Smrg */ 10371d7fec4Smrg#if GFX_VIDEO_DYNAMIC 10471d7fec4Smrgint 10571d7fec4Smrgsc1400_set_vbi_enable(int enable) 10671d7fec4Smrg#else 10771d7fec4Smrgint 10871d7fec4Smrggfx_set_vbi_enable(int enable) 10971d7fec4Smrg#endif 11071d7fec4Smrg{ 11171d7fec4Smrg unsigned long value; 11271d7fec4Smrg 11371d7fec4Smrg value = READ_VIP32(SC1400_VIP_CONTROL); 11471d7fec4Smrg if (enable) 11571d7fec4Smrg value |= SC1400_VIP_VBI_CAPTURE_EN; 11671d7fec4Smrg else 11771d7fec4Smrg value &= ~SC1400_VIP_VBI_CAPTURE_EN; 11871d7fec4Smrg WRITE_VIP32(SC1400_VIP_CONTROL, value); 11971d7fec4Smrg return (0); 12071d7fec4Smrg} 12171d7fec4Smrg 12271d7fec4Smrg/*----------------------------------------------------------------------------- 12371d7fec4Smrg * gfx_set_vbi_base 12471d7fec4Smrg * 12571d7fec4Smrg * This routine sets the odd and even base address values for VBI capture. 12671d7fec4Smrg *----------------------------------------------------------------------------- 12771d7fec4Smrg */ 12871d7fec4Smrg#if GFX_VIDEO_DYNAMIC 12971d7fec4Smrgint 13071d7fec4Smrgsc1400_set_vbi_base(unsigned long even, unsigned long odd) 13171d7fec4Smrg#else 13271d7fec4Smrgint 13371d7fec4Smrggfx_set_vbi_base(unsigned long even, unsigned long odd) 13471d7fec4Smrg#endif 13571d7fec4Smrg{ 13671d7fec4Smrg // TRUE OFFSET IS SPECIFIED, NEED TO SET BIT 23 FOR HARDWARE 13771d7fec4Smrg 13871d7fec4Smrg WRITE_VIP32(SC1400_VBI_EVEN_BASE, even | 0x00800000); 13971d7fec4Smrg WRITE_VIP32(SC1400_VBI_ODD_BASE, odd | 0x00800000); 14071d7fec4Smrg return (0); 14171d7fec4Smrg} 14271d7fec4Smrg 14371d7fec4Smrg/*----------------------------------------------------------------------------- 14471d7fec4Smrg * gfx_set_vbi_pitch 14571d7fec4Smrg * 14671d7fec4Smrg * This routine sets the number of bytes between scanlines for VBI capture. 14771d7fec4Smrg *----------------------------------------------------------------------------- 14871d7fec4Smrg */ 14971d7fec4Smrg#if GFX_VIDEO_DYNAMIC 15071d7fec4Smrgint 15171d7fec4Smrgsc1400_set_vbi_pitch(unsigned long pitch) 15271d7fec4Smrg#else 15371d7fec4Smrgint 15471d7fec4Smrggfx_set_vbi_pitch(unsigned long pitch) 15571d7fec4Smrg#endif 15671d7fec4Smrg{ 15771d7fec4Smrg WRITE_VIP32(SC1400_VBI_PITCH, pitch & 0x0000FFFC); 15871d7fec4Smrg return (0); 15971d7fec4Smrg} 16071d7fec4Smrg 16171d7fec4Smrg/*************************************************************/ 16271d7fec4Smrg/* READ ROUTINES | INCLUDED FOR DIAGNOSTIC PURPOSES ONLY */ 16371d7fec4Smrg/*************************************************************/ 16471d7fec4Smrg 16571d7fec4Smrg#if GFX_READ_ROUTINES 16671d7fec4Smrg 16771d7fec4Smrg/*----------------------------------------------------------------------------- 16871d7fec4Smrg * gfx_get_vip_enable 16971d7fec4Smrg *----------------------------------------------------------------------------- 17071d7fec4Smrg */ 17171d7fec4Smrg#if GFX_VIDEO_DYNAMIC 17271d7fec4Smrgint 17371d7fec4Smrgsc1400_get_vip_enable(void) 17471d7fec4Smrg#else 17571d7fec4Smrgint 17671d7fec4Smrggfx_get_vip_enable(void) 17771d7fec4Smrg#endif 17871d7fec4Smrg{ 17971d7fec4Smrg if (READ_VIP32(SC1400_VIP_CONTROL) & 0x00000100) 18071d7fec4Smrg return (1); 18171d7fec4Smrg return (0); 18271d7fec4Smrg} 18371d7fec4Smrg 18471d7fec4Smrg/*----------------------------------------------------------------------------- 18571d7fec4Smrg * gfx_get_vip_base 18671d7fec4Smrg *----------------------------------------------------------------------------- 18771d7fec4Smrg */ 18871d7fec4Smrg#if GFX_VIDEO_DYNAMIC 18971d7fec4Smrgunsigned long 19071d7fec4Smrgsc1400_get_vip_base(int odd) 19171d7fec4Smrg#else 19271d7fec4Smrgunsigned long 19371d7fec4Smrggfx_get_vip_base(int odd) 19471d7fec4Smrg#endif 19571d7fec4Smrg{ 19671d7fec4Smrg // MASK BIT 23 AND ABOVE TO MAKE IT A TRUE OFFSET 19771d7fec4Smrg 19871d7fec4Smrg if (odd) 19971d7fec4Smrg return (READ_VIP32(SC1400_VIP_ODD_BASE) & 0x007FFFFF); 20071d7fec4Smrg return (READ_VIP32(SC1400_VIP_EVEN_BASE) & 0x007FFFFF); 20171d7fec4Smrg} 20271d7fec4Smrg 20371d7fec4Smrg/*----------------------------------------------------------------------------- 20471d7fec4Smrg * gfx_get_vip_pitch 20571d7fec4Smrg *----------------------------------------------------------------------------- 20671d7fec4Smrg */ 20771d7fec4Smrg#if GFX_VIDEO_DYNAMIC 20871d7fec4Smrgunsigned long 20971d7fec4Smrgsc1400_get_vip_pitch(void) 21071d7fec4Smrg#else 21171d7fec4Smrgunsigned long 21271d7fec4Smrggfx_get_vip_pitch(void) 21371d7fec4Smrg#endif 21471d7fec4Smrg{ 21571d7fec4Smrg return (READ_VIP32(SC1400_VIP_PITCH) & 0x0000FFFF); 21671d7fec4Smrg} 21771d7fec4Smrg 21871d7fec4Smrg/*----------------------------------------------------------------------------- 21971d7fec4Smrg * gfx_get_vbi_enable 22071d7fec4Smrg *----------------------------------------------------------------------------- 22171d7fec4Smrg */ 22271d7fec4Smrg#if GFX_VIDEO_DYNAMIC 22371d7fec4Smrgint 22471d7fec4Smrgsc1400_get_vbi_enable(void) 22571d7fec4Smrg#else 22671d7fec4Smrgint 22771d7fec4Smrggfx_get_vbi_enable(void) 22871d7fec4Smrg#endif 22971d7fec4Smrg{ 23071d7fec4Smrg if (READ_VIP32(SC1400_VIP_CONTROL) & 0x00000200) 23171d7fec4Smrg return (1); 23271d7fec4Smrg return (0); 23371d7fec4Smrg} 23471d7fec4Smrg 23571d7fec4Smrg/*----------------------------------------------------------------------------- 23671d7fec4Smrg * gfx_get_vbi_base 23771d7fec4Smrg *----------------------------------------------------------------------------- 23871d7fec4Smrg */ 23971d7fec4Smrg#if GFX_VIDEO_DYNAMIC 24071d7fec4Smrgunsigned long 24171d7fec4Smrgsc1400_get_vbi_base(int odd) 24271d7fec4Smrg#else 24371d7fec4Smrgunsigned long 24471d7fec4Smrggfx_get_vbi_base(int odd) 24571d7fec4Smrg#endif 24671d7fec4Smrg{ 24771d7fec4Smrg // MASK BIT 23 AND ABOVE TO MAKE IT A TRUE OFFSET 24871d7fec4Smrg 24971d7fec4Smrg if (odd) 25071d7fec4Smrg return (READ_VIP32(SC1400_VBI_ODD_BASE) & 0x007FFFFF); 25171d7fec4Smrg return (READ_VIP32(SC1400_VBI_EVEN_BASE) & 0x007FFFFF); 25271d7fec4Smrg} 25371d7fec4Smrg 25471d7fec4Smrg/*----------------------------------------------------------------------------- 25571d7fec4Smrg * gfx_get_vbi_pitch 25671d7fec4Smrg *----------------------------------------------------------------------------- 25771d7fec4Smrg */ 25871d7fec4Smrg#if GFX_VIDEO_DYNAMIC 25971d7fec4Smrgunsigned long 26071d7fec4Smrgsc1400_get_vbi_pitch(void) 26171d7fec4Smrg#else 26271d7fec4Smrgunsigned long 26371d7fec4Smrggfx_get_vbi_pitch(void) 26471d7fec4Smrg#endif 26571d7fec4Smrg{ 26671d7fec4Smrg return (READ_VIP32(SC1400_VBI_PITCH) & 0x0000FFFF); 26771d7fec4Smrg} 26871d7fec4Smrg 26971d7fec4Smrg#endif /* GFX_READ_ROUTINES */ 27071d7fec4Smrg 27171d7fec4Smrg/* END OF FILE */ 272