1/*
2 * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sub license,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24#ifndef _VIA_DRM_H_
25#define _VIA_DRM_H_
26
27#include "drm.h"
28
29/* WARNING: These defines must be the same as what the Xserver uses.
30 * if you change them, you must change the defines in the Xserver.
31 */
32
33#ifndef _VIA_DEFINES_
34#define _VIA_DEFINES_
35
36#define VIA_NR_SAREA_CLIPRECTS		8
37#define VIA_NR_XVMC_PORTS		10
38#define VIA_NR_XVMC_LOCKS		5
39#define VIA_MAX_CACHELINE_SIZE		64
40#define XVMCLOCKPTR(saPriv,lockNo)					\
41	((volatile struct drm_hw_lock *)(((((unsigned long) (saPriv)->XvMCLockArea) + \
42				      (VIA_MAX_CACHELINE_SIZE - 1)) &	\
43				     ~(VIA_MAX_CACHELINE_SIZE - 1)) +	\
44				    VIA_MAX_CACHELINE_SIZE*(lockNo)))
45
46/* Each region is a minimum of 64k, and there are at most 64 of them.
47 */
48#define VIA_NR_TEX_REGIONS 64
49#define VIA_LOG_MIN_TEX_REGION_SIZE 16
50#endif
51
52#define VIA_UPLOAD_TEX0IMAGE  0x1	/* handled clientside */
53#define VIA_UPLOAD_TEX1IMAGE  0x2	/* handled clientside */
54#define VIA_UPLOAD_CTX        0x4
55#define VIA_UPLOAD_BUFFERS    0x8
56#define VIA_UPLOAD_TEX0       0x10
57#define VIA_UPLOAD_TEX1       0x20
58#define VIA_UPLOAD_CLIPRECTS  0x40
59#define VIA_UPLOAD_ALL        0xff
60
61/* VIA specific ioctls */
62#define DRM_VIA_ALLOCMEM	0x00
63#define DRM_VIA_FREEMEM		0x01
64#define DRM_VIA_AGP_INIT	0x02
65#define DRM_VIA_FB_INIT		0x03
66#define DRM_VIA_MAP_INIT	0x04
67#define DRM_VIA_DEC_FUTEX	0x05
68#define DRM_VIA_OLD_GEM_CREATE	0x06
69#define DRM_VIA_DMA_INIT	0x07
70#define DRM_VIA_CMDBUFFER	0x08
71#define DRM_VIA_FLUSH		0x09
72#define DRM_VIA_PCICMD		0x0a
73#define DRM_VIA_CMDBUF_SIZE	0x0b
74#define NOT_USED
75#define DRM_VIA_WAIT_IRQ	0x0d
76#define DRM_VIA_DMA_BLIT	0x0e
77#define DRM_VIA_BLIT_SYNC	0x0f
78
79/* KMS ioctls */
80#define DRM_VIA_GETPARAM	0x10
81#define DRM_VIA_SETPARAM	0x11
82#define DRM_VIA_GEM_CREATE	0x12
83#define DRM_VIA_GEM_WAIT	0x13
84#define DRM_VIA_GEM_STATE	0x14
85
86#define DRM_IOCTL_VIA_ALLOCMEM	  DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t)
87#define DRM_IOCTL_VIA_FREEMEM	  DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t)
88#define DRM_IOCTL_VIA_AGP_INIT	  DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t)
89#define DRM_IOCTL_VIA_FB_INIT	  DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t)
90#define DRM_IOCTL_VIA_MAP_INIT	  DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t)
91#define DRM_IOCTL_VIA_DEC_FUTEX   DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t)
92#define DRM_IOCTL_VIA_OLD_GEM_CREATE  DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_OLD_GEM_CREATE, struct drm_via_gem_object)
93#define DRM_IOCTL_VIA_DMA_INIT	  DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t)
94#define DRM_IOCTL_VIA_CMDBUFFER	  DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t)
95#define DRM_IOCTL_VIA_FLUSH	  DRM_IO(  DRM_COMMAND_BASE + DRM_VIA_FLUSH)
96#define DRM_IOCTL_VIA_PCICMD	  DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t)
97#define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, \
98					    drm_via_cmdbuf_size_t)
99#define DRM_IOCTL_VIA_WAIT_IRQ    DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t)
100#define DRM_IOCTL_VIA_DMA_BLIT    DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DMA_BLIT, drm_via_dmablit_t)
101#define DRM_IOCTL_VIA_BLIT_SYNC   DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_BLIT_SYNC, drm_via_blitsync_t)
102
103/* KMS ioctls */
104#define DRM_IOCTL_VIA_GETPARAM    DRM_IOR(DRM_COMMAND_BASE + DRM_VIA_GETPARAM, struct drm_via_param)
105#define DRM_IOCTL_VIA_SETPARAM    DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_SETPARAM, struct drm_via_param)
106#define DRM_IOCTL_VIA_GEM_CREATE  DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_GEM_CREATE, struct drm_via_gem_object)
107#define DRM_IOCTL_VIA_GEM_WAIT    DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_GEM_WAIT, struct drm_via_gem_wait)
108#define DRM_IOCTL_VIA_GEM_STATE   DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_GEM_STATE, struct drm_via_gem_object)
109
110/* Indices into buf.Setup where various bits of state are mirrored per
111 * context and per buffer.  These can be fired at the card as a unit,
112 * or in a piecewise fashion as required.
113 */
114
115#define VIA_TEX_SETUP_SIZE 8
116
117/* Flags for clear ioctl
118 */
119#define VIA_FRONT   0x1
120#define VIA_BACK    0x2
121#define VIA_DEPTH   0x4
122#define VIA_STENCIL 0x8
123
124#define VIA_MEM_VIDEO   0	/* matches drm constant */
125#define VIA_MEM_AGP     1	/* matches drm constant */
126#define VIA_MEM_SYSTEM  2
127#define VIA_MEM_MIXED   3
128#define VIA_MEM_UNKNOWN 4
129
130typedef struct {
131	__u32 offset;
132	__u32 size;
133} drm_via_agp_t;
134
135typedef struct {
136	__u32 offset;
137	__u32 size;
138} drm_via_fb_t;
139
140typedef struct {
141	__u32 context;
142	__u32 type;
143	__u32 size;
144	unsigned long index;
145	unsigned long offset;
146} drm_via_mem_t;
147
148typedef struct _drm_via_init {
149	enum {
150		VIA_INIT_MAP = 0x01,
151		VIA_CLEANUP_MAP = 0x02
152	} func;
153
154	unsigned long sarea_priv_offset;
155	unsigned long fb_offset;
156	unsigned long mmio_offset;
157	unsigned long agpAddr;
158} drm_via_init_t;
159
160typedef struct _drm_via_futex {
161	enum {
162		VIA_FUTEX_WAIT = 0x00,
163		VIA_FUTEX_WAKE = 0X01
164	} func;
165	__u32 ms;
166	__u32 lock;
167	__u32 val;
168} drm_via_futex_t;
169
170typedef struct _drm_via_dma_init {
171	enum {
172		VIA_INIT_DMA = 0x01,
173		VIA_CLEANUP_DMA = 0x02,
174		VIA_DMA_INITIALIZED = 0x03
175	} func;
176
177	unsigned long offset;
178	unsigned long size;
179	unsigned long reg_pause_addr;
180} drm_via_dma_init_t;
181
182typedef struct _drm_via_cmdbuffer {
183	char __user *buf;
184	unsigned long size;
185} drm_via_cmdbuffer_t;
186
187/* Warning: If you change the SAREA structure you must change the Xserver
188 * structure as well */
189
190typedef struct _drm_via_tex_region {
191	unsigned char next, prev;	/* indices to form a circular LRU  */
192	unsigned char inUse;	/* owned by a client, or free? */
193	int age;		/* tracked by clients to update local LRU's */
194} drm_via_tex_region_t;
195
196typedef struct _drm_via_sarea {
197	unsigned int dirty;
198	unsigned int nbox;
199	struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS];
200	drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1];
201	int texAge;		/* last time texture was uploaded */
202	int ctxOwner;		/* last context to upload state */
203	int vertexPrim;
204
205	/*
206	 * Below is for XvMC.
207	 * We want the lock integers alone on, and aligned to, a cache line.
208	 * Therefore this somewhat strange construct.
209	 */
210
211	char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)];
212
213	unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS];
214	unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS];
215	unsigned int XvMCCtxNoGrabbed;	/* Last context to hold decoder */
216
217	/* Used by the 3d driver only at this point, for pageflipping:
218	 */
219	unsigned int pfCurrentOffset;
220} drm_via_sarea_t;
221
222typedef struct _drm_via_cmdbuf_size {
223	enum {
224		VIA_CMDBUF_SPACE = 0x01,
225		VIA_CMDBUF_LAG = 0x02
226	} func;
227	int wait;
228	__u32 size;
229} drm_via_cmdbuf_size_t;
230
231typedef enum {
232	VIA_IRQ_ABSOLUTE = 0x0,
233	VIA_IRQ_RELATIVE = 0x1,
234	VIA_IRQ_SIGNAL = 0x10000000,
235	VIA_IRQ_FORCE_SEQUENCE = 0x20000000
236} via_irq_seq_type_t;
237
238#define VIA_IRQ_FLAGS_MASK 0xF0000000
239
240enum drm_via_irqs {
241	drm_via_irq_hqv0 = 0,
242	drm_via_irq_hqv1,
243	drm_via_irq_dma0_dd,
244	drm_via_irq_dma0_td,
245	drm_via_irq_dma1_dd,
246	drm_via_irq_dma1_td,
247	drm_via_irq_num
248};
249
250struct drm_via_wait_irq_request {
251	unsigned irq;
252	via_irq_seq_type_t type;
253	__u32 sequence;
254	__u32 signal;
255};
256
257typedef union drm_via_irqwait {
258	struct drm_via_wait_irq_request request;
259	struct drm_wait_vblank_reply reply;
260} drm_via_irqwait_t;
261
262typedef struct drm_via_blitsync {
263	__u32 sync_handle;
264	unsigned engine;
265} drm_via_blitsync_t;
266
267/* - * Below,"flags" is currently unused but will be used for possible future
268 * extensions like kernel space bounce buffers for bad alignments and
269 * blit engine busy-wait polling for better latency in the absence of
270 * interrupts.
271 */
272
273typedef struct drm_via_dmablit {
274	__u32 num_lines;
275	__u32 line_length;
276
277	__u32 fb_addr;
278	__u32 fb_stride;
279
280	unsigned char *mem_addr;
281	__u32 mem_stride;
282
283	__u32 flags;
284	int to_fb;
285
286	drm_via_blitsync_t sync;
287} drm_via_dmablit_t;
288
289/* Ioctl to query kernel params:
290 */
291#define VIA_PARAM_CHIPSET_ID		0
292#define VIA_PARAM_REVISION_ID		1
293
294struct drm_via_param {
295	uint64_t param;
296	uint64_t value;
297};
298
299struct drm_via_gem_object {
300	/**
301	 * Requested size for the object.
302	 *
303	 * The (page-aligned) allocated size for the object will be returned.
304	 */
305	uint64_t size;
306
307	/*
308	 * Place the memory at the proper byte alignment.
309	 */
310	uint32_t alignment;
311
312	/**
313	 * Format of data i.e tile pitch, for linear it is zero
314	 */
315	uint32_t pitch;
316
317	/**
318	 * Give hints where to allocate this object.
319	 */
320	uint32_t domains;
321
322	/**
323	 * chmod values applied to a buffer.
324	 */
325	uint32_t mode_t;
326
327	/**
328	 * Offset to start of memory region.
329	 */
330	uint64_t offset;
331
332	/**
333	 * Returned handle need to mmap the buffer.
334	 */
335	uint64_t map_handle;
336
337	/**
338	 * Returned handle for the object.
339	 *
340	 * Object handles are nonzero.
341	 */
342	uint32_t handle;
343
344	/**
345	 * Version to tell how to handle this data.
346	 */
347	uint32_t version;
348};
349
350struct drm_via_gem_wait {
351	/* the buffer object handle */
352	uint32_t handle;
353	uint32_t no_wait;
354};
355
356#endif				/* _VIA_DRM_H_ */
357