r128.h revision e1efbb8a
1c582b7e3Smrg/* 2c582b7e3Smrg * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario, 3c582b7e3Smrg * Precision Insight, Inc., Cedar Park, Texas, and 4c582b7e3Smrg * VA Linux Systems Inc., Fremont, California. 5c582b7e3Smrg * 6c582b7e3Smrg * All Rights Reserved. 7c582b7e3Smrg * 8c582b7e3Smrg * Permission is hereby granted, free of charge, to any person obtaining 9c582b7e3Smrg * a copy of this software and associated documentation files (the 10c582b7e3Smrg * "Software"), to deal in the Software without restriction, including 11c582b7e3Smrg * without limitation on the rights to use, copy, modify, merge, 12c582b7e3Smrg * publish, distribute, sublicense, and/or sell copies of the Software, 13c582b7e3Smrg * and to permit persons to whom the Software is furnished to do so, 14c582b7e3Smrg * subject to the following conditions: 15c582b7e3Smrg * 16c582b7e3Smrg * The above copyright notice and this permission notice (including the 17c582b7e3Smrg * next paragraph) shall be included in all copies or substantial 18c582b7e3Smrg * portions of the Software. 19c582b7e3Smrg * 20c582b7e3Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21c582b7e3Smrg * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22c582b7e3Smrg * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 23c582b7e3Smrg * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, PRECISION INSIGHT, VA LINUX 24c582b7e3Smrg * SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 25c582b7e3Smrg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 26c582b7e3Smrg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 27c582b7e3Smrg * OTHER DEALINGS IN THE SOFTWARE. 28c582b7e3Smrg */ 29c582b7e3Smrg 30c582b7e3Smrg/* 31c582b7e3Smrg * Authors: 32c582b7e3Smrg * Rickard E. Faith <faith@valinux.com> 33c582b7e3Smrg * Kevin E. Martin <martin@valinux.com> 34c582b7e3Smrg * 35c582b7e3Smrg */ 36c582b7e3Smrg 37c582b7e3Smrg#ifndef _R128_H_ 38c582b7e3Smrg#define _R128_H_ 39c582b7e3Smrg 40c582b7e3Smrg#include <unistd.h> 41c582b7e3Smrg#include "xf86str.h" 42c582b7e3Smrg 43c582b7e3Smrg /* PCI support */ 44c582b7e3Smrg#include "xf86Pci.h" 45c582b7e3Smrg 4684354367Smrg /* EXA support */ 4784354367Smrg#ifdef USE_EXA 4884354367Smrg#include "exa.h" 4984354367Smrg#endif 5084354367Smrg 51c582b7e3Smrg /* XAA and Cursor Support */ 5284354367Smrg#ifdef HAVE_XAA_H 53c582b7e3Smrg#include "xaa.h" 5484354367Smrg#endif 5584354367Smrg#include "xf86fbman.h" 56c582b7e3Smrg#include "xf86Cursor.h" 57c582b7e3Smrg 58c582b7e3Smrg /* DDC support */ 59c582b7e3Smrg#include "xf86DDC.h" 60c582b7e3Smrg 61c582b7e3Smrg /* Xv support */ 62c582b7e3Smrg#include "xf86xv.h" 63c582b7e3Smrg 64c582b7e3Smrg /* DRI support */ 6584354367Smrg#ifndef XF86DRI 6684354367Smrg#undef R128DRI 6784354367Smrg#endif 6884354367Smrg 6984354367Smrg#if R128DRI 70c582b7e3Smrg#define _XF86DRI_SERVER_ 71c582b7e3Smrg#include "r128_dripriv.h" 72c582b7e3Smrg#include "dri.h" 73c582b7e3Smrg#include "GL/glxint.h" 74c582b7e3Smrg#endif 75c582b7e3Smrg 7684354367Smrg#include "fb.h" 77b3ff493bSmrg#include "xf86Crtc.h" 7884354367Smrg 7984354367Smrg#include "compat-api.h" 80c582b7e3Smrg#include "atipcirename.h" 81c582b7e3Smrg 8284354367Smrg#include "r128_probe.h" 8384354367Smrg 8484354367Smrg#if HAVE_BYTESWAP_H 8584354367Smrg#include <byteswap.h> 8684354367Smrg#elif defined(USE_SYS_ENDIAN_H) 8784354367Smrg#include <sys/endian.h> 8884354367Smrg#else 8984354367Smrg#define bswap_16(value) \ 9084354367Smrg ((((value) & 0xff) << 8) | ((value) >> 8)) 9184354367Smrg 9284354367Smrg#define bswap_32(value) \ 9384354367Smrg (((uint32_t)bswap_16((uint16_t)((value) & 0xffff)) << 16) | \ 9484354367Smrg (uint32_t)bswap_16((uint16_t)((value) >> 16))) 9584354367Smrg 9684354367Smrg#define bswap_64(value) \ 9784354367Smrg (((uint64_t)bswap_32((uint32_t)((value) & 0xffffffff)) \ 9884354367Smrg << 32) | \ 9984354367Smrg (uint64_t)bswap_32((uint32_t)((value) >> 32))) 10084354367Smrg#endif 10184354367Smrg 10284354367Smrg#if X_BYTE_ORDER == X_BIG_ENDIAN 10384354367Smrg#define le32_to_cpu(x) bswap_32(x) 10484354367Smrg#define le16_to_cpu(x) bswap_16(x) 10584354367Smrg#define cpu_to_le32(x) bswap_32(x) 10684354367Smrg#define cpu_to_le16(x) bswap_16(x) 10784354367Smrg#else 10884354367Smrg#define le32_to_cpu(x) (x) 10984354367Smrg#define le16_to_cpu(x) (x) 11084354367Smrg#define cpu_to_le32(x) (x) 11184354367Smrg#define cpu_to_le16(x) (x) 11284354367Smrg#endif 11384354367Smrg 114c582b7e3Smrg#define R128_DEBUG 0 /* Turn off debugging output */ 115c582b7e3Smrg#define R128_IDLE_RETRY 32 /* Fall out of idle loops after this count */ 116c582b7e3Smrg#define R128_TIMEOUT 2000000 /* Fall out of wait loops after this count */ 117c582b7e3Smrg#define R128_MMIOSIZE 0x4000 118c582b7e3Smrg 119c582b7e3Smrg#define R128_VBIOS_SIZE 0x00010000 1209e881af1Smacallan#define R128_NAME "R128" 121c582b7e3Smrg 122c582b7e3Smrg#if R128_DEBUG 12384354367Smrg#include "r128_version.h" 12484354367Smrg 125c582b7e3Smrg#define R128TRACE(x) \ 126c582b7e3Smrg do { \ 127c582b7e3Smrg ErrorF("(**) %s(%d): ", R128_NAME, pScrn->scrnIndex); \ 128c582b7e3Smrg ErrorF x; \ 129c582b7e3Smrg } while (0); 130c582b7e3Smrg#else 131c582b7e3Smrg#define R128TRACE(x) 132c582b7e3Smrg#endif 133c582b7e3Smrg 134c582b7e3Smrg 135c582b7e3Smrg/* Other macros */ 136c582b7e3Smrg#define R128_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) 137c582b7e3Smrg#define R128_ALIGN(x,bytes) (((x) + ((bytes) - 1)) & ~((bytes) - 1)) 138c582b7e3Smrg#define R128PTR(pScrn) ((R128InfoPtr)(pScrn)->driverPrivate) 139c582b7e3Smrg 140b3ff493bSmrg#define R128_BIOS8(v) ((info->VBIOS[(v)])) 141b3ff493bSmrg#define R128_BIOS16(v) ((info->VBIOS[(v)]) | \ 142b3ff493bSmrg (info->VBIOS[(v) + 1] << 8)) 143b3ff493bSmrg#define R128_BIOS32(v) ((info->VBIOS[(v)]) | \ 144b3ff493bSmrg (info->VBIOS[(v) + 1] << 8) | \ 145b3ff493bSmrg (info->VBIOS[(v) + 2] << 16) | \ 146b3ff493bSmrg (info->VBIOS[(v) + 3] << 24)) 147b3ff493bSmrg 148c582b7e3Smrgtypedef struct { /* All values in XCLKS */ 149c582b7e3Smrg int ML; /* Memory Read Latency */ 150c582b7e3Smrg int MB; /* Memory Burst Length */ 151c582b7e3Smrg int Trcd; /* RAS to CAS delay */ 152c582b7e3Smrg int Trp; /* RAS percentage */ 153c582b7e3Smrg int Twr; /* Write Recovery */ 154c582b7e3Smrg int CL; /* CAS Latency */ 155c582b7e3Smrg int Tr2w; /* Read to Write Delay */ 156c582b7e3Smrg int Rloop; /* Loop Latency */ 157c582b7e3Smrg int Rloop_fudge; /* Add to ML to get Rloop */ 158c582b7e3Smrg char *name; 159c582b7e3Smrg} R128RAMRec, *R128RAMPtr; 160c582b7e3Smrg 161c582b7e3Smrgtypedef struct { 162c582b7e3Smrg /* Common registers */ 163b3ff493bSmrg uint32_t ovr_clr; 164b3ff493bSmrg uint32_t ovr_wid_left_right; 165b3ff493bSmrg uint32_t ovr_wid_top_bottom; 166b3ff493bSmrg uint32_t ov0_scale_cntl; 167b3ff493bSmrg uint32_t mpp_tb_config; 168b3ff493bSmrg uint32_t mpp_gp_config; 169b3ff493bSmrg uint32_t subpic_cntl; 170b3ff493bSmrg uint32_t viph_control; 171b3ff493bSmrg uint32_t i2c_cntl_1; 172b3ff493bSmrg uint32_t gen_int_cntl; 173b3ff493bSmrg uint32_t cap0_trig_cntl; 174b3ff493bSmrg uint32_t cap1_trig_cntl; 175b3ff493bSmrg uint32_t bus_cntl; 176b3ff493bSmrg uint32_t config_cntl; 177c582b7e3Smrg 178c582b7e3Smrg /* Other registers to save for VT switches */ 179b3ff493bSmrg uint32_t dp_datatype; 180b3ff493bSmrg uint32_t gen_reset_cntl; 181b3ff493bSmrg uint32_t clock_cntl_index; 182b3ff493bSmrg uint32_t amcgpio_en_reg; 183b3ff493bSmrg uint32_t amcgpio_mask; 184c582b7e3Smrg 185c582b7e3Smrg /* CRTC registers */ 186b3ff493bSmrg uint32_t crtc_gen_cntl; 187b3ff493bSmrg uint32_t crtc_ext_cntl; 188b3ff493bSmrg uint32_t dac_cntl; 189b3ff493bSmrg uint32_t crtc_h_total_disp; 190b3ff493bSmrg uint32_t crtc_h_sync_strt_wid; 191b3ff493bSmrg uint32_t crtc_v_total_disp; 192b3ff493bSmrg uint32_t crtc_v_sync_strt_wid; 193b3ff493bSmrg uint32_t crtc_offset; 194b3ff493bSmrg uint32_t crtc_offset_cntl; 195b3ff493bSmrg uint32_t crtc_pitch; 196c582b7e3Smrg 197c582b7e3Smrg /* CRTC2 registers */ 198b3ff493bSmrg uint32_t crtc2_gen_cntl; 199b3ff493bSmrg uint32_t crtc2_h_total_disp; 200b3ff493bSmrg uint32_t crtc2_h_sync_strt_wid; 201b3ff493bSmrg uint32_t crtc2_v_total_disp; 202b3ff493bSmrg uint32_t crtc2_v_sync_strt_wid; 203b3ff493bSmrg uint32_t crtc2_offset; 204b3ff493bSmrg uint32_t crtc2_offset_cntl; 205b3ff493bSmrg uint32_t crtc2_pitch; 206c582b7e3Smrg 207c582b7e3Smrg /* Flat panel registers */ 208b3ff493bSmrg uint32_t fp_crtc_h_total_disp; 209b3ff493bSmrg uint32_t fp_crtc_v_total_disp; 210b3ff493bSmrg uint32_t fp_gen_cntl; 211b3ff493bSmrg uint32_t fp_h_sync_strt_wid; 212b3ff493bSmrg uint32_t fp_horz_stretch; 213b3ff493bSmrg uint32_t fp_panel_cntl; 214b3ff493bSmrg uint32_t fp_v_sync_strt_wid; 215b3ff493bSmrg uint32_t fp_vert_stretch; 216b3ff493bSmrg uint32_t lvds_gen_cntl; 217b3ff493bSmrg uint32_t tmds_crc; 218b3ff493bSmrg uint32_t tmds_transmitter_cntl; 219c582b7e3Smrg 220c582b7e3Smrg /* Computed values for PLL */ 221b3ff493bSmrg uint32_t dot_clock_freq; 222b3ff493bSmrg uint32_t pll_output_freq; 223c582b7e3Smrg int feedback_div; 224c582b7e3Smrg int post_div; 225c582b7e3Smrg 226c582b7e3Smrg /* PLL registers */ 227b3ff493bSmrg uint32_t ppll_ref_div; 228b3ff493bSmrg uint32_t ppll_div_3; 229b3ff493bSmrg uint32_t ppll_div_0; 230b3ff493bSmrg uint32_t htotal_cntl; 231c582b7e3Smrg 232c582b7e3Smrg /* Computed values for PLL2 */ 233b3ff493bSmrg uint32_t dot_clock_freq_2; 234b3ff493bSmrg uint32_t pll_output_freq_2; 235c582b7e3Smrg int feedback_div_2; 236c582b7e3Smrg int post_div_2; 237c582b7e3Smrg 238c582b7e3Smrg /* PLL2 registers */ 239b3ff493bSmrg uint32_t p2pll_ref_div; 240b3ff493bSmrg uint32_t p2pll_div_0; 241b3ff493bSmrg uint32_t htotal_cntl2; 242c582b7e3Smrg 243c582b7e3Smrg /* DDA register */ 244b3ff493bSmrg uint32_t dda_config; 245b3ff493bSmrg uint32_t dda_on_off; 246c582b7e3Smrg 247c582b7e3Smrg /* DDA2 register */ 248b3ff493bSmrg uint32_t dda2_config; 249b3ff493bSmrg uint32_t dda2_on_off; 250c582b7e3Smrg 251c582b7e3Smrg /* Pallet */ 252c582b7e3Smrg Bool palette_valid; 253b3ff493bSmrg uint32_t palette[256]; 254b3ff493bSmrg uint32_t palette2[256]; 255c582b7e3Smrg} R128SaveRec, *R128SavePtr; 256c582b7e3Smrg 257c582b7e3Smrgtypedef struct { 258b3ff493bSmrg uint16_t reference_freq; 259b3ff493bSmrg uint16_t reference_div; 260c582b7e3Smrg unsigned min_pll_freq; 261c582b7e3Smrg unsigned max_pll_freq; 262b3ff493bSmrg uint16_t xclk; 263c582b7e3Smrg} R128PLLRec, *R128PLLPtr; 264c582b7e3Smrg 265c582b7e3Smrgtypedef struct { 266c582b7e3Smrg int bitsPerPixel; 267c582b7e3Smrg int depth; 268c582b7e3Smrg int displayWidth; 269c582b7e3Smrg int pixel_code; 270c582b7e3Smrg int pixel_bytes; 271c582b7e3Smrg DisplayModePtr mode; 272c582b7e3Smrg} R128FBLayout; 273c582b7e3Smrg 27484354367Smrg#ifdef USE_EXA 27584354367Smrgstruct r128_2d_state { 27684354367Smrg Bool in_use; 27784354367Smrg Bool composite_setup; 27884354367Smrg uint32_t dst_pitch_offset; 27984354367Smrg uint32_t src_pitch_offset; 28084354367Smrg uint32_t dp_gui_master_cntl; 28184354367Smrg uint32_t dp_cntl; 28284354367Smrg uint32_t dp_write_mask; 28384354367Smrg uint32_t dp_brush_frgd_clr; 28484354367Smrg uint32_t dp_brush_bkgd_clr; 28584354367Smrg uint32_t dp_src_frgd_clr; 28684354367Smrg uint32_t dp_src_bkgd_clr; 28784354367Smrg uint32_t default_sc_bottom_right; 28884354367Smrg#if defined(R128DRI) && defined(RENDER) 28984354367Smrg Bool has_mask; 29084354367Smrg int x_offset; 29184354367Smrg int y_offset; 29284354367Smrg int widths[2]; 29384354367Smrg int heights[2]; 29484354367Smrg Bool is_transform[2]; 29584354367Smrg PictTransform *transform[2]; 29684354367Smrg PixmapPtr src_pix; 29784354367Smrg PixmapPtr msk_pix; 29884354367Smrg#endif 29984354367Smrg}; 30084354367Smrg#endif 30184354367Smrg 302c582b7e3Smrgtypedef struct { 303c582b7e3Smrg EntityInfoPtr pEnt; 304c582b7e3Smrg pciVideoPtr PciInfo; 305b3ff493bSmrg#ifndef XSERVER_LIBPCIACCESS 306c582b7e3Smrg PCITAG PciTag; 307b3ff493bSmrg#endif 308c582b7e3Smrg int Chipset; 309c582b7e3Smrg 31079e5230eSmacallan#ifndef AVOID_FBDEV 311c582b7e3Smrg Bool FBDev; 31279e5230eSmacallan#endif 313c582b7e3Smrg 314e1efbb8aSmacallan#ifdef __NetBSD__ 315e1efbb8aSmacallan Bool HaveWSDisplay; 316e1efbb8aSmacallan Bool HaveBacklightControl; 317e1efbb8aSmacallan#endif 318c582b7e3Smrg unsigned long LinearAddr; /* Frame buffer physical address */ 319c582b7e3Smrg unsigned long MMIOAddr; /* MMIO region physical address */ 320c582b7e3Smrg unsigned long BIOSAddr; /* BIOS physical address */ 321c582b7e3Smrg 322c582b7e3Smrg void *MMIO; /* Map of MMIO region */ 323c582b7e3Smrg void *FB; /* Map of frame buffer */ 324b3ff493bSmrg uint8_t *VBIOS; /* Video BIOS for mode validation on FPs */ 325b3ff493bSmrg int FPBIOSstart; /* Start of the flat panel info */ 326c582b7e3Smrg 327b3ff493bSmrg uint32_t MemCntl; 328b3ff493bSmrg uint32_t BusCntl; 329c582b7e3Smrg unsigned long FbMapSize; /* Size of frame buffer, in bytes */ 330c582b7e3Smrg Bool HasPanelRegs; /* Current chip can connect to a FP */ 331c582b7e3Smrg 332c582b7e3Smrg R128PLLRec pll; 333c582b7e3Smrg R128RAMPtr ram; 334c582b7e3Smrg 335c582b7e3Smrg R128SaveRec SavedReg; /* Original (text) mode */ 336c582b7e3Smrg R128SaveRec ModeReg; /* Current mode */ 33784354367Smrg Bool (*CloseScreen)(CLOSE_SCREEN_ARGS_DECL); 33884354367Smrg void (*BlockHandler)(BLOCKHANDLER_ARGS_DECL); 339c582b7e3Smrg 340c582b7e3Smrg Bool PaletteSavedOnVT; /* Palette saved on last VT switch */ 341c582b7e3Smrg 34284354367Smrg#ifdef HAVE_XAA_H 343c582b7e3Smrg XAAInfoRecPtr accel; 34484354367Smrg#endif 345c582b7e3Smrg Bool accelOn; 34684354367Smrg Bool useEXA; 34784354367Smrg Bool RenderAccel; 34884354367Smrg#ifdef USE_EXA 34984354367Smrg ExaDriverPtr ExaDriver; 35084354367Smrg XF86ModReqInfo exaReq; 35184354367Smrg struct r128_2d_state state_2d; 35284354367Smrg#endif 35384354367Smrg 354c582b7e3Smrg int fifo_slots; /* Free slots in the FIFO (64 max) */ 355c582b7e3Smrg int pix24bpp; /* Depth of pixmap for 24bpp framebuffer */ 356c582b7e3Smrg Bool dac6bits; /* Use 6 bit DAC? */ 357c582b7e3Smrg 358c582b7e3Smrg /* Computed values for Rage 128 */ 359c582b7e3Smrg int pitch; 360c582b7e3Smrg int datatype; 361b3ff493bSmrg uint32_t dp_gui_master_cntl; 362c582b7e3Smrg 363c582b7e3Smrg /* Saved values for ScreenToScreenCopy */ 364c582b7e3Smrg int xdir; 365c582b7e3Smrg int ydir; 366c582b7e3Smrg 367c582b7e3Smrg /* ScanlineScreenToScreenColorExpand support */ 368c582b7e3Smrg unsigned char *scratch_buffer[1]; 369c582b7e3Smrg unsigned char *scratch_save; 370c582b7e3Smrg int scanline_x; 371c582b7e3Smrg int scanline_y; 372c582b7e3Smrg int scanline_w; 373c582b7e3Smrg int scanline_h; 37484354367Smrg#ifdef R128DRI 375c582b7e3Smrg int scanline_hpass; 376c582b7e3Smrg int scanline_x1clip; 377c582b7e3Smrg int scanline_x2clip; 378c582b7e3Smrg int scanline_rop; 379c582b7e3Smrg int scanline_fg; 380c582b7e3Smrg int scanline_bg; 38184354367Smrg#endif /* R128DRI */ 382c582b7e3Smrg int scanline_words; 383c582b7e3Smrg int scanline_direct; 384c582b7e3Smrg int scanline_bpp; /* Only used for ImageWrite */ 385c582b7e3Smrg 386c582b7e3Smrg R128FBLayout CurrentLayout; 38784354367Smrg#ifdef R128DRI 388c582b7e3Smrg Bool directRenderingEnabled; 389c582b7e3Smrg DRIInfoPtr pDRIInfo; 390c582b7e3Smrg int drmFD; 391b3ff493bSmrg drm_context_t drmCtx; 392c582b7e3Smrg int numVisualConfigs; 393c582b7e3Smrg __GLXvisualConfig *pVisualConfigs; 394c582b7e3Smrg R128ConfigPrivPtr pVisualConfigsPriv; 395c582b7e3Smrg 396b3ff493bSmrg drm_handle_t fbHandle; 397c582b7e3Smrg 398c582b7e3Smrg drmSize registerSize; 399b3ff493bSmrg drm_handle_t registerHandle; 400c582b7e3Smrg 401c582b7e3Smrg Bool IsPCI; /* Current card is a PCI card */ 402c582b7e3Smrg drmSize pciSize; 403b3ff493bSmrg drm_handle_t pciMemHandle; 404c582b7e3Smrg drmAddress PCI; /* Map */ 405c582b7e3Smrg 406c582b7e3Smrg Bool allowPageFlip; /* Enable 3d page flipping */ 407c582b7e3Smrg Bool have3DWindows; /* Are there any 3d clients? */ 408c582b7e3Smrg int drmMinor; 409c582b7e3Smrg 410c582b7e3Smrg drmSize agpSize; 411b3ff493bSmrg drm_handle_t agpMemHandle; /* Handle from drmAgpAlloc */ 412c582b7e3Smrg unsigned long agpOffset; 413c582b7e3Smrg drmAddress AGP; /* Map */ 414c582b7e3Smrg int agpMode; 415c582b7e3Smrg 416c582b7e3Smrg Bool CCEInUse; /* CCE is currently active */ 417c582b7e3Smrg int CCEMode; /* CCE mode that server/clients use */ 418c582b7e3Smrg int CCEFifoSize; /* Size of the CCE command FIFO */ 419c582b7e3Smrg Bool CCESecure; /* CCE security enabled */ 420c582b7e3Smrg int CCEusecTimeout; /* CCE timeout in usecs */ 421c582b7e3Smrg 422c582b7e3Smrg /* CCE ring buffer data */ 423c582b7e3Smrg unsigned long ringStart; /* Offset into AGP space */ 424b3ff493bSmrg drm_handle_t ringHandle; /* Handle from drmAddMap */ 425c582b7e3Smrg drmSize ringMapSize; /* Size of map */ 426c582b7e3Smrg int ringSize; /* Size of ring (in MB) */ 427c582b7e3Smrg drmAddress ring; /* Map */ 428c582b7e3Smrg int ringSizeLog2QW; 429c582b7e3Smrg 430c582b7e3Smrg unsigned long ringReadOffset; /* Offset into AGP space */ 431b3ff493bSmrg drm_handle_t ringReadPtrHandle;/* Handle from drmAddMap */ 432c582b7e3Smrg drmSize ringReadMapSize; /* Size of map */ 433c582b7e3Smrg drmAddress ringReadPtr; /* Map */ 434c582b7e3Smrg 435c582b7e3Smrg /* CCE vertex/indirect buffer data */ 436c582b7e3Smrg unsigned long bufStart; /* Offset into AGP space */ 437b3ff493bSmrg drm_handle_t bufHandle; /* Handle from drmAddMap */ 438c582b7e3Smrg drmSize bufMapSize; /* Size of map */ 439c582b7e3Smrg int bufSize; /* Size of buffers (in MB) */ 440c582b7e3Smrg drmAddress buf; /* Map */ 441c582b7e3Smrg int bufNumBufs; /* Number of buffers */ 442c582b7e3Smrg drmBufMapPtr buffers; /* Buffer map */ 443c582b7e3Smrg 444c582b7e3Smrg /* CCE AGP Texture data */ 445c582b7e3Smrg unsigned long agpTexStart; /* Offset into AGP space */ 446b3ff493bSmrg drm_handle_t agpTexHandle; /* Handle from drmAddMap */ 447c582b7e3Smrg drmSize agpTexMapSize; /* Size of map */ 448c582b7e3Smrg int agpTexSize; /* Size of AGP tex space (in MB) */ 449c582b7e3Smrg drmAddress agpTex; /* Map */ 450c582b7e3Smrg int log2AGPTexGran; 451c582b7e3Smrg 452c582b7e3Smrg /* CCE 2D accleration */ 453c582b7e3Smrg drmBufPtr indirectBuffer; 454c582b7e3Smrg int indirectStart; 455c582b7e3Smrg 456c582b7e3Smrg /* DRI screen private data */ 457c582b7e3Smrg int fbX; 458c582b7e3Smrg int fbY; 459c582b7e3Smrg int backX; 460c582b7e3Smrg int backY; 461c582b7e3Smrg int depthX; 462c582b7e3Smrg int depthY; 463c582b7e3Smrg 464c582b7e3Smrg int frontOffset; 465c582b7e3Smrg int frontPitch; 466c582b7e3Smrg int backOffset; 467c582b7e3Smrg int backPitch; 468c582b7e3Smrg int depthOffset; 469c582b7e3Smrg int depthPitch; 470c582b7e3Smrg int spanOffset; 471c582b7e3Smrg int textureOffset; 472c582b7e3Smrg int textureSize; 473c582b7e3Smrg int log2TexGran; 474c582b7e3Smrg 475c582b7e3Smrg /* Saved scissor values */ 476b3ff493bSmrg uint32_t sc_left; 477b3ff493bSmrg uint32_t sc_right; 478b3ff493bSmrg uint32_t sc_top; 479b3ff493bSmrg uint32_t sc_bottom; 480c582b7e3Smrg 481b3ff493bSmrg uint32_t re_top_left; 482b3ff493bSmrg uint32_t re_width_height; 483c582b7e3Smrg 484b3ff493bSmrg uint32_t aux_sc_cntl; 485c582b7e3Smrg 486c582b7e3Smrg int irq; 487b3ff493bSmrg uint32_t gen_int_cntl; 488c582b7e3Smrg 489c582b7e3Smrg Bool DMAForXv; 490c582b7e3Smrg#endif 491c582b7e3Smrg 492c582b7e3Smrg XF86VideoAdaptorPtr adaptor; 493c582b7e3Smrg void (*VideoTimerCallback)(ScrnInfoPtr, Time); 494c582b7e3Smrg int videoKey; 495c582b7e3Smrg Bool showCache; 496c582b7e3Smrg OptionInfoPtr Options; 497c582b7e3Smrg 498c582b7e3Smrg Bool isDFP; 499c582b7e3Smrg Bool isPro2; 500b3ff493bSmrg Bool SwitchingMode; 501b3ff493bSmrg Bool DDC; 502c582b7e3Smrg 503c582b7e3Smrg Bool VGAAccess; 504c582b7e3Smrg} R128InfoRec, *R128InfoPtr; 505c582b7e3Smrg 506c582b7e3Smrg#define R128WaitForFifo(pScrn, entries) \ 507c582b7e3Smrgdo { \ 508c582b7e3Smrg if (info->fifo_slots < entries) R128WaitForFifoFunction(pScrn, entries); \ 509c582b7e3Smrg info->fifo_slots -= entries; \ 510c582b7e3Smrg} while (0) 511c582b7e3Smrg 512c582b7e3Smrgextern R128EntPtr R128EntPriv(ScrnInfoPtr pScrn); 513c582b7e3Smrgextern void R128WaitForFifoFunction(ScrnInfoPtr pScrn, int entries); 514c582b7e3Smrgextern void R128WaitForIdle(ScrnInfoPtr pScrn); 515c582b7e3Smrgextern void R128EngineReset(ScrnInfoPtr pScrn); 516c582b7e3Smrgextern void R128EngineFlush(ScrnInfoPtr pScrn); 517c582b7e3Smrg 518c582b7e3Smrgextern unsigned R128INPLL(ScrnInfoPtr pScrn, int addr); 519c582b7e3Smrgextern void R128WaitForVerticalSync(ScrnInfoPtr pScrn); 520c582b7e3Smrg 521c582b7e3Smrgextern Bool R128AccelInit(ScreenPtr pScreen); 522c582b7e3Smrgextern void R128EngineInit(ScrnInfoPtr pScrn); 523c582b7e3Smrgextern Bool R128CursorInit(ScreenPtr pScreen); 524c582b7e3Smrg 525c582b7e3Smrgextern int R128MinBits(int val); 526b3ff493bSmrgextern xf86OutputPtr R128FirstOutput(xf86CrtcPtr crtc); 527c582b7e3Smrg 528c582b7e3Smrgextern void R128InitVideo(ScreenPtr pScreen); 529c582b7e3Smrg 530b3ff493bSmrgextern void R128InitCommonRegisters(R128SavePtr save, R128InfoPtr info); 531b3ff493bSmrgextern void R128InitDACRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output); 532b3ff493bSmrgextern void R128InitRMXRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output, DisplayModePtr mode); 533b3ff493bSmrgextern void R128InitFPRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output); 534b3ff493bSmrgextern void R128InitLVDSRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output); 535b3ff493bSmrgextern Bool R128InitCrtcBase(xf86CrtcPtr crtc, R128SavePtr save, int x, int y); 536b3ff493bSmrgextern Bool R128InitCrtcRegisters(xf86CrtcPtr crtc, R128SavePtr save, DisplayModePtr mode); 537b3ff493bSmrgextern void R128InitPLLRegisters(xf86CrtcPtr crtc, R128SavePtr save, R128PLLPtr pll, double dot_clock); 538b3ff493bSmrgextern Bool R128InitDDARegisters(xf86CrtcPtr crtc, R128SavePtr save, R128PLLPtr pll, DisplayModePtr mode); 539b3ff493bSmrgextern Bool R128InitCrtc2Base(xf86CrtcPtr crtc, R128SavePtr save, int x, int y); 540b3ff493bSmrgextern Bool R128InitCrtc2Registers(xf86CrtcPtr crtc, R128SavePtr save, DisplayModePtr mode); 541b3ff493bSmrgextern void R128InitPLL2Registers(xf86CrtcPtr crtc, R128SavePtr save, R128PLLPtr pll, double dot_clock); 542b3ff493bSmrgextern Bool R128InitDDA2Registers(xf86CrtcPtr crtc, R128SavePtr save, R128PLLPtr pll, DisplayModePtr mode); 543b3ff493bSmrgextern void R128RestoreCommonRegisters(ScrnInfoPtr pScrn, R128SavePtr restore); 544b3ff493bSmrgextern void R128RestoreDACRegisters(ScrnInfoPtr pScrn, R128SavePtr restore); 545b3ff493bSmrgextern void R128RestoreRMXRegisters(ScrnInfoPtr pScrn, R128SavePtr restore); 546b3ff493bSmrgextern void R128RestoreFPRegisters(ScrnInfoPtr pScrn, R128SavePtr restore); 547b3ff493bSmrgextern void R128RestoreLVDSRegisters(ScrnInfoPtr pScrn, R128SavePtr restore); 548b3ff493bSmrgextern void R128RestoreCrtcRegisters(ScrnInfoPtr pScrn, R128SavePtr restore); 549b3ff493bSmrgextern void R128RestorePLLRegisters(ScrnInfoPtr pScrn, R128SavePtr restore); 550b3ff493bSmrgextern void R128RestoreDDARegisters(ScrnInfoPtr pScrn, R128SavePtr restore); 551b3ff493bSmrgextern void R128RestoreCrtc2Registers(ScrnInfoPtr pScrn, R128SavePtr restore); 552b3ff493bSmrgextern void R128RestorePLL2Registers(ScrnInfoPtr pScrn, R128SavePtr restore); 553b3ff493bSmrgextern void R128RestoreDDA2Registers(ScrnInfoPtr pScrn, R128SavePtr restore); 554b3ff493bSmrg 555b3ff493bSmrgextern void r128_crtc_set_cursor_colors(xf86CrtcPtr crtc, int bg, int fg); 556b3ff493bSmrgextern void r128_crtc_set_cursor_position(xf86CrtcPtr crtc, int x, int y); 557b3ff493bSmrgextern void r128_crtc_show_cursor(xf86CrtcPtr crtc); 558b3ff493bSmrgextern void r128_crtc_hide_cursor(xf86CrtcPtr crtc); 559b3ff493bSmrgextern void r128_crtc_load_cursor_image(xf86CrtcPtr crtc, unsigned char *src); 560b3ff493bSmrg 561b3ff493bSmrgextern uint32_t R128AllocateMemory(ScrnInfoPtr pScrn, void **mem_struct, int size, int align, Bool need_accel); 562b3ff493bSmrgextern Bool R128SetupConnectors(ScrnInfoPtr pScrn); 563b3ff493bSmrgextern Bool R128AllocateControllers(ScrnInfoPtr pScrn); 564b3ff493bSmrgextern void R128GetPanelInfoFromBIOS(xf86OutputPtr output); 565b3ff493bSmrgextern void R128Blank(ScrnInfoPtr pScrn); 566b3ff493bSmrgextern void R128Unblank(ScrnInfoPtr pScrn); 567b3ff493bSmrgextern void R128DPMSSetOn(xf86OutputPtr output); 568b3ff493bSmrgextern void R128DPMSSetOff(xf86OutputPtr output); 569b3ff493bSmrgextern ModeStatus R128DoValidMode(xf86OutputPtr output, DisplayModePtr mode, int flags); 570b3ff493bSmrgextern DisplayModePtr R128ProbeOutputModes(xf86OutputPtr output); 571b3ff493bSmrg 57284354367Smrg#ifdef R128DRI 573c582b7e3Smrgextern Bool R128DRIScreenInit(ScreenPtr pScreen); 574c582b7e3Smrgextern void R128DRICloseScreen(ScreenPtr pScreen); 575c582b7e3Smrgextern Bool R128DRIFinishScreenInit(ScreenPtr pScreen); 576c582b7e3Smrg 577c582b7e3Smrg#define R128CCE_START(pScrn, info) \ 578c582b7e3Smrgdo { \ 579c582b7e3Smrg int _ret = drmCommandNone(info->drmFD, DRM_R128_CCE_START); \ 580c582b7e3Smrg if (_ret) { \ 581c582b7e3Smrg xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 582c582b7e3Smrg "%s: CCE start %d\n", __FUNCTION__, _ret); \ 583c582b7e3Smrg } \ 584c582b7e3Smrg} while (0) 585c582b7e3Smrg 586c582b7e3Smrg#define R128CCE_STOP(pScrn, info) \ 587c582b7e3Smrgdo { \ 588c582b7e3Smrg int _ret = R128CCEStop(pScrn); \ 589c582b7e3Smrg if (_ret) { \ 590c582b7e3Smrg xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 591c582b7e3Smrg "%s: CCE stop %d\n", __FUNCTION__, _ret); \ 592c582b7e3Smrg } \ 593c582b7e3Smrg} while (0) 594c582b7e3Smrg 595c582b7e3Smrg#define R128CCE_RESET(pScrn, info) \ 596c582b7e3Smrgdo { \ 597c582b7e3Smrg if (info->directRenderingEnabled \ 598c582b7e3Smrg && R128CCE_USE_RING_BUFFER(info->CCEMode)) { \ 599c582b7e3Smrg int _ret = drmCommandNone(info->drmFD, DRM_R128_CCE_RESET); \ 600c582b7e3Smrg if (_ret) { \ 601c582b7e3Smrg xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 602c582b7e3Smrg "%s: CCE reset %d\n", __FUNCTION__, _ret); \ 603c582b7e3Smrg } \ 604c582b7e3Smrg } \ 605c582b7e3Smrg} while (0) 606c582b7e3Smrg 607c582b7e3Smrgextern drmBufPtr R128CCEGetBuffer(ScrnInfoPtr pScrn); 608c582b7e3Smrg#endif 609c582b7e3Smrg 610c582b7e3Smrgextern void R128CCEFlushIndirect(ScrnInfoPtr pScrn, int discard); 611c582b7e3Smrgextern void R128CCEReleaseIndirect(ScrnInfoPtr pScrn); 612c582b7e3Smrgextern void R128CCEWaitForIdle(ScrnInfoPtr pScrn); 613c582b7e3Smrgextern int R128CCEStop(ScrnInfoPtr pScrn); 614a0e1ef58Smrgextern void R128CopySwap(uint8_t *dst, uint8_t *src, unsigned int size, int swap); 615c582b7e3Smrg 61684354367Smrg#ifdef USE_EXA 61784354367Smrgextern Bool R128EXAInit(ScreenPtr pScreen); 61884354367Smrgextern Bool R128GetDatatypeBpp(int bpp, uint32_t *type); 61984354367Smrgextern Bool R128GetPixmapOffsetPitch(PixmapPtr pPix, uint32_t *pitch_offset); 62084354367Smrgextern void R128DoPrepareCopy(ScrnInfoPtr pScrn, uint32_t src_pitch_offset, 62184354367Smrg uint32_t dst_pitch_offset, uint32_t datatype, int alu, Pixel planemask); 62284354367Smrg#endif 62384354367Smrg 624c582b7e3Smrg 625c582b7e3Smrg#define CCE_PACKET0( reg, n ) \ 626c582b7e3Smrg (R128_CCE_PACKET0 | ((n) << 16) | ((reg) >> 2)) 627c582b7e3Smrg#define CCE_PACKET1( reg0, reg1 ) \ 628c582b7e3Smrg (R128_CCE_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2)) 629c582b7e3Smrg#define CCE_PACKET2() \ 630c582b7e3Smrg (R128_CCE_PACKET2) 631c582b7e3Smrg#define CCE_PACKET3( pkt, n ) \ 632c582b7e3Smrg (R128_CCE_PACKET3 | (pkt) | ((n) << 16)) 633c582b7e3Smrg 634c582b7e3Smrg 635c582b7e3Smrg#define R128_VERBOSE 0 636c582b7e3Smrg 637b3ff493bSmrg#define RING_LOCALS uint32_t *__head; int __count; 638c582b7e3Smrg 639c582b7e3Smrg#define R128CCE_REFRESH(pScrn, info) \ 640c582b7e3Smrgdo { \ 641c582b7e3Smrg if ( R128_VERBOSE ) { \ 642c582b7e3Smrg xf86DrvMsg( pScrn->scrnIndex, X_INFO, "REFRESH( %d ) in %s\n", \ 643c582b7e3Smrg !info->CCEInUse , __FUNCTION__ ); \ 644c582b7e3Smrg } \ 645c582b7e3Smrg if ( !info->CCEInUse ) { \ 646c582b7e3Smrg R128CCEWaitForIdle(pScrn); \ 647c582b7e3Smrg BEGIN_RING( 6 ); \ 648c582b7e3Smrg OUT_RING_REG( R128_RE_TOP_LEFT, info->re_top_left ); \ 649c582b7e3Smrg OUT_RING_REG( R128_RE_WIDTH_HEIGHT, info->re_width_height ); \ 650c582b7e3Smrg OUT_RING_REG( R128_AUX_SC_CNTL, info->aux_sc_cntl ); \ 651c582b7e3Smrg ADVANCE_RING(); \ 652c582b7e3Smrg info->CCEInUse = TRUE; \ 653c582b7e3Smrg } \ 654c582b7e3Smrg} while (0) 655c582b7e3Smrg 656c582b7e3Smrg#define BEGIN_RING( n ) do { \ 657c582b7e3Smrg if ( R128_VERBOSE ) { \ 658c582b7e3Smrg xf86DrvMsg( pScrn->scrnIndex, X_INFO, \ 659c582b7e3Smrg "BEGIN_RING( %d ) in %s\n", n, __FUNCTION__ ); \ 660c582b7e3Smrg } \ 661c582b7e3Smrg if ( !info->indirectBuffer ) { \ 662c582b7e3Smrg info->indirectBuffer = R128CCEGetBuffer( pScrn ); \ 663c582b7e3Smrg info->indirectStart = 0; \ 664c582b7e3Smrg } else if ( (info->indirectBuffer->used + 4*(n)) > \ 665c582b7e3Smrg info->indirectBuffer->total ) { \ 666c582b7e3Smrg R128CCEFlushIndirect( pScrn, 1 ); \ 667c582b7e3Smrg } \ 668c582b7e3Smrg __head = (pointer)((char *)info->indirectBuffer->address + \ 669c582b7e3Smrg info->indirectBuffer->used); \ 670c582b7e3Smrg __count = 0; \ 671c582b7e3Smrg} while (0) 672c582b7e3Smrg 673c582b7e3Smrg#define ADVANCE_RING() do { \ 674c582b7e3Smrg if ( R128_VERBOSE ) { \ 675c582b7e3Smrg xf86DrvMsg( pScrn->scrnIndex, X_INFO, \ 676c582b7e3Smrg "ADVANCE_RING() used: %d+%d=%d/%d\n", \ 677c582b7e3Smrg info->indirectBuffer->used - info->indirectStart, \ 678b3ff493bSmrg __count * (int)sizeof(uint32_t), \ 679c582b7e3Smrg info->indirectBuffer->used - info->indirectStart + \ 680b3ff493bSmrg __count * (int)sizeof(uint32_t), \ 681c582b7e3Smrg info->indirectBuffer->total - info->indirectStart ); \ 682c582b7e3Smrg } \ 683b3ff493bSmrg info->indirectBuffer->used += __count * (int)sizeof(uint32_t); \ 684c582b7e3Smrg} while (0) 685c582b7e3Smrg 686c582b7e3Smrg#define OUT_RING( x ) do { \ 687c582b7e3Smrg if ( R128_VERBOSE ) { \ 688c582b7e3Smrg xf86DrvMsg( pScrn->scrnIndex, X_INFO, \ 689c582b7e3Smrg " OUT_RING( 0x%08x )\n", (unsigned int)(x) ); \ 690c582b7e3Smrg } \ 691c582b7e3Smrg MMIO_OUT32(&__head[__count++], 0, (x)); \ 692c582b7e3Smrg} while (0) 693c582b7e3Smrg 694c582b7e3Smrg#define OUT_RING_REG( reg, val ) \ 695c582b7e3Smrgdo { \ 696c582b7e3Smrg OUT_RING( CCE_PACKET0( reg, 0 ) ); \ 697c582b7e3Smrg OUT_RING( val ); \ 698c582b7e3Smrg} while (0) 699c582b7e3Smrg 700c582b7e3Smrg#define FLUSH_RING() \ 701c582b7e3Smrgdo { \ 702c582b7e3Smrg if ( R128_VERBOSE ) \ 703c582b7e3Smrg xf86DrvMsg( pScrn->scrnIndex, X_INFO, \ 704c582b7e3Smrg "FLUSH_RING in %s\n", __FUNCTION__ ); \ 705c582b7e3Smrg if ( info->indirectBuffer ) { \ 706c582b7e3Smrg R128CCEFlushIndirect( pScrn, 0 ); \ 707c582b7e3Smrg } \ 708c582b7e3Smrg} while (0) 709c582b7e3Smrg 710c582b7e3Smrg#endif 711