r128.h revision e8b4ed9f
1/* 2 * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario, 3 * Precision Insight, Inc., Cedar Park, Texas, and 4 * VA Linux Systems Inc., Fremont, California. 5 * 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining 9 * a copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation on the rights to use, copy, modify, merge, 12 * publish, distribute, sublicense, and/or sell copies of the Software, 13 * and to permit persons to whom the Software is furnished to do so, 14 * subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial 18 * portions of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 23 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, PRECISION INSIGHT, VA LINUX 24 * SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 25 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 26 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 27 * OTHER DEALINGS IN THE SOFTWARE. 28 */ 29 30/* 31 * Authors: 32 * Rickard E. Faith <faith@valinux.com> 33 * Kevin E. Martin <martin@valinux.com> 34 * 35 */ 36 37#ifndef _R128_H_ 38#define _R128_H_ 39 40#include <unistd.h> 41#include "xf86str.h" 42 43 /* PCI support */ 44#include "xf86Pci.h" 45 46 /* EXA support */ 47#ifdef USE_EXA 48#include "exa.h" 49#endif 50 51 /* XAA and Cursor Support */ 52#ifdef HAVE_XAA_H 53#include "xaa.h" 54#endif 55#include "xf86fbman.h" 56#include "xf86Cursor.h" 57 58 /* DDC support */ 59#include "xf86DDC.h" 60 61 /* Xv support */ 62#include "xf86xv.h" 63 64 /* DRI support */ 65#ifndef XF86DRI 66#undef R128DRI 67#endif 68 69#if R128DRI 70#define _XF86DRI_SERVER_ 71#include "r128_dripriv.h" 72#include "dri.h" 73#endif 74 75#include "fb.h" 76#include "xf86Crtc.h" 77 78#include "compat-api.h" 79#include "atipcirename.h" 80 81#include "r128_probe.h" 82 83#if HAVE_BYTESWAP_H 84#include <byteswap.h> 85#elif defined(USE_SYS_ENDIAN_H) 86#include <sys/endian.h> 87#else 88#define bswap_16(value) \ 89 ((((value) & 0xff) << 8) | ((value) >> 8)) 90 91#define bswap_32(value) \ 92 (((uint32_t)bswap_16((uint16_t)((value) & 0xffff)) << 16) | \ 93 (uint32_t)bswap_16((uint16_t)((value) >> 16))) 94 95#define bswap_64(value) \ 96 (((uint64_t)bswap_32((uint32_t)((value) & 0xffffffff)) \ 97 << 32) | \ 98 (uint64_t)bswap_32((uint32_t)((value) >> 32))) 99#endif 100 101#if X_BYTE_ORDER == X_BIG_ENDIAN 102#define le32_to_cpu(x) bswap_32(x) 103#define le16_to_cpu(x) bswap_16(x) 104#define cpu_to_le32(x) bswap_32(x) 105#define cpu_to_le16(x) bswap_16(x) 106#else 107#define le32_to_cpu(x) (x) 108#define le16_to_cpu(x) (x) 109#define cpu_to_le32(x) (x) 110#define cpu_to_le16(x) (x) 111#endif 112 113#define R128_DEBUG 0 /* Turn off debugging output */ 114#define R128_IDLE_RETRY 32 /* Fall out of idle loops after this count */ 115#define R128_TIMEOUT 2000000 /* Fall out of wait loops after this count */ 116#define R128_MMIOSIZE 0x4000 117 118#define R128_VBIOS_SIZE 0x00010000 119#define R128_NAME "R128" 120 121#if R128_DEBUG 122#include "r128_version.h" 123 124#endif 125 126#if R128_DEBUG 127#define DEBUG(x) x 128 129#else 130#define DEBUG(x) 131 132#endif 133 134 135/* Other macros */ 136#define R128_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) 137#define R128_ALIGN(x,bytes) (((x) + ((bytes) - 1)) & ~((bytes) - 1)) 138#define R128PTR(pScrn) ((R128InfoPtr)(pScrn)->driverPrivate) 139 140#define R128_BIOS8(v) ((info->VBIOS[(v)])) 141#define R128_BIOS16(v) ((info->VBIOS[(v)]) | \ 142 (info->VBIOS[(v) + 1] << 8)) 143#define R128_BIOS32(v) ((info->VBIOS[(v)]) | \ 144 (info->VBIOS[(v) + 1] << 8) | \ 145 (info->VBIOS[(v) + 2] << 16) | \ 146 (info->VBIOS[(v) + 3] << 24)) 147 148typedef struct { /* All values in XCLKS */ 149 int ML; /* Memory Read Latency */ 150 int MB; /* Memory Burst Length */ 151 int Trcd; /* RAS to CAS delay */ 152 int Trp; /* RAS percentage */ 153 int Twr; /* Write Recovery */ 154 int CL; /* CAS Latency */ 155 int Tr2w; /* Read to Write Delay */ 156 int Rloop; /* Loop Latency */ 157 int Rloop_fudge; /* Add to ML to get Rloop */ 158 const char *name; 159} R128RAMRec, *R128RAMPtr; 160 161typedef struct { 162 /* Common registers */ 163 uint32_t ovr_clr; 164 uint32_t ovr_wid_left_right; 165 uint32_t ovr_wid_top_bottom; 166 uint32_t ov0_scale_cntl; 167 uint32_t mpp_tb_config; 168 uint32_t mpp_gp_config; 169 uint32_t subpic_cntl; 170 uint32_t viph_control; 171 uint32_t i2c_cntl_1; 172 uint32_t gen_int_cntl; 173 uint32_t cap0_trig_cntl; 174 uint32_t cap1_trig_cntl; 175 uint32_t bus_cntl; 176 uint32_t config_cntl; 177 178 /* Other registers to save for VT switches */ 179 uint32_t dp_datatype; 180 uint32_t gen_reset_cntl; 181 uint32_t clock_cntl_index; 182 uint32_t amcgpio_en_reg; 183 uint32_t amcgpio_mask; 184 185 /* CRTC registers */ 186 uint32_t crtc_gen_cntl; 187 uint32_t crtc_ext_cntl; 188 uint32_t dac_cntl; 189 uint32_t crtc_h_total_disp; 190 uint32_t crtc_h_sync_strt_wid; 191 uint32_t crtc_v_total_disp; 192 uint32_t crtc_v_sync_strt_wid; 193 uint32_t crtc_offset; 194 uint32_t crtc_offset_cntl; 195 uint32_t crtc_pitch; 196 197 /* CRTC2 registers */ 198 uint32_t crtc2_gen_cntl; 199 uint32_t crtc2_h_total_disp; 200 uint32_t crtc2_h_sync_strt_wid; 201 uint32_t crtc2_v_total_disp; 202 uint32_t crtc2_v_sync_strt_wid; 203 uint32_t crtc2_offset; 204 uint32_t crtc2_offset_cntl; 205 uint32_t crtc2_pitch; 206 207 /* Flat panel registers */ 208 uint32_t fp_crtc_h_total_disp; 209 uint32_t fp_crtc_v_total_disp; 210 uint32_t fp_gen_cntl; 211 uint32_t fp_h_sync_strt_wid; 212 uint32_t fp_horz_stretch; 213 uint32_t fp_panel_cntl; 214 uint32_t fp_v_sync_strt_wid; 215 uint32_t fp_vert_stretch; 216 uint32_t lvds_gen_cntl; 217 uint32_t tmds_crc; 218 uint32_t tmds_transmitter_cntl; 219 220 /* Computed values for PLL */ 221 uint32_t dot_clock_freq; 222 uint32_t pll_output_freq; 223 int feedback_div; 224 int post_div; 225 226 /* PLL registers */ 227 uint32_t ppll_ref_div; 228 uint32_t ppll_div_3; 229 uint32_t ppll_div_0; 230 uint32_t htotal_cntl; 231 232 /* Computed values for PLL2 */ 233 uint32_t dot_clock_freq_2; 234 uint32_t pll_output_freq_2; 235 int feedback_div_2; 236 int post_div_2; 237 238 /* PLL2 registers */ 239 uint32_t p2pll_ref_div; 240 uint32_t p2pll_div_0; 241 uint32_t htotal_cntl2; 242 243 /* DDA register */ 244 uint32_t dda_config; 245 uint32_t dda_on_off; 246 247 /* DDA2 register */ 248 uint32_t dda2_config; 249 uint32_t dda2_on_off; 250 251 /* Pallet */ 252 Bool palette_valid; 253 uint32_t palette[256]; 254 uint32_t palette2[256]; 255} R128SaveRec, *R128SavePtr; 256 257typedef struct { 258 uint16_t reference_freq; 259 uint16_t reference_div; 260 unsigned min_pll_freq; 261 unsigned max_pll_freq; 262 uint16_t xclk; 263} R128PLLRec, *R128PLLPtr; 264 265typedef struct { 266 int bitsPerPixel; 267 int depth; 268 int displayWidth; 269 int pixel_code; 270 int pixel_bytes; 271 DisplayModePtr mode; 272} R128FBLayout; 273 274#ifdef USE_EXA 275struct r128_2d_state { 276 Bool in_use; 277 Bool composite_setup; 278 uint32_t dst_pitch_offset; 279 uint32_t src_pitch_offset; 280 uint32_t dp_gui_master_cntl; 281 uint32_t dp_cntl; 282 uint32_t dp_write_mask; 283 uint32_t dp_brush_frgd_clr; 284 uint32_t dp_brush_bkgd_clr; 285 uint32_t dp_src_frgd_clr; 286 uint32_t dp_src_bkgd_clr; 287 uint32_t default_sc_bottom_right; 288#if defined(R128DRI) && defined(RENDER) 289 Bool has_mask; 290 int x_offset; 291 int y_offset; 292 int widths[2]; 293 int heights[2]; 294 Bool is_transform[2]; 295 PictTransform *transform[2]; 296 PixmapPtr src_pix; 297 PixmapPtr msk_pix; 298#endif 299}; 300#endif 301 302typedef struct { 303 EntityInfoPtr pEnt; 304 pciVideoPtr PciInfo; 305#ifndef XSERVER_LIBPCIACCESS 306 PCITAG PciTag; 307#endif 308 int Chipset; 309 310#ifndef AVOID_FBDEV 311 Bool FBDev; 312#endif 313 314#ifdef __NetBSD__ 315 Bool HaveWSDisplay; 316 Bool HaveBacklightControl; 317#endif 318 unsigned long LinearAddr; /* Frame buffer physical address */ 319 unsigned long MMIOAddr; /* MMIO region physical address */ 320 unsigned long BIOSAddr; /* BIOS physical address */ 321 322 void *MMIO; /* Map of MMIO region */ 323 void *FB; /* Map of frame buffer */ 324 uint8_t *VBIOS; /* Video BIOS for mode validation on FPs */ 325 int FPBIOSstart; /* Start of the flat panel info */ 326 327 uint32_t MemCntl; 328 uint32_t BusCntl; 329 unsigned long FbMapSize; /* Size of frame buffer, in bytes */ 330 Bool HasPanelRegs; /* Current chip can connect to a FP */ 331 332 R128PLLRec pll; 333 R128RAMPtr ram; 334 335 R128SaveRec SavedReg; /* Original (text) mode */ 336 R128SaveRec ModeReg; /* Current mode */ 337 Bool (*CloseScreen)(CLOSE_SCREEN_ARGS_DECL); 338 void (*BlockHandler)(BLOCKHANDLER_ARGS_DECL); 339 340 Bool PaletteSavedOnVT; /* Palette saved on last VT switch */ 341 342#ifdef HAVE_XAA_H 343 XAAInfoRecPtr accel; 344#endif 345 346 Bool noAccel; 347 Bool accelOn; 348 Bool useEXA; 349 Bool RenderAccel; 350#ifdef USE_EXA 351 ExaDriverPtr ExaDriver; 352 XF86ModReqInfo exaReq; 353 struct r128_2d_state state_2d; 354#endif 355 356 int fifo_slots; /* Free slots in the FIFO (64 max) */ 357 int pix24bpp; /* Depth of pixmap for 24bpp framebuffer */ 358 Bool dac6bits; /* Use 6 bit DAC? */ 359 Bool swCursor; 360 361 /* Computed values for Rage 128 */ 362 int pitch; 363 int datatype; 364 uint32_t dp_gui_master_cntl; 365 366 /* Saved values for ScreenToScreenCopy */ 367 int xdir; 368 int ydir; 369 370 /* ScanlineScreenToScreenColorExpand support */ 371 unsigned char *scratch_buffer[1]; 372 unsigned char *scratch_save; 373 int scanline_x; 374 int scanline_y; 375 int scanline_w; 376 int scanline_h; 377#ifdef R128DRI 378 int scanline_hpass; 379 int scanline_x1clip; 380 int scanline_x2clip; 381 int scanline_rop; 382 int scanline_fg; 383 int scanline_bg; 384#endif /* R128DRI */ 385 int scanline_words; 386 int scanline_direct; 387 int scanline_bpp; /* Only used for ImageWrite */ 388 389 R128FBLayout CurrentLayout; 390#ifdef R128DRI 391 Bool directRenderingEnabled; 392 DRIInfoPtr pDRIInfo; 393 int drmFD; 394 drm_context_t drmCtx; 395 396 drm_handle_t fbHandle; 397 398 drmSize registerSize; 399 drm_handle_t registerHandle; 400 401 Bool IsPCI; /* Current card is a PCI card */ 402 drmSize pciSize; 403 drm_handle_t pciMemHandle; 404 drmAddress PCI; /* Map */ 405 406 Bool allowPageFlip; /* Enable 3d page flipping */ 407 Bool have3DWindows; /* Are there any 3d clients? */ 408 int drmMinor; 409 410 drmSize agpSize; 411 drm_handle_t agpMemHandle; /* Handle from drmAgpAlloc */ 412 unsigned long agpOffset; 413 drmAddress AGP; /* Map */ 414 int agpMode; 415 416 Bool CCEInUse; /* CCE is currently active */ 417 int CCEMode; /* CCE mode that server/clients use */ 418 int CCEFifoSize; /* Size of the CCE command FIFO */ 419 Bool CCESecure; /* CCE security enabled */ 420 int CCEusecTimeout; /* CCE timeout in usecs */ 421 422 /* CCE ring buffer data */ 423 unsigned long ringStart; /* Offset into AGP space */ 424 drm_handle_t ringHandle; /* Handle from drmAddMap */ 425 drmSize ringMapSize; /* Size of map */ 426 int ringSize; /* Size of ring (in MB) */ 427 drmAddress ring; /* Map */ 428 int ringSizeLog2QW; 429 430 unsigned long ringReadOffset; /* Offset into AGP space */ 431 drm_handle_t ringReadPtrHandle;/* Handle from drmAddMap */ 432 drmSize ringReadMapSize; /* Size of map */ 433 drmAddress ringReadPtr; /* Map */ 434 435 /* CCE vertex/indirect buffer data */ 436 unsigned long bufStart; /* Offset into AGP space */ 437 drm_handle_t bufHandle; /* Handle from drmAddMap */ 438 drmSize bufMapSize; /* Size of map */ 439 int bufSize; /* Size of buffers (in MB) */ 440 drmAddress buf; /* Map */ 441 int bufNumBufs; /* Number of buffers */ 442 drmBufMapPtr buffers; /* Buffer map */ 443 444 /* CCE AGP Texture data */ 445 unsigned long agpTexStart; /* Offset into AGP space */ 446 drm_handle_t agpTexHandle; /* Handle from drmAddMap */ 447 drmSize agpTexMapSize; /* Size of map */ 448 int agpTexSize; /* Size of AGP tex space (in MB) */ 449 drmAddress agpTex; /* Map */ 450 int log2AGPTexGran; 451 452 /* CCE 2D acceleration */ 453 drmBufPtr indirectBuffer; 454 int indirectStart; 455 456 /* DRI screen private data */ 457 int fbX; 458 int fbY; 459 int backX; 460 int backY; 461 int depthX; 462 int depthY; 463 464 int frontOffset; 465 int frontPitch; 466 int backOffset; 467 int backPitch; 468 int depthOffset; 469 int depthPitch; 470 int spanOffset; 471 int textureOffset; 472 int textureSize; 473 int log2TexGran; 474 475 /* Saved scissor values */ 476 uint32_t sc_left; 477 uint32_t sc_right; 478 uint32_t sc_top; 479 uint32_t sc_bottom; 480 481 uint32_t re_top_left; 482 uint32_t re_width_height; 483 484 uint32_t aux_sc_cntl; 485 486 int irq; 487 uint32_t gen_int_cntl; 488 489 Bool DMAForXv; 490#endif 491 492 XF86VideoAdaptorPtr adaptor; 493 void (*VideoTimerCallback)(ScrnInfoPtr, Time); 494 int videoKey; 495 Bool showCache; 496 OptionInfoPtr Options; 497 498 Bool isDFP; 499 Bool isPro2; 500 Bool SwitchingMode; 501 Bool DDC; 502 503 Bool VGAAccess; 504} R128InfoRec, *R128InfoPtr; 505 506#define R128WaitForFifo(pScrn, entries) \ 507do { \ 508 if (info->fifo_slots < entries) R128WaitForFifoFunction(pScrn, entries); \ 509 info->fifo_slots -= entries; \ 510} while (0) 511 512/* Compute n/d with rounding. */ 513static inline int R128Div(int n, int d) 514{ 515 return (n + (d / 2)) / d; 516} 517 518extern R128EntPtr R128EntPriv(ScrnInfoPtr pScrn); 519extern void R128WaitForFifoFunction(ScrnInfoPtr pScrn, int entries); 520extern void R128WaitForIdle(ScrnInfoPtr pScrn); 521extern void R128EngineReset(ScrnInfoPtr pScrn); 522extern void R128EngineFlush(ScrnInfoPtr pScrn); 523 524extern unsigned R128INPLL(ScrnInfoPtr pScrn, int addr); 525extern void R128WaitForVerticalSync(ScrnInfoPtr pScrn); 526 527extern Bool R128XAAAccelInit(ScreenPtr pScreen); 528extern void R128EngineInit(ScrnInfoPtr pScrn); 529extern Bool R128CursorInit(ScreenPtr pScreen); 530 531extern int R128MinBits(int val); 532extern xf86OutputPtr R128FirstOutput(xf86CrtcPtr crtc); 533 534extern void R128InitVideo(ScreenPtr pScreen); 535 536extern void R128InitCommonRegisters(R128SavePtr save, R128InfoPtr info); 537extern void R128InitRMXRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output, DisplayModePtr mode); 538extern void R128InitFPRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output); 539extern void R128InitLVDSRegisters(R128SavePtr orig, R128SavePtr save, xf86OutputPtr output); 540extern void R128RestoreCommonRegisters(ScrnInfoPtr pScrn, R128SavePtr restore); 541extern void R128RestoreDACRegisters(ScrnInfoPtr pScrn, R128SavePtr restore); 542extern void R128RestoreRMXRegisters(ScrnInfoPtr pScrn, R128SavePtr restore); 543extern void R128RestoreFPRegisters(ScrnInfoPtr pScrn, R128SavePtr restore); 544extern void R128RestoreLVDSRegisters(ScrnInfoPtr pScrn, R128SavePtr restore); 545extern void R128RestoreCrtcRegisters(ScrnInfoPtr pScrn, R128SavePtr restore); 546extern void R128RestorePLLRegisters(ScrnInfoPtr pScrn, R128SavePtr restore); 547extern void R128RestoreDDARegisters(ScrnInfoPtr pScrn, R128SavePtr restore); 548extern void R128RestoreCrtc2Registers(ScrnInfoPtr pScrn, R128SavePtr restore); 549extern void R128RestorePLL2Registers(ScrnInfoPtr pScrn, R128SavePtr restore); 550extern void R128RestoreDDA2Registers(ScrnInfoPtr pScrn, R128SavePtr restore); 551 552extern void r128_crtc_set_cursor_colors(xf86CrtcPtr crtc, int bg, int fg); 553extern void r128_crtc_set_cursor_position(xf86CrtcPtr crtc, int x, int y); 554extern void r128_crtc_show_cursor(xf86CrtcPtr crtc); 555extern void r128_crtc_hide_cursor(xf86CrtcPtr crtc); 556extern void r128_crtc_load_cursor_image(xf86CrtcPtr crtc, unsigned char *src); 557 558extern uint32_t R128AllocateMemory(ScrnInfoPtr pScrn, void **mem_struct, int size, int align, Bool need_accel); 559extern Bool R128SetupConnectors(ScrnInfoPtr pScrn); 560extern Bool R128AllocateControllers(ScrnInfoPtr pScrn); 561extern void R128GetPanelInfoFromBIOS(xf86OutputPtr output); 562extern void R128Blank(ScrnInfoPtr pScrn); 563extern void R128Unblank(ScrnInfoPtr pScrn); 564extern void R128DPMSSetOn(xf86OutputPtr output); 565extern void R128DPMSSetOff(xf86OutputPtr output); 566extern ModeStatus R128DoValidMode(xf86OutputPtr output, DisplayModePtr mode, int flags); 567extern DisplayModePtr R128ProbeOutputModes(xf86OutputPtr output); 568 569#ifdef R128DRI 570extern Bool R128DRIScreenInit(ScreenPtr pScreen); 571extern void R128DRICloseScreen(ScreenPtr pScreen); 572extern Bool R128DRIFinishScreenInit(ScreenPtr pScreen); 573 574#define R128CCE_START(pScrn, info) \ 575do { \ 576 int _ret = drmCommandNone(info->drmFD, DRM_R128_CCE_START); \ 577 if (_ret) { \ 578 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 579 "%s: CCE start %d\n", __FUNCTION__, _ret); \ 580 } \ 581} while (0) 582 583#define R128CCE_STOP(pScrn, info) \ 584do { \ 585 int _ret = R128CCEStop(pScrn); \ 586 if (_ret) { \ 587 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 588 "%s: CCE stop %d\n", __FUNCTION__, _ret); \ 589 } \ 590} while (0) 591 592#define R128CCE_RESET(pScrn, info) \ 593do { \ 594 if (info->directRenderingEnabled \ 595 && R128CCE_USE_RING_BUFFER(info->CCEMode)) { \ 596 int _ret = drmCommandNone(info->drmFD, DRM_R128_CCE_RESET); \ 597 if (_ret) { \ 598 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 599 "%s: CCE reset %d\n", __FUNCTION__, _ret); \ 600 } \ 601 } \ 602} while (0) 603 604extern drmBufPtr R128CCEGetBuffer(ScrnInfoPtr pScrn); 605#endif 606 607extern void R128CCEFlushIndirect(ScrnInfoPtr pScrn, int discard); 608extern void R128CCEReleaseIndirect(ScrnInfoPtr pScrn); 609extern void R128CCEWaitForIdle(ScrnInfoPtr pScrn); 610extern int R128CCEStop(ScrnInfoPtr pScrn); 611extern void R128CopySwap(uint8_t *dst, uint8_t *src, unsigned int size, int swap); 612 613#ifdef USE_EXA 614extern Bool R128EXAInit(ScreenPtr pScreen, int total); 615extern Bool R128GetDatatypeBpp(int bpp, uint32_t *type); 616extern Bool R128GetPixmapOffsetPitch(PixmapPtr pPix, uint32_t *pitch_offset); 617extern void R128DoPrepareCopy(ScrnInfoPtr pScrn, uint32_t src_pitch_offset, 618 uint32_t dst_pitch_offset, uint32_t datatype, int alu, Pixel planemask); 619extern void R128Done(PixmapPtr pPixmap); 620 621#ifdef R128DRI 622extern void EmitCCE2DState(ScrnInfoPtr pScrn); 623#endif 624 625#ifdef RENDER 626extern Bool R128CCECheckComposite(int op, 627 PicturePtr pSrcPicture, 628 PicturePtr pMaskPicture, 629 PicturePtr pDstPicture); 630extern Bool R128CCEPrepareComposite(int op, PicturePtr pSrcPicture, 631 PicturePtr pMaskPicture, 632 PicturePtr pDstPicture, 633 PixmapPtr pSrc, 634 PixmapPtr pMask, 635 PixmapPtr pDst); 636extern void R128CCEComposite(PixmapPtr pDst, 637 int srcX, int srcY, 638 int maskX, int maskY, 639 int dstX, int dstY, 640 int w, int h); 641#define R128CCEDoneComposite R128Done 642#endif 643#endif 644 645 646#define CCE_PACKET0( reg, n ) \ 647 (R128_CCE_PACKET0 | ((n) << 16) | ((reg) >> 2)) 648#define CCE_PACKET1( reg0, reg1 ) \ 649 (R128_CCE_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2)) 650#define CCE_PACKET2() \ 651 (R128_CCE_PACKET2) 652#define CCE_PACKET3( pkt, n ) \ 653 (R128_CCE_PACKET3 | (pkt) | ((n) << 16)) 654 655 656#define R128_VERBOSE 0 657 658#define RING_LOCALS uint32_t *__head; int __count; 659 660#define R128CCE_REFRESH(pScrn, info) \ 661do { \ 662 if ( R128_VERBOSE ) { \ 663 xf86DrvMsg( pScrn->scrnIndex, X_INFO, "REFRESH( %d ) in %s\n", \ 664 !info->CCEInUse , __FUNCTION__ ); \ 665 } \ 666 if ( !info->CCEInUse ) { \ 667 R128CCEWaitForIdle(pScrn); \ 668 BEGIN_RING( 6 ); \ 669 OUT_RING_REG( R128_RE_TOP_LEFT, info->re_top_left ); \ 670 OUT_RING_REG( R128_RE_WIDTH_HEIGHT, info->re_width_height ); \ 671 OUT_RING_REG( R128_AUX_SC_CNTL, info->aux_sc_cntl ); \ 672 ADVANCE_RING(); \ 673 info->CCEInUse = TRUE; \ 674 } \ 675} while (0) 676 677#define BEGIN_RING( n ) do { \ 678 if ( R128_VERBOSE ) { \ 679 xf86DrvMsg( pScrn->scrnIndex, X_INFO, \ 680 "BEGIN_RING( %d ) in %s\n", n, __FUNCTION__ ); \ 681 } \ 682 if ( !info->indirectBuffer ) { \ 683 info->indirectBuffer = R128CCEGetBuffer( pScrn ); \ 684 info->indirectStart = 0; \ 685 } else if ( (info->indirectBuffer->used + 4*(n)) > \ 686 info->indirectBuffer->total ) { \ 687 R128CCEFlushIndirect( pScrn, 1 ); \ 688 } \ 689 __head = (pointer)((char *)info->indirectBuffer->address + \ 690 info->indirectBuffer->used); \ 691 __count = 0; \ 692} while (0) 693 694#define ADVANCE_RING() do { \ 695 if ( R128_VERBOSE ) { \ 696 xf86DrvMsg( pScrn->scrnIndex, X_INFO, \ 697 "ADVANCE_RING() used: %d+%d=%d/%d\n", \ 698 info->indirectBuffer->used - info->indirectStart, \ 699 __count * (int)sizeof(uint32_t), \ 700 info->indirectBuffer->used - info->indirectStart + \ 701 __count * (int)sizeof(uint32_t), \ 702 info->indirectBuffer->total - info->indirectStart ); \ 703 } \ 704 info->indirectBuffer->used += __count * (int)sizeof(uint32_t); \ 705} while (0) 706 707#define OUT_RING( x ) do { \ 708 if ( R128_VERBOSE ) { \ 709 xf86DrvMsg( pScrn->scrnIndex, X_INFO, \ 710 " OUT_RING( 0x%08x )\n", (unsigned int)(x) ); \ 711 } \ 712 MMIO_OUT32(&__head[__count++], 0, (x)); \ 713} while (0) 714 715#define OUT_RING_REG( reg, val ) \ 716do { \ 717 OUT_RING( CCE_PACKET0( reg, 0 ) ); \ 718 OUT_RING( val ); \ 719} while (0) 720 721#define FLUSH_RING() \ 722do { \ 723 if ( R128_VERBOSE ) \ 724 xf86DrvMsg( pScrn->scrnIndex, X_INFO, \ 725 "FLUSH_RING in %s\n", __FUNCTION__ ); \ 726 if ( info->indirectBuffer ) { \ 727 R128CCEFlushIndirect( pScrn, 0 ); \ 728 } \ 729} while (0) 730 731#endif 732