1d769e936Smrg#ifndef S3V_PCIIDS_H 2d769e936Smrg#define S3V_PCIIDS_H 3d769e936Smrg 4d769e936Smrg#define PCI_VENDOR_S3 0x5333 5d769e936Smrg#define PCI_CHIP_VIRGE 0x5631 6d769e936Smrg#define PCI_CHIP_TRIO 0x8811 7d769e936Smrg#define PCI_CHIP_TRIO64UVP 0x8814 8d769e936Smrg#define PCI_CHIP_VIRGE_VX 0x883D 9d769e936Smrg#define PCI_CHIP_TRIO64V2_DXGX 0x8901 10d769e936Smrg#define PCI_CHIP_Trio3D 0x8904 11d769e936Smrg#define PCI_CHIP_VIRGE_DXGX 0x8A01 12d769e936Smrg#define PCI_CHIP_VIRGE_GX2 0x8A10 13d769e936Smrg#define PCI_CHIP_Trio3D_2X 0x8A13 14d769e936Smrg#define PCI_CHIP_VIRGE_MX 0x8C01 15d769e936Smrg#define PCI_CHIP_VIRGE_MXPLUS 0x8C02 16d769e936Smrg#define PCI_CHIP_VIRGE_MXP 0x8C03 17d769e936Smrg 18d769e936Smrg#endif /* S3V_PCIIDS_H */ 19