smi.h revision eee1ded1
109885543Smrg/* Header: //Mercury/Projects/archives/XFree86/4.0/smi.h-arc 1.51 29 Nov 2000 17:45:16 Frido $ */ 209885543Smrg 309885543Smrg/* 409885543SmrgCopyright (C) 1994-1999 The XFree86 Project, Inc. All Rights Reserved. 509885543SmrgCopyright (C) 2000 Silicon Motion, Inc. All Rights Reserved. 609885543Smrg 709885543SmrgPermission is hereby granted, free of charge, to any person obtaining a copy of 809885543Smrgthis software and associated documentation files (the "Software"), to deal in 909885543Smrgthe Software without restriction, including without limitation the rights to 1009885543Smrguse, copy, modify, merge, publish, distribute, sublicense, and/or sell copies 1109885543Smrgof the Software, and to permit persons to whom the Software is furnished to do 1209885543Smrgso, subject to the following conditions: 1309885543Smrg 1409885543SmrgThe above copyright notice and this permission notice shall be included in all 1509885543Smrgcopies or substantial portions of the Software. 1609885543Smrg 1709885543SmrgTHE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1809885543SmrgIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FIT- 1909885543SmrgNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 2009885543SmrgXFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 2109885543SmrgAN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 2209885543SmrgWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 2309885543Smrg 2409885543SmrgExcept as contained in this notice, the names of the XFree86 Project and 2509885543SmrgSilicon Motion shall not be used in advertising or otherwise to promote the 2609885543Smrgsale, use or other dealings in this Software without prior written 2709885543Smrgauthorization from the XFree86 Project and Silicon Motion. 2809885543Smrg*/ 2909885543Smrg 3009885543Smrg#ifndef _SMI_H 3109885543Smrg#define _SMI_H 3209885543Smrg 337104f784Smrg#include "smi_pcirename.h" 347104f784Smrg 3509885543Smrg#include <string.h> 3609885543Smrg#include <stdio.h> 37eee1ded1Smrg#include <X11/Xarch.h> 3809885543Smrg 3909885543Smrg#include "xf86.h" 4009885543Smrg#include "xf86_OSproc.h" 4109885543Smrg#include "xf86Pci.h" 4209885543Smrg#include "xf86Cursor.h" 4309885543Smrg#include "vgaHW.h" 4409885543Smrg 4509885543Smrg#include "compiler.h" 4609885543Smrg 4709885543Smrg#include "mipointer.h" 4809885543Smrg#include "micmap.h" 4909885543Smrg 5009885543Smrg#include "fb.h" 5109885543Smrg 525788ca14Smrg#ifdef HAVE_XAA_H 5309885543Smrg#include "xaa.h" 545788ca14Smrg#endif 555788ca14Smrg#include "xf86fbman.h" 5609885543Smrg#include "exa.h" 5709885543Smrg#include "xf86cmap.h" 5809885543Smrg#include "xf86i2c.h" 5909885543Smrg 6009885543Smrg#include "xf86int10.h" 6109885543Smrg#include "vbe.h" 6209885543Smrg 6309885543Smrg#include "xf86xv.h" 6409885543Smrg#include <X11/extensions/Xv.h> 6509885543Smrg 665788ca14Smrg#include "compat-api.h" 6709885543Smrg/******************************************************************************/ 6809885543Smrg/* D E F I N I T I O N S */ 6909885543Smrg/******************************************************************************/ 7009885543Smrg 7100d06012Smacallan#ifdef __NetBSD__ 7200d06012Smacallan#define __BYTE_ORDER BYTE_ORDER 7300d06012Smacallan#define __LITTLE_ENDIAN LITTLE_ENDIAN 7400d06012Smacallan#define __BIG_ENDIAN BIG_ENDIAN 7500d06012Smacallan#endif 7600d06012Smacallan 77621ff18cSmrg#define PCI_VENDOR_SMI 0x126F 78621ff18cSmrg#define PCI_CHIP_SMI910 0x0910 79621ff18cSmrg#define PCI_CHIP_SMI810 0x0810 80621ff18cSmrg#define PCI_CHIP_SMI820 0x0820 81621ff18cSmrg#define PCI_CHIP_SMI710 0x0710 82621ff18cSmrg#define PCI_CHIP_SMI712 0x0712 83621ff18cSmrg#define PCI_CHIP_SMI720 0x0720 84621ff18cSmrg#define PCI_CHIP_SMI731 0x0730 85621ff18cSmrg 8609885543Smrg#ifndef SMI_DEBUG 877104f784Smrg#define SMI_DEBUG 0 8809885543Smrg#endif 8909885543Smrg 9009885543Smrg#define SMI_USE_IMAGE_WRITES 0 9109885543Smrg#define SMI_USE_VIDEO 1 92eb3dced6Smacallan#define SMI_USE_CAPTURE 0 937104f784Smrg#define SMI501_CLI_DEBUG 0 947104f784Smrg 957104f784Smrg/* 967104f784Smrg * Leaving attempt implementation of an argb cursor using alpha plane 977104f784Smrg * for the smi 501/502 under this ifdef for now. Maybe it will be fixed 987104f784Smrg * in a subsequent hardware revision. 997104f784Smrg * The problem is that the alpha plane will only work (that is, become 1007104f784Smrg * visible) if alpha_plane_tl is set to top:=0 and left:=0. 1017104f784Smrg * Also, if alpha_plane_br does not match panel dimensions, the alpha 1027104f784Smrg * plane will be displayed tilled in the "first" row, with corruption on 1037104f784Smrg * on all odd columns. 1047104f784Smrg * Since setting the alpha fb_address works, to implement an argb cursor 1057104f784Smrg * using the alpha plane, with the current hardware bugs, it would be 1067104f784Smrg * required to: 1077104f784Smrg * o allocate an offscreen area of pSmi->lcdWidth * pSmi->lcdHeight * 2 1087104f784Smrg * o set statically tl/tr to 0,0,pSmi->lcdWidth-1,pSmi->lcdHeight-1 1097104f784Smrg * o use alpha format 3 (argb 4:4:4:4), or alternatively format 1 1107104f784Smrg * (rgb 5:6:5), and in the last case, a global 50% alpha is the 1117104f784Smrg * best bet, and for the argb cursors being used at the time of this 1127104f784Smrg * writing, they look correct, while 100% opaque looks wrong. 1137104f784Smrg * o when positioning the pointer, first erase it from the offscreen 1147104f784Smrg * area, then repaint it at the proper offset in the alpha offscreen 1157104f784Smrg * area. 1167104f784Smrg * .... argb software cursor works way better 1177104f784Smrg * (There are some other alternatives, like using 8 bits indexed mode, 1187104f784Smrg * but when using a global alpha value, instead of per pixel, most argb 1197104f784Smrg * cursors will not look correctly, regardless of the alpha value, that 1207104f784Smrg * should be from 50 to 100% transparency). 1217104f784Smrg * But still there would be the problem of memory requiring a 128 bit 1227104f784Smrg * alignment, what would require either moving the image in the memory, 1237104f784Smrg * and/or some trick with the vsync pixel panning. 1247104f784Smrg * 1257104f784Smrg * Until the alpha layer is corrected in some newer revision (or removed?), 1267104f784Smrg * it could be used as something like an alternate crt, that happens to be 1277104f784Smrg * on top of the panel (and has 16 transparency levels). 1287104f784Smrg */ 1297104f784Smrg#define SMI_CURSOR_ALPHA_PLANE 0 13009885543Smrg 13109885543Smrg/******************************************************************************/ 13209885543Smrg/* S T R U C T U R E S */ 13309885543Smrg/******************************************************************************/ 13409885543Smrg 13509885543Smrg/* Driver data structure; this should contain all needed info for a mode */ 13609885543Smrgtypedef struct 13709885543Smrg{ 1387104f784Smrg CARD16 mode; 1397104f784Smrg 1407104f784Smrg CARD8 SR17, SR18; 1417104f784Smrg CARD8 SR20, SR21, SR22, SR23, SR24; 1427104f784Smrg CARD8 SR30, SR31, SR32, SR34; 1437104f784Smrg CARD8 SR40, SR41, SR42, SR43, SR44, SR45, SR48, SR49, SR4A, SR4B, SR4C; 1447104f784Smrg CARD8 SR50, SR51, SR52, SR53, SR54, SR55, SR56, SR57, SR5A; 1457104f784Smrg CARD8 SR66, SR68, SR69, SR6A, SR6B, SR6C, SR6D, SR6E, SR6F; 1467104f784Smrg CARD8 SR81, SRA0; 1477104f784Smrg 1487104f784Smrg CARD8 CR30, CR33, CR33_2, CR3A; 1497104f784Smrg CARD8 CR40[14], CR40_2[14]; 1507104f784Smrg CARD8 CR90[15], CR9F, CR9F_2; 1517104f784Smrg CARD8 CRA0[14]; 1527104f784Smrg 15309885543Smrg CARD8 smiDACMask, smiDacRegs[256][3]; 15409885543Smrg CARD8 smiFont[8192]; 1557104f784Smrg 15609885543Smrg CARD32 DPR10, DPR1C, DPR20, DPR24, DPR28, DPR2C, DPR30, DPR3C, DPR40, 15709885543Smrg DPR44; 15809885543Smrg CARD32 VPR00, VPR0C, VPR10; 15909885543Smrg CARD32 CPR00; 16009885543Smrg CARD32 FPR00_, FPR0C_, FPR10_; 16109885543Smrg} SMIRegRec, *SMIRegPtr; 16209885543Smrg 16309885543Smrg/* Global PDEV structure. */ 16409885543Smrgtypedef struct 16509885543Smrg{ 1667104f784Smrg int Bpp; /* Bytes per pixel */ 1677104f784Smrg int MCLK; /* Memory Clock */ 1687104f784Smrg int MXCLK; /* MSOC Clock for local sdram */ 169e4f6584cSmrg ClockRange clockRange; /* Allowed pixel clock range */ 1707104f784Smrg CloseScreenProcPtr CloseScreen; /* Pointer used to save wrapped 1717104f784Smrg CloseScreen function */ 1727104f784Smrg 1737104f784Smrg I2CBusPtr I2C; /* Pointer into I2C module */ 1747104f784Smrg xf86Int10InfoPtr pInt10; /* Pointer to INT10 module */ 1757104f784Smrg vbeInfoPtr pVbe; /* Pointer to VBE module */ 1767104f784Smrg 1777104f784Smrg pciVideoPtr PciInfo; /* PCI info vars */ 1787104f784Smrg#ifndef XSERVER_LIBPCIACCESS 1797104f784Smrg PCITAG PciTag; 1807104f784Smrg#endif 1817104f784Smrg int Chipset; /* Chip info, set using PCI 1827104f784Smrg above */ 1837104f784Smrg int ChipRev; 1847104f784Smrg 1857104f784Smrg OptionInfoPtr Options; 1867104f784Smrg Bool Dualhead; 1877104f784Smrg 1887104f784Smrg /* Don't attempt to program a video mode. Use kernel framebuffer 1897104f784Smrg * mode instead. */ 1907104f784Smrg Bool UseFBDev; 1917104f784Smrg 1927104f784Smrg /* CSC video uses color space conversion to render video directly to 1937104f784Smrg * the framebuffer, without using an overlay. */ 1947104f784Smrg Bool CSCVideo; 1957104f784Smrg 1967104f784Smrg Bool PCIBurst; /* Enable PCI burst mode for 1977104f784Smrg reads? */ 1987104f784Smrg Bool PCIRetry; /* Enable PCI retries */ 1997104f784Smrg Bool HwCursor; /* hardware cursor enabled */ 2007104f784Smrg 2017104f784Smrg CARD8 DACmask; 2027104f784Smrg int vgaCRIndex, vgaCRReg; 2037104f784Smrg Bool PrimaryVidMapped; /* Flag indicating if 2047104f784Smrg vgaHWMapMem was used 2057104f784Smrg successfully for 2067104f784Smrg this screen */ 2077104f784Smrg Bool ModeStructInit; /* Flag indicating ModeReg has 2087104f784Smrg been duped from console 2097104f784Smrg state */ 2107104f784Smrg 2117104f784Smrg /* Hardware state */ 2127104f784Smrg void (*Save)(ScrnInfoPtr pScrn); /* Function used to save the 2137104f784Smrg current register state */ 21409885543Smrg CARD8 SR18Value; /* PDR#521: original SR18 21509885543Smrg value */ 21609885543Smrg CARD8 SR21Value; /* PDR#521: original SR21 21709885543Smrg value */ 2187104f784Smrg void *save; /* console saved mode 21909885543Smrg registers */ 2207104f784Smrg void *mode; /* XServer video state mode 22109885543Smrg registers */ 22209885543Smrg 2237104f784Smrg /* Memory layout */ 22409885543Smrg int videoRAMBytes; /* In units as noted, set in 22509885543Smrg PreInit */ 22609885543Smrg int videoRAMKBytes; /* In units as noted, set in 22709885543Smrg PreInit */ 22809885543Smrg unsigned char * MapBase; /* Base of mapped memory */ 22909885543Smrg int MapSize; /* Size of mapped memory */ 23009885543Smrg CARD8 * DPRBase; /* Base of DPR registers */ 23109885543Smrg CARD8 * VPRBase; /* Base of VPR registers */ 23209885543Smrg CARD8 * CPRBase; /* Base of CPR registers */ 23309885543Smrg CARD8 * FPRBase; /* Base of FPR registers - for 0730 chipset */ 2347104f784Smrg CARD8 * DCRBase; /* Base of DCR registers - for 0501 chipset */ 2357104f784Smrg CARD8 * SCRBase; /* Base of SCR registers - for 0501 chipset */ 23609885543Smrg CARD8 * DataPortBase; /* Base of data port */ 23709885543Smrg int DataPortSize; /* Size of data port */ 23809885543Smrg CARD8 * IOBase; /* Base of MMIO VGA ports */ 239621ff18cSmrg unsigned int PIOBase; /* Base of I/O ports */ 24009885543Smrg unsigned char * FBBase; /* Base of FB */ 2417104f784Smrg CARD32 fbMapOffset; /* offset for fb mapping */ 24209885543Smrg CARD32 FBOffset; /* Current visual FB starting 24309885543Smrg location */ 24409885543Smrg CARD32 FBCursorOffset; /* Cursor storage location */ 24509885543Smrg CARD32 FBReserved; /* Reserved memory in frame 24609885543Smrg buffer */ 2477104f784Smrg 2487104f784Smrg /* accel additions */ 2497104f784Smrg CARD32 AccelCmd; /* Value for DPR0C */ 2507104f784Smrg Bool NoAccel; /* Disable Acceleration */ 2517104f784Smrg CARD32 ScissorsLeft; /* Left/top of current 2527104f784Smrg scissors */ 2537104f784Smrg CARD32 ScissorsRight; /* Right/bottom of current 2547104f784Smrg scissors */ 2557104f784Smrg Bool ClipTurnedOn; /* Clipping was turned on by 2567104f784Smrg the previous command */ 25709885543Smrg int GEResetCnt; /* Limit the number of errors 25809885543Smrg printed using a counter */ 25909885543Smrg 26009885543Smrg Bool useBIOS; /* Use BIOS for mode sets */ 2615788ca14Smrg#ifdef HAVE_XAA_H 26209885543Smrg XAAInfoRecPtr XAAInfoRec; /* XAA info Rec */ 2635788ca14Smrg#endif 26409885543Smrg 26509885543Smrg /* EXA */ 26609885543Smrg ExaDriverPtr EXADriverPtr; 2677104f784Smrg Bool useEXA; /* enable exa acceleration */ 2687104f784Smrg ExaOffscreenArea* fbArea; /* EXA offscreen area used 2697104f784Smrg as framebuffer */ 2707104f784Smrg PictTransformPtr renderTransform; 27109885543Smrg 27209885543Smrg /* DPMS */ 27309885543Smrg int CurrentDPMS; /* Current DPMS state */ 27409885543Smrg 27509885543Smrg /* Panel information */ 27609885543Smrg Bool lcd; /* LCD active, 1=DSTN, 2=TFT */ 27709885543Smrg int lcdWidth; /* LCD width */ 27809885543Smrg int lcdHeight; /* LCD height */ 27909885543Smrg 2807104f784Smrg /* XvExtension */ 28109885543Smrg int videoKey; /* Video chroma key */ 28209885543Smrg Bool ByteSwap; /* Byte swap for ZV port */ 28309885543Smrg Bool interlaced; /* True: Interlaced Video */ 28409885543Smrg XF86VideoAdaptorPtr ptrAdaptor; /* Pointer to VideoAdapter 28509885543Smrg structure */ 286621ff18cSmrg void (*BlockHandler)(BLOCKHANDLER_ARGS_DECL); 2877104f784Smrg#if SMI501_CLI_DEBUG 2887104f784Smrg /* SMI 501/502 Command List Interpreter */ 2897104f784Smrg Bool batch_active; 2907104f784Smrg int64_t *batch_handle; /* Virtual address */ 2917104f784Smrg int batch_offset; /* Physical smi 501 address */ 2927104f784Smrg int batch_length; /* Length in 8 byte units */ 2937104f784Smrg int batch_finish; /* Last finish command offset */ 2947104f784Smrg int batch_index; 2957104f784Smrg#endif 29609885543Smrg} SMIRec, *SMIPtr; 29709885543Smrg 29809885543Smrg#define SMIPTR(p) ((SMIPtr)((p)->driverPrivate)) 29909885543Smrg 30009885543Smrg/******************************************************************************/ 30109885543Smrg/* M A C R O S */ 30209885543Smrg/******************************************************************************/ 30309885543Smrg 30409885543Smrg#if SMI_DEBUG 3057104f784Smrgextern int smi_indent; 3067104f784Smrg# define VERBLEV 1 3077104f784Smrg# define ENTER() xf86ErrorFVerb(VERBLEV, "%*c %s\n",\ 3087104f784Smrg smi_indent++, '>', __FUNCTION__) 3097104f784Smrg# define LEAVE(...) \ 3107104f784Smrg do { \ 3117104f784Smrg xf86ErrorFVerb(VERBLEV, "%*c %s\n", \ 3127104f784Smrg --smi_indent, '<', __FUNCTION__); \ 3137104f784Smrg return __VA_ARGS__; \ 3147104f784Smrg } while (0) 3157104f784Smrg# define DEBUG(...) xf86ErrorFVerb(VERBLEV, __VA_ARGS__) 31609885543Smrg#else 3177104f784Smrg# define VERBLEV 4 3187104f784Smrg# define ENTER() /**/ 3197104f784Smrg# define LEAVE(...) return __VA_ARGS__ 3207104f784Smrg# define DEBUG(...) /**/ 32109885543Smrg#endif 32209885543Smrg 32309885543Smrg/* Some Silicon Motion structs & registers */ 32409885543Smrg#include "regsmi.h" 32509885543Smrg 32609885543Smrg#if !defined (MetroLink) && !defined (VertDebug) 32709885543Smrg#define VerticalRetraceWait() \ 32809885543Smrgdo \ 32909885543Smrg{ \ 33009885543Smrg if (VGAIN8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x17) & 0x80) \ 33109885543Smrg { \ 33209885543Smrg while ((VGAIN8(pSmi, vgaIOBase + 0x0A) & 0x08) == 0x00); \ 33309885543Smrg while ((VGAIN8(pSmi, vgaIOBase + 0x0A) & 0x08) == 0x08); \ 33409885543Smrg while ((VGAIN8(pSmi, vgaIOBase + 0x0A) & 0x08) == 0x00); \ 33509885543Smrg } \ 33609885543Smrg} while (0) 33709885543Smrg#else 33809885543Smrg#define SPIN_LIMIT 1000000 33909885543Smrg#define VerticalRetraceWait() \ 34009885543Smrgdo \ 34109885543Smrg{ \ 34209885543Smrg if (VGAIN8_INDEX(pSmi, vgaCRIndex, vgaCRData, 0x17) & 0x80) \ 34309885543Smrg { \ 34409885543Smrg volatile unsigned long _spin_me; \ 34509885543Smrg for (_spin_me = SPIN_LIMIT; \ 34609885543Smrg ((VGAIN8(pSmi, vgaIOBase + 0x0A) & 0x08) == 0x00) && \ 34709885543Smrg _spin_me; \ 34809885543Smrg _spin_me--); \ 34909885543Smrg if (!_spin_me) \ 35009885543Smrg ErrorF("smi: warning: VerticalRetraceWait timed out.\n"); \ 35109885543Smrg for (_spin_me = SPIN_LIMIT; \ 35209885543Smrg ((VGAIN8(pSmi, vgaIOBase + 0x0A) & 0x08) == 0x08) && \ 35309885543Smrg _spin_me; \ 35409885543Smrg _spin_me--); \ 35509885543Smrg if (!_spin_me) \ 35609885543Smrg ErrorF("smi: warning: VerticalRetraceWait timed out.\n"); \ 35709885543Smrg for (_spin_me = SPIN_LIMIT; \ 35809885543Smrg ((VGAIN8(pSmi, vgaIOBase + 0x0A) & 0x08) == 0x00) && \ 35909885543Smrg _spin_me; \ 36009885543Smrg _spin_me--); \ 36109885543Smrg if (!_spin_me) \ 36209885543Smrg ErrorF("smi: warning: VerticalRetraceWait timed out.\n"); \ 36309885543Smrg } \ 36409885543Smrg} while (0) 36509885543Smrg#endif 36609885543Smrg 36709885543Smrg/******************************************************************************/ 36809885543Smrg/* F U N C T I O N P R O T O T Y P E S */ 36909885543Smrg/******************************************************************************/ 37009885543Smrg 37109885543Smrg/* smi_dac.c */ 37209885543Smrgvoid SMI_CommonCalcClock(int scrnIndex, long freq, int min_m, int min_n1, 37309885543Smrg int max_n1, int min_n2, int max_n2, long freq_min, 37409885543Smrg long freq_max, unsigned char * mdiv, 37509885543Smrg unsigned char * ndiv); 37609885543Smrg 37709885543Smrg/* smi_i2c */ 37809885543SmrgBool SMI_I2CInit(ScrnInfoPtr pScrn); 37909885543Smrg 38009885543Smrg/* smi_accel.c */ 38109885543Smrgvoid SMI_AccelSync(ScrnInfoPtr pScrn); 382621ff18cSmrgvoid SMI_GEReset(ScrnInfoPtr pScrn, int from_timeout, int line, const char *file); 38309885543Smrgvoid SMI_EngineReset(ScrnInfoPtr); 38409885543Smrgvoid SMI_SetClippingRectangle(ScrnInfoPtr, int, int, int, int); 38509885543Smrgvoid SMI_DisableClipping(ScrnInfoPtr); 3867104f784SmrgCARD32 SMI_DEDataFormat(int bpp); 3877104f784Smrg 3887104f784Smrg/* smi_xaa.c */ 3897104f784SmrgBool SMI_XAAInit(ScreenPtr pScrn); 3907104f784Smrg 3917104f784Smrg/* smi_exa.c */ 3927104f784SmrgBool SMI_EXAInit(ScreenPtr pScrn); 39309885543Smrg 39409885543Smrg/* smi_hwcurs.c */ 39509885543SmrgBool SMI_HWCursorInit(ScreenPtr pScrn); 39609885543Smrg 39709885543Smrg/* smi_driver.c */ 3987104f784SmrgBool SMI_MapMem(ScrnInfoPtr pScrn); 3997104f784Smrgvoid SMI_UnmapMem(ScrnInfoPtr pScrn); 400621ff18cSmrgvoid SMI_AdjustFrame(ADJUST_FRAME_ARGS_DECL); 401621ff18cSmrgBool SMI_SwitchMode(SWITCH_MODE_ARGS_DECL); 4027104f784Smrgvoid SMI_LoadPalette(ScrnInfoPtr pScrn, int numColors, int *indicies, 4037104f784Smrg LOCO *colors, VisualPtr pVisual); 4047104f784Smrgxf86MonPtr SMI_ddc1(ScrnInfoPtr pScrn); 4057104f784Smrgvoid SMI_PrintRegs(ScrnInfoPtr pScrn); 40609885543Smrg 40709885543Smrg/* smi_video.c */ 40809885543Smrgvoid SMI_InitVideo(ScreenPtr pScreen); 4097104f784SmrgCARD32 SMI_AllocateMemory(ScrnInfoPtr pScrn, void **mem_struct, int size); 4107104f784Smrgvoid SMI_FreeMemory(ScrnInfoPtr pScrn, void *mem_struct); 4117104f784Smrg 41209885543Smrg 41309885543Smrg#endif /*_SMI_H*/ 414