172b676d7Smrg/*
272b676d7Smrg * Global definitions for init.c and init301.c
372b676d7Smrg *
472b676d7Smrg * Copyright (C) 2001-2005 by Thomas Winischhofer, Vienna, Austria
572b676d7Smrg *
672b676d7Smrg * If distributed as part of the Linux kernel, the following license terms
772b676d7Smrg * apply:
872b676d7Smrg *
972b676d7Smrg * * This program is free software; you can redistribute it and/or modify
1072b676d7Smrg * * it under the terms of the GNU General Public License as published by
1172b676d7Smrg * * the Free Software Foundation; either version 2 of the named License,
1272b676d7Smrg * * or any later version.
1372b676d7Smrg * *
1472b676d7Smrg * * This program is distributed in the hope that it will be useful,
1572b676d7Smrg * * but WITHOUT ANY WARRANTY; without even the implied warranty of
1672b676d7Smrg * * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1772b676d7Smrg * * GNU General Public License for more details.
1872b676d7Smrg * *
1972b676d7Smrg * * You should have received a copy of the GNU General Public License
2072b676d7Smrg * * along with this program; if not, write to the Free Software
2172b676d7Smrg * * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
2272b676d7Smrg *
2372b676d7Smrg * Otherwise, the following license terms apply:
2472b676d7Smrg *
2572b676d7Smrg * * Redistribution and use in source and binary forms, with or without
2672b676d7Smrg * * modification, are permitted provided that the following conditions
2772b676d7Smrg * * are met:
2872b676d7Smrg * * 1) Redistributions of source code must retain the above copyright
2972b676d7Smrg * *    notice, this list of conditions and the following disclaimer.
3072b676d7Smrg * * 2) Redistributions in binary form must reproduce the above copyright
3172b676d7Smrg * *    notice, this list of conditions and the following disclaimer in the
3272b676d7Smrg * *    documentation and/or other materials provided with the distribution.
3372b676d7Smrg * * 3) The name of the author may not be used to endorse or promote products
3472b676d7Smrg * *    derived from this software without specific prior written permission.
3572b676d7Smrg * *
3672b676d7Smrg * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
3772b676d7Smrg * * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
3872b676d7Smrg * * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
3972b676d7Smrg * * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4072b676d7Smrg * * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4172b676d7Smrg * * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
4272b676d7Smrg * * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
4372b676d7Smrg * * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4472b676d7Smrg * * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4572b676d7Smrg * * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4672b676d7Smrg *
4772b676d7Smrg * Author: 	Thomas Winischhofer <thomas@winischhofer.net>
4872b676d7Smrg *
4972b676d7Smrg */
5072b676d7Smrg
5172b676d7Smrg#ifndef _INITDEF_
5272b676d7Smrg#define _INITDEF_
5372b676d7Smrg
5472b676d7Smrg#define IS_SIS330		(SiS_Pr->ChipType == SIS_330)
5572b676d7Smrg#define IS_SIS550		(SiS_Pr->ChipType == SIS_550)
5672b676d7Smrg#define IS_SIS650		(SiS_Pr->ChipType == SIS_650)  /* All versions, incl 651, M65x */
5772b676d7Smrg#define IS_SIS740		(SiS_Pr->ChipType == SIS_740)
5872b676d7Smrg#define IS_SIS651	        (SiS_Pr->SiS_SysFlags & (SF_Is651 | SF_Is652))
5972b676d7Smrg#define IS_SISM650	        (SiS_Pr->SiS_SysFlags & (SF_IsM650 | SF_IsM652 | SF_IsM653))
6072b676d7Smrg#define IS_SIS65x               (IS_SIS651 || IS_SISM650)       /* Only special versions of 65x */
6172b676d7Smrg#define IS_SIS661		(SiS_Pr->ChipType == SIS_661)
6272b676d7Smrg#define IS_SIS741		(SiS_Pr->ChipType == SIS_741)
6372b676d7Smrg#define IS_SIS660		(SiS_Pr->ChipType == SIS_660)
6472b676d7Smrg#define IS_SIS760		(SiS_Pr->ChipType == SIS_760)
6572b676d7Smrg#define IS_SIS761		(SiS_Pr->ChipType == SIS_761)
6672b676d7Smrg#define IS_SIS661741660760	(IS_SIS661 || IS_SIS741 || IS_SIS660 || IS_SIS760 || IS_SIS761)
6772b676d7Smrg#define IS_SIS650740            ((SiS_Pr->ChipType >= SIS_650) && (SiS_Pr->ChipType < SIS_330))
6872b676d7Smrg#define IS_SIS550650740         (IS_SIS550 || IS_SIS650740)
6972b676d7Smrg#define IS_SIS650740660         (IS_SIS650 || IS_SIS740 || IS_SIS661741660760)
7072b676d7Smrg#define IS_SIS550650740660      (IS_SIS550 || IS_SIS650740660)
7172b676d7Smrg
7272b676d7Smrg#define SISGETROMW(x)		(ROMAddr[(x)] | (ROMAddr[(x)+1] << 8))
7372b676d7Smrg
7472b676d7Smrg/* SiS_VBType */
7572b676d7Smrg#define VB_SIS301		0x0001
7672b676d7Smrg#define VB_SIS301B		0x0002
7772b676d7Smrg#define VB_SIS302B		0x0004
7872b676d7Smrg#define VB_SIS301LV		0x0008
7972b676d7Smrg#define VB_SIS302LV		0x0010
8072b676d7Smrg#define VB_SIS302ELV		0x0020
8172b676d7Smrg#define VB_SIS301C		0x0040
8272b676d7Smrg#define VB_SIS307T		0x0080
8372b676d7Smrg#define VB_SIS307LV		0x0100
8472b676d7Smrg#define VB_UMC			0x4000
8572b676d7Smrg#define VB_NoLCD        	0x8000
8672b676d7Smrg#define VB_SIS30xB		(VB_SIS301B | VB_SIS301C | VB_SIS302B | VB_SIS307T)
8772b676d7Smrg#define VB_SIS30xC		(VB_SIS301C | VB_SIS307T)
8872b676d7Smrg#define VB_SISTMDS		(VB_SIS301 | VB_SIS301B | VB_SIS301C | VB_SIS302B | VB_SIS307T)
8972b676d7Smrg#define VB_SISLVDS		(VB_SIS301LV | VB_SIS302LV | VB_SIS302ELV | VB_SIS307LV)
9072b676d7Smrg#define VB_SIS30xBLV		(VB_SIS30xB | VB_SISLVDS)
9172b676d7Smrg#define VB_SIS30xCLV		(VB_SIS30xC | VB_SIS302ELV | VB_SIS307LV)
9272b676d7Smrg#define VB_SISVB		(VB_SIS301 | VB_SIS30xBLV)
9372b676d7Smrg#define VB_SISLCDA		(VB_SIS302B | VB_SIS301C  | VB_SIS307T  | VB_SISLVDS)
9472b676d7Smrg#define VB_SISTMDSLCDA		(VB_SIS301C | VB_SIS307T)
9572b676d7Smrg#define VB_SISPART4SCALER	(VB_SIS301C | VB_SIS307T | VB_SIS302ELV | VB_SIS307LV)
9672b676d7Smrg#define VB_SISHIVISION		(VB_SIS301 | VB_SIS301B | VB_SIS302B)
9772b676d7Smrg#define VB_SISYPBPR		(VB_SIS301C | VB_SIS307T  | VB_SIS301LV | VB_SIS302LV | VB_SIS302ELV | VB_SIS307LV)
9872b676d7Smrg#define VB_SISTAP4SCALER	(VB_SIS301C | VB_SIS307T | VB_SIS302ELV | VB_SIS307LV)
9972b676d7Smrg#define VB_SISPART4OVERFLOW	(VB_SIS301C | VB_SIS307T | VB_SIS302LV | VB_SIS302ELV | VB_SIS307LV)
10072b676d7Smrg#define VB_SISPWD		(VB_SIS301C | VB_SIS307T | VB_SISLVDS)
10172b676d7Smrg#define VB_SISEMI		(VB_SIS302LV | VB_SIS302ELV | VB_SIS307LV)
10272b676d7Smrg#define VB_SISPOWER		(VB_SIS301C | VB_SIS307T | VB_SIS302LV | VB_SIS302ELV | VB_SIS307LV)
10372b676d7Smrg#define VB_SISDUALLINK		(VB_SIS302LV | VB_SIS302ELV | VB_SIS307T | VB_SIS307LV)
10472b676d7Smrg#define VB_SISVGA2		VB_SISTMDS
10572b676d7Smrg#define VB_SISRAMDAC202		(VB_SIS301C | VB_SIS307T)
10672b676d7Smrg
10772b676d7Smrg/* VBInfo */
10872b676d7Smrg#define SetSimuScanMode         0x0001   /* CR 30 */
10972b676d7Smrg#define SwitchCRT2              0x0002
11072b676d7Smrg#define SetCRT2ToAVIDEO         0x0004
11172b676d7Smrg#define SetCRT2ToSVIDEO         0x0008
11272b676d7Smrg#define SetCRT2ToSCART          0x0010
11372b676d7Smrg#define SetCRT2ToLCD            0x0020
11472b676d7Smrg#define SetCRT2ToRAMDAC         0x0040
11572b676d7Smrg#define SetCRT2ToHiVision       0x0080   		/* for SiS bridge */
11672b676d7Smrg#define SetCRT2ToCHYPbPr       	SetCRT2ToHiVision	/* for Chrontel   */
11772b676d7Smrg#define SetNTSCTV               0x0000   /* CR 31 */
11872b676d7Smrg#define SetPALTV                0x0100   		/* Deprecated here, now in TVMode */
11972b676d7Smrg#define SetInSlaveMode          0x0200
12072b676d7Smrg#define SetNotSimuMode          0x0400
12172b676d7Smrg#define SetNotSimuTVMode        SetNotSimuMode
12272b676d7Smrg#define SetDispDevSwitch        0x0800
12372b676d7Smrg#define SetCRT2ToYPbPr525750    0x0800
12472b676d7Smrg#define LoadDACFlag             0x1000
12572b676d7Smrg#define DisableCRT2Display      0x2000
12672b676d7Smrg#define DriverMode              0x4000
12772b676d7Smrg#define HotKeySwitch            0x8000
12872b676d7Smrg#define SetCRT2ToLCDA           0x8000
12972b676d7Smrg
13072b676d7Smrg/* v-- Needs change in sis_vga.c if changed (GPIO) --v */
13172b676d7Smrg#define SetCRT2ToTV             (SetCRT2ToYPbPr525750|SetCRT2ToHiVision|SetCRT2ToSCART|SetCRT2ToSVIDEO|SetCRT2ToAVIDEO)
13272b676d7Smrg#define SetCRT2ToTVNoYPbPrHiVision (SetCRT2ToSCART | SetCRT2ToSVIDEO | SetCRT2ToAVIDEO)
13372b676d7Smrg#define SetCRT2ToTVNoHiVision  	(SetCRT2ToYPbPr525750 | SetCRT2ToSCART | SetCRT2ToSVIDEO | SetCRT2ToAVIDEO)
13472b676d7Smrg
13572b676d7Smrg/* SiS_ModeType */
13672b676d7Smrg#define ModeText                0x00
13772b676d7Smrg#define ModeCGA                 0x01
13872b676d7Smrg#define ModeEGA                 0x02
13972b676d7Smrg#define ModeVGA                 0x03
14072b676d7Smrg#define Mode15Bpp               0x04
14172b676d7Smrg#define Mode16Bpp               0x05
14272b676d7Smrg#define Mode24Bpp               0x06
14372b676d7Smrg#define Mode32Bpp               0x07
14472b676d7Smrg
14572b676d7Smrg#define ModeTypeMask            0x07
14672b676d7Smrg#define IsTextMode              0x07
14772b676d7Smrg
14872b676d7Smrg#define DACInfoFlag             0x0018
14972b676d7Smrg#define MemoryInfoFlag          0x01E0
15072b676d7Smrg#define MemorySizeShift         5
15172b676d7Smrg
15272b676d7Smrg/* modeflag */
15372b676d7Smrg#define Charx8Dot               0x0200
15472b676d7Smrg#define LineCompareOff          0x0400
15572b676d7Smrg#define CRT2Mode                0x0800
15672b676d7Smrg#define HalfDCLK                0x1000
15772b676d7Smrg#define NoSupportSimuTV         0x2000
15872b676d7Smrg#define NoSupportLCDScale	0x4000 /* SiS bridge: No scaling possible (no matter what panel) */
15972b676d7Smrg#define DoubleScanMode          0x8000
16072b676d7Smrg
16172b676d7Smrg/* Infoflag */
16272b676d7Smrg#define SupportTV               0x0008
16372b676d7Smrg#define SupportTV1024           0x0800
16472b676d7Smrg#define SupportCHTV 		0x0800
16572b676d7Smrg#define Support64048060Hz       0x0800  /* Special for 640x480 LCD */
16672b676d7Smrg#define SupportHiVision         0x0010
16772b676d7Smrg#define SupportYPbPr750p        0x1000
16872b676d7Smrg#define SupportLCD              0x0020
16972b676d7Smrg#define SupportRAMDAC2          0x0040	/* All           (<= 100Mhz) */
17072b676d7Smrg#define SupportRAMDAC2_135      0x0100  /* All except DH (<= 135Mhz) */
17172b676d7Smrg#define SupportRAMDAC2_162      0x0200  /* B, C          (<= 162Mhz) */
17272b676d7Smrg#define SupportRAMDAC2_202      0x0400  /* C             (<= 202Mhz) */
17372b676d7Smrg#define InterlaceMode           0x0080
17472b676d7Smrg#define SyncPP                  0x0000
17572b676d7Smrg#define HaveWideTiming		0x2000	/* Have specific wide- and non-wide timing */
17672b676d7Smrg#define SyncPN                  0x4000
17772b676d7Smrg#define SyncNP                  0x8000
17872b676d7Smrg#define SyncNN                  0xc000
17972b676d7Smrg
18072b676d7Smrg/* SetFlag */
18172b676d7Smrg#define ProgrammingCRT2         0x0001
18272b676d7Smrg#define LowModeTests		0x0002
18372b676d7Smrg/* #define TVSimuMode           0x0002 - deprecated */
18472b676d7Smrg/* #define RPLLDIV2XO           0x0004 - deprecated */
18572b676d7Smrg#define LCDVESATiming           0x0008
18672b676d7Smrg#define EnableLVDSDDA           0x0010
18772b676d7Smrg#define SetDispDevSwitchFlag    0x0020
18872b676d7Smrg#define CheckWinDos             0x0040
18972b676d7Smrg#define SetDOSMode              0x0080
19072b676d7Smrg
19172b676d7Smrg/* TVMode flag */
19272b676d7Smrg#define TVSetPAL		0x00001
19372b676d7Smrg#define TVSetNTSCJ		0x00002
19472b676d7Smrg#define TVSetPALM		0x00004
19572b676d7Smrg#define TVSetPALN		0x00008
19672b676d7Smrg#define TVSetCHOverScan		0x00010
19772b676d7Smrg#define TVSetYPbPr525i		0x00020 /* new 0x10 */
19872b676d7Smrg#define TVSetYPbPr525p		0x00040 /* new 0x20 */
19972b676d7Smrg#define TVSetYPbPr750p		0x00080 /* new 0x40 */
20072b676d7Smrg#define TVSetHiVision		0x00100 /* new 0x80; = 1080i, software-wise identical */
20172b676d7Smrg#define TVSetTVSimuMode		0x00200 /* new 0x200, prev. 0x800 */
20272b676d7Smrg#define TVRPLLDIV2XO		0x00400 /* prev 0x1000 */
20372b676d7Smrg#define TVSetNTSC1024		0x00800 /* new 0x100, prev. 0x2000 */
20472b676d7Smrg#define TVSet525p1024		0x01000 /* TW */
20572b676d7Smrg#define TVAspect43		0x02000
20672b676d7Smrg#define TVAspect169		0x04000
20772b676d7Smrg#define TVAspect43LB		0x08000
20872b676d7Smrg#define TVSetYPbPr625i		0x10000 /* TW YPbPr 625i */
20972b676d7Smrg#define TVSetYPbPr625p		0x20000 /* TW YPbPr 625p */
21072b676d7Smrg#define TVSetHiVi960540		0x40000 /* TW */
21172b676d7Smrg
21272b676d7Smrg#define TVSetYPbPrProg		(TVSetYPbPr525p | TVSetYPbPr625p | TVSetYPbPr750p)
21372b676d7Smrg#define TVSetPALTiming		(TVSetPAL | TVSetYPbPr625i | TVSetYPbPr625p)
21472b676d7Smrg
21572b676d7Smrg/* YPbPr flag (>=315, <661; converted to TVMode) */
21672b676d7Smrg#define YPbPr525p               0x0001
21772b676d7Smrg#define YPbPr750p               0x0002
21872b676d7Smrg#define YPbPr525i               0x0004
21972b676d7Smrg#define YPbPrHiVision           0x0008
22072b676d7Smrg#define YPbPrModeMask           (YPbPr750p | YPbPr525p | YPbPr525i | YPbPrHiVision)
22172b676d7Smrg
22272b676d7Smrg/* SysFlags (to identify special versions) */
22372b676d7Smrg#define SF_Is651                0x0001
22472b676d7Smrg#define SF_IsM650               0x0002
22572b676d7Smrg#define SF_Is652		0x0004
22672b676d7Smrg#define SF_IsM652		0x0008
22772b676d7Smrg#define SF_IsM653		0x0010
22872b676d7Smrg#define SF_IsM661		0x0020
22972b676d7Smrg#define SF_IsM741		0x0040
23072b676d7Smrg#define SF_IsM760		0x0080
23172b676d7Smrg#define SF_760UMA		0x4000  /* 76x: We have UMA */
23272b676d7Smrg#define SF_760LFB		0x8000  /* 76x: We have LFB */
23372b676d7Smrg
23472b676d7Smrg/* CR32 (Newer 630, and 315 series)
23572b676d7Smrg
23672b676d7Smrg   [0]   VB connected with CVBS
23772b676d7Smrg   [1]   VB connected with SVHS
23872b676d7Smrg   [2]   VB connected with SCART
23972b676d7Smrg   [3]   VB connected with LCD
24072b676d7Smrg   [4]   VB connected with CRT2 (secondary VGA)
24172b676d7Smrg   [5]   CRT1 monitor is connected
24272b676d7Smrg   [6]   VB connected with Hi-Vision TV
24372b676d7Smrg   [7]   <= 330: VB connected with DVI combo connector
24472b676d7Smrg         >= 661: VB connected to YPbPr
24572b676d7Smrg*/
24672b676d7Smrg
24772b676d7Smrg/* CR35 (300 series only) */
24872b676d7Smrg#define TVOverScan              0x10
24972b676d7Smrg#define TVOverScanShift         4
25072b676d7Smrg
25172b676d7Smrg/* CR35 (661 series only)
25272b676d7Smrg   [0]    1 = PAL, 0 = NTSC
25372b676d7Smrg   [1]    1 = NTSC-J (if D0 = 0)
25472b676d7Smrg   [2]    1 = PALM (if D0 = 1)
25572b676d7Smrg   [3]    1 = PALN (if D0 = 1)
25672b676d7Smrg   [4]    1 = Overscan (Chrontel only)
25772b676d7Smrg   [7:5]  (only if D2 in CR38 is set)
25872b676d7Smrg	  000  525i/625i
25972b676d7Smrg	  001  525p
26072b676d7Smrg	  010  750p
26172b676d7Smrg	  011  1080i (or HiVision on 301, 301B)
26272b676d7Smrg*/
26372b676d7Smrg
26472b676d7Smrg/* CR37
26572b676d7Smrg   [0]   Set 24/18 bit (0/1) RGB to LVDS/TMDS transmitter (set by BIOS)
26672b676d7Smrg   [3:1] External chip
26772b676d7Smrg         300 series:
26872b676d7Smrg	    001   SiS301 (never seen)
26972b676d7Smrg	    010   LVDS
27072b676d7Smrg	    011   LVDS + Tumpion Zurac
27172b676d7Smrg	    100   LVDS + Chrontel 7005
27272b676d7Smrg	    110   Chrontel 7005
27372b676d7Smrg	  315/330 series
27472b676d7Smrg	    001   SiS30x (never seen)
27572b676d7Smrg	    010   LVDS
27672b676d7Smrg	    011   LVDS + Chrontel 7019
27772b676d7Smrg	  660 series [2:1] only:
27872b676d7Smrg	     reserved (chip type now in CR38)
27972b676d7Smrg	  All other combinations reserved
28072b676d7Smrg   [3]    661 only: Pass 1:1 data
28172b676d7Smrg   [4]    LVDS: 0: Panel Link expands / 1: Panel Link does not expand
28272b676d7Smrg          30x:  0: Bridge scales      / 1: Bridge does not scale = Panel scales (if possible)
28372b676d7Smrg   [5]    LCD polarity select
28472b676d7Smrg          0: VESA DMT Standard
28572b676d7Smrg	  1: EDID 2.x defined
28672b676d7Smrg   [6]    LCD horizontal polarity select
28772b676d7Smrg          0: High active
28872b676d7Smrg	  1: Low active
28972b676d7Smrg   [7]    LCD vertical polarity select
29072b676d7Smrg          0: High active
29172b676d7Smrg	  1: Low active
29272b676d7Smrg*/
29372b676d7Smrg
29472b676d7Smrg/* CR37: LCDInfo */
29572b676d7Smrg#define LCDRGB18Bit           0x0001
29672b676d7Smrg#define LCDNonExpanding       0x0010
29772b676d7Smrg#define LCDSync               0x0020
29872b676d7Smrg#define LCDPass11             0x0100   /* 0: center screen, 1: Pass 1:1 data */
29972b676d7Smrg#define LCDDualLink	      0x0200
30072b676d7Smrg
30172b676d7Smrg#define DontExpandLCD	      LCDNonExpanding
30272b676d7Smrg#define LCDNonExpandingShift       4
30372b676d7Smrg#define DontExpandLCDShift    LCDNonExpandingShift
30472b676d7Smrg#define LCDSyncBit            0x00e0
30572b676d7Smrg#define LCDSyncShift               6
30672b676d7Smrg
30772b676d7Smrg/* CR38 (315 series) */
30872b676d7Smrg#define EnableDualEdge 		0x01
30972b676d7Smrg#define SetToLCDA		0x02   /* LCD channel A (301C/302B/30x(E)LV and 650+LVDS only) */
31072b676d7Smrg#define EnableCHScart           0x04   /* Scart on Ch7019 (unofficial definition - TW) */
31172b676d7Smrg#define EnableCHYPbPr           0x08   /* YPbPr on Ch7019 (480i HDTV); only on 650/Ch7019 systems */
31272b676d7Smrg#define EnableSiSYPbPr          0x08   /* Enable YPbPr mode (30xLV/301C only) */
31372b676d7Smrg#define EnableYPbPr525i         0x00   /* Enable 525i YPbPr mode (30xLV/301C only) (mask 0x30) */
31472b676d7Smrg#define EnableYPbPr525p         0x10   /* Enable 525p YPbPr mode (30xLV/301C only) (mask 0x30) */
31572b676d7Smrg#define EnableYPbPr750p         0x20   /* Enable 750p YPbPr mode (30xLV/301C only) (mask 0x30) */
31672b676d7Smrg#define EnableYPbPr1080i        0x30   /* Enable 1080i YPbPr mode (30xLV/301C only) (mask 0x30) */
31772b676d7Smrg#define EnablePALM              0x40   /* 1 = Set PALM */
31872b676d7Smrg#define EnablePALN              0x80   /* 1 = Set PALN */
31972b676d7Smrg#define EnableNTSCJ             EnablePALM  /* Not BIOS */
32072b676d7Smrg
32172b676d7Smrg/* CR38 (661 and later)
32272b676d7Smrg  D[7:5]  000 No VB
32372b676d7Smrg          001 301 series VB
32472b676d7Smrg	  010 LVDS
32572b676d7Smrg	  011 Chrontel 7019
32672b676d7Smrg	  100 Conexant
32772b676d7Smrg  D2      Enable YPbPr output (see CR35)
32872b676d7Smrg  D[1:0]  LCDA (like before)
32972b676d7Smrg*/
33072b676d7Smrg
33172b676d7Smrg#define EnablePALMN             0x40   /* Romflag: 1 = Allow PALM/PALN */
33272b676d7Smrg
33372b676d7Smrg/* CR39 (650 only) */
33472b676d7Smrg#define LCDPass1_1		0x01   /* 0: center screen, 1: pass 1:1 data output  */
33572b676d7Smrg#define Enable302LV_DualLink    0x04   /* 302LV only; enable dual link */
33672b676d7Smrg
33772b676d7Smrg/* CR39 (661 and later)
33872b676d7Smrg   D[7]   LVDS (SiS or third party)
33972b676d7Smrg   D[1:0] YPbPr Aspect Ratio
34072b676d7Smrg          00 4:3 letterbox
34172b676d7Smrg	  01 4:3
34272b676d7Smrg	  10 16:9
34372b676d7Smrg	  11 4:3
34472b676d7Smrg*/
34572b676d7Smrg
34672b676d7Smrg/* CR3B (651+301C)
34772b676d7Smrg   D[1:0] YPbPr Aspect Ratio
34872b676d7Smrg          ?
34972b676d7Smrg*/
35072b676d7Smrg
35172b676d7Smrg/* CR79 (315/330 series only; not 661 and later)
35272b676d7Smrg   [3-0] Notify driver
35372b676d7Smrg         0001 Mode Switch event (set by BIOS)
35472b676d7Smrg	 0010 Epansion On/Off event
35572b676d7Smrg	 0011 TV UnderScan/OverScan event
35672b676d7Smrg	 0100 Set Brightness event
35772b676d7Smrg	 0101 Set Contrast event
35872b676d7Smrg	 0110 Set Mute event
35972b676d7Smrg	 0111 Set Volume Up/Down event
36072b676d7Smrg   [4]   Enable Backlight Control by BIOS/driver
36172b676d7Smrg         (set by driver; set means that the BIOS should
36272b676d7Smrg	 not touch the backlight registers because eg.
36372b676d7Smrg	 the driver already switched off the backlight)
36472b676d7Smrg   [5]   PAL/NTSC (set by BIOS)
36572b676d7Smrg   [6]   Expansion On/Off (set by BIOS; copied to CR32[4])
36672b676d7Smrg   [7]   TV UnderScan/OverScan (set by BIOS)
36772b676d7Smrg*/
36872b676d7Smrg
36972b676d7Smrg/* CR7C - 661 and later
37072b676d7Smrg   [7]   DualEdge enabled (or: to be enabled)
37172b676d7Smrg   [6]   CRT2 = TV/LCD/VGA enabled (or: to be enabled)
37272b676d7Smrg   [5]   Init done (set at end of SiS_Init)
37372b676d7Smrg   {4]   LVDS LCD capabilities
37472b676d7Smrg   [3]   LVDS LCD capabilities
37572b676d7Smrg   [2]   LVDS LCD capabilities (PWD)
37672b676d7Smrg   [1]   LVDS LCD capabilities (PWD)
37772b676d7Smrg   [0]   LVDS=1, TMDS=0 (SiS or third party)
37872b676d7Smrg*/
37972b676d7Smrg
38072b676d7Smrg/* CR7E - 661 and later
38172b676d7Smrg   VBType:
38272b676d7Smrg   [7] LVDS (third party)
38372b676d7Smrg   [3] 301C
38472b676d7Smrg   [2] 302LV
38572b676d7Smrg   [1] 301LV
38672b676d7Smrg   [0] 301B
38772b676d7Smrg*/
38872b676d7Smrg
38972b676d7Smrg/* LCDResInfo */
39072b676d7Smrg#define Panel300_800x600        0x01	/* CR36 */
39172b676d7Smrg#define Panel300_1024x768       0x02
39272b676d7Smrg#define Panel300_1280x1024      0x03
39372b676d7Smrg#define Panel300_1280x960       0x04
39472b676d7Smrg#define Panel300_640x480        0x05
39572b676d7Smrg#define Panel300_1024x600       0x06
39672b676d7Smrg#define Panel300_1152x768       0x07
39772b676d7Smrg#define Panel300_1280x768       0x0a
39872b676d7Smrg#define Panel300_Custom		0x0f
39972b676d7Smrg#define Panel300_Barco1366      0x10
40072b676d7Smrg
40172b676d7Smrg#define Panel310_800x600        0x01
40272b676d7Smrg#define Panel310_1024x768       0x02
40372b676d7Smrg#define Panel310_1280x1024      0x03
40472b676d7Smrg#define Panel310_640x480        0x04
40572b676d7Smrg#define Panel310_1024x600       0x05
40672b676d7Smrg#define Panel310_1152x864       0x06
40772b676d7Smrg#define Panel310_1280x960       0x07
40872b676d7Smrg#define Panel310_1152x768       0x08	/* LVDS only */
40972b676d7Smrg#define Panel310_1400x1050      0x09
41072b676d7Smrg#define Panel310_1280x768       0x0a
41172b676d7Smrg#define Panel310_1600x1200      0x0b
41272b676d7Smrg#define Panel310_320x240_2      0x0c    /* xSTN */
41372b676d7Smrg#define Panel310_320x240_3      0x0d    /* xSTN */
41472b676d7Smrg#define Panel310_320x240_1      0x0e    /* xSTN - This is fake, can be any */
41572b676d7Smrg#define Panel310_Custom		0x0f
41672b676d7Smrg
41772b676d7Smrg#define Panel661_800x600        0x01
41872b676d7Smrg#define Panel661_1024x768       0x02
41972b676d7Smrg#define Panel661_1280x1024      0x03
42072b676d7Smrg#define Panel661_640x480        0x04
42172b676d7Smrg#define Panel661_1024x600       0x05
42272b676d7Smrg#define Panel661_1152x864       0x06
42372b676d7Smrg#define Panel661_1280x960       0x07
42472b676d7Smrg#define Panel661_1280x854       0x08
42572b676d7Smrg#define Panel661_1400x1050      0x09
42672b676d7Smrg#define Panel661_1280x768       0x0a
42772b676d7Smrg#define Panel661_1600x1200      0x0b
42872b676d7Smrg#define Panel661_1280x800       0x0c
42972b676d7Smrg#define Panel661_1680x1050      0x0d
43072b676d7Smrg#define Panel661_1280x720       0x0e
43172b676d7Smrg#define Panel661_Custom		0x0f
43272b676d7Smrg
43372b676d7Smrg#define Panel_800x600           0x01	/* Unified values */
43472b676d7Smrg#define Panel_1024x768          0x02    /* MUST match BIOS values from 0-e */
43572b676d7Smrg#define Panel_1280x1024         0x03
43672b676d7Smrg#define Panel_640x480           0x04
43772b676d7Smrg#define Panel_1024x600          0x05
43872b676d7Smrg#define Panel_1152x864          0x06
43972b676d7Smrg#define Panel_1280x960          0x07
44072b676d7Smrg#define Panel_1152x768          0x08	/* LVDS only */
44172b676d7Smrg#define Panel_1400x1050         0x09
44272b676d7Smrg#define Panel_1280x768          0x0a    /* 30xB/C and LVDS only (BIOS: all) */
44372b676d7Smrg#define Panel_1600x1200         0x0b
44472b676d7Smrg#define Panel_1280x800		0x0c    /* 661etc (TMDS) */
44572b676d7Smrg#define Panel_1680x1050         0x0d    /* 661etc  */
44672b676d7Smrg#define Panel_1280x720		0x0e    /* 661etc  */
44772b676d7Smrg#define Panel_Custom		0x0f	/* MUST BE 0x0f (for DVI DDC detection) */
44872b676d7Smrg#define Panel_320x240_1         0x10    /* SiS 550 xSTN */
44972b676d7Smrg#define Panel_Barco1366         0x11
45072b676d7Smrg#define Panel_848x480		0x12
45172b676d7Smrg#define Panel_320x240_2		0x13    /* SiS 550 xSTN */
45272b676d7Smrg#define Panel_320x240_3		0x14    /* SiS 550 xSTN */
45372b676d7Smrg#define Panel_1280x768_2        0x15	/* 30xLV */
45472b676d7Smrg#define Panel_1280x768_3        0x16    /* (unused) */
45572b676d7Smrg#define Panel_1280x800_2	0x17    /* 30xLV */
45672b676d7Smrg#define Panel_856x480		0x18
45772b676d7Smrg#define Panel_1280x854		0x19	/* 661etc */
45872b676d7Smrg
45972b676d7Smrg/* Index in ModeResInfo table */
46072b676d7Smrg#define SIS_RI_320x200    0
46172b676d7Smrg#define SIS_RI_320x240    1
46272b676d7Smrg#define SIS_RI_320x400    2
46372b676d7Smrg#define SIS_RI_400x300    3
46472b676d7Smrg#define SIS_RI_512x384    4
46572b676d7Smrg#define SIS_RI_640x400    5
46672b676d7Smrg#define SIS_RI_640x480    6
46772b676d7Smrg#define SIS_RI_800x600    7
46872b676d7Smrg#define SIS_RI_1024x768   8
46972b676d7Smrg#define SIS_RI_1280x1024  9
47072b676d7Smrg#define SIS_RI_1600x1200 10
47172b676d7Smrg#define SIS_RI_1920x1440 11
47272b676d7Smrg#define SIS_RI_2048x1536 12
47372b676d7Smrg#define SIS_RI_720x480   13
47472b676d7Smrg#define SIS_RI_720x576   14
47572b676d7Smrg#define SIS_RI_1280x960  15
47672b676d7Smrg#define SIS_RI_800x480   16
47772b676d7Smrg#define SIS_RI_1024x576  17
47872b676d7Smrg#define SIS_RI_1280x720  18
47972b676d7Smrg#define SIS_RI_856x480   19
48072b676d7Smrg#define SIS_RI_1280x768  20
48172b676d7Smrg#define SIS_RI_1400x1050 21
48272b676d7Smrg#define SIS_RI_1152x864  22  /* Up to here SiS conforming */
48372b676d7Smrg#define SIS_RI_848x480   23
48472b676d7Smrg#define SIS_RI_1360x768  24
48572b676d7Smrg#define SIS_RI_1024x600  25
48672b676d7Smrg#define SIS_RI_1152x768  26
48772b676d7Smrg#define SIS_RI_768x576   27
48872b676d7Smrg#define SIS_RI_1360x1024 28
48972b676d7Smrg#define SIS_RI_1680x1050 29
49072b676d7Smrg#define SIS_RI_1280x800  30
49172b676d7Smrg#define SIS_RI_1920x1080 31
49272b676d7Smrg#define SIS_RI_960x540   32
49372b676d7Smrg#define SIS_RI_960x600   33
49472b676d7Smrg#define SIS_RI_1280x854  34
49572b676d7Smrg
49672b676d7Smrg/* CR5F */
49772b676d7Smrg#define IsM650                  0x80
49872b676d7Smrg
49972b676d7Smrg/* Timing data */
50072b676d7Smrg#define NTSCHT                  1716
50172b676d7Smrg#define NTSC2HT                 1920
50272b676d7Smrg#define NTSCVT                  525
50372b676d7Smrg#define PALHT                   1728
50472b676d7Smrg#define PALVT                   625
50572b676d7Smrg#define StHiTVHT                892
50672b676d7Smrg#define StHiTVVT                1126
50772b676d7Smrg#define StHiTextTVHT            1000
50872b676d7Smrg#define StHiTextTVVT            1126
50972b676d7Smrg#define ExtHiTVHT               2100
51072b676d7Smrg#define ExtHiTVVT               1125
51172b676d7Smrg
51272b676d7Smrg/* Indices in (VB)VCLKData tables */
51372b676d7Smrg
51472b676d7Smrg#define VCLK28                  0x00   /* Index in VCLKData table (300 and 315) */
51572b676d7Smrg#define VCLK40                  0x04   /* Index in VCLKData table (300 and 315) */
51672b676d7Smrg#define VCLK65_300              0x09   /* Index in VCLKData table (300) */
51772b676d7Smrg#define VCLK108_2_300           0x14   /* Index in VCLKData table (300) */
51872b676d7Smrg#define VCLK81_300		0x3f   /* Index in VCLKData table (300) */
51972b676d7Smrg#define VCLK108_3_300           0x42   /* Index in VCLKData table (300) */
52072b676d7Smrg#define VCLK100_300             0x43   /* Index in VCLKData table (300) */
52172b676d7Smrg#define VCLK34_300              0x3d   /* Index in VCLKData table (300) */
52272b676d7Smrg#define VCLK_CUSTOM_300		0x47
52372b676d7Smrg
52472b676d7Smrg#define VCLK65_315              0x0b   /* Indices in (VB)VCLKData table (315) */
52572b676d7Smrg#define VCLK108_2_315           0x19
52672b676d7Smrg#define VCLK81_315		0x5b
52772b676d7Smrg#define VCLK162_315             0x5e
52872b676d7Smrg#define VCLK108_3_315           0x45
52972b676d7Smrg#define VCLK100_315             0x46
53072b676d7Smrg#define VCLK34_315              0x55
53172b676d7Smrg#define VCLK68_315		0x0d
53272b676d7Smrg#define VCLK_1280x800_315_2	0x5c
53372b676d7Smrg#define VCLK121_315		0x5d
53472b676d7Smrg#define VCLK130_315		0x72
53572b676d7Smrg#define VCLK_1280x720		0x5f
53672b676d7Smrg#define VCLK_1280x768_2		0x60
53772b676d7Smrg#define VCLK_1280x768_3		0x61   /* (unused?) */
53872b676d7Smrg#define VCLK_CUSTOM_315		0x62
53972b676d7Smrg#define VCLK_1280x720_2		0x63
54072b676d7Smrg#define VCLK_720x480		0x67
54172b676d7Smrg#define VCLK_720x576		0x68
54272b676d7Smrg#define VCLK_768x576		0x68
54372b676d7Smrg#define VCLK_848x480		0x65
54472b676d7Smrg#define VCLK_856x480		0x66
54572b676d7Smrg#define VCLK_800x480		0x65
54672b676d7Smrg#define VCLK_1024x576		0x51
54772b676d7Smrg#define VCLK_1152x864		0x64
54872b676d7Smrg#define VCLK_1360x768		0x58
54972b676d7Smrg#define VCLK_1280x800_315	0x6c
55072b676d7Smrg#define VCLK_1280x854		0x76
55172b676d7Smrg
55272b676d7Smrg#define TVCLKBASE_300		0x21   /* Indices on TV clocks in VCLKData table (300) */
55372b676d7Smrg#define TVCLKBASE_315	        0x3a   /* Indices on TV clocks in (VB)VCLKData table (315) */
55472b676d7Smrg#define TVVCLKDIV2              0x00   /* Index relative to TVCLKBASE */
55572b676d7Smrg#define TVVCLK                  0x01   /* Index relative to TVCLKBASE */
55672b676d7Smrg#define HiTVVCLKDIV2            0x02   /* Index relative to TVCLKBASE */
55772b676d7Smrg#define HiTVVCLK                0x03   /* Index relative to TVCLKBASE */
55872b676d7Smrg#define HiTVSimuVCLK            0x04   /* Index relative to TVCLKBASE */
55972b676d7Smrg#define HiTVTextVCLK            0x05   /* Index relative to TVCLKBASE */
56072b676d7Smrg#define YPbPr750pVCLK		0x25   /* Index relative to TVCLKBASE; was 0x0f NOT relative */
56172b676d7Smrg
56272b676d7Smrg/* ------------------------------ */
56372b676d7Smrg
56472b676d7Smrg#define SetSCARTOutput          0x01
56572b676d7Smrg
56672b676d7Smrg#define HotPlugFunction         0x08
56772b676d7Smrg
56872b676d7Smrg#define StStructSize            0x06
56972b676d7Smrg
57072b676d7Smrg#define SIS_VIDEO_CAPTURE       0x00 - 0x30
57172b676d7Smrg#define SIS_VIDEO_PLAYBACK      0x02 - 0x30
57272b676d7Smrg#define SIS_CRT2_PORT_04        0x04 - 0x30
57372b676d7Smrg#define SIS_CRT2_PORT_10        0x10 - 0x30
57472b676d7Smrg#define SIS_CRT2_PORT_12        0x12 - 0x30
57572b676d7Smrg#define SIS_CRT2_PORT_14        0x14 - 0x30
57672b676d7Smrg
57772b676d7Smrg#define ADR_CRT2PtrData         0x20E
57872b676d7Smrg#define offset_Zurac            0x210   /* TW: Trumpion Zurac data pointer */
57972b676d7Smrg#define ADR_LVDSDesPtrData      0x212
58072b676d7Smrg#define ADR_LVDSCRT1DataPtr     0x214
58172b676d7Smrg#define ADR_CHTVVCLKPtr         0x216
58272b676d7Smrg#define ADR_CHTVRegDataPtr      0x218
58372b676d7Smrg
58472b676d7Smrg#define LCDDataLen              8
58572b676d7Smrg#define HiTVDataLen             12
58672b676d7Smrg#define TVDataLen               16
58772b676d7Smrg
58872b676d7Smrg#define LVDSDataLen             6
58972b676d7Smrg#define LVDSDesDataLen          3
59072b676d7Smrg#define ActiveNonExpanding      0x40
59172b676d7Smrg#define ActiveNonExpandingShift 6
59272b676d7Smrg#define ActivePAL               0x20
59372b676d7Smrg#define ActivePALShift          5
59472b676d7Smrg#define ModeSwitchStatus        0x0F
59572b676d7Smrg#define SoftTVType              0x40
59672b676d7Smrg#define SoftSettingAddr         0x52
59772b676d7Smrg#define ModeSettingAddr         0x53
59872b676d7Smrg
59972b676d7Smrg#define _PanelType00             0x00
60072b676d7Smrg#define _PanelType01             0x08
60172b676d7Smrg#define _PanelType02             0x10
60272b676d7Smrg#define _PanelType03             0x18
60372b676d7Smrg#define _PanelType04             0x20
60472b676d7Smrg#define _PanelType05             0x28
60572b676d7Smrg#define _PanelType06             0x30
60672b676d7Smrg#define _PanelType07             0x38
60772b676d7Smrg#define _PanelType08             0x40
60872b676d7Smrg#define _PanelType09             0x48
60972b676d7Smrg#define _PanelType0A             0x50
61072b676d7Smrg#define _PanelType0B             0x58
61172b676d7Smrg#define _PanelType0C             0x60
61272b676d7Smrg#define _PanelType0D             0x68
61372b676d7Smrg#define _PanelType0E             0x70
61472b676d7Smrg#define _PanelType0F             0x78
61572b676d7Smrg
61672b676d7Smrg#define PRIMARY_VGA       	0     /* 1: SiS is primary vga 0:SiS is secondary vga */
61772b676d7Smrg
61872b676d7Smrg#define BIOSIDCodeAddr          0x235  /* Offsets to ptrs in BIOS image */
61972b676d7Smrg#define OEMUtilIDCodeAddr       0x237
62072b676d7Smrg#define VBModeIDTableAddr       0x239
62172b676d7Smrg#define OEMTVPtrAddr            0x241
62272b676d7Smrg#define PhaseTableAddr          0x243
62372b676d7Smrg#define NTSCFilterTableAddr     0x245
62472b676d7Smrg#define PALFilterTableAddr      0x247
62572b676d7Smrg#define OEMLCDPtr_1Addr         0x249
62672b676d7Smrg#define OEMLCDPtr_2Addr         0x24B
62772b676d7Smrg#define LCDHPosTable_1Addr      0x24D
62872b676d7Smrg#define LCDHPosTable_2Addr      0x24F
62972b676d7Smrg#define LCDVPosTable_1Addr      0x251
63072b676d7Smrg#define LCDVPosTable_2Addr      0x253
63172b676d7Smrg#define OEMLCDPIDTableAddr      0x255
63272b676d7Smrg
63372b676d7Smrg#define VBModeStructSize        5
63472b676d7Smrg#define PhaseTableSize          4
63572b676d7Smrg#define FilterTableSize         4
63672b676d7Smrg#define LCDHPosTableSize        7
63772b676d7Smrg#define LCDVPosTableSize        5
63872b676d7Smrg#define OEMLVDSPIDTableSize     4
63972b676d7Smrg#define LVDSHPosTableSize       4
64072b676d7Smrg#define LVDSVPosTableSize       6
64172b676d7Smrg
64272b676d7Smrg#define VB_ModeID               0
64372b676d7Smrg#define VB_TVTableIndex         1
64472b676d7Smrg#define VB_LCDTableIndex        2
64572b676d7Smrg#define VB_LCDHIndex            3
64672b676d7Smrg#define VB_LCDVIndex            4
64772b676d7Smrg
64872b676d7Smrg#define OEMLCDEnable            0x0001
64972b676d7Smrg#define OEMLCDDelayEnable       0x0002
65072b676d7Smrg#define OEMLCDPOSEnable         0x0004
65172b676d7Smrg#define OEMTVEnable             0x0100
65272b676d7Smrg#define OEMTVDelayEnable        0x0200
65372b676d7Smrg#define OEMTVFlickerEnable      0x0400
65472b676d7Smrg#define OEMTVPhaseEnable        0x0800
65572b676d7Smrg#define OEMTVFilterEnable       0x1000
65672b676d7Smrg
65772b676d7Smrg#define OEMLCDPanelIDSupport    0x0080
65872b676d7Smrg
65972b676d7Smrg/*
66072b676d7Smrg  =============================================================
66172b676d7Smrg   		  for 315 series (old data layout)
66272b676d7Smrg  =============================================================
66372b676d7Smrg*/
66472b676d7Smrg#define SoftDRAMType        0x80
66572b676d7Smrg#define SoftSetting_OFFSET  0x52
66672b676d7Smrg#define SR07_OFFSET  0x7C
66772b676d7Smrg#define SR15_OFFSET  0x7D
66872b676d7Smrg#define SR16_OFFSET  0x81
66972b676d7Smrg#define SR17_OFFSET  0x85
67072b676d7Smrg#define SR19_OFFSET  0x8D
67172b676d7Smrg#define SR1F_OFFSET  0x99
67272b676d7Smrg#define SR21_OFFSET  0x9A
67372b676d7Smrg#define SR22_OFFSET  0x9B
67472b676d7Smrg#define SR23_OFFSET  0x9C
67572b676d7Smrg#define SR24_OFFSET  0x9D
67672b676d7Smrg#define SR25_OFFSET  0x9E
67772b676d7Smrg#define SR31_OFFSET  0x9F
67872b676d7Smrg#define SR32_OFFSET  0xA0
67972b676d7Smrg#define SR33_OFFSET  0xA1
68072b676d7Smrg
68172b676d7Smrg#define CR40_OFFSET  0xA2
68272b676d7Smrg#define SR25_1_OFFSET  0xF6
68372b676d7Smrg#define CR49_OFFSET  0xF7
68472b676d7Smrg
68572b676d7Smrg#define VB310Data_1_2_Offset  0xB6
68672b676d7Smrg#define VB310Data_4_D_Offset  0xB7
68772b676d7Smrg#define VB310Data_4_E_Offset  0xB8
68872b676d7Smrg#define VB310Data_4_10_Offset 0xBB
68972b676d7Smrg
69072b676d7Smrg#define RGBSenseDataOffset    0xBD
69172b676d7Smrg#define YCSenseDataOffset     0xBF
69272b676d7Smrg#define VideoSenseDataOffset  0xC1
69372b676d7Smrg#define OutputSelectOffset    0xF3
69472b676d7Smrg
69572b676d7Smrg#define ECLK_MCLK_DISTANCE  0x14
69672b676d7Smrg#define VBIOSTablePointerStart    0x100
69772b676d7Smrg#define StandTablePtrOffset       VBIOSTablePointerStart+0x02
69872b676d7Smrg#define EModeIDTablePtrOffset     VBIOSTablePointerStart+0x04
69972b676d7Smrg#define CRT1TablePtrOffset        VBIOSTablePointerStart+0x06
70072b676d7Smrg#define ScreenOffsetPtrOffset     VBIOSTablePointerStart+0x08
70172b676d7Smrg#define VCLKDataPtrOffset         VBIOSTablePointerStart+0x0A
70272b676d7Smrg#define MCLKDataPtrOffset         VBIOSTablePointerStart+0x0E
70372b676d7Smrg#define CRT2PtrDataPtrOffset      VBIOSTablePointerStart+0x10
70472b676d7Smrg#define TVAntiFlickPtrOffset      VBIOSTablePointerStart+0x12
70572b676d7Smrg#define TVDelayPtr1Offset         VBIOSTablePointerStart+0x14
70672b676d7Smrg#define TVPhaseIncrPtr1Offset     VBIOSTablePointerStart+0x16
70772b676d7Smrg#define TVYFilterPtr1Offset       VBIOSTablePointerStart+0x18
70872b676d7Smrg#define LCDDelayPtr1Offset        VBIOSTablePointerStart+0x20
70972b676d7Smrg#define TVEdgePtr1Offset          VBIOSTablePointerStart+0x24
71072b676d7Smrg#define CRT2Delay1Offset          VBIOSTablePointerStart+0x28
71172b676d7Smrg
71272b676d7Smrg#endif
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