1/* 2 * Acceleration for the Creator and Creator3D framebuffer - DAC register layout. 3 * 4 * Copyright (C) 2000 David S. Miller (davem@redhat.com) 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * DAVID MILLER BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 20 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25#ifndef _FFB_DAC_H 26#define _FFB_DAC_H 27 28/* FFB utilizes two different ramdac chips: 29 * 30 * 1) BT9068 "Pacifica1", used in all FFB1 and 31 * FFB2 boards. 32 * 33 * 2) BT498(a) "Pacifica2", used in FFB2+ and 34 * AFB boards. 35 * 36 * They are mostly equivalent, except in a few key areas: 37 * 38 * 1) WID register layout 39 * 2) Number of CLUT tables 40 * 3) Presence of Window Address Mask register 41 * 4) Method of GAMMA correction support 42 */ 43 44/* NOTE: All addresses described in this file are DAC 45 * indirect addresses. 46 */ 47 48/* DAC color values are in the following format. */ 49#define FFBDAC_COLOR_BLUE 0x00ff0000 50#define FFBDAC_COLOR_BLUE_SHFT 16 51#define FFBDAC_COLOR_GREEN 0x0000ff00 52#define FFBDAC_COLOR_GREEN_SHFT 8 53#define FFBDAC_COLOR_RED 0x000000ff 54#define FFBDAC_COLOR_RED_SHFT 0 55 56/* Cursor DAC register addresses. */ 57#define FFBDAC_CUR_BITMAP_P0 0x000 /* Plane 0 cursor bitmap */ 58#define FFBDAC_CUR_BITMAP_P1 0x080 /* Plane 1 cursor bitmap */ 59#define FFBDAC_CUR_CTRL 0x100 /* Cursor control */ 60#define FFBDAC_CUR_COLOR0 0x101 /* Cursor Color 0 */ 61#define FFBDAC_CUR_COLOR1 0x102 /* Cursor Color 1 (bg) */ 62#define FFBDAC_CUR_COLOR2 0x103 /* Cursor Color 2 (fg) */ 63#define FFBDAC_CUR_POS 0x104 /* Active cursor position */ 64 65/* Cursor control register. 66 * WARNING: Be careful, reverse logic on these bits. 67 */ 68#define FFBDAC_CUR_CTRL_P0 0x00000001 /* Plane0 display disable */ 69#define FFBDAC_CUR_CTRL_P1 0x00000002 /* Plane1 display disable */ 70 71/* Active cursor position register */ 72#define FFBDAC_CUR_POS_Y_SIGN 0x80000000 /* Sign of Y position */ 73#define FFBDAC_CUR_POS_Y 0x0fff0000 /* Y position */ 74#define FFBDAC_CUR_POS_X_SIGN 0x00008000 /* Sign of X position */ 75#define FFBDAC_CUR_POS_X 0x00000fff /* X position */ 76 77/* Configuration and Palette DAC register addresses. */ 78#define FFBDAC_CFG_PPLLCTRL 0x0000 /* Pixel PLL Control */ 79#define FFBDAC_CFG_GPLLCTRL 0x0001 /* General Purpose PLL Control */ 80#define FFBDAC_CFG_PFCTRL 0x1000 /* Pixel Format Control */ 81#define FFBDAC_CFG_UCTRL 0x1001 /* User Control */ 82#define FFBDAC_CFG_CLUP_BASE 0x2000 /* Color Lookup Palette */ 83#define FFBDAC_CFG_CLUP(entry) (FFBDAC_CFG_CLUP_BASE + ((entry) * 0x100)) 84#define FFBDAC_PAC2_SOVWLUT0 0x3100 /* Shadow Overlay Window Lookup 0*/ 85#define FFBDAC_PAC2_SOVWLUT1 0x3101 /* Shadow Overlay Window Lookup 1*/ 86#define FFBDAC_PAC2_SOVWLUT2 0x3102 /* Shadow Overlay Window Lookup 2*/ 87#define FFBDAC_PAC2_SOVWLUT3 0x3103 /* Shadow Overlay Window Lookup 3*/ 88#define FFBDAC_PAC2_AOVWLUT0 0x3210 /* Active Overlay Window Lookup 0*/ 89#define FFBDAC_PAC2_AOVWLUT1 0x3211 /* Active Overlay Window Lookup 1*/ 90#define FFBDAC_PAC2_AOVWLUT2 0x3212 /* Active Overlay Window Lookup 2*/ 91#define FFBDAC_PAC2_AOVWLUT3 0x3213 /* Active Overlay Window Lookup 3*/ 92#define FFBDAC_CFG_WTCTRL 0x3150 /* Window Transfer Control */ 93#define FFBDAC_CFG_TMCTRL 0x3151 /* Transparent Mask Control */ 94#define FFBDAC_CFG_TCOLORKEY 0x3152 /* Transparent Color Key */ 95#define FFBDAC_CFG_WAMASK 0x3153 /* Window Address Mask (PAC2 only) */ 96#define FFBDAC_PAC1_SPWLUT_BASE 0x3100 /* Shadow Primary Window Lookups */ 97#define FFBDAC_PAC1_SPWLUT(entry) (FFBDAC_PAC1_SPWLUT_BASE + (entry)) 98#define FFBDAC_PAC1_APWLUT_BASE 0x3120 /* Active Primary Window Lookups */ 99#define FFBDAC_PAC1_APWLUT(entry) (FFBDAC_PAC1_APWLUT_BASE + (entry)) 100#define FFBDAC_PAC2_SPWLUT_BASE 0x3200 /* Shadow Primary Window Lookups */ 101#define FFBDAC_PAC2_SPWLUT(entry) (FFBDAC_PAC2_SPWLUT_BASE + (entry)) 102#define FFBDAC_PAC2_APWLUT_BASE 0x3240 /* Active Primary Window Lookups */ 103#define FFBDAC_PAC2_APWLUT(entry) (FFBDAC_PAC2_APWLUT_BASE + (entry)) 104#define FFBDAC_CFG_SANAL 0x5000 /* Signature Analysis Control */ 105#define FFBDAC_CFG_DACCTRL 0x5001 /* DAC Control */ 106#define FFBDAC_CFG_TGEN 0x6000 /* Timing Generator Control */ 107#define FFBDAC_CFG_VBNP 0x6001 /* Vertical Blank Negation Point */ 108#define FFBDAC_CFG_VBAP 0x6002 /* Vertical Blank Assertion Point*/ 109#define FFBDAC_CFG_VSNP 0x6003 /* Vertical Sync Negation Point */ 110#define FFBDAC_CFG_VSAP 0x6004 /* Vertical Sync Assertion Point */ 111#define FFBDAC_CFG_HSNP 0x6005 /* Horz Serration Negation Point */ 112#define FFBDAC_CFG_HBNP 0x6006 /* Horz Blank Negation Point */ 113#define FFBDAC_CFG_HBAP 0x6007 /* Horz Blank Assertion Point */ 114#define FFBDAC_CFG_HSYNCNP 0x6008 /* Horz Sync Negation Point */ 115#define FFBDAC_CFG_HSYNCAP 0x6009 /* Horz Sync Assertion Point */ 116#define FFBDAC_CFG_HSCENNP 0x600A /* Horz SCEN Negation Point */ 117#define FFBDAC_CFG_HSCENAP 0x600B /* Horz SCEN Assertion Point */ 118#define FFBDAC_CFG_EPNP 0x600C /* Eql'zing Pulse Negation Point */ 119#define FFBDAC_CFG_EINP 0x600D /* Eql'zing Intvl Negation Point */ 120#define FFBDAC_CFG_EIAP 0x600E /* Eql'zing Intvl Assertion Point*/ 121#define FFBDAC_CFG_TGVC 0x600F /* Timing Generator Vert Counter */ 122#define FFBDAC_CFG_TGHC 0x6010 /* Timing Generator Horz Counter */ 123#define FFBDAC_CFG_DID 0x8000 /* Device Identification */ 124#define FFBDAC_CFG_MPDATA 0x8001 /* Monitor Port Data */ 125#define FFBDAC_CFG_MPSENSE 0x8002 /* Monitor Port Sense */ 126 127/* Pixel PLL Control Register */ 128#define FFBDAC_CFG_PPLLCTRL_M 0x0000007f /* PLL VCO Multiplicand */ 129#define FFBDAC_CFG_PPLLCTRL_D 0x00000780 /* PLL VCO Divisor */ 130#define FFBDAC_CFG_PPLLCTRL_PFD 0x00001800 /* Post VCO Frequency Divider */ 131#define FFBDAC_CFG_PPLLCTRL_EN 0x00004000 /* Enable PLL as pixel clock src */ 132 133/* General Purpose PLL Control Register */ 134#define FFBDAC_CFG_GPLLCTRL_M 0x0000007f /* PLL VCO Multiplicand */ 135#define FFBDAC_CFG_GPLLCTRL_D 0x00000780 /* PLL VCO Divisor */ 136#define FFBDAC_CFG_GPLLCTRL_PFD 0x00001800 /* Post VCO Frequency Divider */ 137#define FFBDAC_CFG_GPLLCTRL_EN 0x00004000 /* Enable PLL as Gen. Purpose clk*/ 138 139/* Pixel Format Control Register */ 140#define FFBDAC_CFG_PFCTRL_2_1 0x00000000 /* 2:1 pixel interleave format */ 141#define FFBDAC_CFG_PFCTRL_4_1 0x00000001 /* 4:1 pixel interleave format */ 142#define FFBDAC_CFG_PFCTRL_42_1 0x00000002 /* 4/2:1 pixel interleave format */ 143#define FFBDAC_CFG_PFCTRL_82_1 0x00000003 /* 8/2:1 pixel interleave format */ 144 145/* User Control Register */ 146#define FFBDAC_UCTRL_IPDISAB 0x00000001 /* Disable input pullup resistors*/ 147#define FFBDAC_UCTRL_ABLANK 0x00000002 /* Asynchronous Blank */ 148#define FFBDAC_UCTRL_DBENAB 0x00000004 /* Double-Buffer Enable */ 149#define FFBDAC_UCTRL_OVENAB 0x00000008 /* Overlay Enable */ 150#define FFBDAC_UCTRL_WMODE 0x00000030 /* Window Mode */ 151#define FFBDAC_UCTRL_WM_COMB 0x00000000 /* Window Mode = Combined */ 152#define FFBDAC_UCTRL_WM_S4 0x00000010 /* Window Mode = Seperate_4 */ 153#define FFBDAC_UCTRL_WM_S8 0x00000020 /* Window Mode = Seperate_8 */ 154#define FFBDAC_UCTRL_WM_RESV 0x00000030 /* Window Mode = reserved */ 155#define FFBDAC_UCTRL_MANREV 0x00000f00 /* 4-bit Manufacturing Revision */ 156 157/* Overlay Window Lookup Registers (PAC2 only) */ 158#define FFBDAC_CFG_OVWLUT_PSEL 0x0000000f /* Palette Section, Seperate_4 */ 159#define FFBDAC_CFG_OVWLUT_PTBL 0x00000030 /* Palette Table */ 160#define FFBDAC_CFG_OVWLUT_LKUP 0x00000100 /* 1 = Use palette, 0 = Bypass */ 161#define FFBDAC_CFG_OVWLUT_OTYP 0x00000c00 /* Overlay Type */ 162#define FFBDAC_CFG_OVWLUT_O_N 0x00000000 /* Overlay Type - None */ 163#define FFBDAC_CFG_OVWLUT_O_T 0x00000400 /* Overlay Type - Transparent */ 164#define FFBDAC_CFG_OVWLUT_O_O 0x00000800 /* Overlay Type - Opaque */ 165#define FFBDAC_CFG_OVWLUT_O_R 0x00000c00 /* Overlay Type - Reserved */ 166#define FFBDAC_CFG_OVWLUT_PCS 0x00003000 /* Psuedocolor Src */ 167#define FFBDAC_CFG_OVWLUT_P_XO 0x00000000 /* Psuedocolor Src - XO[7:0] */ 168#define FFBDAC_CFG_OVWLUT_P_R 0x00001000 /* Psuedocolor Src - R[7:0] */ 169#define FFBDAC_CFG_OVWLUT_P_G 0x00002000 /* Psuedocolor Src - G[7:0] */ 170#define FFBDAC_CFG_OVWLUT_P_B 0x00003000 /* Psuedocolor Src - B[7:0] */ 171 172/* Window Transfer Control Register */ 173#define FFBDAC_CFG_WTCTRL_DS 0x00000001 /* Device Status, 1 = Busy */ 174#define FFBDAC_CFG_WTCTRL_TCMD 0x00000002 /* Transfer Command 175 * 1 = Transfer, 0 = No Action 176 */ 177#define FFBDAC_CFG_WTCTRL_TE 0x00000004 /* Transfer Event 178 * 1 = Next Frame, 0 = Next Field 179 */ 180#define FFBDAC_CFG_WTCTRL_DRD 0x00000008 /* Drawing Data 181 * 1 = Local Drawing Active 182 * 0 = Local Drawing Idle 183 */ 184#define FFBDAC_CFG_WTCTRL_DRS 0x00000010 /* Drawing Status 185 * 1 = Network Drawing Active 186 * 0 = Network Drawing Idle 187 */ 188 189/* Transparent Mask Control Register */ 190#define FFBDAC_CFG_TMCTRL_OMSK 0x000000ff /* Overlay Mask */ 191 192/* Transparent Color Key Register */ 193#define FFBDAC_CFG_TCOLORKEY_K 0x000000ff /* Overlay Color Key */ 194 195/* Window Address Mask Register (PAC2 only) */ 196#define FFBDAC_CFG_WAMASK_PMSK 0x0000003f /* PWLUT select PMASK */ 197#define FFBDAC_CFG_WAMASK_OMSK 0x00000300 /* OWLUT control OMASK */ 198 199/* (non-Overlay) Window Lookup Table Registers, PAC1 format */ 200#define FFBDAC_PAC1_WLUT_DB 0x00000020 /* 0 = Buffer A, 1 = Buffer B */ 201#define FFBDAC_PAC1_WLUT_C 0x0000001c /* C: Color Model Selection */ 202#define FFBDAC_PAC1_WLUT_C_8P 0x00000000 /* C: 8bpp Pseudocolor */ 203#define FFBDAC_PAC1_WLUT_C_8LG 0x00000004 /* C: 8bpp Linear Grey */ 204#define FFBDAC_PAC1_WLUT_C_8NG 0x00000008 /* C: 8bpp Non-Linear Grey */ 205#define FFBDAC_PAC1_WLUT_C_24D 0x00000010 /* C: 24bpp Directcolor */ 206#define FFBDAC_PAC1_WLUT_C_24LT 0x00000014 /* C: 24bpp Linear Truecolor */ 207#define FFBDAC_PAC1_WLUT_C_24NT 0x00000018 /* C: 24bpp Non-Linear Truecolor */ 208#define FFBDAC_PAC1_WLUT_PCS 0x00000003 /* Pseudocolor Src */ 209#define FFBDAC_PAC1_WLUT_P_XO 0x00000000 /* Pseudocolor Src - XO[7:0] */ 210#define FFBDAC_PAC1_WLUT_P_R 0x00000001 /* Pseudocolor Src - R[7:0] */ 211#define FFBDAC_PAC1_WLUT_P_G 0x00000002 /* Pseudocolor Src - G[7:0] */ 212#define FFBDAC_PAC1_WLUT_P_B 0x00000003 /* Pseudocolor Src - B[7:0] */ 213 214/* (non-Overlay) Window Lookup Table Registers, PAC2 format */ 215#define FFBDAC_PAC2_WLUT_PTBL 0x00000030 /* Palette Table Entry */ 216#define FFBDAC_PAC2_WLUT_LKUP 0x00000100 /* 1 = Use palette, 0 = Bypass */ 217#define FFBDAC_PAC2_WLUT_PCS 0x00003000 /* Pseudocolor Src */ 218#define FFBDAC_PAC2_WLUT_P_XO 0x00000000 /* Pseudocolor Src - XO[7:0] */ 219#define FFBDAC_PAC2_WLUT_P_R 0x00001000 /* Pseudocolor Src - R[7:0] */ 220#define FFBDAC_PAC2_WLUT_P_G 0x00002000 /* Pseudocolor Src - G[7:0] */ 221#define FFBDAC_PAC2_WLUT_P_B 0x00003000 /* Pseudocolor Src - B[7:0] */ 222#define FFBDAC_PAC2_WLUT_DEPTH 0x00004000 /* 0 = Pseudocolor, 1 = Truecolor*/ 223#define FFBDAC_PAC2_WLUT_DB 0x00008000 /* 0 = Buffer A, 1 = Buffer B */ 224 225/* Signature Analysis Control Register */ 226#define FFBDAC_CFG_SANAL_SRR 0x000000ff /* DAC Seed/Result for Red */ 227#define FFBDAC_CFG_SANAL_SRG 0x0000ff00 /* DAC Seed/Result for Green */ 228#define FFBDAC_CFG_SANAL_SRB 0x00ff0000 /* DAC Seed/Result for Blue */ 229#define FFBDAC_CFG_SANAL_RQST 0x01000000 /* Signature Capture Request */ 230#define FFBDAC_CFG_SANAL_BSY 0x02000000 /* Signature Analysis Busy */ 231#define FFBDAC_CFG_SANAL_DSM 0x04000000 /* Data Strobe Mode 232 * 0 = Signature Analysis Mode 233 * 1 = Data Strobe Mode 234 */ 235 236/* DAC Control Register */ 237#define FFBDAC_CFG_DACCTRL_O2 0x00000003 /* Operand 2 Select 238 * 00 = Normal Operation 239 * 01 = Select 145mv Reference 240 * 10 = Select Blue DAC Output 241 * 11 = Reserved 242 */ 243#define FFBDAC_CFG_DACCTRL_O1 0x0000000c /* Operand 1 Select 244 * 00 = Normal Operation 245 * 01 = Select Green DAC Output 246 * 10 = Select Red DAC Output 247 * 11 = Reserved 248 */ 249#define FFBDAC_CFG_DACCTRL_CR 0x00000010 /* Comparator Result 250 * 0 = operand1 < operand2 251 * 1 = operand1 > operand2 252 */ 253#define FFBDAC_CFG_DACCTRL_SGE 0x00000020 /* Sync-on-Green Enable */ 254#define FFBDAC_CFG_DACCTRL_PE 0x00000040 /* Pedestal Enable */ 255#define FFBDAC_CFG_DACCTRL_VPD 0x00000080 /* VSYNC* Pin Disable */ 256#define FFBDAC_CFG_DACCTRL_SPB 0x00000100 /* Sync Polarity Bit 257 * 0 = VSYNC* and CSYNC* active low 258 * 1 = VSYNC* and CSYNC* active high 259 */ 260 261/* Timing Generator Control Register */ 262#define FFBDAC_CFG_TGEN_VIDE 0x00000001 /* Video Enable */ 263#define FFBDAC_CFG_TGEN_TGE 0x00000002 /* Timing Generator Enable */ 264#define FFBDAC_CFG_TGEN_HSD 0x00000004 /* HSYNC* Disabled */ 265#define FFBDAC_CFG_TGEN_VSD 0x00000008 /* VSYNC* Disabled */ 266#define FFBDAC_CFG_TGEN_EQD 0x00000010 /* Equalization Disabled */ 267#define FFBDAC_CFG_TGEN_MM 0x00000020 /* 0 = Slave, 1 = Master */ 268#define FFBDAC_CFG_TGEN_IM 0x00000040 /* 1 = Interlaced Mode */ 269 270/* Device Identification Register, should be 0xA236E1AD for FFB bt497/bt498 */ 271#define FFBDAC_CFG_DID_ONE 0x00000001 /* Always set */ 272#define FFBDAC_CFG_DID_MANUF 0x00000ffe /* Manufacturer ID */ 273#define FFBDAC_CFG_DID_PNUM 0x0ffff000 /* Device Part Number */ 274#define FFBDAC_CFG_DID_REV 0xf0000000 /* Device Revision */ 275 276/* Monitor Port Data Register */ 277#define FFBDAC_CFG_MPDATA_SCL 0x00000001 /* SCL Data */ 278#define FFBDAC_CFG_MPDATA_SDA 0x00000002 /* SDA Data */ 279 280/* Monitor Port Sense Register */ 281#define FFBDAC_CFG_MPSENSE_SCL 0x00000001 /* SCL Sense */ 282#define FFBDAC_CFG_MPSENSE_SDA 0x00000002 /* SDA Sense */ 283 284/* DAC register access shorthands. */ 285#define DACCUR_READ(DAC, ADDR) ((DAC)->cur = (ADDR), (DAC)->curdata) 286#define DACCUR_WRITE(DAC, ADDR, VAL) ((DAC)->cur = (ADDR), (DAC)->curdata = (VAL)) 287#define DACCFG_READ(DAC, ADDR) ((DAC)->cfg = (ADDR), (DAC)->cfgdata) 288#define DACCFG_WRITE(DAC, ADDR, VAL) ((DAC)->cfg = (ADDR), (DAC)->cfgdata = (VAL)) 289 290typedef struct ffb_dac_hwstate { 291 unsigned int ppllctrl; 292 unsigned int gpllctrl; 293 unsigned int pfctrl; 294 unsigned int uctrl; 295 unsigned int clut[256 * 4]; /* One 256 entry clut on PAC1, 4 on PAC2 */ 296 unsigned int ovluts[4]; /* Overlay WLUTS, PAC2 only */ 297 unsigned int wtctrl; 298 unsigned int tmctrl; 299 unsigned int tcolorkey; 300 unsigned int wamask; 301 unsigned int pwluts[64]; 302 unsigned int dacctrl; 303 unsigned int tgen; 304 unsigned int vbnp; 305 unsigned int vbap; 306 unsigned int vsnp; 307 unsigned int vsap; 308 unsigned int hsnp; 309 unsigned int hbnp; 310 unsigned int hbap; 311 unsigned int hsyncnp; 312 unsigned int hsyncap; 313 unsigned int hscennp; 314 unsigned int hscenap; 315 unsigned int epnp; 316 unsigned int einp; 317 unsigned int eiap; 318} ffb_dac_hwstate_t; 319 320typedef struct { 321 Bool InUse; 322 323 /* The following fields are undefined unless InUse is TRUE. */ 324 int refcount; 325 Bool canshare; 326 unsigned int wlut_regval; 327 int buffer; /* 0 = Buffer A, 1 = Buffer B */ 328 int depth; /* 8 or 32 bpp */ 329 int greyscale; /* 1 = greyscale, 0 = color */ 330 int linear; /* 1 = linear, 0 = non-linear */ 331 int direct; /* 1 = 24bpp directcolor */ 332 int channel; /* 0 = X, 1 = R, 2 = G, 3 = B */ 333 int palette; /* Only PAC2 has multiple CLUTs */ 334} ffb_wid_info_t; 335 336#define FFB_MAX_PWIDS 64 337typedef struct { 338 int num_wids; 339 int wid_shift; /* To get X channel value */ 340 ffb_wid_info_t wid_pool[FFB_MAX_PWIDS]; 341} ffb_wid_pool_t; 342 343typedef struct ffb_dac_info { 344 unsigned int flags; 345#define FFB_DAC_PAC1 0x00000001 /* Pacifica1 DAC, BT9068 */ 346#define FFB_DAC_PAC2 0x00000002 /* Pacifica2 DAC, BT498 */ 347#define FFB_DAC_ICURCTL 0x00000004 /* Inverted CUR_CTRL bits */ 348 349 unsigned int kernel_wid; 350 351 /* These registers need to be modified when changing DAC 352 * timing state, so at init time we capture their values. 353 */ 354 unsigned int ffbcfg0; 355 unsigned int ffbcfg2; 356 unsigned int ffb_passin_ctrl; /* FFB2+/AFB only */ 357 358 ffb_dac_hwstate_t kern_dac_state; 359 ffb_dac_hwstate_t x_dac_state; 360 361 ffb_wid_pool_t wid_table; 362} ffb_dac_info_t; 363 364#endif /* _FFB_DAC_H */ 365