17706df26Smrg/*
27706df26Smrg * Copyright 1998 by Alan Hourihane, Wigan, England.
37706df26Smrg *
47706df26Smrg * Permission to use, copy, modify, distribute, and sell this software and its
57706df26Smrg * documentation for any purpose is hereby granted without fee, provided that
67706df26Smrg * the above copyright notice appear in all copies and that both that
77706df26Smrg * copyright notice and this permission notice appear in supporting
87706df26Smrg * documentation, and that the name of Alan Hourihane not be used in
97706df26Smrg * advertising or publicity pertaining to distribution of the software without
107706df26Smrg * specific, written prior permission.  Alan Hourihane makes no representations
117706df26Smrg * about the suitability of this software for any purpose.  It is provided
127706df26Smrg * "as is" without express or implied warranty.
137706df26Smrg *
147706df26Smrg * ALAN HOURIHANE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
157706df26Smrg * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
167706df26Smrg * EVENT SHALL ALAN HOURIHANE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
177706df26Smrg * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
187706df26Smrg * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
197706df26Smrg * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
207706df26Smrg * PERFORMANCE OF THIS SOFTWARE.
217706df26Smrg *
227706df26Smrg * Authors:  Alan Hourihane, <alanh@fairlite.demon.co.uk>
237706df26Smrg *
247706df26Smrg * tgaBTOutIndReg() and tgaBTInIndReg() are used to access
257706df26Smrg * the indirect TGA BT RAMDAC registers only.
267706df26Smrg */
277706df26Smrg
287706df26Smrg#ifdef HAVE_CONFIG_H
297706df26Smrg#include "config.h"
307706df26Smrg#endif
317706df26Smrg
327706df26Smrg#include "xf86.h"
337706df26Smrg#include "xf86_OSproc.h"
347706df26Smrg
357706df26Smrg#include "xf86PciInfo.h"
367706df26Smrg#include "xf86Pci.h"
377706df26Smrg
387706df26Smrg#include "tga_regs.h"
397706df26Smrg#include "BT.h"
407706df26Smrg#include "tga.h"
417706df26Smrg
427706df26Smrgvoid
437706df26SmrgtgaBTOutIndReg(ScrnInfoPtr pScrn,
447706df26Smrg		     CARD32 reg, unsigned char mask, unsigned char data)
457706df26Smrg{
467706df26Smrg  TGAPtr pTga;
477706df26Smrg  unsigned char tmp = 0x00;
487706df26Smrg
497706df26Smrg  pTga = TGAPTR(pScrn);
507706df26Smrg
517706df26Smrg  TGA_WRITE_REG(reg << 1 | BT485_READ_BIT, TGA_RAMDAC_SETUP_REG);
527706df26Smrg
537706df26Smrg  if (mask != 0x00)
547706df26Smrg    tmp = (TGA_READ_REG(TGA_RAMDAC_REG)>>16) & mask;
557706df26Smrg
567706df26Smrg  TGA_WRITE_REG(reg << 1 | BT485_WRITE_BIT, TGA_RAMDAC_SETUP_REG);
577706df26Smrg
587706df26Smrg  TGA_WRITE_REG ((tmp | data) | (reg<<9), TGA_RAMDAC_REG);
597706df26Smrg}
607706df26Smrg
617706df26Smrgunsigned char
627706df26SmrgtgaBTInIndReg (ScrnInfoPtr pScrn, CARD32 reg)
637706df26Smrg{
647706df26Smrg  TGAPtr pTga;
657706df26Smrg  unsigned char ret;
667706df26Smrg
677706df26Smrg  pTga  = TGAPTR(pScrn);
687706df26Smrg
697706df26Smrg  TGA_WRITE_REG(reg << 1 | BT485_READ_BIT, TGA_RAMDAC_SETUP_REG);
707706df26Smrg  ret = TGA_READ_REG (TGA_RAMDAC_REG)>>16;
717706df26Smrg
727706df26Smrg  return (ret);
737706df26Smrg}
747706df26Smrg
757706df26Smrgvoid
767706df26SmrgtgaBTWriteAddress (ScrnInfoPtr pScrn, CARD32 index)
777706df26Smrg{
787706df26Smrg    TGAPtr pTga;
797706df26Smrg
807706df26Smrg    pTga = TGAPTR(pScrn);
817706df26Smrg
827706df26Smrg    TGA_WRITE_REG(BT_WRITE_ADDR << 1 | BT485_WRITE_BIT, TGA_RAMDAC_SETUP_REG);
837706df26Smrg    TGA_WRITE_REG(index | (BT_WRITE_ADDR<<9), TGA_RAMDAC_REG);
847706df26Smrg    TGA_WRITE_REG(BT_RAMDAC_DATA << 1 | BT485_WRITE_BIT, TGA_RAMDAC_SETUP_REG);
857706df26Smrg}
867706df26Smrg
877706df26Smrgvoid
887706df26SmrgtgaBTWriteData (ScrnInfoPtr pScrn, unsigned char data)
897706df26Smrg{
907706df26Smrg    TGAPtr pTga;
917706df26Smrg
927706df26Smrg    pTga = TGAPTR(pScrn);
937706df26Smrg
947706df26Smrg    TGA_WRITE_REG(data | (BT_RAMDAC_DATA << 9), TGA_RAMDAC_REG);
957706df26Smrg}
967706df26Smrg
977706df26Smrgvoid
987706df26SmrgtgaBTReadAddress (ScrnInfoPtr pScrn, CARD32 index)
997706df26Smrg{
1007706df26Smrg    TGAPtr pTga;
1017706df26Smrg
1027706df26Smrg    pTga = TGAPTR(pScrn);
1037706df26Smrg
1047706df26Smrg    TGA_WRITE_REG(BT_PIXEL_MASK << 1 | BT485_WRITE_BIT, TGA_RAMDAC_SETUP_REG);
1057706df26Smrg    TGA_WRITE_REG(0xFF | (BT_PIXEL_MASK<<9), TGA_RAMDAC_REG);
1067706df26Smrg    TGA_WRITE_REG(BT_READ_ADDR << 1 | BT485_WRITE_BIT, TGA_RAMDAC_SETUP_REG);
1077706df26Smrg    TGA_WRITE_REG(index | (BT_READ_ADDR<<9), TGA_RAMDAC_REG);
1087706df26Smrg    TGA_WRITE_REG(BT_RAMDAC_DATA << 1 | BT485_READ_BIT, TGA_RAMDAC_SETUP_REG);
1097706df26Smrg}
1107706df26Smrg
1117706df26Smrgunsigned char
1127706df26SmrgtgaBTReadData (ScrnInfoPtr pScrn)
1137706df26Smrg{
1147706df26Smrg    TGAPtr pTga;
1157706df26Smrg
1167706df26Smrg    pTga = TGAPTR(pScrn);
1177706df26Smrg
1187706df26Smrg    return(TGA_READ_REG(TGA_RAMDAC_REG)>>16);
1197706df26Smrg}
1207706df26Smrg
1217706df26Smrg/********************* TGA2 stuff below here ********************/
1227706df26Smrg
1237706df26Smrgvoid
1247706df26Smrgtga2BTOutIndReg(ScrnInfoPtr pScrn,
1257706df26Smrg		     CARD32 reg, unsigned char mask, unsigned char data)
1267706df26Smrg{
1277706df26Smrg  TGAPtr pTga;
1287706df26Smrg  unsigned char tmp = 0x00;
1297706df26Smrg  unsigned int addr = 0xe000U | (reg << 8);
1307706df26Smrg
1317706df26Smrg  pTga = TGAPTR(pScrn);
1327706df26Smrg
1337706df26Smrg  if (mask != 0x00)
1347706df26Smrg    tmp = TGA2_READ_RAMDAC_REG(addr) & mask;
1357706df26Smrg
1367706df26Smrg#if 0
1377706df26Smrg  xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "tga2OutIndReg: reg 0x%x data 0x%x\n",
1387706df26Smrg	     reg, tmp|data);
1397706df26Smrg#endif
1407706df26Smrg  TGA2_WRITE_RAMDAC_REG ((tmp | data), addr);
1417706df26Smrg}
1427706df26Smrg
1437706df26Smrgunsigned char
1447706df26Smrgtga2BTInIndReg (ScrnInfoPtr pScrn, CARD32 reg)
1457706df26Smrg{
1467706df26Smrg  TGAPtr pTga;
1477706df26Smrg  unsigned char ret;
1487706df26Smrg  unsigned int addr = 0xe000U | (reg << 8);
1497706df26Smrg
1507706df26Smrg  pTga  = TGAPTR(pScrn);
1517706df26Smrg
1527706df26Smrg  ret = TGA2_READ_RAMDAC_REG(addr);
1537706df26Smrg
1547706df26Smrg  return (ret);
1557706df26Smrg}
1567706df26Smrg
1577706df26Smrgvoid
1587706df26Smrgtga2BTWriteAddress (ScrnInfoPtr pScrn, CARD32 index)
1597706df26Smrg{
1607706df26Smrg    tga2BTOutIndReg(pScrn, BT_WRITE_ADDR, 0, index);
1617706df26Smrg}
1627706df26Smrg
1637706df26Smrgvoid
1647706df26Smrgtga2BTWriteData (ScrnInfoPtr pScrn, unsigned char data)
1657706df26Smrg{
1667706df26Smrg    tga2BTOutIndReg(pScrn, BT_RAMDAC_DATA, 0, data);
1677706df26Smrg}
1687706df26Smrg
1697706df26Smrgvoid
1707706df26Smrgtga2BTReadAddress (ScrnInfoPtr pScrn, CARD32 index)
1717706df26Smrg{
1727706df26Smrg    tga2BTOutIndReg(pScrn, BT_PIXEL_MASK, 0, 0xff);
1737706df26Smrg    tga2BTOutIndReg(pScrn, BT_READ_ADDR, 0, index);
1747706df26Smrg}
1757706df26Smrg
1767706df26Smrgunsigned char
1777706df26Smrgtga2BTReadData (ScrnInfoPtr pScrn)
1787706df26Smrg{
1797706df26Smrg    return tga2BTInIndReg(pScrn, BT_RAMDAC_DATA);
1807706df26Smrg}
181