tga_dac.c revision 7706df26
17706df26Smrg/* 27706df26Smrg * Copyright 1997,1998 by Alan Hourihane <alanh@fairlite.demon.co.uk> 37706df26Smrg * 47706df26Smrg * Permission to use, copy, modify, distribute, and sell this software and its 57706df26Smrg * documentation for any purpose is hereby granted without fee, provided that 67706df26Smrg * the above copyright notice appear in all copies and that both that 77706df26Smrg * copyright notice and this permission notice appear in supporting 87706df26Smrg * documentation, and that the name of Alan Hourihane not be used in 97706df26Smrg * advertising or publicity pertaining to distribution of the software without 107706df26Smrg * specific, written prior permission. Alan Hourihane makes no representations 117706df26Smrg * about the suitability of this software for any purpose. It is provided 127706df26Smrg * "as is" without express or implied warranty. 137706df26Smrg * 147706df26Smrg * ALAN HOURIHANE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 157706df26Smrg * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 167706df26Smrg * EVENT SHALL ALAN HOURIHANE BE LIABLE FOR ANY SPECIAL, INDIRECT OR 177706df26Smrg * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 187706df26Smrg * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 197706df26Smrg * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 207706df26Smrg * PERFORMANCE OF THIS SOFTWARE. 217706df26Smrg * 227706df26Smrg * Authors: Alan Hourihane, <alanh@fairlite.demon.co.uk> 237706df26Smrg */ 247706df26Smrg/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/tga/tga_dac.c,v 1.13 2001/02/17 14:18:30 tsi Exp $ */ 257706df26Smrg 267706df26Smrg#ifdef HAVE_CONFIG_H 277706df26Smrg#include "config.h" 287706df26Smrg#endif 297706df26Smrg 307706df26Smrg#include "xf86.h" 317706df26Smrg#include "xf86_OSproc.h" 327706df26Smrg 337706df26Smrg#include "xf86PciInfo.h" 347706df26Smrg#include "xf86Pci.h" 357706df26Smrg 367706df26Smrg#include "BT.h" 377706df26Smrg#include "tga_regs.h" 387706df26Smrg#include "tga.h" 397706df26Smrg 407706df26Smrgstatic void ICS1562ClockSelect(ScrnInfoPtr pScrn, int freq); 417706df26Smrgstatic void ICS9110ClockSelect(ScrnInfoPtr pScrn, int freq); 427706df26Smrgextern void ICS1562_CalcClockBits(long f, unsigned char *bits); 437706df26Smrg 447706df26Smrgstatic void 457706df26SmrgICS1562ClockSelect(ScrnInfoPtr pScrn, int freq) 467706df26Smrg{ 477706df26Smrg TGAPtr pTga = TGAPTR(pScrn); 487706df26Smrg unsigned char pll_bits[7]; 497706df26Smrg unsigned long temp; 507706df26Smrg int i, j; 517706df26Smrg 527706df26Smrg /* There lies an ICS1562 Clock Generator. */ 537706df26Smrg ICS1562_CalcClockBits(freq, pll_bits); 547706df26Smrg 557706df26Smrg /* 567706df26Smrg * For the DEC 21030 TGA: 577706df26Smrg * This requires the 55 clock bits be written in a serial manner to 587706df26Smrg * bit 0 of the CLOCK register and on the 56th bit set the hold flag. 597706df26Smrg */ 607706df26Smrg for (i = 0;i <= 6; i++) { 617706df26Smrg for (j = 0; j <= 7; j++) { 627706df26Smrg temp = (pll_bits[i] >> (7-j)) & 1; 637706df26Smrg if (i == 6 && j == 7) 647706df26Smrg temp |= 2; 657706df26Smrg TGA_WRITE_REG(temp, TGA_CLOCK_REG); 667706df26Smrg } 677706df26Smrg } 687706df26Smrg} 697706df26Smrg 707706df26Smrgstruct monitor_data tga_crystal_table[] = { 717706df26Smrg{ 727706df26Smrg/* Option 0 Monitor Info 130.8 */ 737706df26Smrg1024, /* rows */ 747706df26Smrg1280, /* columns */ 757706df26Smrg130, /* 130.8 Mhz */ 767706df26Smrg72, /* refresh rate */ 777706df26Smrg1024, /* v scanlines */ 787706df26Smrg3, /* v front porch */ 797706df26Smrg3, /* v sync */ 807706df26Smrg33, /* v back porch */ 817706df26Smrg1280, /* h pixels */ 827706df26Smrg32, /* h front porch */ 837706df26Smrg160, /* h sync */ 847706df26Smrg232, /* h back porch */ 857706df26Smrg/* AV9110 clock serial load information 130.808 */ 867706df26Smrg0x40, /* 0:6 VCO frequency divider N */ 877706df26Smrg0x7, /* 7:13 Reference frequency divide M */ 887706df26Smrg0x0, /* 14 VCO pre-scale divide V (0=div.by 1,1=by 8) 897706df26Smrg*/ 907706df26Smrg0x1, /* 15:16 CLK/X output divide X */ 917706df26Smrg0x1, /* 17:18 VCO output divide R */ 927706df26Smrg1, /* 19 CLK Output enable. */ 937706df26Smrg1, /* 20 CLK/X Output enable */ 947706df26Smrg0, /* reserved, should be set to 0 */ 957706df26Smrg0, /* Reference clock select on CLK 1=ref */ 967706df26Smrg1, /* reserved, should be set to 1 */ 977706df26Smrg/* IBM561 PLL setup data 130.808 */ 987706df26Smrg0xC8, /* VCO Div: PFR=0x3, M-65=49 */ 997706df26Smrg0x8 /* REF: N=0x8 */ 1007706df26Smrg}, 1017706df26Smrg{ 1027706df26Smrg/* Option 3 Monitor Info 104.00 Mhz */ 1037706df26Smrg900, /* rows */ 1047706df26Smrg1152, /* columns */ 1057706df26Smrg104, /* 104 Mhz */ 1067706df26Smrg72, /* refresh rate */ 1077706df26Smrg900, /* v scanlines */ 1087706df26Smrg6, /* v front porch */ 1097706df26Smrg10, /* v sync */ 1107706df26Smrg44, /* v back porch */ 1117706df26Smrg1152, /* h pixels */ 1127706df26Smrg64, /* h front porch */ 1137706df26Smrg112, /* h sync */ 1147706df26Smrg176, /* h back porch */ 1157706df26Smrg/* 103.994 MHz av9110 clock serial load information */ 1167706df26Smrg0x6d, /* 0:6 VCO frequency divider N */ 1177706df26Smrg0xf, /* 7:13 Reference frequency divide M */ 1187706df26Smrg0x0, /* 14 VCO pre-scale divide V (0=div.by 1,1=by 8) 1197706df26Smrg*/ 1207706df26Smrg0x1, /* 15:16 CLK/X output divide X */ 1217706df26Smrg0x1, /* 17:18 VCO output divide R */ 1227706df26Smrg1, /* 19 CLK Output enable. */ 1237706df26Smrg1, /* 20 CLK/X Output enable */ 1247706df26Smrg0, /* reserved, should be set to 0 */ 1257706df26Smrg0, /* Reference clock select on CLK 1=ref */ 1267706df26Smrg1, /* reserved, should be set to 1 */ 1277706df26Smrg/* 104.00 MHz IBM561 PLL setup data */ 1287706df26Smrg0x96, /* VCO Div: PFR=2, M=57 */ 1297706df26Smrg0x6 /* REF: N=6 */ 1307706df26Smrg}, 1317706df26Smrg#if 1 1327706df26Smrg{ 1337706df26Smrg/* Option 6 Monitor Info 74.00 Mhz */ 1347706df26Smrg768, /* rows */ 1357706df26Smrg1024, /* columns */ 1367706df26Smrg74, /* 74 Mhz */ 1377706df26Smrg72, /* refresh rate */ 1387706df26Smrg768, /* v scanlines */ 1397706df26Smrg1, /* v front porch */ 1407706df26Smrg6, /* v sync */ 1417706df26Smrg22, /* v back porch */ 1427706df26Smrg1024, /* h pixels */ 1437706df26Smrg16, /* h front porch */ 1447706df26Smrg128, /* h sync */ 1457706df26Smrg128, /* h back porch */ 1467706df26Smrg/* 74.00 MHz AV9110 clock serial load information */ 1477706df26Smrg0x2a, /* 0:6 VCO frequency divider N */ 1487706df26Smrg0x41, /* 7:13 Reference frequency divide M */ 1497706df26Smrg0x1, /* 14 VCO pre-scale divide V (0=div.by 1,1=by 8) 1507706df26Smrg*/ 1517706df26Smrg0x1, /* 15:16 CLK/X output divide X */ 1527706df26Smrg0x1, /* 17:18 VCO output divide R */ 1537706df26Smrg1, /* 19 CLK Output enable. */ 1547706df26Smrg1, /* 20 CLK/X Output enable */ 1557706df26Smrg0, /* reserved, should be set to 0 */ 1567706df26Smrg0, /* Reference clock select on CLK 1=ref */ 1577706df26Smrg1, /* reserved, should be set to 1 */ 1587706df26Smrg/* 74.00 MHz IBM561 PLL setup data */ 1597706df26Smrg0x9C, /* VCO Div: PFR=2, M=0x5D*/ 1607706df26Smrg0x9 /* REF: N=0x9 */ 1617706df26Smrg}, 1627706df26Smrg#else 1637706df26Smrg{ 1647706df26Smrg/* Option 5 Monitor Info 75.00 Mhz */ 1657706df26Smrg768, /* rows */ 1667706df26Smrg1024, /* columns */ 1677706df26Smrg75, /* 74 Mhz */ 1687706df26Smrg70, /* refresh rate */ 1697706df26Smrg768, /* v scanlines */ 1707706df26Smrg3, /* v front porch */ 1717706df26Smrg6, /* v sync */ 1727706df26Smrg29, /* v back porch */ 1737706df26Smrg1024, /* h pixels */ 1747706df26Smrg24, /* h front porch */ 1757706df26Smrg136, /* h sync */ 1767706df26Smrg144, /* h back porch */ 1777706df26Smrg/* 75.00 MHz AV9110 clock serial load information */ 1787706df26Smrg0x6e, /* 0:6 VCO frequency divider N */ 1797706df26Smrg0x15, /* 7:13 Reference frequency divide M */ 1807706df26Smrg0x0, /* 14 VCO pre-scale divide V (0=div.by 1,1=by 8) 1817706df26Smrg*/ 1827706df26Smrg0x1, /* 15:16 CLK/X output divide X */ 1837706df26Smrg0x1, /* 17:18 VCO output divide R */ 1847706df26Smrg1, /* 19 CLK Output enable. */ 1857706df26Smrg1, /* 20 CLK/X Output enable */ 1867706df26Smrg0, /* reserved, should be set to 0 */ 1877706df26Smrg0, /* Reference clock select on CLK 1=ref */ 1887706df26Smrg1, /* reserved, should be set to 1 */ 1897706df26Smrg/* 75.00 MHz IBM561 PLL setup data */ 1907706df26Smrg0x93, /* VCO Div: PFR=2, M=0x54 */ 1917706df26Smrg0x8 /* REF: N=0x8 */ 1927706df26Smrg}, 1937706df26Smrg#endif 1947706df26Smrg{ 1957706df26Smrg/* Option 9 Monitor Info 50 Mhz ergo SVGA */ 1967706df26Smrg600, /* rows */ 1977706df26Smrg800, /* columns */ 1987706df26Smrg50, /* 50 Mhz */ 1997706df26Smrg72, /* refresh rate */ 2007706df26Smrg600, /* v scanlines */ 2017706df26Smrg37, /*(31 tga)v front porch */ 2027706df26Smrg6, /* v sync */ 2037706df26Smrg23, /*(29 tga)v back porch */ 2047706df26Smrg800, /* h pixels */ 2057706df26Smrg56, /* h front porch */ 2067706df26Smrg120, /* h sync */ 2077706df26Smrg64, /* h back porch */ 2087706df26Smrg/*50.00 Mhz AV9110 clock serial load information */ 2097706df26Smrg0x37, /* 0:6 VCO frequency divider N */ 2107706df26Smrg0x3f, /* 7:13 Reference frequency divide M */ 2117706df26Smrg0x1, /* 14 VCO pre-scale divide V (0=div.by 1,1=by 8) 2127706df26Smrg*/ 2137706df26Smrg0x1, /* 15:16 CLK/X output divide X */ 2147706df26Smrg0x2, /* 17:18 VCO output divide R */ 2157706df26Smrg1, /* 19 CLK Output enable. */ 2167706df26Smrg1, /* 20 CLK/X Output enable */ 2177706df26Smrg0, /* reserved, should be set to 0 */ 2187706df26Smrg0, /* Reference clock select on CLK 1=ref */ 2197706df26Smrg1, /* reserved, should be set to 1 */ 2207706df26Smrg/* 50.00 MHz IBM561 PLL setup data */ 2217706df26Smrg0x45, /* VCO Div: PFR=1, M=46*/ 2227706df26Smrg0x5 /* REF: N=5 */ 2237706df26Smrg}, 2247706df26Smrg{ 2257706df26Smrg/* Option B Monitor Info 31.5 Mhz ergo VGA */ 2267706df26Smrg480, /* rows */ 2277706df26Smrg640, /* columns */ 2287706df26Smrg32, /* 32 Mhz */ 2297706df26Smrg72, /* refresh rate */ 2307706df26Smrg480, /* v scanlines */ 2317706df26Smrg9, /* v front porch */ 2327706df26Smrg3, /* v sync */ 2337706df26Smrg28, /* v back porch */ 2347706df26Smrg640, /* h pixels */ 2357706df26Smrg24, /* h front porch */ 2367706df26Smrg40, /* h sync */ 2377706df26Smrg128, /* h back porch */ 2387706df26Smrg/* 31.50 MHz AV9110 clock serial load information */ 2397706df26Smrg0x16, /* 0:6 VCO frequency divider N */ 2407706df26Smrg0x05, /* 7:13 Reference frequency divide M */ 2417706df26Smrg0x0, /* 14 VCO pre-scale divide V (0=div.by 1,1=by 8) 2427706df26Smrg*/ 2437706df26Smrg0x1, /* 15:16 CLK/X output divide X */ 2447706df26Smrg0x2, /* 17:18 VCO output divide R */ 2457706df26Smrg1, /* 19 CLK Output enable. */ 2467706df26Smrg1, /* 20 CLK/X Output enable */ 2477706df26Smrg0, /* reserved, should be set to 0 */ 2487706df26Smrg0, /* Reference clock select on CLK 1=ref */ 2497706df26Smrg1, /* reserved, should be set to 1 */ 2507706df26Smrg/* 31.50 MHz IBM561 PLL setup data */ 2517706df26Smrg0x17, /* VCO Div: PFR=0, M=0x58 */ 2527706df26Smrg0x5 /* REF: N=0x5 */ 2537706df26Smrg}, 2547706df26Smrg#ifdef ALLOW_LT_72_HZ 2557706df26Smrg{ 2567706df26Smrg/* Option 1 Monitor Info 119.84 Mhz */ 2577706df26Smrg1024, /* rows */ 2587706df26Smrg1280, /* columns */ 2597706df26Smrg119, /* 119 Mhz */ 2607706df26Smrg66, /* refresh rate */ 2617706df26Smrg1024, /* v scanlines */ 2627706df26Smrg3, /* v front porch */ 2637706df26Smrg3, /* v sync */ 2647706df26Smrg33, /* v back porch */ 2657706df26Smrg1280, /* h pixels */ 2667706df26Smrg32, /* h front porch */ 2677706df26Smrg160, /* h sync */ 2687706df26Smrg232, /* h back porch */ 2697706df26Smrg/* 119.84MHz AV9110 clock serial load information */ 2707706df26Smrg0x2d, /* 0:6 VCO frequency divider N */ 2717706df26Smrg0x2b, /* 7:13 Reference frequency divide M */ 2727706df26Smrg0x1, /* 14 VCO pre-scale divide V (0=div.by 1,1=by 8) */ 2737706df26Smrg0x1, /* 15:16 CLK/X output divide X */ 2747706df26Smrg0x1, /* 17:18 VCO output divide R */ 2757706df26Smrg1, /* 19 CLK Output enable. */ 2767706df26Smrg1, /* 20 CLK/X Output enable */ 2777706df26Smrg0, /* reserved, should be set to 0 */ 2787706df26Smrg0, /* Reference clock select on CLK 1=ref */ 2797706df26Smrg1, /* reserved, should be set to 1 */ 2807706df26Smrg/* IBM561 PLL setup data 119.84 */ 2817706df26Smrg0x82, /* VCO Div: PFR=0x2, M=0x43 */ 2827706df26Smrg0x4 /* REF: N=0x4 */ 2837706df26Smrg}, 2847706df26Smrg{ 2857706df26Smrg/* Option 2 Monitor Info 108.18 Mhz */ 2867706df26Smrg1024, /* rows */ 2877706df26Smrg1280, /* columns */ 2887706df26Smrg108, /* 108 Mhz */ 2897706df26Smrg60, /* refresh rate */ 2907706df26Smrg1024, /* v scanlines */ 2917706df26Smrg3, /* v front porch */ 2927706df26Smrg3, /* v sync */ 2937706df26Smrg26, /* v back porch */ 2947706df26Smrg1280, /* h pixels */ 2957706df26Smrg44, /* h front porch */ 2967706df26Smrg184, /* h sync */ 2977706df26Smrg200, /* h back porch */ 2987706df26Smrg/* 108.18 MHz av9110 Clk serial load information */ 2997706df26Smrg0x11, /* 0:6 VCO frequency divider N */ 3007706df26Smrg0x9, /* 7:13 Reference frequency divide M */ 3017706df26Smrg0x1, /* 14 VCO pre-scale divide V (0=div.by 1,1=by 8) 3027706df26Smrg*/ 3037706df26Smrg0x1, /* 15:16 CLK/X output divide X */ 3047706df26Smrg0x2, /* 17:18 VCO output divide R */ 3057706df26Smrg1, /* 19 CLK Output enable. */ 3067706df26Smrg1, /* 20 CLK/X Output enable */ 3077706df26Smrg0, /* reserved, should be set to 0 */ 3087706df26Smrg0, /* Reference clock select on CLK 1=ref */ 3097706df26Smrg1, /* reserved, should be set to 1 */ 3107706df26Smrg/* 108.18 MHz IBM561 PLL setup data */ 3117706df26Smrg0xB8, /* VCO Div: PFR=2, M=79 */ 3127706df26Smrg0x8 /* REF: N=0x8 */ 3137706df26Smrg}, 3147706df26Smrg{ 3157706df26Smrg/* Option 5 Monitor Info 75.00 Mhz */ 3167706df26Smrg768, /* rows */ 3177706df26Smrg1024, /* columns */ 3187706df26Smrg75, /* 74 Mhz */ 3197706df26Smrg70, /* refresh rate */ 3207706df26Smrg768, /* v scanlines */ 3217706df26Smrg3, /* v front porch */ 3227706df26Smrg6, /* v sync */ 3237706df26Smrg29, /* v back porch */ 3247706df26Smrg1024, /* h pixels */ 3257706df26Smrg24, /* h front porch */ 3267706df26Smrg136, /* h sync */ 3277706df26Smrg144, /* h back porch */ 3287706df26Smrg/* 75.00 MHz AV9110 clock serial load information */ 3297706df26Smrg0x6e, /* 0:6 VCO frequency divider N */ 3307706df26Smrg0x15, /* 7:13 Reference frequency divide M */ 3317706df26Smrg0x0, /* 14 VCO pre-scale divide V (0=div.by 1,1=by 8) 3327706df26Smrg*/ 3337706df26Smrg0x1, /* 15:16 CLK/X output divide X */ 3347706df26Smrg0x1, /* 17:18 VCO output divide R */ 3357706df26Smrg1, /* 19 CLK Output enable. */ 3367706df26Smrg1, /* 20 CLK/X Output enable */ 3377706df26Smrg0, /* reserved, should be set to 0 */ 3387706df26Smrg0, /* Reference clock select on CLK 1=ref */ 3397706df26Smrg1, /* reserved, should be set to 1 */ 3407706df26Smrg/* 75.00 MHz IBM561 PLL setup data */ 3417706df26Smrg0x93, /* VCO Div: PFR=2, M=0x54 */ 3427706df26Smrg0x8 /* REF: N=0x8 */ 3437706df26Smrg}, 3447706df26Smrg{ 3457706df26Smrg/* Option 7 Monitor Info 69 Mhz DEC 72 Hz */ 3467706df26Smrg864, /* rows */ 3477706df26Smrg1024, /* columns */ 3487706df26Smrg69, /* 69.x Mhz */ 3497706df26Smrg60, /* refresh rate */ 3507706df26Smrg864, /* v scanlines */ 3517706df26Smrg0, /* v front porch */ 3527706df26Smrg3, /* v sync */ 3537706df26Smrg34, /* v back porch */ 3547706df26Smrg1024, /* h pixels */ 3557706df26Smrg12, /* h front porch */ 3567706df26Smrg128, /* h sync */ 3577706df26Smrg116, /* h back porch */ 3587706df26Smrg/* 69.00 Mhz AV9110 clock serial load information */ 3597706df26Smrg0x35, /* 0:6 VCO frequency divider N */ 3607706df26Smrg0xb, /* 7:13 Reference frequency divide M */ 3617706df26Smrg0x0, /* 14 VCO pre-scale divide V (0=div.by 1,1=by 8) 3627706df26Smrg*/ 3637706df26Smrg0x1, /* 15:16 CLK/X output divide X */ 3647706df26Smrg0x1, /* 17:18 VCO output divide R */ 3657706df26Smrg1, /* 19 CLK Output enable. */ 3667706df26Smrg1, /* 20 CLK/X Output enable */ 3677706df26Smrg0, /* reserved, should be set to 0 */ 3687706df26Smrg0, /* Reference clock select on CLK 1=ref */ 3697706df26Smrg1, /* reserved, should be set to 1 */ 3707706df26Smrg/* 69.00 MHz IBM561 PLL setup data */ 3717706df26Smrg0xA9, /* VCO Div: PFR=2, M=0x6A */ 3727706df26Smrg0xB /* REF: N=0xB */ 3737706df26Smrg}, 3747706df26Smrg{ 3757706df26Smrg/* Option 8 Monitor Info 65 Mhz */ 3767706df26Smrg768, /* rows */ 3777706df26Smrg1024, /* columns */ 3787706df26Smrg65, /* 65 Mhz */ 3797706df26Smrg60, /* refresh rate */ 3807706df26Smrg768, /* v scanlines */ 3817706df26Smrg7, /* v front porch */ 3827706df26Smrg9, /* v sync */ 3837706df26Smrg26, /* v back porch */ 3847706df26Smrg1024, /* h pixels */ 3857706df26Smrg56, /* h front porch */ 3867706df26Smrg64, /* h sync */ 3877706df26Smrg200, /* h back porch */ 3887706df26Smrg/* 65.00 MHz AV9110 clock serial load information */ 3897706df26Smrg0x6d, /* 0:6 VCO frequency divider N */ 3907706df26Smrg0x0c, /* 7:13 Reference frequency divide M */ 3917706df26Smrg0x0, /* 14 VCO pre-scale divide V (0=div.by 1,1=by 8) 3927706df26Smrg*/ 3937706df26Smrg0x1, /* 15:16 CLK/X output divide X */ 3947706df26Smrg0x2, /* 17:18 VCO output divide R */ 3957706df26Smrg1, /* 19 CLK Output enable. */ 3967706df26Smrg1, /* 20 CLK/X Output enable */ 3977706df26Smrg0, /* reserved, should be set to 0 */ 3987706df26Smrg0, /* Reference clock select on CLK 1=ref */ 3997706df26Smrg1, /* reserved, should be set to 1 */ 4007706df26Smrg/* 65.00 MHz IBM561 PLL setup data */ 4017706df26Smrg0xAC, /* VCO Div: PFR=2, M=0x6D */ 4027706df26Smrg0xC /* REF: N=0xC */ 4037706df26Smrg}, 4047706df26Smrg{ 4057706df26Smrg/* Option A Monitor Info 40 Mhz SVGA */ 4067706df26Smrg600, /* rows */ 4077706df26Smrg800, /* columns */ 4087706df26Smrg40, /* 40 Mhz */ 4097706df26Smrg60, /* refresh rate */ 4107706df26Smrg600, /* v scanlines */ 4117706df26Smrg1, /* v front porch */ 4127706df26Smrg4, /* v sync */ 4137706df26Smrg23, /* v back porch */ 4147706df26Smrg800, /* h pixels */ 4157706df26Smrg40, /* h front porch */ 4167706df26Smrg128, /* h sync */ 4177706df26Smrg88, /* h back porch */ 4187706df26Smrg/* 40.00 MHz AV9110 clock serial load information */ 4197706df26Smrg0x5f, /* 0:6 VCO frequency divider N */ 4207706df26Smrg0x11, /* 7:13 Reference frequency divide M */ 4217706df26Smrg0x0, /* 14 VCO pre-scale divide V (0=div.by 1,1=by 8) 4227706df26Smrg*/ 4237706df26Smrg0x1, /* 15:16 CLK/X output divide X */ 4247706df26Smrg0x2, /* 17:18 VCO output divide R */ 4257706df26Smrg1, /* 19 CLK Output enable. */ 4267706df26Smrg1, /* 20 CLK/X Output enable */ 4277706df26Smrg0, /* reserved, should be set to 0 */ 4287706df26Smrg0, /* Reference clock select on CLK 1=ref */ 4297706df26Smrg1, /* reserved, should be set to 1 */ 4307706df26Smrg/* 40.00 MHz IBM561 PLL setup data */ 4317706df26Smrg0x42, /* VCO Div: PFR=1, M=43 */ 4327706df26Smrg0x6 /* REF: N=0x6 */ 4337706df26Smrg}, 4347706df26Smrg{ 4357706df26Smrg/* Option C Monitor Info 25.175 Mhz VGA */ 4367706df26Smrg480, /* rows */ 4377706df26Smrg640, /* columns */ 4387706df26Smrg25, /* 25.175 Mhz */ 4397706df26Smrg60, /* refresh rate */ 4407706df26Smrg480, /* v scanlines */ 4417706df26Smrg10, /* v front porch */ 4427706df26Smrg2, /* v sync */ 4437706df26Smrg33, /* v back porch */ 4447706df26Smrg640, /* h pixels */ 4457706df26Smrg16, /* h front porch */ 4467706df26Smrg96, /* h sync */ 4477706df26Smrg48, /* h back porch */ 4487706df26Smrg/* 25.175 MHz AV9110 clock serial load information */ 4497706df26Smrg0x66, /* 0:6 VCO frequency divider N */ 4507706df26Smrg0x1d, /* 7:13 Reference frequency divide M */ 4517706df26Smrg0x0, /* 14 VCO pre-scale divide V (0=div.by 1,1=by 8) 4527706df26Smrg*/ 4537706df26Smrg0x1, /* 15:16 CLK/X output divide X */ 4547706df26Smrg0x2, /* 17:18 VCO output divide R */ 4557706df26Smrg1, /* 19 CLK Output enable. */ 4567706df26Smrg1, /* 20 CLK/X Output enable */ 4577706df26Smrg0, /* reserved, should be set to 0 */ 4587706df26Smrg0, /* Reference clock select on CLK 1=ref */ 4597706df26Smrg1, /* reserved, should be set to 1 */ 4607706df26Smrg/* 25.175 MHz IBM561 PLL setup data */ 4617706df26Smrg0x3E, /* VCO Div: PFR=0, M=0x7F */ 4627706df26Smrg0x9 /* REF: N=0x9 */ 4637706df26Smrg}, 4647706df26Smrg{ 4657706df26Smrg/* Option E Monitor Info 110 Mhz */ 4667706df26Smrg1024, /* rows */ 4677706df26Smrg1280, /* columns */ 4687706df26Smrg110, 4697706df26Smrg60, /* refresh rate */ 4707706df26Smrg1024, /* v scanlines */ 4717706df26Smrg6, /* v front porch */ 4727706df26Smrg7, /* v sync */ 4737706df26Smrg44, /* v back porch */ 4747706df26Smrg1280, /* h pixels */ 4757706df26Smrg19, /* h front porch */ 4767706df26Smrg163, /* h sync */ 4777706df26Smrg234, /* h back porch */ 4787706df26Smrg/* 110.0 MHz AV9110 clock serial load information */ 4797706df26Smrg0x60, /* 0:6 VCO frequency divider N */ 4807706df26Smrg0x32, /* 7:13 Reference frequency divide M */ 4817706df26Smrg0x1, /* 14 VCO pre-scale divide V (0=div.by 1,1=by 8) */ 4827706df26Smrg0x1, /* 15:16 CLK/X output divide X */ 4837706df26Smrg0x2, /* 17:18 VCO output divide R */ 4847706df26Smrg1, /* 19 CLK Output enable. */ 4857706df26Smrg1, /* 20 CLK/X Output enable */ 4867706df26Smrg0, /* reserved, should be set to 0 */ 4877706df26Smrg0, /* Reference clock select on CLK 1=ref */ 4887706df26Smrg1, /* reserved, should be set to 1 */ 4897706df26Smrg/* 110.0 MHz IBM561 PLL setup data */ 4907706df26Smrg0xBA, /* VCO Div: PFR=0x2, M=0x7B */ 4917706df26Smrg0x8 /* REF: N=0x8 */ 4927706df26Smrg}, 4937706df26Smrg#endif /* ALLOW_LT_72_HZ */ 4947706df26Smrg#ifdef ALLOW_GT_72_HZ 4957706df26Smrg{ 4967706df26Smrg/* Option D Monitor Info 135 Mhz */ 4977706df26Smrg1024, /* rows */ 4987706df26Smrg1280, /* columns */ 4997706df26Smrg135, /* 135 Mhz */ 5007706df26Smrg75, /* refresh rate */ 5017706df26Smrg1024, /* v scanlines */ 5027706df26Smrg1, /* v front porch */ 5037706df26Smrg3, /* v sync */ 5047706df26Smrg38, /* v back porch */ 5057706df26Smrg1280, /* h pixels */ 5067706df26Smrg16, /* h front porch */ 5077706df26Smrg144, /* h sync */ 5087706df26Smrg248, /* h back porch */ 5097706df26Smrg/* 135.0 MHz AV9110 clock serial load information */ 5107706df26Smrg0x42, /* 0:6 VCO frequency divider N */ 5117706df26Smrg0x07, /* 7:13 Reference frequency divide M */ 5127706df26Smrg0x0, /* 14 VCO pre-scale divide V (0=div.by 1,1=by 8) */ 5137706df26Smrg0x1, /* 15:16 CLK/X output divide X */ 5147706df26Smrg0x1, /* 17:18 VCO output divide R */ 5157706df26Smrg1, /* 19 CLK Output enable. */ 5167706df26Smrg1, /* 20 CLK/X Output enable */ 5177706df26Smrg0, /* reserved, should be set to 0 */ 5187706df26Smrg0, /* Reference clock select on CLK 1=ref */ 5197706df26Smrg1, /* reserved, should be set to 1 */ 5207706df26Smrg/* 135.0 MHz IBM561 PLL setup data */ 5217706df26Smrg0xC1, /* VCO Div: PFR=0x3, M=0x42 */ 5227706df26Smrg0x7 /* REF: N=0x7 */ 5237706df26Smrg}, 5247706df26Smrg#ifdef ALLOW_GT_1280x1024 5257706df26Smrg{ 5267706df26Smrg/* Option 4 Monitor Info 175.5 Mhz (8-plane) */ 5277706df26Smrg1200, /* rows */ 5287706df26Smrg1600, /* columns */ 5297706df26Smrg175, /* clock */ 5307706df26Smrg65, /* refresh rate */ 5317706df26Smrg1200, /* v scanlines */ 5327706df26Smrg1, /* v front porch */ 5337706df26Smrg3, /* v sync */ 5347706df26Smrg46, /* v back porch */ 5357706df26Smrg1600, /* h pixels */ 5367706df26Smrg32, /* h front porch */ 5377706df26Smrg192, /* h sync */ 5387706df26Smrg336, /* h back porch */ 5397706df26Smrg/* 110.0 MHz AV9110 clock serial load information */ 5407706df26Smrg0x5F, /* 0:6 VCO frequency divider N */ 5417706df26Smrg0x3E, /* 7:13 Reference frequency divide M */ 5427706df26Smrg0x1, /* 14 VCO pre-scale divide V (0=div.by 1,1=by 8) 5437706df26Smrg*/ 5447706df26Smrg0x1, /* 15:16 CLK/X output divide X */ 5457706df26Smrg0x1, /* 17:18 VCO output divide R */ 5467706df26Smrg1, /* 19 CLK Output enable. */ 5477706df26Smrg1, /* 20 CLK/X Output enable */ 5487706df26Smrg0, /* reserved, should be set to 0 */ 5497706df26Smrg0, /* Reference clock select on CLK 1=ref */ 5507706df26Smrg1, /* reserved, should be set to 1 */ 5517706df26Smrg/* 110.0 MHz IBM561 PLL setup data */ 5527706df26Smrg0xE1, /* VCO Div: PFR=0x3, M-65=0x21 */ 5537706df26Smrg0x8 /* REF: N=0x8 */ 5547706df26Smrg}, 5557706df26Smrg{ 5567706df26Smrg/* Option F Monitor Info (24-plane) */ 5577706df26Smrg1200, /* rows */ 5587706df26Smrg1600, /* columns */ 5597706df26Smrg202.5, /* 130.8 Mhz */ 5607706df26Smrg75, /* refresh rate */ 5617706df26Smrg1200, /* v scanlines */ 5627706df26Smrg1, /* v front porch */ 5637706df26Smrg3, /* v sync */ 5647706df26Smrg46, /* v back porch */ 5657706df26Smrg1600, /* h pixels */ 5667706df26Smrg32, /* h front porch */ 5677706df26Smrg192, /* h sync */ 5687706df26Smrg336, /* h back porch */ 5697706df26Smrg/* AV9110 clock serial load information 130.808 */ 5707706df26Smrg0x60, /* 0:6 VCO frequency divider N */ 5717706df26Smrg0x32, /* 7:13 Reference frequency divide M */ 5727706df26Smrg0x1, /* 14 VCO pre-scale divide V (0=div.by 1,1=by 8) */ 5737706df26Smrg0x1, /* 15:16 CLK/X output divide X */ 5747706df26Smrg0x2, /* 17:18 VCO output divide R */ 5757706df26Smrg1, /* 19 CLK Output enable. */ 5767706df26Smrg1, /* 20 CLK/X Output enable */ 5777706df26Smrg0, /* reserved, should be set to 0 */ 5787706df26Smrg0, /* Reference clock select on CLK 1=ref */ 5797706df26Smrg1, /* reserved, should be set to 1 */ 5807706df26Smrg/* 110.0 MHz IBM561 PLL setup data */ 5817706df26Smrg0xE2, /* bogus VCO Div: PFR=0x2, M=0x7B */ 5827706df26Smrg0x7 /* bogus REF: N=0x8 */ 5837706df26Smrg} 5847706df26Smrg#endif /* ALLOW_GT_1280x1024 */ 5857706df26Smrg#endif /* ALLOW_GT_72_HZ */ 5867706df26Smrg}; 5877706df26Smrg 5887706df26Smrgint tga_crystal_table_entries = sizeof(tga_crystal_table)/sizeof(struct monitor_data); 5897706df26Smrg 5907706df26Smrgstruct monitor_data *tga_c_table; 5917706df26Smrg 5927706df26Smrg/* ICS av9110 is only used on TGA2 */ 5937706df26Smrg 5947706df26Smrgvoid 5957706df26Smrgwrite_av9110(ScrnInfoPtr pScrn, unsigned int *temp) 5967706df26Smrg{ 5977706df26Smrg TGAPtr pTga = TGAPTR(pScrn); 5987706df26Smrg 5997706df26Smrg /* the following is based on write_av9110() from the 6007706df26Smrg TRU64 kernel TGA driver */ 6017706df26Smrg 6027706df26Smrg TGA2_WRITE_CLOCK_REG(0x0, 0xf800); 6037706df26Smrg TGA2_WRITE_CLOCK_REG(0x0, 0xf000); 6047706df26Smrg 6057706df26Smrg TGA2_WRITE_CLOCK_REG(temp[0], 0x0000); 6067706df26Smrg TGA2_WRITE_CLOCK_REG(temp[1], 0x0000); 6077706df26Smrg TGA2_WRITE_CLOCK_REG(temp[2], 0x0000); 6087706df26Smrg TGA2_WRITE_CLOCK_REG(temp[3], 0x0000); 6097706df26Smrg TGA2_WRITE_CLOCK_REG(temp[4], 0x0000); 6107706df26Smrg TGA2_WRITE_CLOCK_REG(temp[5], 0x0000); 6117706df26Smrg 6127706df26Smrg TGA2_WRITE_CLOCK_REG(0x0, 0xf800); 6137706df26Smrg} 6147706df26Smrg 6157706df26Smrgvoid TGA2SetupMode(ScrnInfoPtr pScrn) 6167706df26Smrg{ 6177706df26Smrg int i; 6187706df26Smrg 6197706df26Smrg /* 6207706df26Smrg * HACK HACK HACK 6217706df26Smrg * 6227706df26Smrg * We do not know how to generate arbitrary clocks, so we search 6237706df26Smrg * the crystal_table above for a match. Sigh... 6247706df26Smrg */ 6257706df26Smrg tga_c_table = tga_crystal_table; 6267706df26Smrg for (i = 0; i < tga_crystal_table_entries; i++, tga_c_table++) { 6277706df26Smrg if ((tga_c_table->max_rows == pScrn->currentMode->VDisplay) && 6287706df26Smrg (tga_c_table->max_cols == pScrn->currentMode->HDisplay)) { 6297706df26Smrg ErrorF("Found a matching mode (%d)!\n", i); 6307706df26Smrg break; 6317706df26Smrg } 6327706df26Smrg } 6337706df26Smrg if (i == tga_crystal_table_entries) { 6347706df26Smrg#ifdef FOR_NOW 6357706df26Smrg FatalError("Unable to find a workable mode"); 6367706df26Smrg#else 6377706df26Smrg ErrorF("Unable to find a matching mode!\n"); 6387706df26Smrg /* tga_c_table = &tga_crystal_table[4]; *//* 640x480 @ 72 */ 6397706df26Smrg tga_c_table = &tga_crystal_table[2]; /* 1024x768 @ 72 */ 6407706df26Smrg#endif 6417706df26Smrg } 6427706df26Smrg return; 6437706df26Smrg} 6447706df26Smrg 6457706df26Smrgstatic void 6467706df26SmrgICS9110ClockSelect(ScrnInfoPtr pScrn, int freq) 6477706df26Smrg{ 6487706df26Smrg unsigned int temp, temp1[6]; 6497706df26Smrg 6507706df26Smrg /* There lies an ICS9110 Clock Generator. */ 6517706df26Smrg /* ICS9110_CalcClockBits(freq, pll_bits); */ 6527706df26Smrg 6537706df26Smrg /* the following is based on munge_ics() from the 6547706df26Smrg TRU64 kernel TGA driver */ 6557706df26Smrg 6567706df26Smrg temp = (unsigned int)(tga_c_table->vco_div | 6577706df26Smrg (tga_c_table->ref_div << 7) | 6587706df26Smrg (tga_c_table->vco_pre << 14) | 6597706df26Smrg (tga_c_table->clk_div << 15) | 6607706df26Smrg (tga_c_table->vco_out_div << 17) | 6617706df26Smrg (tga_c_table->clk_out_en << 19) | 6627706df26Smrg (tga_c_table->clk_out_enX << 20) | 6637706df26Smrg (tga_c_table->res0 << 21) | 6647706df26Smrg (tga_c_table->clk_sel << 22) | 6657706df26Smrg (tga_c_table->res1 << 23)); 6667706df26Smrg 6677706df26Smrg temp1[0] = (temp & 0x00000001) | ((temp & 0x00000002) << 7) | 6687706df26Smrg ((temp & 0x00000004) << 14) | ((temp & 0x00000008) << 21); 6697706df26Smrg 6707706df26Smrg temp1[1] = ((temp & 0x00000010) >> 4) | ((temp & 0x00000020) << 3) | 6717706df26Smrg ((temp & 0x00000040) << 10) | ((temp & 0x00000080) << 17); 6727706df26Smrg 6737706df26Smrg temp1[2] = ((temp & 0x00000100) >> 8) | ((temp & 0x00000200) >> 1) | 6747706df26Smrg ((temp & 0x00000400) << 6) | ((temp & 0x00000800) << 13); 6757706df26Smrg 6767706df26Smrg temp1[3] = ((temp & 0x00001000) >> 12) | ((temp & 0x00002000) >> 5) | 6777706df26Smrg ((temp & 0x00004000) << 2) | ((temp & 0x00008000) << 9); 6787706df26Smrg 6797706df26Smrg temp1[4] = ((temp & 0x00010000) >> 16) | ((temp & 0x00020000) >> 9) | 6807706df26Smrg ((temp & 0x00040000) >> 2) | ((temp & 0x00080000) << 5); 6817706df26Smrg 6827706df26Smrg temp1[5] = ((temp & 0x00100000) >> 20) | ((temp & 0x00200000) >> 13) | 6837706df26Smrg ((temp & 0x00400000) >> 6) | ((temp & 0x00800000) << 1); 6847706df26Smrg 6857706df26Smrg write_av9110(pScrn, temp1); 6867706df26Smrg 6877706df26Smrg} 6887706df26Smrg 6897706df26Smrgvoid 6907706df26SmrgIbm561Init(TGAPtr pTga) 6917706df26Smrg{ 6927706df26Smrg unsigned char *Ibm561 = pTga->Ibm561modeReg; 6937706df26Smrg int i, j; 6947706df26Smrg 6957706df26Smrg/* ?? FIXME FIXME FIXME FIXME */ 6967706df26Smrg 6977706df26Smrg /* Command registers */ 6987706df26Smrg Ibm561[0] = 0x40; Ibm561[1] = 0x08; 6997706df26Smrg Ibm561[2] = (pTga->SyncOnGreen ? 0x80 : 0x00); 7007706df26Smrg 7017706df26Smrg /* Read mask */ 7027706df26Smrg Ibm561[3] = 0xff; Ibm561[4] = 0xff; Ibm561[5] = 0xff; Ibm561[6] = 0x0f; 7037706df26Smrg 7047706df26Smrg /* Blink mask */ 7057706df26Smrg Ibm561[7] = 0x00; Ibm561[8] = 0x00; Ibm561[9] = 0x00; Ibm561[10] = 0x00; 7067706df26Smrg 7077706df26Smrg /* Window attributes */ 7087706df26Smrg for (i = 0, j=11; i < 16; i++) { 7097706df26Smrg Ibm561[j++] = 0x00; Ibm561[j++] = 0x01; Ibm561[j++] = 0x80; 7107706df26Smrg } 7117706df26Smrg} 7127706df26Smrg 7137706df26Smrgvoid 7147706df26SmrgBt463Init(TGAPtr pTga) 7157706df26Smrg{ 7167706df26Smrg unsigned char *Bt463 = pTga->Bt463modeReg; 7177706df26Smrg int i, j; 7187706df26Smrg 7197706df26Smrg /* Command registers */ 7207706df26Smrg Bt463[0] = 0x40; Bt463[1] = 0x08; 7217706df26Smrg Bt463[2] = (pTga->SyncOnGreen ? 0x80 : 0x00); 7227706df26Smrg 7237706df26Smrg /* Read mask */ 7247706df26Smrg Bt463[3] = 0xff; Bt463[4] = 0xff; Bt463[5] = 0xff; Bt463[6] = 0x0f; 7257706df26Smrg 7267706df26Smrg /* Blink mask */ 7277706df26Smrg Bt463[7] = 0x00; Bt463[8] = 0x00; Bt463[9] = 0x00; Bt463[10] = 0x00; 7287706df26Smrg 7297706df26Smrg /* Window attributes */ 7307706df26Smrg for (i = 0, j=11; i < 16; i++) { 7317706df26Smrg Bt463[j++] = 0x00; Bt463[j++] = 0x01; Bt463[j++] = 0x80; 7327706df26Smrg } 7337706df26Smrg} 7347706df26Smrg 7357706df26SmrgBool 7367706df26SmrgDEC21030Init(ScrnInfoPtr pScrn, DisplayModePtr mode) 7377706df26Smrg{ 7387706df26Smrg TGAPtr pTga = TGAPTR(pScrn); 7397706df26Smrg TGARegPtr pReg = &pTga->ModeReg; 7407706df26Smrg 7417706df26Smrg if (pTga->RamDac != NULL) { /* this really means 8-bit and BT485 */ 7427706df26Smrg RamDacHWRecPtr pBT = RAMDACHWPTR(pScrn); 7437706df26Smrg RamDacRegRecPtr ramdacReg = &pBT->ModeReg; 7447706df26Smrg 7457706df26Smrg ramdacReg->DacRegs[BT_COMMAND_REG_0] = 0xA0 | 7467706df26Smrg (!pTga->Dac6Bit ? 0x2 : 0x0) | (pTga->SyncOnGreen ? 0x8 : 0x0); 7477706df26Smrg#if 1 7487706df26Smrg ramdacReg->DacRegs[BT_COMMAND_REG_2] = 0x20; 7497706df26Smrg#else 7507706df26Smrg ramdacReg->DacRegs[BT_COMMAND_REG_2] = 0x27; /* ?? was 0x20 */ 7517706df26Smrg#endif 7527706df26Smrg ramdacReg->DacRegs[BT_STATUS_REG] = 0x14; 7537706df26Smrg (*pTga->RamDac->SetBpp)(pScrn, ramdacReg); 7547706df26Smrg 7557706df26Smrg } else { 7567706df26Smrg switch (pTga->Chipset) { 7577706df26Smrg case PCI_CHIP_DEC21030: /* always BT463 */ 7587706df26Smrg Bt463Init(pTga); 7597706df26Smrg break; 7607706df26Smrg case PCI_CHIP_TGA2: /* always IBM 561 */ 7617706df26Smrg Ibm561Init(pTga); 7627706df26Smrg break; 7637706df26Smrg } 7647706df26Smrg } 7657706df26Smrg 7667706df26Smrg pReg->tgaRegs[0x00] = mode->CrtcHDisplay; 7677706df26Smrg pReg->tgaRegs[0x01] = mode->CrtcHSyncStart - mode->CrtcHDisplay; 7687706df26Smrg pReg->tgaRegs[0x02] = (mode->CrtcHSyncEnd - mode->CrtcHSyncStart) / 4; 7697706df26Smrg pReg->tgaRegs[0x03] = (mode->CrtcHTotal - mode->CrtcHSyncEnd) / 4; 7707706df26Smrg pReg->tgaRegs[0x04] = mode->CrtcVDisplay; 7717706df26Smrg pReg->tgaRegs[0x05] = mode->CrtcVSyncStart - mode->CrtcVDisplay; 7727706df26Smrg pReg->tgaRegs[0x06] = mode->CrtcVSyncEnd - mode->CrtcVSyncStart; 7737706df26Smrg pReg->tgaRegs[0x07] = mode->CrtcVTotal - mode->CrtcVSyncEnd; 7747706df26Smrg 7757706df26Smrg /* 7767706df26Smrg * We do polarity the Step B way of the 21030 7777706df26Smrg * Tell me how I can detect a Step A, and I'll support that too. 7787706df26Smrg * But I think that the Step B's are most common 7797706df26Smrg */ 7807706df26Smrg if (mode->Flags & V_PHSYNC) 7817706df26Smrg pReg->tgaRegs[0x08] = 1; /* Horizontal Polarity */ 7827706df26Smrg else 7837706df26Smrg pReg->tgaRegs[0x08] = 0; 7847706df26Smrg 7857706df26Smrg if (mode->Flags & V_PVSYNC) 7867706df26Smrg pReg->tgaRegs[0x09] = 1; /* Vertical Polarity */ 7877706df26Smrg else 7887706df26Smrg pReg->tgaRegs[0x09] = 0; 7897706df26Smrg 7907706df26Smrg pReg->tgaRegs[0x0A] = mode->Clock; 7917706df26Smrg 7927706df26Smrg pReg->tgaRegs[0x10] = (((pReg->tgaRegs[0x00]) / 4) & 0x1FF) | 7937706df26Smrg ((((pReg->tgaRegs[0x00]) / 4) & 0x600) << 19) | 7947706df26Smrg (((pReg->tgaRegs[0x01]) / 4) << 9) | 7957706df26Smrg (pReg->tgaRegs[0x02] << 14) | 7967706df26Smrg (pReg->tgaRegs[0x03] << 21) | 7977706df26Smrg#if 0 7987706df26Smrg (1 << 31) | /* ?? */ 7997706df26Smrg#endif 8007706df26Smrg (pReg->tgaRegs[0x08] << 30); 8017706df26Smrg pReg->tgaRegs[0x11] = pReg->tgaRegs[0x04] | 8027706df26Smrg (pReg->tgaRegs[0x05] << 11) | 8037706df26Smrg (pReg->tgaRegs[0x06] << 16) | 8047706df26Smrg (pReg->tgaRegs[0x07] << 22) | 8057706df26Smrg (pReg->tgaRegs[0x09] << 30); 8067706df26Smrg 8077706df26Smrg pReg->tgaRegs[0x12] = 0x01; 8087706df26Smrg 8097706df26Smrg pReg->tgaRegs[0x13] = 0x0000; 8107706df26Smrg return TRUE; 8117706df26Smrg} 8127706df26Smrg 8137706df26Smrgvoid 8147706df26SmrgDEC21030Save(ScrnInfoPtr pScrn, TGARegPtr tgaReg) 8157706df26Smrg{ 8167706df26Smrg TGAPtr pTga = TGAPTR(pScrn); 8177706df26Smrg 8187706df26Smrg tgaReg->tgaRegs[0x10] = TGA_READ_REG(TGA_HORIZ_REG); 8197706df26Smrg tgaReg->tgaRegs[0x11] = TGA_READ_REG(TGA_VERT_REG); 8207706df26Smrg tgaReg->tgaRegs[0x12] = TGA_READ_REG(TGA_VALID_REG); 8217706df26Smrg tgaReg->tgaRegs[0x13] = TGA_READ_REG(TGA_BASE_ADDR_REG); 8227706df26Smrg 8237706df26Smrg return; 8247706df26Smrg} 8257706df26Smrg 8267706df26Smrgvoid 8277706df26SmrgDEC21030Restore(ScrnInfoPtr pScrn, TGARegPtr tgaReg) 8287706df26Smrg{ 8297706df26Smrg TGAPtr pTga = TGAPTR(pScrn); 8307706df26Smrg 8317706df26Smrg TGA_WRITE_REG(0x00, TGA_VALID_REG); /* Disable Video */ 8327706df26Smrg 8337706df26Smrg switch (pTga->Chipset) { 8347706df26Smrg case PCI_CHIP_DEC21030: 8357706df26Smrg ICS1562ClockSelect(pScrn, tgaReg->tgaRegs[0x0A]); 8367706df26Smrg break; 8377706df26Smrg case PCI_CHIP_TGA2: 8387706df26Smrg ICS9110ClockSelect(pScrn, tgaReg->tgaRegs[0x0A]); 8397706df26Smrg break; 8407706df26Smrg } 8417706df26Smrg 8427706df26Smrg TGA_WRITE_REG(tgaReg->tgaRegs[0x10], TGA_HORIZ_REG); 8437706df26Smrg TGA_WRITE_REG(tgaReg->tgaRegs[0x11], TGA_VERT_REG); 8447706df26Smrg TGA_WRITE_REG(tgaReg->tgaRegs[0x13], TGA_BASE_ADDR_REG); 8457706df26Smrg 8467706df26Smrg TGA_WRITE_REG(tgaReg->tgaRegs[0x12], TGA_VALID_REG); /* Re-enable Video */ 8477706df26Smrg 8487706df26Smrg return; 8497706df26Smrg} 850