1/* Copyright (C) 2003-2006 by XGI Technology, Taiwan. 2 * 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation on the rights to use, copy, modify, merge, 9 * publish, distribute, sublicense, and/or sell copies of the Software, 10 * and to permit persons to whom the Software is furnished to do so, 11 * subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial 15 * portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 20 * NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR 21 * ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 22 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 */ 26#ifdef HAVE_CONFIG_H 27#include "config.h" 28#endif 29 30#include "osdef.h" 31#include "vgatypes.h" 32 33 34#ifdef LINUX_KERNEL 35#include <linux/version.h> 36#include <linux/types.h> 37#include <linux/delay.h> /* udelay */ 38#include "XGIfb.h" 39#endif 40 41#include "vb_def.h" 42#include "vb_struct.h" 43#include "vb_setmode.h" 44#include "vb_init.h" 45#include "vb_ext.h" 46 47#ifdef LINUX_XF86 48#include "xf86.h" 49#include "xf86PciInfo.h" 50#include "xgi.h" 51#include "xgi_regs.h" 52#endif 53 54#ifdef LINUX_KERNEL 55#include <asm/io.h> 56#include <linux/types.h> 57#endif 58 59 60 61 62static UCHAR XGINew_ChannelAB; 63static UCHAR XGINew_DataBusWidth; 64 65USHORT XGINew_DRAMType[17][5]={{0x0C,0x0A,0x02,0x40,0x39},{0x0D,0x0A,0x01,0x40,0x48}, 66 {0x0C,0x09,0x02,0x20,0x35},{0x0D,0x09,0x01,0x20,0x44}, 67 {0x0C,0x08,0x02,0x10,0x31},{0x0D,0x08,0x01,0x10,0x40}, 68 {0x0C,0x0A,0x01,0x20,0x34},{0x0C,0x09,0x01,0x08,0x32}, 69 {0x0B,0x08,0x02,0x08,0x21},{0x0C,0x08,0x01,0x08,0x30}, 70 {0x0A,0x08,0x02,0x04,0x11},{0x0B,0x0A,0x01,0x10,0x28}, 71 {0x09,0x08,0x02,0x02,0x01},{0x0B,0x09,0x01,0x08,0x24}, 72 {0x0B,0x08,0x01,0x04,0x20},{0x0A,0x08,0x01,0x02,0x10}, 73 {0x09,0x08,0x01,0x01,0x00}}; 74 75static const USHORT XGINew_SDRDRAM_TYPE[13][5]= 76{ 77 { 2,12, 9,64,0x35}, 78 { 1,13, 9,64,0x44}, 79 { 2,12, 8,32,0x31}, 80 { 2,11, 9,32,0x25}, 81 { 1,12, 9,32,0x34}, 82 { 1,13, 8,32,0x40}, 83 { 2,11, 8,16,0x21}, 84 { 1,12, 8,16,0x30}, 85 { 1,11, 9,16,0x24}, 86 { 1,11, 8, 8,0x20}, 87 { 2, 9, 8, 4,0x01}, 88 { 1,10, 8, 4,0x10}, 89 { 1, 9, 8, 2,0x00} 90}; 91 92static const USHORT XGINew_DDRDRAM_TYPE[4][5]= 93{ 94 { 2,12, 9,64,0x35}, 95 { 2,12, 8,32,0x31}, 96 { 2,11, 8,16,0x21}, 97 { 2, 9, 8, 4,0x01} 98}; 99 100static const USHORT XGINew_DDRDRAM_TYPE340[4][5]= 101{ 102 { 2,13, 9,64,0x45}, 103 { 2,12, 9,32,0x35}, 104 { 2,12, 8,16,0x31}, 105 { 2,11, 8, 8,0x21} 106}; 107 108/* Jong 10/05/2007; merge code */ 109USHORT XGINew_DDRDRAM_TYPE20[12][5]= 110{ 111{ 2,14,11,128,0x5D}, 112{ 2,14,10,64,0x59}, 113{ 2,13,11,64,0x4D}, 114{ 2,14, 9,32,0x55}, 115{ 2,13,10,32,0x49}, 116{ 2,12,11,32,0x3D}, 117{ 2,14, 8,16,0x51}, 118{ 2,13, 9,16,0x45}, 119{ 2,12,10,16,0x39}, 120{ 2,13, 8, 8,0x41}, 121{ 2,12, 9, 8,0x35}, 122{ 2,12, 8, 4,0x31} 123}; 124 125static void XGINew_SetDRAMSize_340(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO); 126static void XGINew_SetDRAMSize_XG45(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO); 127static void XGINew_SetMemoryClock(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO); 128static void XGINew_SetDRAMModeRegister340(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO); 129static void XGINew_SetDRAMDefaultRegister340(PXGI_HW_DEVICE_INFO, USHORT, 130 PVB_DEVICE_INFO); 131static void XGINew_SetDRAMDefaultRegisterXG45(PXGI_HW_DEVICE_INFO, USHORT, 132 PVB_DEVICE_INFO); 133static UCHAR XGINew_Get340DRAMType(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO); 134 135static int XGINew_SetDDRChannel(int index, UCHAR ChannelNo, 136 UCHAR XGINew_ChannelAB, const USHORT DRAMTYPE_TABLE[][5], 137 PVB_DEVICE_INFO pVBInfo); 138 139static void XGINew_SetDRAMSizingType(int index , 140 const USHORT DRAMTYPE_TABLE[][5], PVB_DEVICE_INFO pVBInfo); 141static USHORT XGINew_SetDRAMSizeReg(int index, 142 const USHORT DRAMTYPE_TABLE[][5], PVB_DEVICE_INFO pVBInfo); 143 144static int XGINew_SetRank(int index, UCHAR RankNo, UCHAR XGINew_ChannelAB, 145 const USHORT DRAMTYPE_TABLE[][5], PVB_DEVICE_INFO pVBInfo); 146 147static int XGINew_CheckRanks(int RankNo, int index, 148 const USHORT DRAMTYPE_TABLE[][5], PVB_DEVICE_INFO pVBInfo); 149static int XGINew_CheckRank(int RankNo, int index, 150 const USHORT DRAMTYPE_TABLE[][5], PVB_DEVICE_INFO pVBInfo); 151static int XGINew_CheckDDRRank(int RankNo, int index, 152 const USHORT DRAMTYPE_TABLE[][5], PVB_DEVICE_INFO pVBInfo); 153static int XGINew_CheckDDRRanks(int RankNo, int index, 154 const USHORT DRAMTYPE_TABLE[][5], PVB_DEVICE_INFO pVBInfo); 155 156static int XGINew_CheckBanks(int index, const USHORT DRAMTYPE_TABLE[][5], 157 PVB_DEVICE_INFO pVBInfo); 158static int XGINew_CheckColumn(int index, const USHORT DRAMTYPE_TABLE[][5], 159 PVB_DEVICE_INFO pVBInfo); 160 161static int XGINew_DDRSizing340(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO); 162static int XGINew_DDRSizingXG45(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO); 163static int XGINew_SDRSizing(PVB_DEVICE_INFO); 164static int XGINew_DDRSizing(PVB_DEVICE_INFO); 165 166/* Jong 10/05/2007; merge code */ 167static void XGINew_GetXG21Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) ; 168static UCHAR GetXG21FPBits(PVB_DEVICE_INFO pVBInfo); 169static void XGINew_GetXG27Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) ; 170static UCHAR GetXG27FPBits(PVB_DEVICE_INFO pVBInfo); 171 172static void XGINew_DDR_MRS(PVB_DEVICE_INFO pVBInfo); 173static void XGINew_SDR_MRS(PVB_DEVICE_INFO pVBInfo); 174static void XGINew_DDR1x_MRS_340(PXGI_HW_DEVICE_INFO HwDeviceExtension, 175 USHORT P3c4, PVB_DEVICE_INFO pVBInfo); 176static void XGINew_DDR2x_MRS_340(PXGI_HW_DEVICE_INFO HwDeviceExtension, 177 USHORT P3c4, PVB_DEVICE_INFO pVBInfo); 178static void XGINew_DDR2_MRS_340(PXGI_HW_DEVICE_INFO HwDeviceExtension, 179 USHORT P3c4, PVB_DEVICE_INFO pVBInfo); 180static void XGINew_DDR1x_DefaultRegister(PXGI_HW_DEVICE_INFO HwDeviceExtension, 181 USHORT Port, PVB_DEVICE_INFO pVBInfo); 182static void XGINew_DDR2x_DefaultRegister(PXGI_HW_DEVICE_INFO HwDeviceExtension, 183 USHORT Port, PVB_DEVICE_INFO pVBInfo); 184static void XGINew_DDR2_DefaultRegister(PXGI_HW_DEVICE_INFO HwDeviceExtension, 185 USHORT Port, PVB_DEVICE_INFO pVBInfo); 186 187static void XGINew_DisableChannelInterleaving(int index, 188 const USHORT XGINew_DDRDRAM_TYPE[][5], PVB_DEVICE_INFO pVBInfo); 189 190static void DualChipInit(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO); 191 192static void XGINew_DisableRefresh(PXGI_HW_DEVICE_INFO ,PVB_DEVICE_INFO); 193static void XGINew_EnableRefresh(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO); 194 195static void XGINew_Delay15us(ULONG); 196static void SetPowerConsume(PXGI_HW_DEVICE_INFO, USHORT); 197static void XGINew_DDR1x_MRS_XG20(USHORT, PVB_DEVICE_INFO); 198static void XGINew_SetDRAMModeRegister_XG20(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO); 199static void XGINew_ChkSenseStatus(PXGI_HW_DEVICE_INFO, PVB_DEVICE_INFO); 200 201static int XGINew_ReadWriteRest( USHORT StopAddr, USHORT StartAddr, 202 PVB_DEVICE_INFO pVBInfo); 203static int XGI45New_ReadWriteRest(USHORT StopAddr, USHORT StartAddr, 204 PVB_DEVICE_INFO pVBInfo); 205static UCHAR XGINew_CheckFrequence(PVB_DEVICE_INFO pVBInfo); 206static void XGINew_CheckChannel(PXGI_HW_DEVICE_INFO HwDeviceExtension, 207 PVB_DEVICE_INFO pVBInfo); 208 209static int XGINew_RAMType; /*int ModeIDOffset,StandTable,CRT1Table,ScreenOffset,REFIndex;*/ 210static ULONG UNIROM; /* UNIROM */ 211 212 213#ifdef LINUX_KERNEL 214void DelayUS(ULONG MicroSeconds) 215{ 216 udelay(MicroSeconds); 217} 218#endif 219 220/* --------------------------------------------------------------------- */ 221/* Function : XGIInitNew */ 222/* Input : */ 223/* Output : */ 224/* Description : */ 225/* --------------------------------------------------------------------- */ 226BOOLEAN XGIInitNew(PXGI_HW_DEVICE_INFO HwDeviceExtension, 227 PVB_DEVICE_INFO pVBInfo) 228{ 229#ifndef LINUX_XF86 230 USHORT Mclockdata[ 30 ] , Eclockdata[ 30 ] ; 231 UCHAR j , SR11 , SR17 = 0 , SR18 = 0 , SR19 = 0 ; 232 UCHAR CR37 = 0 , CR38 = 0 , CR79 = 0 , CR7A = 0 , 233 CR7B = 0 , CR36 = 0 , CR78 = 0 , CR3C = 0 , 234 CR3D = 0 , CR3E = 0 , CR3F = 0 , CR35 = 0 ; 235#endif 236 UCHAR i , temp = 0 , temp1 , 237 VBIOSVersion[ 5 ] ; 238 ULONG base,ChipsetID,VendorID,GraphicVendorID; 239 PUCHAR volatile pVideoMemory; 240 241 /* ULONG j, k ; */ 242 243 PXGI_DSReg pSR ; 244 245 ULONG Temp ; 246 247 248 XGINew_InitVBIOSData(HwDeviceExtension, pVBInfo); 249 250 pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr; 251 252 253 Newdebugcode( 0x99 ) ; 254 255 /* if ( pVBInfo->ROMAddr == 0 ) */ 256 /* return( FALSE ) ; */ 257 258 if ( pVBInfo->FBAddr == 0 ) 259 return( FALSE ) ; 260 261 if ( pVBInfo->BaseAddr == 0 ) 262 return( FALSE ) ; 263 264 XGI_SetRegByte((XGIIOADDRESS) ( USHORT )( pVBInfo->BaseAddr + 0x12 ) , 0x67 ) ; /* 3c2 <- 67 ,ynlai */ 265 266 267 if ( !HwDeviceExtension->bIntegratedMMEnabled ) 268 return( FALSE ) ; /* alan */ 269 270 271 272 XGI_MemoryCopy( VBIOSVersion , HwDeviceExtension->szVBIOSVer , 4 ) ; 273 274 VBIOSVersion[ 4 ] = 0x0 ; 275 276 277 /* ReadVBIOSData */ 278 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ; 279 280 /* 1.Openkey */ 281 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x05 , 0x86 ) ; 282 283 284 285 /* 2.Reset Extended register */ 286 287 for( i = 0x06 ; i < 0x20 ; i++ ) 288 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , i , 0 ) ; 289 290 for( i = 0x21 ; i <= 0x27 ; i++ ) 291 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , i , 0 ) ; 292 293 /* for( i = 0x06 ; i <= 0x27 ; i++ ) */ 294 /* XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , i , 0 ) ; */ 295 296 297 if(( HwDeviceExtension->jChipType == XG20 ) || ( HwDeviceExtension->jChipType >= XG40)) 298 { 299 for( i = 0x31 ; i <= 0x3B ; i++ ) 300 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , i , 0 ) ; 301 } 302 else 303 { 304 for( i = 0x31 ; i <= 0x3D ; i++ ) 305 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , i , 0 ) ; 306 } 307 308 if ( HwDeviceExtension->jChipType == XG42 ) /* [Hsuan] 2004/08/20 Auto over driver for XG42 */ 309 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x3B , 0xC0 ) ; 310 311 /* for( i = 0x30 ; i <= 0x3F ; i++ ) */ 312 /* XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , i , 0 ) ; */ 313 314 for( i = 0x79 ; i <= 0x7C ; i++ ) 315 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , i , 0 ) ; /* shampoo 0208 */ 316 317 /* Jong 10/01/2007; SetDefPCIRegs */ /* alan 12/07/2006 */ 318 if ( HwDeviceExtension->jChipType == XG27 ) 319 { 320 for( i = 0xD0 ; i <= 0xDB ; i++ ) 321 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3d4 , i , pVBInfo->pCRD0[i-0xd0] ) ; 322 for( i = 0xDE ; i <= 0xDF ; i++ ) 323 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3d4 , i , pVBInfo->pCRDE[i-0xdE] ) ; 324 } 325 326 327 if ( HwDeviceExtension->jChipType >= XG20 ) 328 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4, 0x97, pVBInfo->CR97); 329 330 /* 3.SetMemoryClock */ 331 if (!(pVBInfo->SoftSetting & SoftDRAMType)) { 332 if (( HwDeviceExtension->jChipType == XG20 )||( HwDeviceExtension->jChipType == XG21 )||( HwDeviceExtension->jChipType == XG27 )) 333 { 334 temp = ( UCHAR )XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x97 ) ; 335 } 336 else if (HwDeviceExtension->jChipType == XG45) 337 { 338 temp = 0x02 ; 339 } 340 else 341 { 342 temp = ( UCHAR )XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x3A ) ; 343 } 344 } 345 346 347 if ( HwDeviceExtension->jChipType == XG20 ) 348 XGINew_RAMType = temp & 0x01 ; 349 else 350 { 351 XGINew_RAMType = temp & 0x03 ; /* alan */ 352 } 353 354 /* Get DRAM type */ 355 if ( HwDeviceExtension->jChipType == XG45 ) 356 { } 357 else if ( HwDeviceExtension->jChipType >= XG40 ) 358 XGINew_RAMType = ( int )XGINew_Get340DRAMType( HwDeviceExtension , pVBInfo) ; 359 360 if ( UNIROM == 1 ) XGINew_RAMType = 0; 361 362 if ( HwDeviceExtension->jChipType < XG40 ) 363 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; 364 365 /* 4.SetDefExt1Regs begin */ 366 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x07, pVBInfo->SR07); 367 368 /* Jong 10/01/2007; add for ??? */ 369 if ( HwDeviceExtension->jChipType == XG27 ) 370 { 371 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3c4 , 0x40 , *pVBInfo->pSR40 ) ; 372 XGI_SetReg( (XGIIOADDRESS)pVBInfo->P3c4 , 0x41 , *pVBInfo->pSR41 ) ; 373 } 374 375 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x11, 0x0F); 376 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x1F, pVBInfo->SR1F); 377 /* XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x20, 0x20); */ 378 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x20, 0xA0); /* alan, 2001/6/26 Frame buffer can read/write SR20 */ 379 380 /* Jong 10/01/2007; added for ??? */ 381 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3c4 , 0x36 , 0x70 ) ; /* Hsuan, 2006/01/01 H/W request for slow corner chip */ 382 if ( HwDeviceExtension->jChipType == XG27 ) /* Alan 12/07/2006 */ 383 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3c4 , 0x36 , *pVBInfo->pSR36 ) ; 384 385 /* SR11 = 0x0F ; */ 386 /* XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x11 , SR11 ) ; */ 387 388 389 if ( (HwDeviceExtension->jChipType != XG20) 390 &&(HwDeviceExtension->jChipType != XG21) 391 &&(HwDeviceExtension->jChipType != XG27) 392 &&(HwDeviceExtension->jChipType != XG45) ) /* kuku 2004/06/25 */ 393 { 394 /* Set AGP Rate */ 395 temp1 = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x3B ) ; 396 temp1 &= 0x02 ; 397 if ( temp1 == 0x02 ) 398 { 399 XGI_SetRegLong((XGIIOADDRESS) 0xcf8 , 0x80000000 ) ; 400 ChipsetID = XGI_GetRegLong((XGIIOADDRESS) 0x0cfc ) ; 401 XGI_SetRegLong((XGIIOADDRESS) 0xcf8 , 0x8000002C ) ; 402 VendorID = XGI_GetRegLong((XGIIOADDRESS) 0x0cfc ) ; 403 VendorID &= 0x0000FFFF ; 404 XGI_SetRegLong((XGIIOADDRESS) 0xcf8 , 0x8001002C ) ; 405 GraphicVendorID = XGI_GetRegLong((XGIIOADDRESS) 0x0cfc ) ; 406 GraphicVendorID &= 0x0000FFFF; 407 408 if ( ChipsetID == 0x7301039 ) 409 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x5F , 0x09 ) ; 410 411 ChipsetID &= 0x0000FFFF ; 412 413 if ( ( ChipsetID == 0x700E ) || ( ChipsetID == 0x1022 ) || ( ChipsetID == 0x1106 ) || ( ChipsetID == 0x10DE ) ) 414 { 415 if ( ChipsetID == 0x1106 ) 416 { 417 if ( ( VendorID == 0x1019 ) && ( GraphicVendorID == 0x1019 ) ) 418 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x5F , 0x0D ) ; 419 else 420 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x5F , 0x0B ) ; 421 } 422 else 423 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x5F , 0x0B ) ; 424 } 425 } 426 427 if ( HwDeviceExtension->jChipType >= XG40 ) 428 { 429 /* Set AGP customize registers (in SetDefAGPRegs) Start */ 430 for( i = 0x47 ; i <= 0x4C ; i++ ) 431 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , i , pVBInfo->AGPReg[ i - 0x47 ] ) ; 432 433 for( i = 0x70 ; i <= 0x71 ; i++ ) 434 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 6 + i - 0x70 ] ) ; 435 436 for( i = 0x74 ; i <= 0x77 ; i++ ) 437 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 8 + i - 0x74 ] ) ; 438 /* Set AGP customize registers (in SetDefAGPRegs) End */ 439 /*[Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */ 440 XGI_SetRegLong((XGIIOADDRESS) 0xcf8 , 0x80000000 ) ; 441 ChipsetID = XGI_GetRegLong((XGIIOADDRESS) 0x0cfc ) ; 442 if ( ChipsetID == 0x25308086 ) 443 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x77 , 0xF0 ) ; 444 445 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x50 , 0 , &Temp ) ; /* Get */ 446 Temp >>= 20 ; 447 Temp &= 0xF ; 448 449 if ( Temp == 1 ) 450 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x48 , 0x20 ) ; /* CR48 */ 451 } 452 453 if ( HwDeviceExtension->jChipType < XG40 ) 454 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x49 , pVBInfo->CR49[ 0 ] ) ; 455 } /* != XG20 */ 456 457 /* Set PCI */ 458 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x23, pVBInfo->SR23); 459 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x24, pVBInfo->SR24); 460 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x25, pVBInfo->SR25[0]); 461 462 if ( (HwDeviceExtension->jChipType != XG20) && 463 (HwDeviceExtension->jChipType != XG21) && 464 (HwDeviceExtension->jChipType != XG27) ) /* kuku 2004/06/25 */ 465 { 466 /* Set VB */ 467 XGI_UnLockCRT2( HwDeviceExtension, pVBInfo) ; 468 XGI_SetRegANDOR((XGIIOADDRESS) pVBInfo->Part0Port , 0x3F , 0xEF , 0x00 ) ; /* alan, disable VideoCapture */ 469 XGI_SetReg((XGIIOADDRESS) pVBInfo->Part1Port , 0x00 , 0x00 ) ; 470 temp1 = ( UCHAR )XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x7B ) ; /* chk if BCLK>=100MHz */ 471 temp = ( UCHAR )( ( temp1 >> 4 ) & 0x0F ) ; 472 473 474 XGI_SetReg((XGIIOADDRESS) pVBInfo->Part1Port, 0x02, 475 pVBInfo->CRT2Data_1_2); 476 477 478 XGI_SetReg((XGIIOADDRESS) pVBInfo->Part1Port , 0x2E , 0x08 ) ; /* use VB */ 479 } /* != XG20 */ 480 481 482 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x27 , 0x1F ) ; 483 484 /* Not DDR */ 485 if ((HwDeviceExtension->jChipType == XG42) 486 && XGINew_Get340DRAMType(HwDeviceExtension, pVBInfo) != 0) { 487 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x31, (pVBInfo->SR31 & 0x3F) | 0x40); 488 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x32, (pVBInfo->SR32 & 0xFC) | 0x01); 489 } 490 else { 491 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x31, pVBInfo->SR31); 492 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x32, pVBInfo->SR32); 493 } 494 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x33, pVBInfo->SR33); 495 496 497 498 if ( HwDeviceExtension->jChipType >= XG40 ) 499 SetPowerConsume ( HwDeviceExtension , pVBInfo->P3c4); 500 501 if ( (HwDeviceExtension->jChipType != XG20) && 502 (HwDeviceExtension->jChipType != XG21) && 503 (HwDeviceExtension->jChipType != XG27) ) /* kuku 2004/06/25 */ 504 { 505 if ( XGI_BridgeIsOn( pVBInfo ) == 1 ) 506 { 507 { 508 XGI_SetReg((XGIIOADDRESS) pVBInfo->Part2Port, 0x00, 0x1C); 509 XGI_SetReg((XGIIOADDRESS) pVBInfo->Part4Port, 0x0D, pVBInfo->CRT2Data_4_D); 510 XGI_SetReg((XGIIOADDRESS) pVBInfo->Part4Port, 0x0E, pVBInfo->CRT2Data_4_E); 511 XGI_SetReg((XGIIOADDRESS) pVBInfo->Part4Port, 0x10, pVBInfo->CRT2Data_4_10); 512 XGI_SetReg((XGIIOADDRESS) pVBInfo->Part4Port, 0x0F, 0x3F); 513 } 514 515 XGI_LockCRT2( HwDeviceExtension, pVBInfo ) ; 516 } 517 } /* != XG20 */ 518 519 if ( HwDeviceExtension->jChipType < XG40 ) 520 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x83 , 0x00 ) ; 521 522 523 /* Jong 10/01/2007; added for ??? */ 524 if ( HwDeviceExtension->bSkipSense == FALSE ) 525 { 526 XGI_SenseCRT1(pVBInfo) ; 527 /* XGINew_DetectMonitor( HwDeviceExtension ) ; */ 528 if ( ( HwDeviceExtension->jChipType == XG21 ) && (pVBInfo->IF_DEF_CH7007) ) 529 { 530 XGI_GetSenseStatus( HwDeviceExtension , pVBInfo ) ; /* sense CRT2 */ 531 } 532 if ( HwDeviceExtension->jChipType == XG21 ) 533 { 534 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */ 535 temp = GetXG21FPBits( pVBInfo ) ; 536 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x37 , ~0x01, temp ) ; 537 } 538 if ( HwDeviceExtension->jChipType == XG27 ) 539 { 540 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */ 541 temp = GetXG27FPBits( pVBInfo ) ; 542 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x37 , ~0x03, temp ) ; 543 } 544 } 545 546 if ( HwDeviceExtension->jChipType >= XG40 ) 547 { 548 if (HwDeviceExtension->jChipType == XG45) 549 XGINew_SetDRAMDefaultRegisterXG45( HwDeviceExtension , pVBInfo->P3d4, pVBInfo ) ; 550 else 551 XGINew_SetDRAMDefaultRegister340( HwDeviceExtension , pVBInfo->P3d4, pVBInfo ) ; 552 553 if ( HwDeviceExtension->bSkipDramSizing == TRUE ) 554 { 555 pSR = HwDeviceExtension->pSR ; 556 if ( pSR!=NULL ) 557 { 558 while( pSR->jIdx != 0xFF ) 559 { 560 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , pSR->jIdx , pSR->jVal ) ; 561 pSR++ ; 562 } 563 } 564 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */ 565 } /* SkipDramSizing */ 566 else 567 { 568/* if ( HwDeviceExtension->jChipType == XG20 ) 569 { 570 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , pVBInfo->SR15[0][XGINew_RAMType] ) ; 571 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , pVBInfo->SR15[1][XGINew_RAMType] ) ; 572 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x20 , 0x20 ) ; 573 } 574 else*/ 575 if ( HwDeviceExtension->jChipType == XG45 ) 576 XGINew_SetDRAMSize_XG45( HwDeviceExtension , pVBInfo) ; 577 else 578 XGINew_SetDRAMSize_340( HwDeviceExtension , pVBInfo) ; 579 } 580 } /* XG40 */ 581 582 583 584 585 /* SetDefExt2Regs begin */ 586/* 587 AGP = 1 ; 588 temp =( UCHAR )XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x3A ) ; 589 temp &= 0x30 ; 590 if ( temp == 0x30 ) 591 AGP = 0 ; 592 593 if ( AGP == 0 ) 594 pVBInfo->SR21 &= 0xEF ; 595 596 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 , pVBInfo->SR21 ) ; 597 if ( AGP == 1 ) 598 pVBInfo->SR22 &= 0x20; 599 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x22 , pVBInfo->SR22 ) ; 600*/ 601 602 base = 0x80000000; 603 XGI_SetRegLong(0xcf8, base); 604 Temp = (XGI_GetRegLong(0xcfc) & 0x0000FFFF); 605 if (Temp == 0x1039) { 606 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x22, pVBInfo->SR22 & 0xFE); 607 } 608 else { 609 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x22, pVBInfo->SR22); 610 } 611 612 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4, 0x21, pVBInfo->SR21); 613 614 if ( HwDeviceExtension->jChipType == XG40 ) /* Initialize seconary chip */ 615 { 616 if ( CheckDualChip(pVBInfo) ) 617 DualChipInit( HwDeviceExtension , pVBInfo) ; 618 /* SetDefExt2Regs end */ 619 } 620 621 /* Jong 10/01/2007; be removed and recoded */ 622#if 0 623 if ( HwDeviceExtension->bSkipSense == FALSE ) 624 { 625 XGI_SenseCRT1(pVBInfo) ; 626 /* XGINew_DetectMonitor( HwDeviceExtension ) ; */ 627 XGI_GetSenseStatus( HwDeviceExtension , pVBInfo ) ; /* sense CRT2 */ 628 } 629#endif 630 631 XGINew_ChkSenseStatus ( HwDeviceExtension , pVBInfo ) ; 632 XGINew_SetModeScratch ( HwDeviceExtension , pVBInfo ) ; 633 634 Newdebugcode( 0x88 ) ; 635 636 /* Johnson@062403. To save time for power management. */ 637 /* DelayMS(1000); */ 638 /* ~Johnson@062403. */ 639 /* XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x32 , 0x28 ) ; //0207 temp */ 640 /* XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x36 , 0x02 ) ; //0207 temp */ 641 642 return( TRUE ) ; 643} /* end of init */ 644 645 646 647/* --------------------------------------------------------------------- */ 648/* Function : DualChipInit */ 649/* Input : */ 650/* Output : */ 651/* Description : Initialize the secondary chip. */ 652/* --------------------------------------------------------------------- */ 653void DualChipInit( PXGI_HW_DEVICE_INFO HwDeviceExtension ,PVB_DEVICE_INFO pVBInfo) 654{ 655#ifdef LINUX_XF86 656 USHORT BaseAddr2nd = (USHORT)(ULONG)HwDeviceExtension->pj2ndIOAddress ; 657#else 658 USHORT BaseAddr2nd = (USHORT)HwDeviceExtension->pj2ndIOAddress ; 659#endif 660 USHORT XGINew_P3C3 = pVBInfo->BaseAddr + VIDEO_SUBSYSTEM_ENABLE_PORT ; 661 USHORT XGINew_P3CC = pVBInfo->BaseAddr + MISC_OUTPUT_REG_READ_PORT ; 662 USHORT XGINew_2ndP3C3 = BaseAddr2nd + VIDEO_SUBSYSTEM_ENABLE_PORT ; 663 USHORT XGINew_2ndP3D4 = BaseAddr2nd + CRTC_ADDRESS_PORT_COLOR ; 664 USHORT XGINew_2ndP3C4 = BaseAddr2nd + SEQ_ADDRESS_PORT ; 665 USHORT XGINew_2ndP3C2 = BaseAddr2nd + MISC_OUTPUT_REG_WRITE_PORT ; 666 ULONG Temp ; 667 UCHAR tempal , i ; 668 669 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ; 670 pVBInfo->BaseAddr = (USHORT)HwDeviceExtension->pjIOAddress ; 671 /* Programming Congiguration Space in Secondary Chip */ 672 /* set CRA1 D[6] = 1 */ 673 XGI_SetRegANDOR((XGIIOADDRESS) pVBInfo->P3d4 , 0xA1 , 0xBF , 0x40 ) ; 674 675 /* Write 2nd Chip Configuration Info into Configuration Space */ 676 /* Command CNFG04 */ 677 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , PCI_COMMAND , 0 , &Temp ) ; /* Get */ 678 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , PCI_COMMAND + 0x80 , 1 , &Temp ) ; /* Set */ 679 /* Latency Timer CNFG0C */ 680 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x0c , 0 , &Temp ) ; /* Get */ 681 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x0c + 0x80 , 1 , &Temp ) ; /* Set */ 682 /* Linear space */ 683 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x10 , 0 , &Temp ) ; /* Get */ 684 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x10 + 0x80 , 1 , &Temp ) ; /* Set */ 685 /* MMIO space */ 686 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x14 , 0 , &Temp ) ; /* Get */ 687 Temp += 0x40000; 688 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x14 + 0x80 , 1 , &Temp ) ; /* Set */ 689 /* Relocated IO space */ 690 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x18 , 0 , &Temp ) ; /* Get */ 691 Temp += 0x80; 692 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x18 + 0x80 , 1 , &Temp ) ; /* Set */ 693 /* Miscellaneous reg(input port 3cch,output port 3c2h) */ 694 tempal = XGI_GetRegByte((XGIIOADDRESS) XGINew_P3CC ) ; /* 3cc */ 695 XGI_SetRegByte((XGIIOADDRESS) XGINew_2ndP3C2 , tempal ) ; 696 /* VGA enable reg(port 3C3h) */ 697 tempal = XGI_GetRegByte((XGIIOADDRESS) XGINew_P3C3 ) ; /* 3c3 */ 698 XGI_SetRegByte((XGIIOADDRESS) XGINew_2ndP3C3 , tempal ) ; 699 SetPowerConsume ( HwDeviceExtension , XGINew_2ndP3D4); 700 /* ----- CRA0=42, CRA1=81, CRA2=60, CRA3=20, CRA4=50, CRA5=40, CRA8=88 -----// */ 701 /* ----- CRA9=10, CRAA=80, CRAB=01, CRAC=F1, CRAE=80, CRAF=45, CRB7=24 -----// */ 702 /* primary chip */ 703 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xA0 , 0x72 ) ; 704 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xA1 , 0x81 ) ; 705 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xA2 , 0x60 ) ; 706 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xA3 , 0x20 ) ; 707 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xA4 , 0x50 ) ; 708 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xA5 , 0x40 ) ; 709 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xA8 , 0x88 ) ; 710 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xA9 , 0x10 ) ; 711 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xAA , 0x80 ) ; 712 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xAB , 0x01 ) ; 713 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xAC , 0xF1 ) ; 714 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xAE , 0x80 ) ; 715 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xAF , 0x45 ) ; 716 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0xB7 , 0x24 ) ; 717 718 /* secondary chip */ 719 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xA0 , 0x72 ) ; 720 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xA1 , 0x81 ) ; 721 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xA2 , 0x60 ) ; 722 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xA3 , 0x20 ) ; 723 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xA4 , 0x50 ) ; 724 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xA5 , 0x40 ) ; 725 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xA8 , 0x88 ) ; 726 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xA9 , 0x10 ) ; 727 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xAA , 0x80 ) ; 728 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xAB , 0x01 ) ; 729 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xAC , 0xF1 ) ; 730 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xAE , 0x80 ) ; 731 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xAF , 0x45 ) ; 732 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3D4 , 0xB7 , 0x24 ) ; 733 734 /* 06/20/2003 [christine] CRT threshold setting request */ 735 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x78 , 0x40 ) ; 736 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x79 , 0x0C ) ; 737 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x7A , 0x34 ) ; 738 739 /* OpenKey in 2nd chip */ 740 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3C4 , 0x05 , 0x86 ) ; 741 742 /* Set PCI registers */ 743 tempal = (UCHAR)XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x06 ) ; 744 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3C4 , 0x06 , tempal ) ; 745 746 for( i = 0x20 ; i <= 0x25 ; i++ ) 747 { 748 tempal = ( UCHAR )XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , i ) ; 749 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3C4 , i , tempal ) ; 750 } 751 for(i = 0x31; i <= 0x32; i++ ) 752 { 753 tempal = ( UCHAR )XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , i ) ; 754 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3C4 , i , tempal ) ; 755 } 756 XGINew_SetDRAMDefaultRegister340( HwDeviceExtension , XGINew_2ndP3D4 , pVBInfo) ; 757 758 for(i = 0x13; i <= 0x14; i++ ) 759 { 760 tempal = ( UCHAR )XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , i ) ; 761 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3C4 , i , tempal ) ; 762 } 763 764 /* Close key in 2nd chip */ 765 XGI_SetReg((XGIIOADDRESS) XGINew_2ndP3C4 , 0x05 , 0x00 ) ; 766} 767 768 769 770 771/* ============== alan ====================== */ 772 773/* --------------------------------------------------------------------- */ 774/* Function : XGINew_Get340DRAMType */ 775/* Input : */ 776/* Output : */ 777/* Description : */ 778/* --------------------------------------------------------------------- */ 779UCHAR XGINew_Get340DRAMType( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo) 780{ 781 UCHAR data, temp ; /* Jong 10/05/2007; merge code */ 782 783 if ( HwDeviceExtension->jChipType < XG20 ) 784 { 785 if (pVBInfo->SoftSetting & SoftDRAMType) { 786 return (pVBInfo->SoftSetting & 0x07); 787 } 788 else 789 { 790 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x39 ) & 0x02 ; 791 792 if ( data == 0 ) 793 data = ( XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x3A ) & 0x02 ) >> 1 ; 794 795 return( data ) ; 796 } 797 } 798 else if ( HwDeviceExtension->jChipType == XG27 ) 799 { 800 if ( pVBInfo->SoftSetting & SoftDRAMType ) 801 { 802 data = pVBInfo->SoftSetting & 0x07 ; 803 return( data ) ; 804 } 805 temp = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3c4 , 0x3B ) ; 806 807 if (( temp & 0x88 )==0x80) /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */ 808 data = 0 ; /*DDR*/ 809 else 810 data = 1 ; /*DDRII*/ 811 return( data ) ; 812 } 813 else if ( HwDeviceExtension->jChipType == XG21 ) 814 { 815 XGI_SetRegAND( (XGIIOADDRESS) pVBInfo->P3d4 , 0xB4 , ~0x02 ) ; /* Independent GPIO control */ 816 DelayUS(800); 817 XGI_SetRegOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x4A , 0x80 ) ; /* Enable GPIOH read */ 818 temp = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x48 ) ; /* GPIOF 0:DVI 1:DVO */ 819 820 /* HOTPLUG_SUPPORT */ 821 /* for current XG20 & XG21, GPIOH is floating, driver will fix DDR temporarily */ 822 if ( temp & 0x01 ) /* DVI read GPIOH */ 823 data = 1 ; /*DDRII*/ 824 else 825 data = 0 ; /*DDR*/ 826 827 /*~HOTPLUG_SUPPORT */ 828 XGI_SetRegOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0xB4 , 0x02 ) ; 829 return( data ) ; 830 } 831 else 832 { 833 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x97 ) & 0x01 ; 834 835 if ( data == 1 ) 836 data ++ ; 837 838 return( data ); 839 } 840} 841 842 843/* --------------------------------------------------------------------- */ 844/* Function : XGINew_Delay15us */ 845/* Input : */ 846/* Output : */ 847/* Description : */ 848/* --------------------------------------------------------------------- */ 849/* 850void XGINew_Delay15us(ULONG ulMicrsoSec) 851{ 852} 853*/ 854 855 856/* --------------------------------------------------------------------- */ 857/* Function : XGINew_SDR_MRS */ 858/* Input : */ 859/* Output : */ 860/* Description : */ 861/* --------------------------------------------------------------------- */ 862void XGINew_SDR_MRS(PVB_DEVICE_INFO pVBInfo) 863{ 864 USHORT data ; 865 866 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 ) ; 867 data &= 0x3F ; /* SR16 D7=0,D6=0 */ 868 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) low */ 869 /* XGINew_Delay15us( 0x100 ) ; */ 870 data |= 0x80 ; /* SR16 D7=1,D6=0 */ 871 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) high */ 872 /* XGINew_Delay15us( 0x100 ) ; */ 873} 874 875 876/* --------------------------------------------------------------------- */ 877/* Function : XGINew_DDR1x_MRS_340 */ 878/* Input : */ 879/* Output : */ 880/* Description : */ 881/* --------------------------------------------------------------------- */ 882void XGINew_DDR1x_MRS_340(PXGI_HW_DEVICE_INFO HwDeviceExtension, USHORT P3c4, 883 PVB_DEVICE_INFO pVBInfo) 884{ 885 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x01 ) ; 886 if ( HwDeviceExtension->jChipType == XG42 ) /* XG42 BA0 & BA1 layout change */ 887 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ; 888 else 889 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x20 ) ; 890 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 891 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 892 893 /* Samsung F Die */ 894 if (pVBInfo->DRAMTypeDefinition != 0x0C) { 895 DelayUS( 3000 ) ; /* Delay 67 x 3 Delay15us */ 896 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; 897 if ( HwDeviceExtension->jChipType == XG42 ) 898 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ; 899 else 900 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x20 ) ; 901 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 902 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 903 } 904 905 DelayUS( 60 ) ; 906 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */ 907 908 if (HwDeviceExtension->jChipType == XG45) 909 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x01 ) ; /*TSop DRAM DLL pin jump to A9*/ 910 else 911 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x02 ) ; /*TSop DRAM DLL pin jump to A9*/ 912 913 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , pVBInfo->SR16[ 0 ] ) ; 914 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , pVBInfo->SR16[ 1 ] ) ; 915 DelayUS( 1000 ) ; 916 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , 0x03 ) ; 917 DelayUS( 500 ) ; 918 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */ 919 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x00 ) ; 920 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , pVBInfo->SR16[ 2 ] ) ; 921 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , pVBInfo->SR16[ 3 ] ) ; 922 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , 0x00 ) ; 923} 924 925 926/* --------------------------------------------------------------------- */ 927/* Function : XGINew_DDR2x_MRS_340 */ 928/* Input : */ 929/* Output : */ 930/* Description : */ 931/* --------------------------------------------------------------------- */ 932void XGINew_DDR2x_MRS_340(PXGI_HW_DEVICE_INFO HwDeviceExtension, USHORT P3c4, 933 PVB_DEVICE_INFO pVBInfo) 934{ 935 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; 936 if ( HwDeviceExtension->jChipType == XG42 ) /*XG42 BA0 & BA1 layout change*/ 937 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ; 938 else 939 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x20 ) ; 940 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 941 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 942 943 /* Samsung F Die */ 944 if (pVBInfo->DRAMTypeDefinition != 0x0C) { 945 DelayUS( 3000 ) ; /* Delay 67 x 3 Delay15us */ 946 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; 947 if ( HwDeviceExtension->jChipType == XG42 ) 948 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ; 949 else 950 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x20 ) ; 951 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 952 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 953 } 954 955 DelayUS( 60 ) ; 956 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */ 957 /* XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x31 ) ; */ 958 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x02 ) ; /*TSop DRAM DLL pin jump to A9*/ 959 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , pVBInfo->SR16[ 0 ] ) ; 960 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , pVBInfo->SR16[ 1 ] ) ; 961 DelayUS( 1000 ) ; 962 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , 0x03 ) ; 963 DelayUS( 500 ) ; 964 /* XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x31 ) ; */ 965 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */ 966 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x00 ) ; 967 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , pVBInfo->SR16[ 2 ] ) ; 968 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , pVBInfo->SR16[ 3 ] ) ; 969 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , 0x00 ) ; 970} 971 972 973/* --------------------------------------------------------------------- */ 974/* Function : XGINew_DDR2_MRS_340 */ 975/* Input : */ 976/* Output : */ 977/* Description : */ 978/* --------------------------------------------------------------------- */ 979void XGINew_DDR2_MRS_340(PXGI_HW_DEVICE_INFO HwDeviceExtension, USHORT P3c4, 980 PVB_DEVICE_INFO pVBInfo) 981{ 982 USHORT P3d4 = P3c4 + 0x10 ; 983 UCHAR data ; 984 985 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x28 , 0x64 ) ; /* SR28 */ 986 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x29 , 0x63 ) ; /* SR29 */ 987 DelayUS( 200 ) ; 988 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; 989 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x20 ) ; 990 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 991 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 992 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0xC5 ) ; 993 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x23 ) ; 994 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 995 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 996 DelayUS( 2 ) ; 997 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x97 , 0x11 ) ; /* CR97 */ 998 999 if( P3c4 != pVBInfo->P3c4 ) 1000 { 1001 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x28 ) ; 1002 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x28 , data ) ; /* SR28 */ 1003 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x29 ) ; 1004 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x29 , data ) ; /* SR29 */ 1005 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x2A ) ; 1006 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x2A , data ) ; /* SR2A */ 1007 1008 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x2E ) ; 1009 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x2e , data ) ; /* SR2E */ 1010 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x2F ) ; 1011 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x2f , data ) ; /* SR2F */ 1012 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x30 ) ; 1013 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x30 , data ) ; /* SR30 */ 1014 } 1015 else 1016 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; 1017 1018 DelayUS( 1000 ) ; 1019 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0xC5 ) ; 1020 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x23 ) ; 1021 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 1022 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 1023 DelayUS( 1 ) ; 1024 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , 0x04 ) ; /* SR1B */ 1025 DelayUS( 5) ; 1026 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , 0x00 ) ; /* SR1B */ 1027 DelayUS( 5 ) ; 1028 /* XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x72 ) ; */ 1029 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */ 1030 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x06 ) ; 1031 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x05 ) ; 1032 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x85 ) ; 1033 DelayUS( 1 ) ; 1034} 1035 1036/* --------------------------------------------------------------------- */ 1037/* Function : XGINew_DDRII_Bootup_XG27 */ 1038/* Input : */ 1039/* Output : */ 1040/* Description : */ 1041/* --------------------------------------------------------------------- */ 1042void XGINew_DDRII_Bootup_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension , USHORT P3c4 , PVB_DEVICE_INFO pVBInfo) 1043{ 1044 USHORT P3d4 = P3c4 + 0x10 ; 1045 UCHAR data ; 1046 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ; 1047 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; 1048 1049 /* Set Double Frequency */ 1050 /* XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; */ /* CR97 */ 1051 XGI_SetReg( (XGIIOADDRESS) P3d4 , 0x97 , pVBInfo->CR97 ) ; /* CR97 */ 1052 1053 DelayUS( 200 ) ; 1054 1055 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ /*EMRS2*/ 1056 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x80 ) ; /* Set SR19 */ 1057 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */ 1058 DelayUS( 15 ) ; 1059 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */ 1060 DelayUS( 15 ) ; 1061 1062 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ /*EMRS3*/ 1063 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0xC0 ) ; /* Set SR19 */ 1064 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */ 1065 DelayUS( 15 ) ; 1066 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */ 1067 DelayUS( 15) ; 1068 1069 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ /*EMRS1*/ 1070 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ; /* Set SR19 */ 1071 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */ 1072 DelayUS( 30 ) ; 1073 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */ 1074 DelayUS( 15 ) ; 1075 1076 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x42 ) ; /* Set SR18 */ /*MRS, DLL Enable*/ 1077 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x0A ) ; /* Set SR19 */ 1078 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */ 1079 DelayUS( 30 ) ; 1080 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */ 1081 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; /* Set SR16 */ 1082 /* DelayUS( 15 ) ; */ 1083 1084 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x1B , 0x04 ) ; /* Set SR1B */ 1085 DelayUS( 60 ) ; 1086 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x1B , 0x00 ) ; /* Set SR1B */ 1087 1088 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x42 ) ; /* Set SR18 */ /*MRS, DLL Reset*/ 1089 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x08 ) ; /* Set SR19 */ 1090 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */ 1091 1092 DelayUS( 30 ) ; 1093 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x83 ) ; /* Set SR16 */ 1094 DelayUS( 15 ) ; 1095 1096 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x80 ) ; /* Set SR18 */ /*MRS, ODT*/ 1097 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x46 ) ; /* Set SR19 */ 1098 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */ 1099 DelayUS( 30 ) ; 1100 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */ 1101 DelayUS( 15 ) ; 1102 1103 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ /*EMRS*/ 1104 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ; /* Set SR19 */ 1105 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */ 1106 DelayUS( 30 ) ; 1107 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */ 1108 DelayUS( 15 ) ; 1109 1110 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x1B , 0x04 ) ; /* Set SR1B refresh control 000:close; 010:open */ 1111 DelayUS( 200 ) ; 1112} 1113/* --------------------------------------------------------------------- */ 1114/* Function : XGINew_DDR2_MRS_XG20 */ 1115/* Input : */ 1116/* Output : */ 1117/* Description : */ 1118/* --------------------------------------------------------------------- */ 1119void XGINew_DDR2_MRS_XG20( PXGI_HW_DEVICE_INFO HwDeviceExtension , USHORT P3c4 , PVB_DEVICE_INFO pVBInfo) 1120{ 1121 USHORT P3d4 = P3c4 + 0x10 ; 1122 UCHAR data ; 1123 1124 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ; 1125 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; 1126 1127 XGI_SetReg( (XGIIOADDRESS) P3d4 , 0x97 , 0x11 ) ; /* CR97 */ 1128 1129 DelayUS( 200 ) ; 1130 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* EMRS2 */ 1131 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x80 ) ; 1132 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x05 ) ; 1133 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x85 ) ; 1134 1135 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* EMRS3 */ 1136 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0xC0 ) ; 1137 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x05 ) ; 1138 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x85 ) ; 1139 1140 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* EMRS1 */ 1141 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ; 1142 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x05 ) ; 1143 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x85 ) ; 1144 1145 /* XGINew_SetReg1( P3c4 , 0x18 , 0x52 ) ;*/ /* MRS1 */ 1146 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x42 ) ; /* MRS1 */ 1147 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x02 ) ; 1148 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x05 ) ; 1149 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x85 ) ; 1150 1151 DelayUS( 15 ) ; 1152 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x1B , 0x04 ) ; /* SR1B */ 1153 DelayUS( 30 ) ; 1154 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x1B , 0x00 ) ; /* SR1B */ 1155 DelayUS( 100 ) ; 1156 1157 /*XGINew_SetReg1( P3c4 , 0x18 , 0x52 ) ;*/ /* MRS2 */ 1158 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x42 ) ; /* MRS1 */ 1159 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x00 ) ; 1160 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x05 ) ; 1161 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x85 ) ; 1162 1163 DelayUS( 200 ) ; 1164} 1165 1166/* --------------------------------------------------------------------- */ 1167/* Function : XGINew_DDR2_MRS_XG27 */ 1168/* Input : */ 1169/* Output : */ 1170/* Description : */ 1171/* --------------------------------------------------------------------- */ 1172void XGINew_DDR2_MRS_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension , USHORT P3c4 , PVB_DEVICE_INFO pVBInfo) 1173{ 1174 USHORT P3d4 = P3c4 + 0x10 ; 1175 UCHAR data ; 1176 1177 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ; 1178 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; 1179 1180 XGI_SetReg( (XGIIOADDRESS) P3d4 , 0x97 , 0x11 ) ; /* CR97 */ 1181 DelayUS( 200 ) ; 1182 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* EMRS2 */ 1183 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x80 ) ; 1184 1185 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x10 ) ; 1186 DelayUS( 15 ) ; /* 06/11/23 XG27 A0 for CKE enable*/ 1187 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x90 ) ; 1188 1189 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* EMRS3 */ 1190 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0xC0 ) ; 1191 1192 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 1193 DelayUS( 15 ) ; /*06/11/22 XG27 A0*/ 1194 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 1195 1196 1197 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; /* EMRS1 */ 1198 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ; 1199 1200 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 1201 DelayUS( 15 ) ; /*06/11/22 XG27 A0 */ 1202 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 1203 1204 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x42 ) ; /* MRS1 */ 1205 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x06 ) ; /*[Billy]06/11/22 DLL Reset for XG27 Hynix DRAM*/ 1206 1207 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 1208 DelayUS( 15 ) ; /*06/11/23 XG27 A0*/ 1209 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 1210 1211 DelayUS( 30 ) ; /*06/11/23 XG27 A0 Start Auto-PreCharge*/ 1212 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x1B , 0x04 ) ; /* SR1B */ 1213 DelayUS( 60 ) ; 1214 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x1B , 0x00 ) ; /* SR1B */ 1215 1216 1217 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x42 ) ; /* MRS1 */ 1218 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x04 ) ; /* DLL without Reset for XG27 Hynix DRAM*/ 1219 1220 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 1221 DelayUS( 30 ) ; 1222 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 1223 1224 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x80 ); /*XG27 OCD ON */ 1225 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x46 ); 1226 1227 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 1228 DelayUS( 30 ) ; 1229 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 1230 1231 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x18 , 0x00 ); 1232 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x19 , 0x40 ); 1233 1234 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 1235 DelayUS( 30 ) ; 1236 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 1237 1238 DelayUS( 15 ) ; /*Start Auto-PreCharge*/ 1239 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x1B , 0x04 ) ; /* SR1B */ 1240 DelayUS( 200 ) ; 1241 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x1B , 0x03 ) ; /* SR1B */ 1242} 1243 1244 1245/* --------------------------------------------------------------------- */ 1246/* Function : XGINew_DDR1x_DefaultRegister */ 1247/* Input : */ 1248/* Output : */ 1249/* Description : */ 1250/* --------------------------------------------------------------------- */ 1251void XGINew_DDR1x_DefaultRegister(PXGI_HW_DEVICE_INFO HwDeviceExtension, 1252 USHORT Port, PVB_DEVICE_INFO pVBInfo) 1253{ 1254 USHORT P3d4 = Port , 1255 P3c4 = Port - 0x10 ; 1256#ifndef LINUX_XF86 1257 UCHAR data ; 1258#endif 1259 if ( HwDeviceExtension->jChipType >= XG20 ) 1260 { 1261 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; 1262 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */ 1263 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */ 1264 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */ 1265 1266 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x98 , 0x01 ) ; 1267 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x9A , 0x02 ) ; 1268 1269 XGINew_DDR1x_MRS_XG20( P3c4 , pVBInfo) ; 1270 } 1271 else 1272 { 1273 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; 1274 1275 switch( HwDeviceExtension->jChipType ) 1276 { 1277 case XG41: 1278 case XG42: 1279 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */ 1280 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */ 1281 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */ 1282 break ; 1283 default: 1284 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , 0x88 ) ; 1285 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , 0x00 ) ; 1286 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x86 ) ; /* Insert read command for delay */ 1287 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , 0x88 ) ; 1288 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x86 ) ; 1289 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; 1290 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , 0x77 ) ; 1291 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , 0x00 ) ; 1292 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x85 ) ; /* Insert read command for delay */ 1293 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , 0x88 ) ; 1294 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x85 ) ; /* Insert read command for delay */ 1295 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */ 1296 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */ 1297 break ; 1298 } 1299 if (HwDeviceExtension->jChipType != XG45) 1300 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x97 , 0x00 ) ; 1301 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x98 , 0x01 ) ; 1302 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x9A , 0x02 ) ; 1303 XGINew_DDR1x_MRS_340( HwDeviceExtension , P3c4 , pVBInfo ) ; 1304 } 1305} 1306 1307 1308/* --------------------------------------------------------------------- */ 1309/* Function : XGINew_DDR2x_DefaultRegister */ 1310/* Input : */ 1311/* Output : */ 1312/* Description : */ 1313/* --------------------------------------------------------------------- */ 1314void XGINew_DDR2x_DefaultRegister(PXGI_HW_DEVICE_INFO HwDeviceExtension, 1315 USHORT Port, PVB_DEVICE_INFO pVBInfo) 1316{ 1317 USHORT P3d4 = Port , 1318 P3c4 = Port - 0x10 ; 1319 1320#ifndef LINUX_XF86 1321 UCHAR data ; 1322#endif 1323 1324 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; 1325 1326 /* 20040906 Hsuan modify CR82, CR85, CR86 for XG42 */ 1327 switch( HwDeviceExtension->jChipType ) 1328 { 1329 case XG41: 1330 case XG42: 1331 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */ 1332 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */ 1333 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */ 1334 break ; 1335 default: 1336 /* keep following setting sequence, each setting in the same reg insert idle */ 1337 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , 0x88 ) ; 1338 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , 0x00 ) ; 1339 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x86 ) ; /* Insert read command for delay */ 1340 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , 0x88 ) ; 1341 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , 0x77 ) ; 1342 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , 0x00 ) ; 1343 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x85 ) ; /* Insert read command for delay */ 1344 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , 0x88 ) ; 1345 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x85 ) ; /* Insert read command for delay */ 1346 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */ 1347 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */ 1348 } 1349 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x97 , 0x11 ) ; 1350 if ( HwDeviceExtension->jChipType == XG42 ) 1351 { 1352 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x98 , 0x01 ) ; 1353 } 1354 else 1355 { 1356 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x98 , 0x03 ) ; 1357 } 1358 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x9A , 0x02 ) ; 1359 1360 XGINew_DDR2x_MRS_340( HwDeviceExtension , P3c4 , pVBInfo ) ; 1361} 1362 1363 1364/* --------------------------------------------------------------------- */ 1365/* Function : XGINew_DDR2_DefaultRegister */ 1366/* Input : */ 1367/* Output : */ 1368/* Description : */ 1369/* --------------------------------------------------------------------- */ 1370void XGINew_DDR2_DefaultRegister(PXGI_HW_DEVICE_INFO HwDeviceExtension, 1371 USHORT Port, PVB_DEVICE_INFO pVBInfo) 1372{ 1373 USHORT P3d4 = Port , 1374 P3c4 = Port - 0x10 ; 1375 1376 /* keep following setting sequence, each setting in the same reg insert idle */ 1377 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , 0x77 ) ; 1378 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , 0x00 ) ; 1379 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x86 ) ; /* Insert read command for delay */ 1380 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , 0x88 ) ; 1381 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x86 ) ; /* Insert read command for delay */ 1382 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */ 1383 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , 0x77 ) ; 1384 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , 0x00 ) ; 1385 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x85 ) ; /* Insert read command for delay */ 1386 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , 0x88 ) ; 1387 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x85 ) ; /* Insert read command for delay */ 1388 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */ 1389 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */ 1390 1391 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x98 , 0x03 ) ; 1392 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x9A , 0x02 ) ; 1393 1394 /* Jong 10/01/2007 */ 1395 if ( HwDeviceExtension->jChipType == XG27 ) 1396 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , P3c4 , pVBInfo) ; 1397 else if ( HwDeviceExtension->jChipType >= XG20 ) 1398 XGINew_DDR2_MRS_XG20( HwDeviceExtension , P3c4, pVBInfo ) ; 1399 else 1400 XGINew_DDR2_MRS_340( HwDeviceExtension , P3c4, pVBInfo ) ; 1401} 1402 1403 1404/* --------------------------------------------------------------------- */ 1405/* Function : XGINew_SetDRAMDefaultRegister340 */ 1406/* Input : */ 1407/* Output : */ 1408/* Description : */ 1409/* --------------------------------------------------------------------- */ 1410void XGINew_SetDRAMDefaultRegister340( PXGI_HW_DEVICE_INFO HwDeviceExtension , USHORT Port , PVB_DEVICE_INFO pVBInfo) 1411{ 1412 UCHAR temp , temp1 , temp2 , temp3 , 1413 i , j , k ; 1414 1415 USHORT P3d4 = Port , 1416 P3c4 = Port - 0x10 ; 1417 1418 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6D , pVBInfo->CR40[ 8 ][ XGINew_RAMType ] ) ; 1419 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x68 , pVBInfo->CR40[ 5 ][ XGINew_RAMType ] ) ; 1420 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x69 , pVBInfo->CR40[ 6 ][ XGINew_RAMType ] ) ; 1421 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6A , pVBInfo->CR40[ 7 ][ XGINew_RAMType ] ) ; 1422 1423 temp2 = 0 ; 1424 for( i = 0 ; i < 4 ; i++ ) 1425 { 1426 temp = pVBInfo->CR6B[ XGINew_RAMType ][ i ] ; /* CR6B DQS fine tune delay */ 1427 for( j = 0 ; j < 4 ; j++ ) 1428 { 1429 temp1 = ( ( temp >> ( 2 * j ) ) & 0x03 ) << 2 ; 1430 temp2 |= temp1 ; 1431 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6B , temp2 ) ; 1432 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x6B ) ; /* Insert read command for delay */ 1433 temp2 &= 0xF0 ; 1434 temp2 += 0x10 ; 1435 } 1436 } 1437 1438 temp2 = 0 ; 1439 for( i = 0 ; i < 4 ; i++ ) 1440 { 1441 temp = pVBInfo->CR6E[ XGINew_RAMType ][ i ] ; /* CR6E DQM fine tune delay */ 1442 for( j = 0 ; j < 4 ; j++ ) 1443 { 1444 temp1 = ( ( temp >> ( 2 * j ) ) & 0x03 ) << 2 ; 1445 temp2 |= temp1 ; 1446 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6E , temp2 ) ; 1447 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x6E ) ; /* Insert read command for delay */ 1448 temp2 &= 0xF0 ; 1449 temp2 += 0x10 ; 1450 } 1451 } 1452 1453 temp3 = 0 ; 1454 for( k = 0 ; k < 4 ; k++ ) 1455 { 1456 XGI_SetRegANDOR((XGIIOADDRESS) P3d4 , 0x6E , 0xFC , temp3 ) ; /* CR6E_D[1:0] select channel */ 1457 temp2 = 0 ; 1458 for( i = 0 ; i < 8 ; i++ ) 1459 { 1460 temp = pVBInfo->CR6F[ XGINew_RAMType ][ 8 * k + i ] ; /* CR6F DQ fine tune delay */ 1461 for( j = 0 ; j < 4 ; j++ ) 1462 { 1463 temp1 = ( temp >> ( 2 * j ) ) & 0x03 ; 1464 temp2 |= temp1 ; 1465 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6F , temp2 ) ; 1466 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x6F ) ; /* Insert read command for delay */ 1467 temp2 &= 0xF8 ; 1468 temp2 += 0x08 ; 1469 } 1470 } 1471 temp3 += 0x01 ; 1472 } 1473 1474 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x80 , pVBInfo->CR40[ 9 ][ XGINew_RAMType ] ) ; /* CR80 */ 1475 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x81 , pVBInfo->CR40[ 10 ][ XGINew_RAMType ] ) ; /* CR81 */ 1476 1477 temp2 = 0x80 ; 1478 temp = pVBInfo->CR89[ XGINew_RAMType ][ 0 ] ; /* CR89 terminator type select */ 1479 for( j = 0 ; j < 4 ; j++ ) 1480 { 1481 temp1 = ( temp >> ( 2 * j ) ) & 0x03 ; 1482 temp2 |= temp1 ; 1483 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x89 , temp2 ) ; 1484 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x89 ) ; /* Insert read command for delay */ 1485 temp2 &= 0xF0 ; 1486 temp2 += 0x10 ; 1487 } 1488 1489 temp = pVBInfo->CR89[ XGINew_RAMType ][ 1 ] ; 1490 temp1 = temp & 0x03 ; 1491 temp2 |= temp1 ; 1492 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x89 , temp2 ) ; 1493 1494 temp = pVBInfo->CR40[ 3 ][ XGINew_RAMType ] ; 1495 temp1 = temp & 0x0F ; 1496 temp2 = ( temp >> 4 ) & 0x07 ; 1497 temp3 = temp & 0x80 ; 1498 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x45 , temp1 ) ; /* CR45 */ 1499 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x99 , temp2 ) ; /* CR99 */ 1500 XGI_SetRegOR((XGIIOADDRESS) P3d4 , 0x40 , temp3 ) ; /* CR40_D[7] */ 1501 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x41 , pVBInfo->CR40[ 0 ][ XGINew_RAMType ] ) ; /* CR41 */ 1502 1503 /* Jong 10/01/2007; */ 1504 if ( HwDeviceExtension->jChipType == XG27 ) 1505 XGI_SetReg( (XGIIOADDRESS) P3d4 , 0x8F , *pVBInfo->pCR8F ) ; /* CR8F */ 1506 1507 for( j = 0 ; j <= 6 ; j++ ) 1508 XGI_SetReg((XGIIOADDRESS) P3d4 , ( 0x90 + j ) , pVBInfo->CR40[ 14 + j ][ XGINew_RAMType ] ) ; /* CR90 - CR96 */ 1509 1510 for( j = 0 ; j <= 2 ; j++ ) 1511 XGI_SetReg((XGIIOADDRESS) P3d4 , ( 0xC3 + j ) , pVBInfo->CR40[ 21 + j ][ XGINew_RAMType ] ) ; /* CRC3 - CRC5 */ 1512 1513 for( j = 0 ; j < 2 ; j++ ) 1514 XGI_SetReg((XGIIOADDRESS) P3d4 , ( 0x8A + j ) , pVBInfo->CR40[ 1 + j ][ XGINew_RAMType ] ) ; /* CR8A - CR8B */ 1515 1516 if ( ( HwDeviceExtension->jChipType == XG41 ) || ( HwDeviceExtension->jChipType == XG42 ) ) 1517 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x8C , 0x87 ) ; 1518 1519 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x59 , pVBInfo->CR40[ 4 ][ XGINew_RAMType ] ) ; /* CR59 */ 1520 1521 XGI_SetReg((XGIIOADDRESS) P3d4, 0x83, 0x09); /* CR83 */ 1522 XGI_SetReg((XGIIOADDRESS) P3d4, 0x87, 0x00); /* CR87 */ 1523 XGI_SetReg((XGIIOADDRESS) P3d4, 0xCF, pVBInfo->CRCF); /* CRCF */ 1524 1525 /* Jong 10/01/2007 */ 1526 if ( XGINew_RAMType ) 1527 { 1528 /*XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x17 , 0xC0 ) ;*/ /* SR17 DDRII */ 1529 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x17 , 0x80 ) ; /* SR17 DDRII */ 1530 if ( HwDeviceExtension->jChipType == XG27 ) 1531 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x17 , 0x02 ) ; /* SR17 DDRII */ 1532 1533 } 1534 else 1535 XGI_SetReg( (XGIIOADDRESS) P3c4 , 0x17 , 0x00 ) ; /* SR17 DDR */ 1536 1537 XGI_SetReg((XGIIOADDRESS) P3c4, 0x1A, 0x87); /* SR1A */ 1538 1539 temp = XGINew_Get340DRAMType( HwDeviceExtension, pVBInfo) ; 1540 if( temp == 0 ) 1541 XGINew_DDR1x_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ; 1542 else if ( temp == 0x02 ) 1543 XGINew_DDR2x_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ; 1544 else 1545 XGINew_DDR2_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ; 1546 1547 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */ 1548} 1549 1550/* --------------------------------------------------------------------- */ 1551/* Function : XGINew_SetDRAMDefaultRegisterXG45 */ 1552/* Input : */ 1553/* Output : */ 1554/* Description : */ 1555/* --------------------------------------------------------------------- */ 1556void XGINew_SetDRAMDefaultRegisterXG45( PXGI_HW_DEVICE_INFO HwDeviceExtension , USHORT Port , PVB_DEVICE_INFO pVBInfo) 1557{ 1558 UCHAR temp , temp1 , temp2 , 1559 i , j , k ; 1560 1561 USHORT P3d4 = Port , 1562 P3c4 = Port - 0x10 ; 1563 1564 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6D , pVBInfo->CR40[ 8 ][ XGINew_RAMType ] ) ; 1565 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6E , pVBInfo->XG45CR6E[ XGINew_RAMType ] ) ; 1566 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6F , pVBInfo->XG45CR6F[ XGINew_RAMType ] ) ; 1567 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x68 , pVBInfo->CR40[ 5 ][ XGINew_RAMType ] ) ; 1568 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x69 , pVBInfo->CR40[ 6 ][ XGINew_RAMType ] ) ; 1569 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6A , pVBInfo->CR40[ 7 ][ XGINew_RAMType ] ) ; 1570 1571 temp = 0x00 ; 1572 for ( j = 0 ; j < 24 ; j ++ ) 1573 { 1574 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x6B , temp ); 1575 temp += 0x08 ; 1576 } 1577 1578 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x80 , pVBInfo->CR40[ 9 ][ XGINew_RAMType ] ) ; /* CR80 */ 1579 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x81 , pVBInfo->CR40[ 10 ][ XGINew_RAMType ] ) ; /* CR81 */ 1580 1581 temp2 = 0x80 ; 1582 temp = pVBInfo->CR89[ XGINew_RAMType ][ 0 ] ; /* CR89 terminator type select */ 1583 for( j = 0 ; j < 4 ; j++ ) 1584 { 1585 temp1 = ( temp >> ( 2 * j ) ) & 0x03 ; 1586 temp2 |= temp1 ; 1587 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x89 , temp2 ) ; 1588 XGI_GetReg((XGIIOADDRESS) P3d4 , 0x89 ) ; /* Insert read command for delay */ 1589 temp2 &= 0xF0 ; 1590 temp2 += 0x10 ; 1591 } 1592 1593 temp = pVBInfo->CR89[ XGINew_RAMType ][ 1 ] ; 1594 temp1 = temp & 0x03 ; 1595 temp2 |= temp1 ; 1596 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x89 , temp2 ) ; 1597 1598 temp = 0x00 ; 1599 for ( j = 0 ; j < 3 ; j ++ ) 1600 { 1601 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x40 , temp ); 1602 temp += 0x40 ; 1603 } 1604 1605 temp = 0x00 ; 1606 for ( j = 0 ; j < 24 ; j ++ ) 1607 { 1608 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x41 , temp ); 1609 temp += 0x08 ; 1610 } 1611 1612 temp = 0x00 ; 1613 for ( j = 0 ; j < 24 ; j ++ ) 1614 { 1615 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x42 , temp ); 1616 temp += 0x08 ; 1617 } 1618 1619 for ( k = 0 ; k < 2 ; k ++ ) 1620 { 1621 XGI_SetRegANDOR((XGIIOADDRESS) P3d4 , 0x43 , ~0x04 , k * 0x04 ); 1622 1623 for ( i = 0 ; i < 3 ; i ++ ) 1624 { 1625 1626 XGI_SetRegANDOR((XGIIOADDRESS) P3d4 , 0x43 , ~0x03 , i * 0x01 ); 1627 1628 for ( j = 0 ; j < 32 ; j ++ ) 1629 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x44 , j * 0x08 ); 1630 } 1631 } 1632 1633 for ( j = 0 ; j < 3 ; j ++ ) 1634 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x45 , j * 0x08 ) ; /* CR45 */ 1635 1636 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x97 , 0x84 ) ; 1637 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x98 , 0x01 ) ; 1638 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x99 , 0x22 ) ; 1639 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x9A , 0x02 ) ; 1640 1641 for( j = 0 ; j <= 6 ; j++ ) 1642 XGI_SetReg((XGIIOADDRESS) P3d4 , ( 0x90 + j ) , pVBInfo->CR40[ 14 + j ][ XGINew_RAMType ] ) ; /* CR90 - CR96 */ 1643 1644 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x59 , pVBInfo->CR40[ 4 ][ XGINew_RAMType ] ) ; /* CR59 */ 1645 1646 for( j = 0 ; j <= 2 ; j++ ) 1647 XGI_SetReg((XGIIOADDRESS) P3d4 , ( 0xC3 + j ) , pVBInfo->CR40[ 21 + j ][ XGINew_RAMType ] ) ; /* CRC3 - CRC5 */ 1648 1649 XGI_SetReg((XGIIOADDRESS) P3d4 , 0xC8 , 0x04 ) ; 1650 1651 for( j = 0 ; j < 2 ; j++ ) 1652 XGI_SetReg((XGIIOADDRESS) P3d4 , ( 0x8A + j ) , pVBInfo->CR40[ 1 + j ][ XGINew_RAMType ] ) ; /* CR8A - CR8B */ 1653 1654 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x8C , 0x40 ) ; 1655 1656 if ( ( HwDeviceExtension->jChipType == XG41 ) || ( HwDeviceExtension->jChipType == XG42 ) ) 1657 XGI_SetReg((XGIIOADDRESS) P3d4 , 0x8C , 0x87 ) ; 1658 1659 XGI_SetReg((XGIIOADDRESS) P3d4, 0xCF, pVBInfo->CRCF); /* CRCF */ 1660 XGI_SetReg((XGIIOADDRESS) P3d4, 0x83, 0x09); /* CR83 */ 1661 XGI_SetReg((XGIIOADDRESS) P3d4, 0x87, 0x00); /* CR87 */ 1662 XGI_SetReg((XGIIOADDRESS) P3d4, 0x8D, 0x87); /* CR8D */ 1663 1664 XGINew_DDR1x_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ; 1665 1666 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1A , 0x87 ) ; /* SR1A */ 1667 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */ 1668} 1669 1670/* --------------------------------------------------------------------- */ 1671/* Function : XGINew_DDR_MRS */ 1672/* Input : */ 1673/* Output : */ 1674/* Description : */ 1675/* --------------------------------------------------------------------- */ 1676void XGINew_DDR_MRS(PVB_DEVICE_INFO pVBInfo) 1677{ 1678 USHORT data ; 1679 1680 PUCHAR volatile pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr ; 1681 1682 /* SR16 <- 1F,DF,2F,AF */ 1683 /* yriver modified SR16 <- 0F,DF,0F,AF */ 1684 /* enable DLL of DDR SD/SGRAM , SR16 D4=1 */ 1685 data = pVideoMemory[ 0xFB ] ; 1686 /* data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 ) ; */ 1687 1688 data &= 0x0F ; 1689 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ; 1690 data |= 0xC0 ; 1691 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ; 1692 data &= 0x0F ; 1693 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ; 1694 data |= 0x80 ; 1695 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ; 1696 data &= 0x0F ; 1697 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ; 1698 data |= 0xD0 ; 1699 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ; 1700 data &= 0x0F ; 1701 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ; 1702 data |= 0xA0 ; 1703 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x16 , data ) ; 1704/* 1705 else { 1706 data &= 0x0F; 1707 data |= 0x10; 1708 XGI_SetReg((XGIIOADDRESS)pVBInfo->P3c4,0x16,data); 1709 1710 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10)) 1711 { 1712 data &= 0x0F; 1713 } 1714 1715 data |= 0xC0; 1716 XGI_SetReg((XGIIOADDRESS)pVBInfo->P3c4,0x16,data); 1717 1718 1719 data &= 0x0F; 1720 data |= 0x20; 1721 XGI_SetReg((XGIIOADDRESS)pVBInfo->P3c4,0x16,data); 1722 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10)) 1723 { 1724 data &= 0x0F; 1725 } 1726 1727 data |= 0x80; 1728 XGI_SetReg((XGIIOADDRESS)pVBInfo->P3c4,0x16,data); 1729 } 1730*/ 1731} 1732 1733 1734/* --------------------------------------------------------------------- */ 1735/* Function : XGINew_SetDRAMSize_340 */ 1736/* Input : */ 1737/* Output : */ 1738/* Description : */ 1739/* --------------------------------------------------------------------- */ 1740void XGINew_SetDRAMSize_340( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo) 1741{ 1742 USHORT data ; 1743 1744 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ; 1745 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ; 1746 XGISetModeNew(HwDeviceExtension, pVBInfo, 0x2e); 1747 1748 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 ) ; 1749 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 , ( USHORT )( data & 0xDF ) ) ; /* disable read cache */ 1750 1751 /* Jong 10/03/2007; add support for DVO, XG27, ...*/ 1752 XGI_DisplayOff(HwDeviceExtension, pVBInfo ); 1753 /* data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x1 ) ; 1754 data |= 0x20 ; 1755 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x01 , data ) ; */ /* Turn OFF Display */ 1756 1757 XGINew_DDRSizing340( HwDeviceExtension, pVBInfo ) ; 1758 1759 data=XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 ) ; 1760 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 , ( USHORT )( data | 0x20 ) ) ; /* enable read cache */ 1761} 1762 1763 1764/*--------------------------------------------------------------------- */ 1765/* Function : XGINew_SetDRAMSize_XG45 */ 1766/*Input : */ 1767/*Output : */ 1768/*Description : */ 1769/*--------------------------------------------------------------------- */ 1770void XGINew_SetDRAMSize_XG45( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo) 1771{ 1772 USHORT data ; 1773 1774 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ; 1775 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ; 1776 XGISetModeNew(HwDeviceExtension, pVBInfo, 0x2e); 1777 1778 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 ) ; 1779 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 , ( USHORT )( data & 0xDF ) ) ; /*disable read cache*/ 1780 1781 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x1 ) ; 1782 data |= 0x20 ; 1783 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x01 , data ) ; /*Turn OFF Display*/ 1784 1785 XGINew_DDRSizingXG45( HwDeviceExtension, pVBInfo ) ; 1786 1787 data=XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 ) ; 1788 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x21 , ( USHORT )( data | 0x20 ) ) ; /*enable read cache*/ 1789} 1790 1791 1792/* --------------------------------------------------------------------- */ 1793/* Function : XGINew_SetDRAMModeRegister340 */ 1794/* Input : */ 1795/* Output : */ 1796/* Description : */ 1797/* --------------------------------------------------------------------- */ 1798 1799void XGINew_SetDRAMModeRegister340(PXGI_HW_DEVICE_INFO HwDeviceExtension, 1800 PVB_DEVICE_INFO pVBInfo) 1801{ 1802 UCHAR data ; 1803 1804 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ; 1805 1806 if (HwDeviceExtension->jChipType == XG45) 1807 XGINew_DDR1x_MRS_340( HwDeviceExtension, pVBInfo->P3c4, pVBInfo ) ; 1808 else 1809 { 1810 if ( XGINew_Get340DRAMType( HwDeviceExtension, pVBInfo) == 0 ) 1811 { 1812 data = ( XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x39 ) & 0x02 ) >> 1 ; 1813 if ( data == 0x01 ) 1814 XGINew_DDR2x_MRS_340( HwDeviceExtension, pVBInfo->P3c4, pVBInfo ) ; 1815 else 1816 XGINew_DDR1x_MRS_340( HwDeviceExtension, pVBInfo->P3c4, pVBInfo ) ; 1817 } 1818 else 1819 XGINew_DDR2_MRS_340( HwDeviceExtension, pVBInfo->P3c4, pVBInfo); 1820 } 1821 1822 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x1B , 0x03 ) ; 1823} 1824 1825 1826/* --------------------------------------------------------------------- */ 1827/* Function : XGINew_DisableRefresh */ 1828/* Input : */ 1829/* Output : */ 1830/* Description : */ 1831/* --------------------------------------------------------------------- */ 1832void XGINew_DisableRefresh( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo) 1833{ 1834 USHORT data ; 1835 1836 1837 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x1B ) ; 1838 data &= 0xF8 ; 1839 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x1B , data ) ; 1840 1841} 1842 1843 1844/* --------------------------------------------------------------------- */ 1845/* Function : XGINew_EnableRefresh */ 1846/* Input : */ 1847/* Output : */ 1848/* Description : */ 1849/* --------------------------------------------------------------------- */ 1850void XGINew_EnableRefresh( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo) 1851{ 1852 1853 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */ 1854 1855 1856} 1857 1858 1859/* --------------------------------------------------------------------- */ 1860/* Function : XGINew_DisableChannelInterleaving */ 1861/* Input : */ 1862/* Output : */ 1863/* Description : */ 1864/* --------------------------------------------------------------------- */ 1865void XGINew_DisableChannelInterleaving(int index, 1866 const USHORT XGINew_DDRDRAM_TYPE[][5], 1867 PVB_DEVICE_INFO pVBInfo) 1868{ 1869 USHORT data ; 1870 1871 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x15 ) ; 1872 data &= 0x1F ; 1873 1874 switch( XGINew_DDRDRAM_TYPE[ index ][ 3 ] ) 1875 { 1876 case 64: 1877 data |= 0 ; 1878 break ; 1879 case 32: 1880 data |= 0x20 ; 1881 break ; 1882 case 16: 1883 data |= 0x40 ; 1884 break ; 1885 case 4: 1886 data |= 0x60 ; 1887 break ; 1888 default: 1889 break ; 1890 } 1891 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x15 , data ) ; 1892} 1893 1894 1895/* --------------------------------------------------------------------- */ 1896/* Function : XGINew_SetDRAMSizingType */ 1897/* Input : */ 1898/* Output : */ 1899/* Description : */ 1900/* --------------------------------------------------------------------- */ 1901void XGINew_SetDRAMSizingType(int index , const USHORT DRAMTYPE_TABLE[][5], 1902 PVB_DEVICE_INFO pVBInfo) 1903{ 1904 USHORT data ; 1905 1906 data = DRAMTYPE_TABLE[ index ][ 4 ] ; 1907 XGI_SetRegANDOR((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x80 , data ) ; 1908 /* should delay 50 ns */ 1909} 1910 1911 1912/* --------------------------------------------------------------------- */ 1913/* Function : XGINew_SetRank */ 1914/* Input : */ 1915/* Output : */ 1916/* Description : */ 1917/* --------------------------------------------------------------------- */ 1918int XGINew_SetRank(int index, UCHAR RankNo, UCHAR XGINew_ChannelAB, 1919 const USHORT DRAMTYPE_TABLE[][5], PVB_DEVICE_INFO pVBInfo) 1920{ 1921 USHORT data ; 1922 int RankSize ; 1923 1924 if ( ( RankNo == 2 ) && ( DRAMTYPE_TABLE[ index ][ 0 ] == 2 ) ) 1925 return 0 ; 1926 1927 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] / 2 * XGINew_DataBusWidth / 32 ; 1928 1929 if ( ( RankNo * RankSize ) <= 128 ) 1930 { 1931 data = 0 ; 1932 1933 while( ( RankSize >>= 1 ) > 0 ) 1934 { 1935 data += 0x10 ; 1936 } 1937 data |= ( RankNo - 1 ) << 2 ; 1938 data |= ( XGINew_DataBusWidth / 64 ) & 2 ; 1939 data |= XGINew_ChannelAB ; 1940 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , data ) ; 1941 /* should delay */ 1942 XGINew_SDR_MRS( pVBInfo ) ; 1943 return( 1 ) ; 1944 } 1945 else 1946 return( 0 ) ; 1947} 1948 1949 1950/* --------------------------------------------------------------------- */ 1951/* Function : XGINew_SetDDRChannel */ 1952/* Input : */ 1953/* Output : */ 1954/* Description : */ 1955/* --------------------------------------------------------------------- */ 1956int XGINew_SetDDRChannel(int index, UCHAR ChannelNo, UCHAR XGINew_ChannelAB, 1957 const USHORT DRAMTYPE_TABLE[][5], 1958 PVB_DEVICE_INFO pVBInfo) 1959{ 1960 USHORT data ; 1961 int RankSize ; 1962 1963 RankSize = DRAMTYPE_TABLE[index][3]/2 * XGINew_DataBusWidth/32; 1964 /* RankSize = DRAMTYPE_TABLE[ index ][ 3 ] ; */ 1965 if ( ChannelNo * RankSize <= 128 ) 1966 { 1967 data = 0 ; 1968 while( ( RankSize >>= 1 ) > 0 ) 1969 { 1970 data += 0x10 ; 1971 } 1972 1973 if ( ChannelNo == 2 ) 1974 data |= 0x0C ; 1975 1976 data |= ( XGINew_DataBusWidth / 32 ) & 2 ; 1977 data |= XGINew_ChannelAB ; 1978 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , data ) ; 1979 /* should delay */ 1980 XGINew_DDR_MRS( pVBInfo ) ; 1981 return( 1 ) ; 1982 } 1983 else 1984 return( 0 ) ; 1985} 1986 1987 1988/* --------------------------------------------------------------------- */ 1989/* Function : XGINew_CheckColumn */ 1990/* Input : */ 1991/* Output : */ 1992/* Description : */ 1993/* --------------------------------------------------------------------- */ 1994int XGINew_CheckColumn(int index, const USHORT DRAMTYPE_TABLE[][5], 1995 PVB_DEVICE_INFO pVBInfo) 1996{ 1997 int i ; 1998 ULONG Increment , Position ; 1999 2000 /* Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + XGINew_DataBusWidth / 64 + 1 ) ; */ 2001 Increment = 1 << ( 10 + XGINew_DataBusWidth / 64 ) ; 2002 2003 for( i = 0 , Position = 0 ; i < 2 ; i++ ) 2004 { 2005 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ; 2006 Position += Increment ; 2007 } 2008 2009 for( i = 0 , Position = 0 ; i < 2 ; i++ ) 2010 { 2011 /* if ( pVBInfo->FBAddr[ Position ] != Position ) */ 2012 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position ) 2013 return( 0 ) ; 2014 Position += Increment ; 2015 } 2016 return( 1 ) ; 2017} 2018 2019 2020/* --------------------------------------------------------------------- */ 2021/* Function : XGINew_CheckBanks */ 2022/* Input : */ 2023/* Output : */ 2024/* Description : */ 2025/* --------------------------------------------------------------------- */ 2026int XGINew_CheckBanks(int index, const USHORT DRAMTYPE_TABLE[][5], 2027 PVB_DEVICE_INFO pVBInfo) 2028{ 2029 int i ; 2030 ULONG Increment , Position ; 2031 2032 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + XGINew_DataBusWidth / 64 + 2 ) ; 2033 2034 for( i = 0 , Position = 0 ; i < 4 ; i++ ) 2035 { 2036 /* pVBInfo->FBAddr[ Position ] = Position ; */ 2037 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ; 2038 Position += Increment ; 2039 } 2040 2041 for( i = 0 , Position = 0 ; i < 4 ; i++ ) 2042 { 2043 /* if (pVBInfo->FBAddr[ Position ] != Position ) */ 2044 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position ) 2045 return( 0 ) ; 2046 Position += Increment ; 2047 } 2048 return( 1 ) ; 2049} 2050 2051 2052/* --------------------------------------------------------------------- */ 2053/* Function : XGINew_CheckRank */ 2054/* Input : */ 2055/* Output : */ 2056/* Description : */ 2057/* --------------------------------------------------------------------- */ 2058int XGINew_CheckRank(int RankNo, int index, const USHORT DRAMTYPE_TABLE[][5], 2059 PVB_DEVICE_INFO pVBInfo) 2060{ 2061 int i ; 2062 ULONG Increment , Position ; 2063 2064 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + DRAMTYPE_TABLE[ index ][ 1 ] + 2065 DRAMTYPE_TABLE[ index ][ 0 ] + XGINew_DataBusWidth / 64 + RankNo ) ; 2066 2067 for( i = 0 , Position = 0 ; i < 2 ; i++ ) 2068 { 2069 /* pVBInfo->FBAddr[ Position ] = Position ; */ 2070 /* *( ( PULONG )( pVBInfo->FBAddr ) ) = Position ; */ 2071 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ; 2072 Position += Increment ; 2073 } 2074 2075 for( i = 0 , Position = 0 ; i < 2 ; i++ ) 2076 { 2077 /* if ( pVBInfo->FBAddr[ Position ] != Position ) */ 2078 /* if ( ( *( PULONG )( pVBInfo->FBAddr ) ) != Position ) */ 2079 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position ) 2080 return( 0 ) ; 2081 Position += Increment ; 2082 } 2083 return( 1 ); 2084} 2085 2086 2087/* --------------------------------------------------------------------- */ 2088/* Function : XGINew_CheckDDRRank */ 2089/* Input : */ 2090/* Output : */ 2091/* Description : */ 2092/* --------------------------------------------------------------------- */ 2093int XGINew_CheckDDRRank(int RankNo, int index, 2094 const USHORT DRAMTYPE_TABLE[][5], 2095 PVB_DEVICE_INFO pVBInfo) 2096{ 2097 ULONG Increment , Position ; 2098 USHORT data ; 2099 2100 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + DRAMTYPE_TABLE[ index ][ 1 ] + 2101 DRAMTYPE_TABLE[ index ][ 0 ] + XGINew_DataBusWidth / 64 + RankNo ) ; 2102 2103 Increment += Increment / 2 ; 2104 2105 Position = 0; 2106 *( ( PULONG )( pVBInfo->FBAddr + Position + 0 ) ) = 0x01234567 ; 2107 *( ( PULONG )( pVBInfo->FBAddr + Position + 1 ) ) = 0x456789AB ; 2108 *( ( PULONG )( pVBInfo->FBAddr + Position + 2 ) ) = 0x55555555 ; 2109 *( ( PULONG )( pVBInfo->FBAddr + Position + 3 ) ) = 0x55555555 ; 2110 *( ( PULONG )( pVBInfo->FBAddr + Position + 4 ) ) = 0xAAAAAAAA ; 2111 *( ( PULONG )( pVBInfo->FBAddr + Position + 5 ) ) = 0xAAAAAAAA ; 2112 2113 if ( ( *( PULONG )( pVBInfo->FBAddr + 1 ) ) == 0x456789AB ) 2114 return( 1 ) ; 2115 2116 if ( ( *( PULONG )( pVBInfo->FBAddr + 0 ) ) == 0x01234567 ) 2117 return( 0 ) ; 2118 2119 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 ) ; 2120 data &= 0xF3 ; 2121 data |= 0x0E ; 2122 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , data ) ; 2123 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x15 ) ; 2124 data += 0x20 ; 2125 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x15 , data ) ; 2126 2127 return( 1 ) ; 2128} 2129 2130 2131/* --------------------------------------------------------------------- */ 2132/* Function : XGINew_CheckRanks */ 2133/* Input : */ 2134/* Output : */ 2135/* Description : */ 2136/* --------------------------------------------------------------------- */ 2137int XGINew_CheckRanks(int RankNo, int index, const USHORT DRAMTYPE_TABLE[][5], 2138 PVB_DEVICE_INFO pVBInfo) 2139{ 2140 int r ; 2141 2142 for( r = RankNo ; r >= 1 ; r-- ) 2143 { 2144 if ( !XGINew_CheckRank( r , index , DRAMTYPE_TABLE, pVBInfo ) ) 2145 return( 0 ) ; 2146 } 2147 2148 if ( !XGINew_CheckBanks( index , DRAMTYPE_TABLE, pVBInfo ) ) 2149 return( 0 ) ; 2150 2151 if ( !XGINew_CheckColumn( index , DRAMTYPE_TABLE, pVBInfo ) ) 2152 return( 0 ) ; 2153 2154 return( 1 ) ; 2155} 2156 2157 2158/* --------------------------------------------------------------------- */ 2159/* Function : XGINew_CheckDDRRanks */ 2160/* Input : */ 2161/* Output : */ 2162/* Description : */ 2163/* --------------------------------------------------------------------- */ 2164int XGINew_CheckDDRRanks(int RankNo, int index, 2165 const USHORT DRAMTYPE_TABLE[][5], 2166 PVB_DEVICE_INFO pVBInfo) 2167{ 2168 int r ; 2169 2170 for( r = RankNo ; r >= 1 ; r-- ) 2171 { 2172 if ( !XGINew_CheckDDRRank( r , index , DRAMTYPE_TABLE, pVBInfo ) ) 2173 return( 0 ) ; 2174 } 2175 2176 if ( !XGINew_CheckBanks( index , DRAMTYPE_TABLE, pVBInfo ) ) 2177 return( 0 ) ; 2178 2179 if ( !XGINew_CheckColumn( index , DRAMTYPE_TABLE, pVBInfo ) ) 2180 return( 0 ) ; 2181 2182 return( 1 ) ; 2183} 2184 2185 2186/* --------------------------------------------------------------------- */ 2187/* Function : */ 2188/* Input : */ 2189/* Output : */ 2190/* Description : */ 2191/* --------------------------------------------------------------------- */ 2192int XGINew_SDRSizing(PVB_DEVICE_INFO pVBInfo) 2193{ 2194 int i ; 2195 UCHAR j ; 2196 2197 for( i = 0 ; i < 13 ; i++ ) 2198 { 2199 XGINew_SetDRAMSizingType( i , XGINew_SDRDRAM_TYPE , pVBInfo) ; 2200 2201 for( j = 2 ; j > 0 ; j-- ) 2202 { 2203 if ( !XGINew_SetRank( i , ( UCHAR )j , XGINew_ChannelAB , XGINew_SDRDRAM_TYPE , pVBInfo) ) 2204 continue ; 2205 else 2206 { 2207 if ( XGINew_CheckRanks( j , i , XGINew_SDRDRAM_TYPE, pVBInfo) ) 2208 return( 1 ) ; 2209 } 2210 } 2211 } 2212 return( 0 ) ; 2213} 2214 2215 2216/* --------------------------------------------------------------------- */ 2217/* Function : XGINew_SetDRAMSizeReg */ 2218/* Input : */ 2219/* Output : */ 2220/* Description : */ 2221/* --------------------------------------------------------------------- */ 2222USHORT XGINew_SetDRAMSizeReg(int index, const USHORT DRAMTYPE_TABLE[][5], 2223 PVB_DEVICE_INFO pVBInfo) 2224{ 2225 USHORT data = 0 , memsize = 0 ; 2226 int RankSize ; 2227 UCHAR ChannelNo ; 2228 2229 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] * XGINew_DataBusWidth / 32 ; 2230 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 ) ; 2231 data &= 0x80 ; 2232 2233 if ( data == 0x80 ) 2234 RankSize *= 2 ; 2235 2236 data = 0 ; 2237 2238 if( XGINew_ChannelAB == 3 ) 2239 ChannelNo = 4 ; 2240 else 2241 ChannelNo = XGINew_ChannelAB ; 2242 2243 if ( ChannelNo * RankSize <= 256 ) 2244 { 2245 while( ( RankSize >>= 1 ) > 0 ) 2246 { 2247 data += 0x10 ; 2248 } 2249 2250 memsize = data >> 4 ; 2251 2252 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */ 2253 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , ( XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ; 2254 2255 /* data |= XGINew_ChannelAB << 2 ; */ 2256 /* data |= ( XGINew_DataBusWidth / 64 ) << 1 ; */ 2257 /* XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , data ) ; */ 2258 2259 /* should delay */ 2260 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */ 2261 } 2262 return( memsize ) ; 2263} 2264 2265/* --------------------------------------------------------------------- */ 2266/* Function : XGINew_SetDRAMSize20Reg */ 2267/* Input : */ 2268/* Output : */ 2269/* Description : */ 2270/* --------------------------------------------------------------------- */ 2271USHORT XGINew_SetDRAMSize20Reg( int index , USHORT DRAMTYPE_TABLE[][ 5 ], PVB_DEVICE_INFO pVBInfo) 2272{ 2273 USHORT data = 0 , memsize = 0 ; 2274 int RankSize ; 2275 UCHAR ChannelNo ; 2276 2277 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] * XGINew_DataBusWidth / 8 ; 2278 data = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3c4 , 0x13 ) ; 2279 data &= 0x80 ; 2280 2281 if ( data == 0x80 ) 2282 RankSize *= 2 ; 2283 2284 data = 0 ; 2285 2286 if( XGINew_ChannelAB == 3 ) 2287 ChannelNo = 4 ; 2288 else 2289 ChannelNo = XGINew_ChannelAB ; 2290 2291 if ( ChannelNo * RankSize <= 256 ) 2292 { 2293 while( ( RankSize >>= 1 ) > 0 ) 2294 { 2295 data += 0x10 ; 2296 } 2297 2298 memsize = data >> 4 ; 2299 2300 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */ 2301 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , ( XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ; 2302 DelayUS( 15 ) ; 2303 2304 /* data |= XGINew_ChannelAB << 2 ; */ 2305 /* data |= ( XGINew_DataBusWidth / 64 ) << 1 ; */ 2306 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; */ 2307 2308 /* should delay */ 2309 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */ 2310 } 2311 return( memsize ) ; 2312} 2313 2314 2315/* --------------------------------------------------------------------- */ 2316/* Function : XGINew_ReadWriteRest */ 2317/* Input : */ 2318/* Output : */ 2319/* Description : */ 2320/* --------------------------------------------------------------------- */ 2321int XGINew_ReadWriteRest( USHORT StopAddr, USHORT StartAddr, 2322 PVB_DEVICE_INFO pVBInfo) 2323{ 2324 int i ; 2325 ULONG Position = 0 ; 2326 2327 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ; 2328 2329 for( i = StartAddr ; i <= StopAddr ; i++ ) 2330 { 2331 Position = 1 << i ; 2332 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ; 2333 } 2334 2335 DelayUS( 500 ) ; /* [Vicent] 2004/04/16. Fix #1759 Memory Size error in Multi-Adapter. */ 2336 2337 Position = 0 ; 2338 2339 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position ) 2340 return( 0 ) ; 2341 2342 for( i = StartAddr ; i <= StopAddr ; i++ ) 2343 { 2344 Position = 1 << i ; 2345 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position ) 2346 return( 0 ) ; 2347 } 2348 return( 1 ) ; 2349} 2350 2351 2352/*--------------------------------------------------------------------- */ 2353/* Function : XGI45New_ReadWriteRest */ 2354/* Input : */ 2355/* Output : */ 2356/* Description : return 0 : fail, 1 : pass */ 2357/*--------------------------------------------------------------------- */ 2358int XGI45New_ReadWriteRest(USHORT StopAddr, USHORT StartAddr, 2359 PVB_DEVICE_INFO pVBInfo) 2360{ 2361 int i ; 2362 ULONG Position = 0 ; 2363 2364 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ; 2365 2366 for( i = StartAddr ; i <= StopAddr ; i++ ) 2367 { 2368 Position = 1 << i ; 2369 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ; 2370 } 2371 2372 if ( XGINew_ChannelAB == 4 ) 2373 { 2374 Position = ( 1 << StopAddr ) + ( 1 << ( StopAddr - 1 ) ); 2375 *( ( PULONG )( pVBInfo->FBAddr + Position ) ) = Position ; 2376 } 2377 2378 DelayUS( 500 ) ; /* [Vicent] 2004/04/16. Fix #1759 Memory Size error in Multi-Adapter. */ 2379 2380 Position = 0 ; 2381 2382 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position ) 2383 return( 0 ) ; 2384 2385 for( i = StartAddr ; i <= StopAddr ; i++ ) 2386 { 2387 Position = 1 << i ; 2388 if ( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position ) 2389 return( 0 ) ; 2390 } 2391 2392 if ( XGINew_ChannelAB == 4 ) 2393 { 2394 Position = ( 1 << StopAddr ) + ( 1 << ( StopAddr - 1 ) ); 2395 if( ( *( PULONG )( pVBInfo->FBAddr + Position ) ) != Position ); 2396 return( 0 ) ; 2397 } 2398 return( 1 ) ; 2399} 2400 2401 2402/* --------------------------------------------------------------------- */ 2403/* Function : XGINew_CheckFrequence */ 2404/* Input : */ 2405/* Output : */ 2406/* Description : */ 2407/* --------------------------------------------------------------------- */ 2408UCHAR XGINew_CheckFrequence(PVB_DEVICE_INFO pVBInfo) 2409{ 2410 UCHAR data ; 2411 2412 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x97 ) ; 2413 2414 if ( ( data & 0x10 ) == 0 ) 2415 { 2416 data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x39 ) ; 2417 data = ( data & 0x02 ) >> 1 ; 2418 return( data ) ; 2419 } 2420 else 2421 return( data & 0x01 ) ; 2422} 2423 2424 2425/* --------------------------------------------------------------------- */ 2426/* Function : XGINew_CheckChannel */ 2427/* Input : */ 2428/* Output : */ 2429/* Description : */ 2430/* --------------------------------------------------------------------- */ 2431void XGINew_CheckChannel(PXGI_HW_DEVICE_INFO HwDeviceExtension, 2432 PVB_DEVICE_INFO pVBInfo) 2433{ 2434 UCHAR i, data ; 2435 2436 switch( HwDeviceExtension->jChipType ) 2437 { 2438 case XG20: 2439 case XG21: 2440 data = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x97 ) ; 2441 data = data & 0x01; 2442 XGINew_ChannelAB = 1 ; /* XG20 "JUST" one channel */ 2443 2444 if ( data == 0 ) /* Single_32_16 */ 2445 { 2446 /* Jong 10/03/2007 */ 2447 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x1000000) 2448 { 2449 2450 XGINew_DataBusWidth = 32 ; /* 32 bits */ 2451 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 32bit */ 2452 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x52 ) ; 2453 DelayUS( 15 ) ; 2454 2455 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2456 return ; 2457 2458 /* Jong 10/03/2007 */ 2459 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000) 2460 { 2461 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* 22bit + 1 rank + 32bit */ 2462 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x42 ) ; 2463 DelayUS( 15 ) ; 2464 2465 if ( XGINew_ReadWriteRest( 23 , 23 , pVBInfo ) == 1 ) 2466 return ; 2467 } 2468 } 2469 2470 /* Jong 10/03/2007 */ 2471 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000) 2472 { 2473 XGINew_DataBusWidth = 16 ; /* 16 bits */ 2474 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 16bit */ 2475 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x41 ) ; 2476 DelayUS( 15 ) ; 2477 2478 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 ) 2479 return ; 2480 else 2481 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x31 ) ; 2482 2483 DelayUS( 15 ) ; 2484 } 2485 } 2486 else /* Dual_16_8 */ 2487 { 2488 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000) 2489 { 2490 2491 XGINew_DataBusWidth = 16 ; /* 16 bits */ 2492 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xB1 ) ; 2493 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x41 ) ; 2494 DelayUS( 15 ) ; 2495 2496 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 ) 2497 return ; 2498 2499 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x400000) 2500 { 2501 2502 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x31 ) ; 2503 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x31 ) ; 2504 DelayUS( 15 ) ; 2505 2506 if ( XGINew_ReadWriteRest( 22 , 22 , pVBInfo ) == 1 ) 2507 return ; 2508 } 2509 } 2510 2511 2512 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x400000) 2513 { 2514 XGINew_DataBusWidth = 8 ; /* 8 bits */ 2515 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xB1 ) ; 2516 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x30 ) ; 2517 DelayUS( 15 ) ; 2518 2519 if ( XGINew_ReadWriteRest( 22 , 21 , pVBInfo ) == 1 ) 2520 return ; 2521 else 2522 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x31 ) ; 2523 DelayUS( 15 ) ; 2524 } 2525 } 2526 break ; 2527 2528 case XG27: 2529 XGINew_DataBusWidth = 16 ; /* 16 bits */ 2530 XGINew_ChannelAB = 1 ; /* Single channel */ 2531 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x51 ) ; /* 32Mx16 bit*/ 2532 break ; 2533 2534 case XG41: 2535 if ( XGINew_CheckFrequence(pVBInfo) == 1 ) 2536 { 2537 XGINew_DataBusWidth = 32 ; /* 32 bits */ 2538 XGINew_ChannelAB = 3 ; /* Quad Channel */ 2539 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ; 2540 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x4C ) ; 2541 2542 if ( XGINew_ReadWriteRest( 25 , 23 , pVBInfo ) == 1 ) 2543 return ; 2544 2545 XGINew_ChannelAB = 2 ; /* Dual channels */ 2546 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x48 ) ; 2547 2548 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2549 return ; 2550 2551 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x49 ) ; 2552 2553 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2554 return ; 2555 2556 XGINew_ChannelAB = 3 ; 2557 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2558 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x3C ) ; 2559 2560 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2561 return ; 2562 2563 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x38 ) ; 2564 2565 if ( XGINew_ReadWriteRest( 8 , 4 , pVBInfo ) == 1 ) 2566 return ; 2567 else 2568 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x39 ) ; 2569 } 2570 else 2571 { /* DDR */ 2572 XGINew_DataBusWidth = 64 ; /* 64 bits */ 2573 XGINew_ChannelAB = 2 ; /* Dual channels */ 2574 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ; 2575 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x5A ) ; 2576 2577 if ( XGINew_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 ) 2578 return ; 2579 2580 XGINew_ChannelAB = 1 ; /* Single channels */ 2581 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x52 ) ; 2582 2583 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2584 return ; 2585 2586 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x53 ) ; 2587 2588 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2589 return ; 2590 2591 XGINew_ChannelAB = 2 ; /* Dual channels */ 2592 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2593 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x4A ) ; 2594 2595 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2596 return ; 2597 2598 XGINew_ChannelAB = 1 ; /* Single channels */ 2599 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x42 ) ; 2600 2601 if ( XGINew_ReadWriteRest( 8 , 4 , pVBInfo ) == 1 ) 2602 return ; 2603 else 2604 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x43 ) ; 2605 } 2606 2607 break ; 2608 2609 case XG42: 2610/* 2611 XG42 SR14 D[3] Reserve 2612 D[2] = 1, Dual Channel 2613 = 0, Single Channel 2614 2615 It's Different from Other XG40 Series. 2616*/ 2617 if ( XGINew_CheckFrequence(pVBInfo) == 1 ) /* DDRII, DDR2x */ 2618 { 2619 XGINew_DataBusWidth = 32 ; /* 32 bits */ 2620 XGINew_ChannelAB = 2 ; /* 2 Channel */ 2621 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ; 2622 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x44 ) ; 2623 2624 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2625 return ; 2626 2627 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2628 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x34 ) ; 2629 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 ) 2630 return ; 2631 2632 XGINew_ChannelAB = 1 ; /* Single Channel */ 2633 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ; 2634 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x40 ) ; 2635 2636 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 ) 2637 return ; 2638 else 2639 { 2640 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2641 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x30 ) ; 2642 } 2643 } 2644 else 2645 { /* DDR */ 2646 XGINew_DataBusWidth = 64 ; /* 64 bits */ 2647 XGINew_ChannelAB = 1 ; /* 1 channels */ 2648 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ; 2649 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x52 ) ; 2650 2651 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2652 return ; 2653 else 2654 { 2655 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2656 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x42 ) ; 2657 } 2658 } 2659 2660 break ; 2661 2662 case XG45: 2663 2664 XGINew_DataBusWidth = 64 ; /* 64 bits */ 2665 XGINew_ChannelAB = 4 ; /* 3+1 Channel */ 2666 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2667 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x4C ) ; 2668 2669 if ( XGI45New_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 ) 2670 return ; 2671 2672 XGINew_ChannelAB = 3 ; /* 3 Channel */ 2673 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ; 2674 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x58 ) ; 2675 2676 if ( XGI45New_ReadWriteRest( 26 , 24 , pVBInfo ) == 1 ) 2677 return ; 2678 2679 XGINew_ChannelAB = 2 ; /* 2 Channel */ 2680 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ; 2681 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x54 ) ; 2682 2683 if ( XGI45New_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 ) 2684 return ; 2685 2686 XGINew_ChannelAB = 1 ; /* 1 Channel */ 2687 for ( i = 0; i <= 2; i++) 2688 { 2689 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ; 2690 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x50+i ) ; 2691 2692 if ( XGI45New_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2693 return ; 2694 } 2695 2696 XGINew_ChannelAB = 3 ; /* 3 Channel */ 2697 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2698 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x58 ) ; 2699 2700 if ( XGI45New_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 ) 2701 return ; 2702 2703 XGINew_ChannelAB = 2 ; /* 2 Channel */ 2704 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2705 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x54 ) ; 2706 2707 if ( XGI45New_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2708 return ; 2709 2710 XGINew_ChannelAB = 1 ; /* 1 Channel */ 2711 for ( i = 0; i <= 2; i++) 2712 { 2713 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2714 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x50+i ) ; 2715 2716 if ( XGI45New_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 ) 2717 return ; 2718 } 2719 break ; 2720 2721 default: /* XG40 */ 2722 2723 if ( XGINew_CheckFrequence(pVBInfo) == 1 ) /* DDRII */ 2724 { 2725 XGINew_DataBusWidth = 32 ; /* 32 bits */ 2726 XGINew_ChannelAB = 3 ; 2727 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ; 2728 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x4C ) ; 2729 2730 if ( XGINew_ReadWriteRest( 25 , 23 , pVBInfo ) == 1 ) 2731 return ; 2732 2733 XGINew_ChannelAB = 2 ; /* 2 channels */ 2734 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x48 ) ; 2735 2736 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2737 return ; 2738 2739 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2740 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x3C ) ; 2741 2742 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 ) 2743 XGINew_ChannelAB = 3 ; /* 4 channels */ 2744 else 2745 { 2746 XGINew_ChannelAB = 2 ; /* 2 channels */ 2747 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x38 ) ; 2748 } 2749 } 2750 else 2751 { /* DDR */ 2752 XGINew_DataBusWidth = 64 ; /* 64 bits */ 2753 XGINew_ChannelAB = 2 ; /* 2 channels */ 2754 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0xA1 ) ; 2755 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x5A ) ; 2756 2757 if ( XGINew_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 ) 2758 return ; 2759 else 2760 { 2761 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x13 , 0x21 ) ; 2762 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x14 , 0x4A ) ; 2763 } 2764 } 2765 break ; 2766 } 2767} 2768 2769 2770/* --------------------------------------------------------------------- */ 2771/* Function : XGINew_DDRSizing340 */ 2772/* Input : */ 2773/* Output : */ 2774/* Description : */ 2775/* --------------------------------------------------------------------- */ 2776int XGINew_DDRSizing340( PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) 2777{ 2778 int i ; 2779 USHORT memsize , addr ; 2780 2781 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x15 , 0x00 ) ; /* noninterleaving */ 2782 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x1C , 0x00 ) ; /* nontiling */ 2783 XGINew_CheckChannel( HwDeviceExtension, pVBInfo ) ; 2784 2785 /* Jong 10/03/2007 */ 2786 if ( HwDeviceExtension->jChipType >= XG20 ) 2787 { 2788 for( i = 0 ; i < 12 ; i++ ) 2789 { 2790 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE20, pVBInfo ) ; 2791 memsize = XGINew_SetDRAMSize20Reg( i , XGINew_DDRDRAM_TYPE20, pVBInfo ) ; 2792 if ( memsize == 0 ) 2793 continue ; 2794 2795 addr = memsize + ( XGINew_ChannelAB - 2 ) + 20 ; 2796 if ( ( HwDeviceExtension->ulVideoMemorySize - 1 ) < ( ULONG )( 1 << addr ) ) 2797 continue ; 2798 2799 if ( XGINew_ReadWriteRest( addr , 5, pVBInfo ) == 1 ) 2800 return( 1 ) ; 2801 } 2802 } 2803 else 2804 { 2805 for( i = 0 ; i < 4 ; i++ ) 2806 { 2807 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ; 2808 memsize = XGINew_SetDRAMSizeReg( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ; 2809 if ( memsize == 0 ) 2810 continue ; 2811 2812 addr = memsize + ( XGINew_ChannelAB - 2 ) + 20 ; 2813 if ( ( HwDeviceExtension->ulVideoMemorySize - 1 ) < ( ULONG )( 1 << addr ) ) 2814 continue ; 2815 2816 if ( XGINew_ReadWriteRest( addr , 9, pVBInfo ) == 1 ) 2817 return( 1 ) ; 2818 } 2819 } 2820 return( 0 ) ; 2821} 2822 2823 2824/*--------------------------------------------------------------------- */ 2825/* Function : XGINew_DDRSizingXG45 */ 2826/* Input : */ 2827/* Output : */ 2828/* Description : */ 2829/*--------------------------------------------------------------------- */ 2830int XGINew_DDRSizingXG45( PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) 2831{ 2832 int i ; 2833 USHORT memsize , addr ; 2834 2835 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x15 , 0x00 ) ; /* noninterleaving */ 2836 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x1C , 0x00 ) ; /* nontiling */ 2837 XGINew_CheckChannel( HwDeviceExtension, pVBInfo ) ; 2838 2839 for( i = 0 ; i < 4 ; i++ ) 2840 { 2841 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ; 2842 memsize = XGINew_SetDRAMSizeReg( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ; 2843 if ( memsize == 0 ) 2844 continue ; 2845 2846 addr = memsize + ( XGINew_ChannelAB - 2 ) + 20 ; 2847 if ( ( HwDeviceExtension->ulVideoMemorySize - 1 ) < ( ULONG )( 1 << addr ) ) 2848 continue ; 2849 2850 if ( XGI45New_ReadWriteRest( addr , 9, pVBInfo ) == 1 ) 2851 return( 1 ) ; 2852 } 2853 return( 0 ) ; 2854} 2855 2856 2857/* --------------------------------------------------------------------- */ 2858/* Function : XGINew_DDRSizing */ 2859/* Input : */ 2860/* Output : */ 2861/* Description : */ 2862/* --------------------------------------------------------------------- */ 2863int XGINew_DDRSizing(PVB_DEVICE_INFO pVBInfo) 2864{ 2865 int i ; 2866 UCHAR j ; 2867 2868 for( i = 0 ; i < 4 ; i++ ) 2869 { 2870 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE, pVBInfo ) ; 2871 XGINew_DisableChannelInterleaving( i , XGINew_DDRDRAM_TYPE , pVBInfo) ; 2872 for( j = 2 ; j > 0 ; j-- ) 2873 { 2874 XGINew_SetDDRChannel( i , j , XGINew_ChannelAB , XGINew_DDRDRAM_TYPE , pVBInfo ) ; 2875 if ( !XGINew_SetRank( i , ( UCHAR )j , XGINew_ChannelAB , XGINew_DDRDRAM_TYPE, pVBInfo ) ) 2876 continue ; 2877 else 2878 { 2879 if ( XGINew_CheckDDRRanks( j , i , XGINew_DDRDRAM_TYPE, pVBInfo ) ) 2880 return( 1 ) ; 2881 } 2882 } 2883 } 2884 return( 0 ) ; 2885} 2886 2887/* --------------------------------------------------------------------- */ 2888/* Function : XGINew_SetMemoryClock */ 2889/* Input : */ 2890/* Output : */ 2891/* Description : */ 2892/* --------------------------------------------------------------------- */ 2893void XGINew_SetMemoryClock( PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) 2894{ 2895#ifndef LINUX_XF86 2896 UCHAR tempal ; 2897#endif 2898 2899 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x28 , pVBInfo->MCLKData[ XGINew_RAMType ].SR28 ) ; 2900 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x29 , pVBInfo->MCLKData[ XGINew_RAMType ].SR29 ) ; 2901 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x2A , pVBInfo->MCLKData[ XGINew_RAMType ].SR2A ) ; 2902 2903 2904 2905 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x2E , pVBInfo->ECLKData[ XGINew_RAMType ].SR2E ) ; 2906 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x2F , pVBInfo->ECLKData[ XGINew_RAMType ].SR2F ) ; 2907 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x30 , pVBInfo->ECLKData[ XGINew_RAMType ].SR30 ) ; 2908 2909 /* [Vicent] 2004/07/07, When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */ 2910 /* [Hsuan] 2004/08/20, Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz, Set SR32 D[1:0] = 10b */ 2911 if ( HwDeviceExtension->jChipType == XG42 ) 2912 { 2913 if ( ( pVBInfo->MCLKData[ XGINew_RAMType ].SR28 == 0x1C ) && ( pVBInfo->MCLKData[ XGINew_RAMType ].SR29 == 0x01 ) 2914 && ( ( ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2E == 0x1C ) && ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2F == 0x01 ) ) 2915 || ( ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2E == 0x22 ) && ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2F == 0x01 ) ) ) ) 2916 { 2917 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x32 , ( ( UCHAR )XGI_GetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x32 ) & 0xFC ) | 0x02 ) ; 2918 } 2919 } 2920} 2921 2922 2923/* --------------------------------------------------------------------- */ 2924/* input : dx ,valid value : CR or second chip's CR */ 2925/* */ 2926/* SetPowerConsume : */ 2927/* Description: reduce 40/43 power consumption in first chip or */ 2928/* in second chip, assume CR A1 D[6]="1" in this case */ 2929/* output : none */ 2930/* --------------------------------------------------------------------- */ 2931void SetPowerConsume ( PXGI_HW_DEVICE_INFO HwDeviceExtension , USHORT XGI_P3d4Port ) 2932{ 2933 ULONG lTemp ; 2934 UCHAR bTemp; 2935 2936 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x08 , 0 , &lTemp ) ; /* Get */ 2937 if ((lTemp&0xFF)==0) 2938 { 2939 /* set CR58 D[5]=0 D[3]=0 */ 2940 XGI_SetRegAND((XGIIOADDRESS) XGI_P3d4Port , 0x58 , 0xD7 ) ; 2941 bTemp = (UCHAR) XGI_GetReg((XGIIOADDRESS) XGI_P3d4Port , 0xCB ) ; 2942 if (bTemp&0x20) 2943 { 2944 if (!(bTemp&0x10)) 2945 { 2946 XGI_SetRegANDOR((XGIIOADDRESS) XGI_P3d4Port , 0x58 , 0xD7 , 0x20 ) ; /* CR58 D[5]=1 D[3]=0 */ 2947 } 2948 else 2949 { 2950 XGI_SetRegANDOR((XGIIOADDRESS) XGI_P3d4Port , 0x58 , 0xD7 , 0x08 ) ; /* CR58 D[5]=0 D[3]=1 */ 2951 } 2952 2953 } 2954 2955 } 2956} 2957 2958 2959void XGINew_InitVBIOSData(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) 2960{ 2961 2962 /* ULONG ROMAddr = (ULONG)HwDeviceExtension->pjVirtualRomBase; */ 2963 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ; 2964 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ; 2965 2966 /* pVBInfo->BaseAddr = ( USHORT )HwDeviceExtension->pjIOAddress ; */ 2967 pVBInfo->BaseAddr = ( ULONG )HwDeviceExtension->pjIOAddress ; 2968 2969 pVBInfo->RelIO = HwDeviceExtension->pjIOAddress - 0x30; 2970 pVBInfo->ISXPDOS = 0 ; 2971 2972 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ; 2973 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ; 2974 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ; 2975 2976 pVBInfo->P3cc = pVBInfo->BaseAddr + 0x1c ; /* Jong 07/31/2009 */ 2977 PDEBUG(ErrorF("XGINew_InitVBIOSData()-pVBInfo->P3cc = %d\n", pVBInfo->P3cc)); 2978 2979 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ; 2980 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ; 2981 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ; 2982 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ; 2983 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ; 2984 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ; 2985 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ; 2986 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ; 2987 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ; 2988 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ; 2989 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ; 2990 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ; 2991 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ; 2992 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ; 2993 2994 pVBInfo->IF_DEF_LCDA = 1 ; 2995 pVBInfo->IF_DEF_VideoCapture = 0 ; 2996 pVBInfo->IF_DEF_ScaleLCD = 0 ; 2997 pVBInfo->IF_DEF_OEMUtil = 0 ; 2998 pVBInfo->IF_DEF_PWD = 0 ; 2999 3000 if ( HwDeviceExtension->jChipType >= XG20 ) /* kuku 2004/06/25 */ 3001 { 3002 pVBInfo->IF_DEF_YPbPr = 0 ; 3003 pVBInfo->IF_DEF_HiVision = 0 ; 3004 pVBInfo->IF_DEF_CRT2Monitor = 0 ; 3005 } 3006 else if ( HwDeviceExtension->jChipType >= XG40 ) 3007 { 3008 pVBInfo->IF_DEF_YPbPr = 1 ; 3009 pVBInfo->IF_DEF_HiVision = 1 ; 3010 pVBInfo->IF_DEF_CRT2Monitor = 1 ; 3011 } 3012 else 3013 { 3014 pVBInfo->IF_DEF_YPbPr = 1 ; 3015 pVBInfo->IF_DEF_HiVision = 1 ; 3016 pVBInfo->IF_DEF_CRT2Monitor = 0 ; 3017 } 3018 3019 if ( (HwDeviceExtension->jChipType != XG20) && 3020 (HwDeviceExtension->jChipType != XG21) && 3021 (HwDeviceExtension->jChipType != XG27)) { 3022 /* alan, disable VideoCapture */ 3023 XGI_SetRegANDOR((XGIIOADDRESS) pVBInfo->Part0Port, 0x3F, 0xEF, 0x00); 3024 } 3025 3026 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */ 3027 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo); 3028} 3029 3030 3031/* --------------------------------------------------------------------- */ 3032/* Function : ReadVBIOSTablData */ 3033/* Input : */ 3034/* Output : */ 3035/* Description : */ 3036/* --------------------------------------------------------------------- */ 3037void ReadVBIOSTablData( UCHAR ChipType , PVB_DEVICE_INFO pVBInfo) 3038{ 3039#ifndef LINUX_XF86 3040 ULONG ulOffset ; 3041 UCHAR temp , index , l ; 3042#endif 3043 PUCHAR volatile pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr ; 3044 ULONG i ; 3045 UCHAR j , k ; 3046 ULONG ii , jj ; 3047 3048 /* Jong@08212009; no valid address of VBIOS ROM */ 3049 if(pVideoMemory == NULL) 3050 { 3051 ErrorF("XGI - No valid address of VBIOS ROM!\n"); 3052 return; 3053 } 3054 else 3055 ErrorF("XGI - Read data from VBIOS ROM...\n"); 3056 3057 i = pVideoMemory[ 0x1CF ] | ( pVideoMemory[ 0x1D0 ] << 8 ) ; /* UniROM */ 3058 if ( i != 0 ) 3059 UNIROM = 1 ; 3060 3061 ii = 0x90 ; 3062 for( jj = 0x00 ; jj < 0x08 ; jj++ ) 3063 { 3064 pVBInfo->MCLKData[ jj ].SR28 = pVideoMemory[ ii ] ; 3065 pVBInfo->MCLKData[ jj ].SR29 = pVideoMemory[ ii + 1] ; 3066 pVBInfo->MCLKData[ jj ].SR2A = pVideoMemory[ ii + 2] ; 3067 pVBInfo->MCLKData[ jj ].CLOCK = pVideoMemory[ ii + 3 ] | ( pVideoMemory[ ii + 4 ] << 8 ) ; 3068 ii += 0x05 ; 3069 } 3070 3071 ii = 0xB8 ; 3072 for( jj = 0x00 ; jj < 0x08 ; jj++ ) 3073 { 3074 pVBInfo->ECLKData[ jj ].SR2E = pVideoMemory[ ii ] ; 3075 pVBInfo->ECLKData[ jj ].SR2F=pVideoMemory[ ii + 1 ] ; 3076 pVBInfo->ECLKData[ jj ].SR30= pVideoMemory[ ii + 2 ] ; 3077 pVBInfo->ECLKData[ jj ].CLOCK= pVideoMemory[ ii + 3 ] | ( pVideoMemory[ ii + 4 ] << 8 ) ; 3078 ii += 0x05 ; 3079 } 3080 3081 /* Volari customize data area start */ 3082 /* if ( ChipType == XG40 ) */ 3083 if ( ChipType >= XG40 ) 3084 { 3085 ii = 0xE0 ; 3086 for( jj = 0x00 ; jj < 0x03 ; jj++ ) 3087 { 3088 pVBInfo->SR15[ jj ][ 0 ] = pVideoMemory[ ii ] ; /* SR13, SR14, and SR18 */ 3089 pVBInfo->SR15[ jj ][ 1 ] = pVideoMemory[ ii + 1 ] ; 3090 pVBInfo->SR15[ jj ][ 2 ] = pVideoMemory[ ii + 2 ] ; 3091 pVBInfo->SR15[ jj ][ 3 ] = pVideoMemory[ ii + 3 ] ; 3092 pVBInfo->SR15[ jj ][ 4 ] = pVideoMemory[ ii + 4 ] ; 3093 pVBInfo->SR15[ jj ][ 5 ] = pVideoMemory[ ii + 5 ] ; 3094 pVBInfo->SR15[ jj ][ 6 ] = pVideoMemory[ ii + 6 ] ; 3095 pVBInfo->SR15[ jj ][ 7 ] = pVideoMemory[ ii + 7 ] ; 3096 ii += 0x08 ; 3097 } 3098 ii = 0x110 ; 3099 jj = 0x03 ; 3100 pVBInfo->SR15[ jj ][ 0 ] = pVideoMemory[ ii ] ; /* SR1B */ 3101 pVBInfo->SR15[ jj ][ 1 ] = pVideoMemory[ ii + 1 ] ; 3102 pVBInfo->SR15[ jj ][ 2 ] = pVideoMemory[ ii + 2 ] ; 3103 pVBInfo->SR15[ jj ][ 3 ] = pVideoMemory[ ii + 3 ] ; 3104 pVBInfo->SR15[ jj ][ 4 ] = pVideoMemory[ ii + 4 ] ; 3105 pVBInfo->SR15[ jj ][ 5 ] = pVideoMemory[ ii + 5 ] ; 3106 pVBInfo->SR15[ jj ][ 6 ] = pVideoMemory[ ii + 6 ] ; 3107 pVBInfo->SR15[ jj ][ 7 ] = pVideoMemory[ ii + 7 ] ; 3108 3109 pVBInfo->SR07 = pVideoMemory[0x74]; 3110 pVBInfo->SR1F = pVideoMemory[0x75]; 3111 pVBInfo->SR21 = pVideoMemory[0x76]; 3112 pVBInfo->SR22 = pVideoMemory[0x77]; 3113 pVBInfo->SR23 = pVideoMemory[0x78]; 3114 pVBInfo->SR24 = pVideoMemory[0x79]; 3115 pVBInfo->SR25[0] = pVideoMemory[0x7A]; 3116 pVBInfo->SR31 = pVideoMemory[0x7B]; 3117 pVBInfo->SR32 = pVideoMemory[0x7C]; 3118 pVBInfo->SR33 = pVideoMemory[0x7D]; 3119 ii = 0xF8 ; 3120 3121 for( jj = 0 ; jj < 3 ; jj++ ) 3122 { 3123 pVBInfo->CR40[ jj ][ 0 ] = pVideoMemory[ ii ] ; 3124 pVBInfo->CR40[ jj ][ 1 ] = pVideoMemory[ ii + 1 ] ; 3125 pVBInfo->CR40[ jj ][ 2 ] = pVideoMemory[ ii + 2 ] ; 3126 pVBInfo->CR40[ jj ][ 3 ] = pVideoMemory[ ii + 3 ] ; 3127 pVBInfo->CR40[ jj ][ 4 ] = pVideoMemory[ ii + 4 ] ; 3128 pVBInfo->CR40[ jj ][ 5 ] = pVideoMemory[ ii + 5 ] ; 3129 pVBInfo->CR40[ jj ][ 6 ] = pVideoMemory[ ii + 6 ] ; 3130 pVBInfo->CR40[ jj ][ 7 ] = pVideoMemory[ ii + 7 ] ; 3131 ii += 0x08 ; 3132 } 3133 3134 ii = 0x118 ; 3135 for( j = 3 ; j < 24 ; j++ ) 3136 { 3137 pVBInfo->CR40[ j ][ 0 ] = pVideoMemory[ ii ] ; 3138 pVBInfo->CR40[ j ][ 1 ] = pVideoMemory[ ii + 1 ] ; 3139 pVBInfo->CR40[ j ][ 2 ] = pVideoMemory[ ii + 2 ] ; 3140 pVBInfo->CR40[ j ][ 3 ] = pVideoMemory[ ii + 3 ] ; 3141 pVBInfo->CR40[ j ][ 4 ] = pVideoMemory[ ii + 4 ] ; 3142 pVBInfo->CR40[ j ][ 5 ] = pVideoMemory[ ii + 5 ] ; 3143 pVBInfo->CR40[ j ][ 6 ] = pVideoMemory[ ii + 6 ] ; 3144 pVBInfo->CR40[ j ][ 7 ] = pVideoMemory[ ii + 7 ] ; 3145 ii += 0x08 ; 3146 } 3147 3148 i = pVideoMemory[ 0x1C0 ] | ( pVideoMemory[ 0x1C1 ] << 8 ) ; 3149 3150 for( j = 0 ; j < 8 ; j++ ) 3151 { 3152 for( k = 0 ; k < 4 ; k++ ) 3153 pVBInfo->CR6B[ j ][ k ] = pVideoMemory[ i + 4 * j + k ] ; 3154 } 3155 3156 i = pVideoMemory[ 0x1C2 ] | ( pVideoMemory[ 0x1C3 ] << 8 ) ; 3157 3158 if (ChipType == XG45) 3159 { 3160 for( j = 0 ; j < 8 ; j++ ) 3161 { 3162 pVBInfo->XG45CR6E[ j ] = pVideoMemory[i] ; 3163 } 3164 } 3165 else 3166 { 3167 for( j = 0 ; j < 8 ; j++ ) 3168 { 3169 for( k = 0 ; k < 4 ; k++ ) 3170 pVBInfo->CR6E[ j ][ k ] = pVideoMemory[ i + 4 * j + k ] ; 3171 } 3172 } 3173 3174 i = pVideoMemory[ 0x1C4 ] | ( pVideoMemory[ 0x1C5 ] << 8 ) ; 3175 if (ChipType == XG45) 3176 { 3177 for( j = 0 ; j < 8 ; j++ ) 3178 { 3179 pVBInfo->XG45CR6F[ j ] = pVideoMemory[i] ; 3180 } 3181 } 3182 else 3183 { 3184 for( j = 0 ; j < 8 ; j++ ) 3185 { 3186 for( k = 0 ; k < 32 ; k++ ) 3187 pVBInfo->CR6F[ j ][ k ] = pVideoMemory[ i + 32 * j + k ] ; 3188 } 3189 } 3190 3191 i = pVideoMemory[ 0x1C6 ] | ( pVideoMemory[ 0x1C7 ] << 8 ) ; 3192 3193 for( j = 0 ; j < 8 ; j++ ) 3194 { 3195 for( k = 0 ; k < 2 ; k++ ) 3196 pVBInfo->CR89[ j ][ k ] = pVideoMemory[ i + 2 * j + k ] ; 3197 } 3198 3199 i = pVideoMemory[ 0x1C8 ] | ( pVideoMemory[ 0x1C9 ] << 8 ) ; 3200 for( j = 0 ; j < 12 ; j++ ) 3201 pVBInfo->AGPReg[ j ] = pVideoMemory[ i + j ] ; 3202 3203 i = pVideoMemory[ 0x1CF ] | ( pVideoMemory[ 0x1D0 ] << 8 ) ; 3204 for( j = 0 ; j < 4 ; j++ ) 3205 pVBInfo->SR16[ j ] = pVideoMemory[ i + j ] ; 3206 3207 /* Jong 10/03/2007 */ 3208 /* 3209 pVBInfo->CRCF = pVideoMemory[0x1CA]; 3210 pVBInfo->DRAMTypeDefinition = pVideoMemory[0x1CB]; 3211 pVBInfo->I2CDefinition = pVideoMemory[0x1D1]; 3212 if ( ChipType == XG20 ) 3213 pVBInfo->CR97 = pVideoMemory[0x1D2]; */ 3214 if ( ChipType == XG21 ) 3215 { 3216 if (pVideoMemory[ 0x67 ] & 0x80) 3217 { 3218 *pVBInfo->pDVOSetting = pVideoMemory[ 0x67 ]; 3219 } 3220 if ( (pVideoMemory[ 0x67 ] & 0xC0) == 0xC0 ) 3221 { 3222 *pVBInfo->pCR2E = pVideoMemory[ i + 4 ] ; 3223 *pVBInfo->pCR2F = pVideoMemory[ i + 5 ] ; 3224 *pVBInfo->pCR46 = pVideoMemory[ i + 6 ] ; 3225 *pVBInfo->pCR47 = pVideoMemory[ i + 7 ] ; 3226 } 3227 } 3228 3229 if ( ChipType == XG27 ) 3230 { 3231 jj = i+j; 3232 for( i = 0 ; i <= 0xB ; i++,jj++ ) 3233 pVBInfo->pCRD0[i] = pVideoMemory[ jj ] ; 3234 for( i = 0x0 ; i <= 0x1 ; i++,jj++ ) 3235 pVBInfo->pCRDE[i] = pVideoMemory[ jj ] ; 3236 3237 *pVBInfo->pSR40 = pVideoMemory[ jj ] ; 3238 jj++; 3239 *pVBInfo->pSR41 = pVideoMemory[ jj ] ; 3240 3241 if (pVideoMemory[ 0x67 ] & 0x80) 3242 { 3243 *pVBInfo->pDVOSetting = pVideoMemory[ 0x67 ]; 3244 } 3245 if ( (pVideoMemory[ 0x67 ] & 0xC0) == 0xC0 ) 3246 { 3247 jj++; 3248 *pVBInfo->pCR2E = pVideoMemory[ jj ] ; 3249 *pVBInfo->pCR2F = pVideoMemory[ jj + 1 ] ; 3250 *pVBInfo->pCR46 = pVideoMemory[ jj + 2 ] ; 3251 *pVBInfo->pCR47 = pVideoMemory[ jj + 3 ] ; 3252 } 3253 3254 } 3255 3256 pVBInfo->CRCF = pVideoMemory[ 0x1CA ] ; 3257 pVBInfo->DRAMTypeDefinition = pVideoMemory[ 0x1CB ] ; 3258 pVBInfo->I2CDefinition = pVideoMemory[ 0x1D1 ] ; 3259 if ( ChipType >= XG20 ) 3260 { 3261 pVBInfo->CR97 = pVideoMemory[ 0x1D2 ] ; 3262 if ( ChipType == XG27 ) 3263 { 3264 *pVBInfo->pSR36 = pVideoMemory[ 0x1D3 ] ; 3265 *pVBInfo->pCR8F = pVideoMemory[ 0x1D5 ] ; 3266 } 3267 } 3268 } 3269 /* Volari customize data area end */ 3270 3271 if ( ChipType == XG21 ) 3272 { 3273 pVBInfo->IF_DEF_LVDS = 0 ; 3274 if (pVideoMemory[ 0x65 ] & 0x1) 3275 { 3276 pVBInfo->IF_DEF_LVDS = 1 ; 3277 i = pVideoMemory[ 0x316 ] | ( pVideoMemory[ 0x317 ] << 8 ); 3278 j = pVideoMemory[ i-1 ] ; 3279 if ( j != 0xff ) 3280 { 3281 k = 0; 3282 do 3283 { 3284 pVBInfo->XG21_LVDSCapList[k].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 ); 3285 pVBInfo->XG21_LVDSCapList[k].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ; 3286 pVBInfo->XG21_LVDSCapList[k].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 ); 3287 pVBInfo->XG21_LVDSCapList[k].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 ); 3288 pVBInfo->XG21_LVDSCapList[k].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 ); 3289 pVBInfo->XG21_LVDSCapList[k].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 ); 3290 pVBInfo->XG21_LVDSCapList[k].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 ); 3291 pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 ); 3292 pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 ); 3293 pVBInfo->XG21_LVDSCapList[k].VCLKData1 = pVideoMemory[ i + 18 ] ; 3294 pVBInfo->XG21_LVDSCapList[k].VCLKData2 = pVideoMemory[ i + 19 ] ; 3295 pVBInfo->XG21_LVDSCapList[k].PSC_S1 = pVideoMemory[ i + 20 ] ; 3296 pVBInfo->XG21_LVDSCapList[k].PSC_S2 = pVideoMemory[ i + 21 ] ; 3297 pVBInfo->XG21_LVDSCapList[k].PSC_S3 = pVideoMemory[ i + 22 ] ; 3298 pVBInfo->XG21_LVDSCapList[k].PSC_S4 = pVideoMemory[ i + 23 ] ; 3299 pVBInfo->XG21_LVDSCapList[k].PSC_S5 = pVideoMemory[ i + 24 ] ; 3300 i += 25; 3301 j--; 3302 k++; 3303 } while ( (j>0) && ( k < (sizeof(XGI21_LCDCapList)/sizeof(XGI21_LVDSCapStruct)) ) ); 3304 } 3305 else 3306 { 3307 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 ); 3308 pVBInfo->XG21_LVDSCapList[0].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ; 3309 pVBInfo->XG21_LVDSCapList[0].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 ); 3310 pVBInfo->XG21_LVDSCapList[0].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 ); 3311 pVBInfo->XG21_LVDSCapList[0].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 ); 3312 pVBInfo->XG21_LVDSCapList[0].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 ); 3313 pVBInfo->XG21_LVDSCapList[0].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 ); 3314 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 ); 3315 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 ); 3316 pVBInfo->XG21_LVDSCapList[0].VCLKData1 = pVideoMemory[ i + 18 ] ; 3317 pVBInfo->XG21_LVDSCapList[0].VCLKData2 = pVideoMemory[ i + 19 ] ; 3318 pVBInfo->XG21_LVDSCapList[0].PSC_S1 = pVideoMemory[ i + 20 ] ; 3319 pVBInfo->XG21_LVDSCapList[0].PSC_S2 = pVideoMemory[ i + 21 ] ; 3320 pVBInfo->XG21_LVDSCapList[0].PSC_S3 = pVideoMemory[ i + 22 ] ; 3321 pVBInfo->XG21_LVDSCapList[0].PSC_S4 = pVideoMemory[ i + 23 ] ; 3322 pVBInfo->XG21_LVDSCapList[0].PSC_S5 = pVideoMemory[ i + 24 ] ; 3323 } 3324 } 3325 pVBInfo->IF_DEF_CH7007 = 0 ; 3326 if ( ( pVideoMemory[ 0x65 ] & 0x02 ) ) /* For XG21 CH7007 */ 3327 { 3328 /* VideoDebugPrint((0, "ReadVBIOSTablData: pVideoMemory[ 0x65 ] =%x\n",pVideoMemory[ 0x65 ])); */ 3329 pVBInfo->IF_DEF_CH7007 = 1 ; /* [Billy] 07/05/03 */ 3330 } 3331 } 3332 3333 if ( ChipType == XG27 ) 3334 { 3335 if (pVideoMemory[ 0x65 ] & 0x1) 3336 { 3337 i = pVideoMemory[ 0x316 ] | ( pVideoMemory[ 0x317 ] << 8 ); 3338 j = pVideoMemory[ i-1 ] ; 3339 if ( j != 0xff ) 3340 { 3341 k = 0; 3342 do 3343 { 3344 pVBInfo->XG21_LVDSCapList[k].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 ); 3345 pVBInfo->XG21_LVDSCapList[k].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ; 3346 pVBInfo->XG21_LVDSCapList[k].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 ); 3347 pVBInfo->XG21_LVDSCapList[k].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 ); 3348 pVBInfo->XG21_LVDSCapList[k].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 ); 3349 pVBInfo->XG21_LVDSCapList[k].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 ); 3350 pVBInfo->XG21_LVDSCapList[k].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 ); 3351 pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 ); 3352 pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 ); 3353 pVBInfo->XG21_LVDSCapList[k].VCLKData1 = pVideoMemory[ i + 18 ] ; 3354 pVBInfo->XG21_LVDSCapList[k].VCLKData2 = pVideoMemory[ i + 19 ] ; 3355 pVBInfo->XG21_LVDSCapList[k].PSC_S1 = pVideoMemory[ i + 20 ] ; 3356 pVBInfo->XG21_LVDSCapList[k].PSC_S2 = pVideoMemory[ i + 21 ] ; 3357 pVBInfo->XG21_LVDSCapList[k].PSC_S3 = pVideoMemory[ i + 22 ] ; 3358 pVBInfo->XG21_LVDSCapList[k].PSC_S4 = pVideoMemory[ i + 23 ] ; 3359 pVBInfo->XG21_LVDSCapList[k].PSC_S5 = pVideoMemory[ i + 24 ] ; 3360 i += 25; 3361 j--; 3362 k++; 3363 } while ( (j>0) && ( k < (sizeof(XGI21_LCDCapList)/sizeof(XGI21_LVDSCapStruct)) ) ); 3364 } 3365 else 3366 { 3367 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 ); 3368 pVBInfo->XG21_LVDSCapList[0].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ; 3369 pVBInfo->XG21_LVDSCapList[0].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 ); 3370 pVBInfo->XG21_LVDSCapList[0].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 ); 3371 pVBInfo->XG21_LVDSCapList[0].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 ); 3372 pVBInfo->XG21_LVDSCapList[0].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 ); 3373 pVBInfo->XG21_LVDSCapList[0].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 ); 3374 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 ); 3375 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 ); 3376 pVBInfo->XG21_LVDSCapList[0].VCLKData1 = pVideoMemory[ i + 18 ] ; 3377 pVBInfo->XG21_LVDSCapList[0].VCLKData2 = pVideoMemory[ i + 19 ] ; 3378 pVBInfo->XG21_LVDSCapList[0].PSC_S1 = pVideoMemory[ i + 20 ] ; 3379 pVBInfo->XG21_LVDSCapList[0].PSC_S2 = pVideoMemory[ i + 21 ] ; 3380 pVBInfo->XG21_LVDSCapList[0].PSC_S3 = pVideoMemory[ i + 22 ] ; 3381 pVBInfo->XG21_LVDSCapList[0].PSC_S4 = pVideoMemory[ i + 23 ] ; 3382 pVBInfo->XG21_LVDSCapList[0].PSC_S5 = pVideoMemory[ i + 24 ] ; 3383 } 3384 } 3385 } 3386 3387 ErrorF("XGI - Read data from VBIOS ROM...End\n"); 3388} 3389 3390/* --------------------------------------------------------------------- */ 3391/* Function : XGINew_DDR1x_MRS_XG20 */ 3392/* Input : */ 3393/* Output : */ 3394/* Description : */ 3395/* --------------------------------------------------------------------- */ 3396void XGINew_DDR1x_MRS_XG20( USHORT P3c4 , PVB_DEVICE_INFO pVBInfo) 3397{ 3398 3399 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x01 ) ; 3400 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ; 3401 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 3402 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 3403 DelayUS( 60 ) ; 3404 3405 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x00 ) ; 3406 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x40 ) ; 3407 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x00 ) ; 3408 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x80 ) ; 3409 DelayUS( 60 ) ; 3410 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */ 3411 /* XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x31 ) ; */ 3412 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x01 ) ; 3413 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x03 ) ; 3414 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x83 ) ; 3415 DelayUS( 1000 ) ; 3416 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , 0x03 ) ; 3417 DelayUS( 500 ) ; 3418 /* XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , 0x31 ) ; */ 3419 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */ 3420 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x19 , 0x00 ) ; 3421 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x03 ) ; 3422 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x16 , 0x83 ) ; 3423 XGI_SetReg((XGIIOADDRESS) P3c4 , 0x1B , 0x00 ) ; 3424} 3425 3426/* --------------------------------------------------------------------- */ 3427/* Function : XGINew_SetDRAMModeRegister_XG20 */ 3428/* Input : */ 3429/* Output : */ 3430/* Description : */ 3431/* --------------------------------------------------------------------- */ 3432void XGINew_SetDRAMModeRegister_XG20(PXGI_HW_DEVICE_INFO HwDeviceExtension, 3433 PVB_DEVICE_INFO pVBInfo) 3434{ 3435#ifndef LINUX_XF86 3436 UCHAR data ; 3437#endif 3438 3439 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ; 3440 3441 if ( XGINew_Get340DRAMType( HwDeviceExtension, pVBInfo) == 0 ) 3442 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ; 3443 else 3444 XGINew_DDR2x_MRS_340( HwDeviceExtension, pVBInfo->P3c4, pVBInfo ) ; 3445 3446 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3c4 , 0x1B , 0x03 ) ; 3447} 3448 3449void XGINew_SetDRAMModeRegister_XG27( PXGI_HW_DEVICE_INFO HwDeviceExtension ) 3450{ 3451#ifndef LINUX_XF86 3452 UCHAR data ; 3453#endif 3454 VB_DEVICE_INFO VBINF; 3455 PVB_DEVICE_INFO pVBInfo = &VBINF; 3456 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ; 3457 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ; 3458 pVBInfo->BaseAddr = ( USHORT )HwDeviceExtension->pjIOAddress ; 3459 pVBInfo->ISXPDOS = 0 ; 3460 3461 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ; 3462 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ; 3463 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ; 3464 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ; 3465 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ; 3466 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ; 3467 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ; 3468 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ; 3469 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ; 3470 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ; 3471 3472 pVBInfo->P3cc = pVBInfo->BaseAddr + 0x1c ; /* Jong 07/31/2009 */ 3473 PDEBUG(ErrorF("XGINew_SetDRAMModeRegister_XG27()-pVBInfo->P3cc = %d\n", pVBInfo->P3cc)); 3474 3475 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ; 3476 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ; 3477 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ; 3478 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ; 3479 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ; 3480 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ; 3481 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ; 3482 3483 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo); 3484 3485 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ; 3486 3487 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 ) 3488 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ; 3489 else 3490 /*XGINew_DDR2_MRS_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;*/ 3491 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo) ; 3492 3493 /*XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;*/ 3494 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */ 3495 3496} 3497 3498/* -------------------------------------------------------- */ 3499/* Function : XGINew_ChkSenseStatus */ 3500/* Input : */ 3501/* Output : */ 3502/* Description : */ 3503/* -------------------------------------------------------- */ 3504void XGINew_ChkSenseStatus ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo) 3505{ 3506 USHORT tempbx=0 , temp , tempcx , CR3CData; 3507 3508 temp = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x32 ) ; 3509 3510 if ( temp & Monitor1Sense ) 3511 tempbx |= ActiveCRT1 ; 3512 if ( temp & LCDSense ) 3513 tempbx |= ActiveLCD ; 3514 if ( temp & Monitor2Sense ) 3515 tempbx |= ActiveCRT2 ; 3516 if ( temp & TVSense ) 3517 { 3518 tempbx |= ActiveTV ; 3519 if ( temp & AVIDEOSense ) 3520 tempbx |= ( ActiveAVideo << 8 ); 3521 if ( temp & SVIDEOSense ) 3522 tempbx |= ( ActiveSVideo << 8 ); 3523 if ( temp & SCARTSense ) 3524 tempbx |= ( ActiveSCART << 8 ); 3525 if ( temp & HiTVSense ) 3526 tempbx |= ( ActiveHiTV << 8 ); 3527 if ( temp & YPbPrSense ) 3528 tempbx |= ( ActiveYPbPr << 8 ); 3529 } 3530 3531 tempcx = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x3d ) ; 3532 tempcx |= ( XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x3e ) << 8 ) ; 3533 3534 if ( tempbx & tempcx ) 3535 { 3536 CR3CData = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x3c ) ; 3537 if ( !( CR3CData & DisplayDeviceFromCMOS ) ) 3538 { 3539 tempcx = 0x1FF0 ; 3540 if (pVBInfo->SoftSetting & ModeSoftSetting) { 3541 tempbx = 0x1FF0 ; 3542 } 3543 } 3544 } 3545 else 3546 { 3547 tempcx = 0x1FF0 ; 3548 if (pVBInfo->SoftSetting & ModeSoftSetting) { 3549 tempbx = 0x1FF0 ; 3550 } 3551 } 3552 3553 tempbx &= tempcx ; 3554 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4, 0x3d , ( tempbx & 0x00FF ) ) ; 3555 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4, 0x3e , ( ( tempbx & 0xFF00 ) >> 8 )) ; 3556} 3557/* -------------------------------------------------------- */ 3558/* Function : XGINew_SetModeScratch */ 3559/* Input : */ 3560/* Output : */ 3561/* Description : */ 3562/* -------------------------------------------------------- */ 3563void XGINew_SetModeScratch ( PXGI_HW_DEVICE_INFO HwDeviceExtension , PVB_DEVICE_INFO pVBInfo ) 3564{ 3565 USHORT temp , tempcl = 0 , tempch = 0 , CR31Data , CR38Data; 3566 3567 temp = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x3d ) ; 3568 temp |= XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x3e ) << 8 ; 3569 temp |= ( XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x31 ) & ( DriverMode >> 8) ) << 8 ; 3570 3571 if ( pVBInfo->IF_DEF_CRT2Monitor == 1) 3572 { 3573 if ( temp & ActiveCRT2 ) 3574 tempcl = SetCRT2ToRAMDAC ; 3575 } 3576 3577 if ( temp & ActiveLCD ) 3578 { 3579 tempcl |= SetCRT2ToLCD ; 3580 if ( temp & DriverMode ) 3581 { 3582 if ( temp & ActiveTV ) 3583 { 3584 tempch = SetToLCDA | EnableDualEdge ; 3585 temp ^= SetCRT2ToLCD ; 3586 3587 if ( ( temp >> 8 ) & ActiveAVideo ) 3588 tempcl |= SetCRT2ToAVIDEO ; 3589 if ( ( temp >> 8 ) & ActiveSVideo ) 3590 tempcl |= SetCRT2ToSVIDEO ; 3591 if ( ( temp >> 8 ) & ActiveSCART ) 3592 tempcl |= SetCRT2ToSCART ; 3593 3594 if ( pVBInfo->IF_DEF_HiVision == 1 ) 3595 { 3596 if ( ( temp >> 8 ) & ActiveHiTV ) 3597 tempcl |= SetCRT2ToHiVisionTV ; 3598 } 3599 3600 if ( pVBInfo->IF_DEF_YPbPr == 1 ) 3601 { 3602 if ( ( temp >> 8 ) & ActiveYPbPr ) 3603 tempch |= SetYPbPr ; 3604 } 3605 } 3606 } 3607 } 3608 else 3609 { 3610 if ( ( temp >> 8 ) & ActiveAVideo ) 3611 tempcl |= SetCRT2ToAVIDEO ; 3612 if ( ( temp >> 8 ) & ActiveSVideo ) 3613 tempcl |= SetCRT2ToSVIDEO ; 3614 if ( ( temp >> 8 ) & ActiveSCART ) 3615 tempcl |= SetCRT2ToSCART ; 3616 3617 if ( pVBInfo->IF_DEF_HiVision == 1 ) 3618 { 3619 if ( ( temp >> 8 ) & ActiveHiTV ) 3620 tempcl |= SetCRT2ToHiVisionTV ; 3621 } 3622 3623 if ( pVBInfo->IF_DEF_YPbPr == 1 ) 3624 { 3625 if ( ( temp >> 8 ) & ActiveYPbPr ) 3626 tempch |= SetYPbPr ; 3627 } 3628 } 3629 3630 tempcl |= SetSimuScanMode ; 3631 if ( (!( temp & ActiveCRT1 )) && ( ( temp & ActiveLCD ) || ( temp & ActiveTV ) || ( temp & ActiveCRT2 ) ) ) 3632 tempcl ^= ( SetSimuScanMode | SwitchToCRT2 ) ; 3633 if ( ( temp & ActiveLCD ) && ( temp & ActiveTV ) ) 3634 tempcl ^= ( SetSimuScanMode | SwitchToCRT2 ) ; 3635 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4, 0x30 , tempcl ) ; 3636 3637 CR31Data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x31 ) ; 3638 CR31Data &= ~( SetNotSimuMode >> 8 ) ; 3639 if ( !( temp & ActiveCRT1 ) ) 3640 CR31Data |= ( SetNotSimuMode >> 8 ) ; 3641 CR31Data &= ~( DisableCRT2Display >> 8 ) ; 3642 if (!( ( temp & ActiveLCD ) || ( temp & ActiveTV ) || ( temp & ActiveCRT2 ) ) ) 3643 CR31Data |= ( DisableCRT2Display >> 8 ) ; 3644 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4, 0x31 , CR31Data ) ; 3645 3646 CR38Data = XGI_GetReg((XGIIOADDRESS) pVBInfo->P3d4 , 0x38 ) ; 3647 CR38Data &= ~SetYPbPr ; 3648 CR38Data |= tempch ; 3649 XGI_SetReg((XGIIOADDRESS) pVBInfo->P3d4, 0x38 , CR38Data ) ; 3650 3651} 3652 3653/* -------------------------------------------------------- */ 3654/* Function : XGINew_GetXG21Sense */ 3655/* Input : */ 3656/* Output : */ 3657/* Description : */ 3658/* -------------------------------------------------------- */ 3659void XGINew_GetXG21Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) 3660{ 3661 UCHAR Temp; 3662 PUCHAR volatile pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr ; 3663 3664 pVBInfo->IF_DEF_LVDS = 0 ; 3665 3666 if ( ( pVideoMemory[ 0x65 ] & 0x01 ) ) /* For XG21 LVDS */ 3667 { 3668 pVBInfo->IF_DEF_LVDS = 1 ; 3669 XGI_SetRegOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x32 , LCDSense ) ; 3670 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS on chip */ 3671 } 3672 else 3673 { 3674 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* Enable GPIOA/B read */ 3675 Temp = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x48 ) & 0xC0; 3676 if ( Temp == 0xC0 ) 3677 { /* DVI & DVO GPIOA/B pull high */ 3678 XGINew_SenseLCD( HwDeviceExtension, pVBInfo ) ; 3679 XGI_SetRegOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x32 , LCDSense ) ; 3680 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x4A , ~0x20 , 0x20 ) ; /* Enable read GPIOF */ 3681 Temp = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x48 ) & 0x04 ; 3682 if ( !Temp ) 3683 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x38 , ~0xE0 , 0x80 ) ; /* TMDS on chip */ 3684 else 3685 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* Only DVO on chip */ 3686 3687 XGI_SetRegAND( (XGIIOADDRESS)pVBInfo->P3d4 , 0x4A , ~0x20 ) ; /* Disable read GPIOF */ 3688 } 3689 } 3690} 3691 3692/* -------------------------------------------------------- */ 3693/* Function : XGINew_GetXG27Sense */ 3694/* Input : */ 3695/* Output : */ 3696/* Description : */ 3697/* -------------------------------------------------------- */ 3698void XGINew_GetXG27Sense(PXGI_HW_DEVICE_INFO HwDeviceExtension, PVB_DEVICE_INFO pVBInfo) 3699{ 3700 UCHAR Temp,bCR4A; 3701 PUCHAR volatile pVideoMemory = ( PUCHAR )pVBInfo->ROMAddr ; 3702 3703 pVBInfo->IF_DEF_LVDS = 0 ; 3704 bCR4A = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x4A ) ; 3705 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x4A , ~0x07 , 0x07 ) ; /* Enable GPIOA/B/C read */ 3706 Temp = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x48 ) & 0x07; 3707 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3d4, 0x4A , bCR4A ) ; 3708 3709 if ( Temp <= 0x02 ) 3710 { 3711 pVBInfo->IF_DEF_LVDS = 1 ; 3712 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS setting */ 3713 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3d4, 0x30 , 0x21 ) ; 3714 } 3715 else 3716 { 3717 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* TMDS/DVO setting */ 3718 } 3719 3720 XGI_SetRegOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x32 , LCDSense ) ; 3721} 3722 3723UCHAR GetXG21FPBits(PVB_DEVICE_INFO pVBInfo) 3724{ 3725 UCHAR CR38,CR4A,temp; 3726 3727 CR4A = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x4A ) ; 3728 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x4A , ~0x10 , 0x10 ) ; /* enable GPIOE read */ 3729 CR38 = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x38 ) ; 3730 temp =0; 3731 if ( ( CR38 & 0xE0 ) > 0x80 ) 3732 { 3733 temp = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x48 ) ; 3734 temp &= 0x08; 3735 temp >>= 3; 3736 } 3737 3738 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3d4, 0x4A , CR4A ) ; 3739 3740 return temp; 3741} 3742 3743UCHAR GetXG27FPBits(PVB_DEVICE_INFO pVBInfo) 3744{ 3745 UCHAR CR38,CR4A,temp; 3746 3747 CR4A = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x4A ) ; 3748 XGI_SetRegANDOR( (XGIIOADDRESS) pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* enable GPIOA/B/C read */ 3749 temp = XGI_GetReg( (XGIIOADDRESS) pVBInfo->P3d4 , 0x48 ) ; 3750 if ( temp <= 2 ) 3751 { 3752 temp &= 0x03; 3753 } 3754 else 3755 { 3756 temp = ((temp&0x04)>>1) || ((~temp)&0x01); 3757 } 3758 3759 XGI_SetReg( (XGIIOADDRESS) pVBInfo->P3d4, 0x4A , CR4A ) ; 3760 3761 return temp; 3762} 3763 3764