xgi_setup.c revision dfe64dd3 
1/*
2 * Basic hardware and memory detection
3 *
4 * Copyright (C) 2001-2004 by Thomas Winischhofer, Vienna, Austria.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1) Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2) Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 * 3) The name of the author may not be used to endorse or promote products
15 *    derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESSED OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Author:  	Thomas Winischhofer <thomas@winischhofer.net>
29 *
30 * Ideas and methods for old series based on code by Can-Ru Yeou, XGI Inc.
31 *
32 */
33
34#ifdef HAVE_CONFIG_H
35#include "config.h"
36#endif
37
38#include "xf86PciInfo.h"
39#include "xf86Pci.h"
40#include "xf86.h"
41#include "fb.h"
42#include "xf86_OSproc.h"
43#include "xorgVersion.h"
44
45#include "xf86cmap.h"
46
47#include "xgi.h"
48#include "xgi_regs.h"
49#include "xgi_dac.h"
50/* #include "valid_mode.h" */
51
52#define _XF86DGA_SERVER_
53#include <X11/extensions/xf86dgastr.h>
54
55#include "globals.h"
56#ifdef HAVE_XEXTPROTO_71
57#include <X11/extensions/dpmsconst.h>
58#else
59#define DPMS_SERVER
60#include <X11/extensions/dpms.h>
61#endif
62
63
64#include "vb_def.h"
65extern  int  FbDevExist;
66
67static Bool bAccessVGAPCIInfo(PXGI_HW_DEVICE_INFO pHwDevInfo, ULONG ulOffset,
68    ULONG ulSet, ULONG *pulValue);
69static Bool bAccessNBridgePCIInfo(PXGI_HW_DEVICE_INFO pHwDevInfo,
70    ULONG ulOffset, ULONG ulSet, ULONG *pulValue);
71static Bool XGI_IsXG21(ScrnInfoPtr pScrn);
72
73static void XGI_InitHwDevInfo(ScrnInfoPtr pScrn);
74
75/* Jong 10/16/2007; merge code */
76static void
77xgiXG2X_Setup(ScrnInfoPtr pScrn)
78{
79
80/*********************************************************************
81 * Setup
82 * Decide the following item of execution data:
83 *
84 * pXGI->BusWidth
85 * pXGI->videoRam (with KB unit)
86 * pXGI->CursorOffset (with Byte Unit)
87 * pXGI->cmdQueueSize (with Byte Unit)
88 * pXGI->cmdQueueSizeMask (with Byte Unit)
89 * pXGI->cmdQueueOffset (with Byte Unit)
90 * pXGI->cmdQueueLen = 0 ; // init value
91 * pXGI->cmdQueueLenMin = 0x200 ; // init value
92 * pXGI->cmdQueueLenMax = pXGI->cmdQueueSize -  pXGI->cmdQueueLenMin ;
93 *********************************************************************/
94
95    XGIPtr        pXGI = XGIPTR(pScrn);
96    unsigned int  ulMemConfig = 0;
97    unsigned long ulMemSize   = 0;
98    unsigned long ulDramType  = 0;
99    char *dramTypeStr ;
100    unsigned long ulTemp ;
101
102    /* DumpDDIName("xgiXG2X_Setup()\n") ; */
103
104    inXGIIDXREG(XGICR, 0x48, ulTemp) ;
105    if(ulTemp & (1<<0)) /* GPIOH, CR48 D[0] read */
106    {
107        dramTypeStr = "DDRII DRAM" ;
108    }
109    else
110    {
111        dramTypeStr = "DDR DRAM" ;
112    }
113
114
115    pXGI->MemClock = XG40Mclk(pXGI);
116
117    /*********************************************************************************************************
118     * SR14 DRAM Size Register
119     *     Default value: XXh
120     *     D[7:4]    Memory size per channel {BChMemSize}
121     *         0011: 8 MB
122     *         0100: 16 MB
123     *         0101: 32 MB
124     *         0110: 64 MB
125     *         0111: 128 MB
126     *         1000: 256MB
127     *        others: reserved
128     *     D[3:2]    Number of  dram channels [1:0] {BChNum}
129     *         00: uni-channel
130     *         01: reserved
131     *         10: dual-channel.
132     *         11: quad-channel
133     *     D1  Data width per channel selection {BDataWidth}
134     *         0: 32-bits
135     *         1: 64-bits
136     *     D0  Dram channel mapping {BReverseChMapping}
137     *         0: Normal mapping
138     *         1: Reversal mapping
139     *             Dual-channel: Logical channel A/B to physical channel B/A
140     *             Quad-channel: Logical  channel A/B/C/D to physical channel C/D/A/B
141     *
142     *********************************************************************************************************/
143
144    outXGIIDXREG(XGISR, 0x5, 0x86) ;
145    inXGIIDXREG(XGISR, 0x14, ulMemConfig) ;
146    inXGIIDXREG(XGISR, 0x3A, ulDramType) ;
147
148    PDEBUG(ErrorF("xg40_Setup(): ulMemConfig = %02X\n",ulMemConfig)) ;
149    PDEBUG(ErrorF("xg40_Setup(): ulDramType = %02X\n",ulDramType)) ;
150
151    pXGI->BusWidth = (ulMemConfig & (1<<1) )?64:32 ;
152
153    switch(ulMemConfig>>4)
154    {
155    case 8:
156        ulMemSize = 256*1024 ;
157        break ;
158    case 7:
159        ulMemSize = 128*1024 ;
160        break ;
161    case 6:
162        ulMemSize = 64*1024 ;
163        break ;
164    case 5:
165        ulMemSize = 32*1024 ;
166        break ;
167    case 4:
168        ulMemSize = 16*1024 ;
169        break ;
170    case 3:
171        ulMemSize = 8*1024 ;
172        break ;
173    default:
174        ulMemSize = 8*1024 ;
175    }
176
177    if (pXGI->Chipset == PCI_CHIP_XGIXG40) {
178	const unsigned revision =
179#ifdef XSERVER_LIBPCIACCESS
180	    pXGI->PciInfo->revision
181#else
182	    pciReadLong(pXGI->PciTag, 0x08) & 0x0FF
183#endif
184	    ;
185
186	/* Revision 2 cards encode the memory config bits slightly differently
187	 * from revision 1 cards.
188	 */
189        if (revision == 2) {
190            switch((ulMemConfig>>2)&0x1)
191            {
192            case 0:
193                /* Uni channel */
194                ulMemSize *= 1 ;
195       	        break ;
196            case 1:
197                /* Dual channel */
198                ulMemSize *= 2 ;
199    	        break ;
200            }
201        }
202        else
203        {
204            switch((ulMemConfig>>2)&0x3)
205            {
206            case 2:
207                /* Dual channel */
208                ulMemSize *= 2 ;
209        	break ;
210            case 3:
211                /* Quad channel */
212                ulMemSize *= 4 ;
213    	        break ;
214           }
215        }
216    }
217
218    pScrn->videoRam = ulMemSize ;
219
220    /*********************************************************************************************************
221     * SR15 DRAM Address Mapping Register
222     * Default value: XXh
223     *     D7  Channel  interleaving configuration { BChConfig }
224     *         0: Divide the whole memory  into 2/4 equal-sized regions , each mapped to one channel
225     *         1: Divide the whole memory into 2 regions according to BTilingSize[1:0] . The low-address region
226     *         will be channel-interleaved as per BFineGranSize; the high-address region will be channel-
227     *         interleaved  as per BCoarseGranSize[1:0]
228     *     D[6:5]    Memory size of tile-mapped region {BTilingSize}
229     *         00: 4 MB
230     *         01: 8 MB
231     *         10: 16 MB
232     *         11: 32 MB
233     *         The following bits are effective only when D7=1
234     *     D4  Channel-interleaving granularity for tile-mapped region {BFineGranSize}
235     *         0:  64 B
236     *         1:  128 B
237     *     D[3:2] Channel-interleaving granularity for linearly mapped region {BCoarseGranSize}
238     *         00: 1KB
239     *         01: 2KB
240     *         10: 4KB
241     *         11: 1MB
242     *     D[1:0] reserved
243     *********************************************************************************************************/
244
245    /* Accelerator parameter Initialization */
246    if(( pXGI->Chipset == PCI_CHIP_XGIXG20 )||( pXGI->Chipset == PCI_CHIP_XGIXG21 )||( pXGI->Chipset == PCI_CHIP_XGIXG27 ))
247    {
248        pXGI->cmdQueueSize = VOLARI_CQSIZEXG20;
249    /* XgiMode = XG20_Mode ; */
250        PDEBUG(ErrorF(" ---XG20_Mode \n"));
251    }
252
253
254    pXGI->cmdQueueSizeMask = pXGI->cmdQueueSize - 1 ;
255    pXGI->pCQ_shareWritePort = &(pXGI->cmdQueue_shareWP_only2D);
256
257
258    /*
259     If FbDevExist, XFree86 driver use the 8MB only. The rest
260     frame buffer is used by other AP.
261     */
262
263    if( FbDevExist && (pXGI->Chipset != PCI_CHIP_XGIXG20 ) && (pXGI->Chipset != PCI_CHIP_XGIXG21 ) && (pXGI->Chipset != PCI_CHIP_XGIXG27 ) )
264    {
265        if( pScrn->videoRam < 8*1024 )
266        {
267            pXGI->cmdQueueOffset = 4*1024*1024 - pXGI->cmdQueueSize ;
268        }
269        else if( pScrn->videoRam < 16*1024 )
270        {
271            pXGI->cmdQueueOffset = 8*1024*1024 - pXGI->cmdQueueSize ;
272        }
273        else
274        {
275            pXGI->cmdQueueOffset = 13*1024*1024 - pXGI->cmdQueueSize ;
276        }
277    }
278    else
279    {
280        pXGI->cmdQueueOffset = (pScrn->videoRam)*1024 - pXGI->cmdQueueSize ;
281    }
282
283    pXGI->CursorOffset = pXGI->cmdQueueOffset - 64*1024 ;
284    PDEBUG4(ErrorF("pScrn->videoRam = %08lX pXGI->cmdQueueSize = %08lX\n",
285			pScrn->videoRam, pXGI->cmdQueueSize)) ;
286    PDEBUG4(ErrorF("pXGI->cmdQueueOffset = %08lX pXGI->CursorOffset = %08lX\n",
287		pXGI->cmdQueueOffset, pXGI->CursorOffset)) ;
288
289    pXGI->cmdQueueLen = 0 ;
290    pXGI->cmdQueueLenMin = 0x200 ;
291    pXGI->cmdQueueLenMax = pXGI->cmdQueueSize -  pXGI->cmdQueueLenMin ;
292
293    /*****************************************************************
294     * Dual Chip support put here                                    *
295     *****************************************************************/
296    xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
297            "Detected DRAM type : %s\n", dramTypeStr);
298    xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
299            "Detected memory clock : %3.3fMHz\n",
300            pXGI->MemClock/1000.0);
301    xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
302            "Detected VRAM bus width is %d\n", pXGI->BusWidth);
303    xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
304            "Detected Cmd Queue size is %d KB\n", pXGI->cmdQueueSize / 1024);
305    xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
306            "Detected Cmd Queue Offset is %d\n", pXGI->cmdQueueOffset ) ;
307    XGI_InitHwDevInfo(pScrn);
308}
309
310static void
311xgiXG40_Setup(ScrnInfoPtr pScrn)
312{
313    static const char *const dramChannelStr[5] = {
314	"<invalid>", "Single", "Dual", "<invalid>", "Quad"
315    };
316
317    static const char *const dramTypeStr[4] = {
318	"DDR SDRAM",
319	"DDR2 SDRAM",
320	"DDR2x SDRAM",
321	""
322    };
323
324/*********************************************************************
325 * Setup
326 * Decide the following item of execution data:
327 *
328 * pXGI->BusWidth
329 * pXGI->videoRam (with KB unit)
330 * pXGI->CursorOffset (with Byte Unit)
331 * pXGI->cmdQueueSize (with Byte Unit)
332 * pXGI->cmdQueueSizeMask (with Byte Unit)
333 * pXGI->cmdQueueOffset (with Byte Unit)
334 * pXGI->cmdQueueLen = 0 ; // init value
335 * pXGI->cmdQueueLenMin = 0x200 ; // init value
336 * pXGI->cmdQueueLenMax = pXGI->cmdQueueSize -  pXGI->cmdQueueLenMin ;
337 *********************************************************************/
338
339    XGIPtr        pXGI = XGIPTR(pScrn);
340    unsigned int  ulMemConfig = 0;
341    unsigned mem_per_channel;
342    unsigned mem_channels = 1;
343    unsigned long ulDramType  = 0;
344
345    PDEBUG4(ErrorF("xgiXG40_Setup()\n")) ;
346
347    pXGI->MemClock = XG40Mclk(pXGI);
348
349    /* SR14 DRAM Size Register
350     *     Default value: XXh
351     *     D[7:4]    Memory size per channel {BChMemSize}
352     *         0011: 8 MB
353     *         0100: 16 MB
354     *         0101: 32 MB
355     *         0110: 64 MB
356     *         0111: 128 MB
357     *         1000: 256MB
358     *        others: reserved
359     *     D[3:2]    Number of  dram channels [1:0] {BChNum}
360     *         00: uni-channel
361     *         01: reserved
362     *         10: dual-channel
363     *         11: quad-channel
364     *     D1  Data width per channel selection {BDataWidth}
365     *         0: 32-bits
366     *         1: 64-bits
367     *     D0  Dram channel mapping {BReverseChMapping}
368     *         0: Normal mapping
369     *         1: Reversal mapping
370     *             Dual-channel: Logical channel A/B to physical channel B/A
371     *             Quad-channel: Logical channel A/B/C/D to physical channel
372     *                           C/D/A/B
373     */
374
375    outXGIIDXREG(XGISR, 0x5, 0x86) ;
376    inXGIIDXREG(XGISR, 0x14, ulMemConfig) ;
377
378    /* FIXME: Is this correct?  The SiS driver detects this differently
379     * FIXME: for XG20.
380     */
381    inXGIIDXREG(XGISR, 0x3A, ulDramType) ;
382
383    PDEBUG(ErrorF("xg40_Setup(): ulMemConfig = %02X\n",ulMemConfig)) ;
384    PDEBUG(ErrorF("xg40_Setup(): ulDramType = %02X\n",ulDramType)) ;
385
386    /* FIXME: Is this correct?  The SiS driver detects this differently
387     * FIXME: for XG20.
388     */
389    pXGI->BusWidth = (ulMemConfig & 0x02) ? 64 : 32;
390
391    mem_per_channel = ((ulMemConfig >> 4) >= 3)
392        ? (1 << (ulMemConfig >> 4)) * 1024
393        : 8 * 1024;
394
395
396    /* All XG20 family chips are single channel, so only test the channel
397     * count field on XG40 family chips.
398     */
399    if (pXGI->Chipset == PCI_CHIP_XGIXG40) {
400        /* Check the PCI revision field.  For whatever reason, rev. 2 XG40
401         * chips encode the DRAM channel count differently than other
402         * revisions.
403         */
404        if (pXGI->ChipRev == 2) {
405            switch ((ulMemConfig >> 2) & 0x1) {
406            case 1:
407                /* Dual channel */
408                mem_channels = 2;
409                break ;
410            }
411        }
412        else {
413            switch ((ulMemConfig >> 2) & 0x3) {
414            case 2:
415                /* Dual channel */
416                mem_channels = 2;
417                break ;
418            case 3:
419                /* Quad channel */
420                mem_channels = 4;
421                break ;
422            }
423        }
424    }
425
426    pScrn->videoRam = mem_per_channel * mem_channels;
427
428    /* SR15 DRAM Address Mapping Register
429     * Default value: XXh
430     *     D7  Channel  interleaving configuration { BChConfig }
431     *         0: Divide the whole memory  into 2/4 equal-sized regions , each mapped to one channel
432     *         1: Divide the whole memory into 2 regions according to BTilingSize[1:0] . The low-address region
433     *         will be channel-interleaved as per BFineGranSize; the high-address region will be channel-
434     *         interleaved  as per BCoarseGranSize[1:0]
435     *     D[6:5]    Memory size of tile-mapped region {BTilingSize}
436     *         00: 4 MB
437     *         01: 8 MB
438     *         10: 16 MB
439     *         11: 32 MB
440     *         The following bits are effective only when D7=1
441     *     D4  Channel-interleaving granularity for tile-mapped region {BFineGranSize}
442     *         0:  64 B
443     *         1:  128 B
444     *     D[3:2] Channel-interleaving granularity for linearly mapped region {BCoarseGranSize}
445     *         00: 1KB
446     *         01: 2KB
447     *         10: 4KB
448     *         11: 1MB
449     *     D[1:0] reserved
450     */
451
452    /* Accelerator parameter Initialization */
453
454    pXGI->cmdQueueSize = ((pXGI->Chipset == PCI_CHIP_XGIXG20)||(pXGI->Chipset == PCI_CHIP_XGIXG21||(pXGI->Chipset == PCI_CHIP_XGIXG27)))
455	? VOLARI_CQSIZEXG20 : VOLARI_CQSIZE;
456    pXGI->cmdQueueSizeMask = pXGI->cmdQueueSize - 1 ;
457    pXGI->pCQ_shareWritePort = &(pXGI->cmdQueue_shareWP_only2D);
458
459
460    /* If FbDevExist, X.org driver uses 8MB only. The rest of the framebuffer
461     * is used by the fbdev driver.
462     */
463    if (FbDevExist) {
464	/* FIXME: Is it even possible to have less than 8Mb of video memory?
465	 */
466        if (pScrn->videoRam < 8*1024) {
467            pXGI->cmdQueueOffset = 4*1024*1024 - pXGI->cmdQueueSize;
468        }
469	else if (pScrn->videoRam < 16*1024) {
470	    pXGI->cmdQueueOffset = 8*1024*1024 - pXGI->cmdQueueSize;
471	}
472        else {
473            pXGI->cmdQueueOffset = 13*1024*1024 - pXGI->cmdQueueSize;
474        }
475    }
476    else {
477        pXGI->cmdQueueOffset = (pScrn->videoRam)*1024 - pXGI->cmdQueueSize;
478    }
479
480    pXGI->CursorOffset = pXGI->cmdQueueOffset - 64*1024;
481    PDEBUG4(ErrorF("pScrn->videoRam = %08lX pXGI->cmdQueueSize = %08lX\n",
482			pScrn->videoRam, pXGI->cmdQueueSize)) ;
483    PDEBUG4(ErrorF("pXGI->cmdQueueOffset = %08lX pXGI->CursorOffset = %08lX\n",
484		pXGI->cmdQueueOffset, pXGI->CursorOffset)) ;
485
486    pXGI->cmdQueueLen = 0 ;
487    pXGI->cmdQueueLenMin = 0x200 ;
488    pXGI->cmdQueueLenMax = pXGI->cmdQueueSize -  pXGI->cmdQueueLenMin ;
489
490    /* Dual Chip support put here
491     */
492    xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
493	       "Detected DRAM type : %s channel %s\n",
494	       dramChannelStr[mem_channels],
495	       dramTypeStr[(ulDramType & 0x02) >> 1]);
496    xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
497            "Detected memory clock : %3.3fMHz\n",
498            pXGI->MemClock/1000.0);
499    xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
500            "Detected VRAM bus width is %d\n", pXGI->BusWidth);
501    xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
502            "Detected Cmd Queue size is %d KB\n", pXGI->cmdQueueSize / 1024);
503    xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
504            "Detected Cmd Queue Offset is %d\n", pXGI->cmdQueueOffset ) ;
505    XGI_InitHwDevInfo(pScrn);
506}
507
508void
509XGISetup(ScrnInfoPtr pScrn)
510{
511    XGIPtr pXGI = XGIPTR(pScrn);
512
513    pXGI->Flags = 0;
514    pXGI->VBFlags = 0;
515
516	/* Jong 10/16/2007; merge code */
517    switch (pXGI->Chipset) {
518		case PCI_CHIP_XGIXG20:
519		case PCI_CHIP_XGIXG21:
520		case PCI_CHIP_XGIXG27:
521			xgiXG2X_Setup(pScrn);
522			break;
523
524		case PCI_CHIP_XGIXG40:
525		default:
526			xgiXG40_Setup(pScrn);
527			break;
528    }
529}
530
531/* Jong 01/07/2008; Force to disable 2D engine by SR3A[6]=1 */
532Bool ForceToDisable2DEngine(ScrnInfoPtr pScrn)
533{
534    XGIPtr pXGI ;
535	Bool   bReturn=FALSE;
536    CARD8  bForce;
537
538    pXGI = XGIPTR(pScrn);
539
540	if(pXGI->Chipset == PCI_CHIP_XGIXG21)
541	{
542	    inXGIIDXREG(XGISR, 0x3A, bForce) ;
543		bForce &= 0x40;
544
545		if(bForce == 0)
546			bReturn=FALSE;
547		else
548			bReturn=TRUE;
549	}
550	else
551	{
552		bReturn=FALSE;
553	}
554
555	return(bReturn);
556}
557
558Bool
559XGI_IsXG21(ScrnInfoPtr pScrn)
560{
561    XGIPtr pXGI = XGIPTR(pScrn);
562    Bool is_XG21 = FALSE;
563
564    if (pXGI->Chipset == PCI_CHIP_XGIXG20) {
565		int temp;
566
567        orXGIIDXREG(XGICR, Index_CR_GPIO_Reg3, GPIOG_EN);
568        inXGIIDXREG(XGICR, Index_CR_GPIO_Reg1, temp);
569
570		is_XG21 = ((temp & GPIOG_READ) != 0);
571    }
572
573    return is_XG21;
574}
575
576void
577XGI_InitHwDevInfo(ScrnInfoPtr pScrn)
578{
579    XGIPtr pXGI = XGIPTR(pScrn);
580    PXGI_HW_DEVICE_INFO pHwDevInfo = &pXGI->xgi_HwDevExt;
581    int i;
582
583    pHwDevInfo->pDevice = pXGI ;
584    pHwDevInfo->pjVirtualRomBase = pXGI->BIOS ;
585    pHwDevInfo->pjCustomizedROMImage = NULL ;
586    pHwDevInfo->pjVideoMemoryAddress = (UCHAR*)(pXGI->FbBase) ;
587    PDEBUG(ErrorF("pXGI->FbBase = 0x%08lx\n",(ULONG)(pXGI->FbBase))) ;
588    PDEBUG(ErrorF("pHwDevInfo->pjVideoMemoryAddress = 0x%08lx\n",(ULONG)(pHwDevInfo->pjVideoMemoryAddress))) ;
589    pHwDevInfo->ulVideoMemorySize = pXGI->FbMapSize ;
590    pHwDevInfo->pjIOAddress = pXGI->RelIO + 0x30 ;
591
592    switch (pXGI->Chipset) {
593    case PCI_CHIP_XGIXG40:
594        pHwDevInfo->jChipType = XG40 ;
595        break ;
596    case PCI_CHIP_XGIXG20:
597        pHwDevInfo->jChipType = XGI_IsXG21(pScrn)?XG21:XG20 ;
598        break ;
599    case PCI_CHIP_XGIXG27:
600    pHwDevInfo->jChipType = XG27;
601        break;
602    case PCI_CHIP_XGIXG21:
603	pHwDevInfo->jChipType = XG21;
604	break;
605    default:
606        pHwDevInfo->jChipType = XG40 ;
607        break ;
608    }
609
610    pHwDevInfo->jChipRevision = pXGI->ChipRev;
611    pHwDevInfo->ujVBChipID = VB_CHIP_UNKNOWN ;
612    pHwDevInfo->ulExternalChip = 0 ;
613
614    pHwDevInfo->ulCRT2LCDType = LCD_1024x768 ;
615    pHwDevInfo->bIntegratedMMEnabled = FALSE ;
616    pHwDevInfo->bSkipDramSizing = TRUE ;
617
618    pHwDevInfo->pSR = pXGI->SRList ;
619    pHwDevInfo->pCR = pXGI->CRList ;
620    pHwDevInfo->pQueryVGAConfigSpace = (PXGI_QUERYSPACE) bAccessVGAPCIInfo;
621
622    for( i = 0 ; i < ExtRegSize ; i++ ){
623        pHwDevInfo->pSR[i].jIdx = 0xFF ;
624        pHwDevInfo->pSR[i].jVal = 0xFF ;
625        pHwDevInfo->pCR[i].jIdx = 0xFF ;
626        pHwDevInfo->pCR[i].jVal = 0xFF ;
627    }
628
629    for( i = 0 ; i < VBIOS_VER_MAX_LENGTH ; i++ ){
630        pHwDevInfo -> szVBIOSVer[i] = '\0' ;
631    }
632
633
634    XGINew_InitVBIOSData(pHwDevInfo, pXGI->XGI_Pr);
635    PDEBUG(ErrorF("XGINew_InitVBIOSData(pHwDevInfo) done\n")) ;
636
637    ErrorF("XGI_InitVBIOSData  VBType = %x\n", pXGI->XGI_Pr->VBType);
638    XGI_New_GetVBType(pXGI->XGI_Pr, pHwDevInfo); //yilin
639    ErrorF("XGI_New_GetVBType  VBType = %x\n", pXGI->XGI_Pr->VBType);
640
641 //   pHwDevInfo->ujVBChipID = VB_CHIP_301 ; //yilin
642    if( pXGI->XGI_Pr->VBType & (VB_XGI301 | VB_XGI301B | VB_XGI301C))
643    {
644    PDEBUG(ErrorF("VB chip = 301 \n")) ;
645	 pHwDevInfo->ujVBChipID = VB_CHIP_301 ;
646    }
647    else if( pXGI->VBFlags & ( VB_XGI302B| VB_XGI302LV ))
648    {
649        pHwDevInfo->ujVBChipID = VB_CHIP_302 ;
650    }
651/*
652    else if (pXGI->VBFlags & VB_LVDS) {
653        pHwDevInfo->ulExternalChip |= 0x01 ;
654    }
655*/ //yilin
656
657
658    PDEBUG(ErrorF("pHwDevInfo->jChipType = %08lX done\n",pHwDevInfo->jChipType)) ;
659}
660
661Bool
662bAccessVGAPCIInfo(PXGI_HW_DEVICE_INFO pHwDevInfo, ULONG ulOffset, ULONG ulSet, ULONG *pulValue)
663{
664    XGIPtr pXGI ;
665#ifdef XSERVER_LIBPCIACCESS
666    int err;
667#else
668    PCITAG pciDev;
669#endif
670
671    if (!pHwDevInfo || !pulValue) {
672        return FALSE;
673    }
674
675    pXGI = (XGIPtr)pHwDevInfo->pDevice ;
676#ifdef XSERVER_LIBPCIACCESS
677    if (ulSet) {
678	err = pci_device_cfg_write_u32(pXGI->PciInfo, *pulValue,
679				       ulOffset & ~3);
680    } else {
681	err = pci_device_cfg_write_u32(pXGI->PciInfo, pulValue,
682				       ulOffset & ~3);
683    }
684
685    return (err == 0);
686#else
687    pciDev = pXGI->PciTag ;
688
689    if (ulSet) {
690        pciWriteLong(pciDev, ulOffset&0xFFFFFFFc, *pulValue);
691    } else {
692        *pulValue = pciReadLong(pciDev, ulOffset&0xFFFFFFFc);
693    }
694
695    return TRUE ;
696#endif
697}
698