1706f2543Smrg/*
2706f2543Smrg * edid.h: defines to parse an EDID block
3706f2543Smrg *
4706f2543Smrg * This file contains all information to interpret a standard EDIC block
5706f2543Smrg * transmitted by a display device via DDC (Display Data Channel). So far
6706f2543Smrg * there is no information to deal with optional EDID blocks.
7706f2543Smrg * DDC is a Trademark of VESA (Video Electronics Standard Association).
8706f2543Smrg *
9706f2543Smrg * Copyright 1998 by Egbert Eich <Egbert.Eich@Physik.TU-Darmstadt.DE>
10706f2543Smrg */
11706f2543Smrg
12706f2543Smrg#ifndef _EDID_H_
13706f2543Smrg#define _EDID_H_
14706f2543Smrg
15706f2543Smrg#include <X11/Xmd.h>
16706f2543Smrg
17706f2543Smrg#ifndef _X_EXPORT
18706f2543Smrg# include <X11/Xfuncproto.h>
19706f2543Smrg#endif
20706f2543Smrg
21706f2543Smrg/* read complete EDID record */
22706f2543Smrg#define EDID1_LEN 128
23706f2543Smrg#define BITS_PER_BYTE 9
24706f2543Smrg#define NUM BITS_PER_BYTE*EDID1_LEN
25706f2543Smrg#define HEADER 6
26706f2543Smrg
27706f2543Smrg#define STD_TIMINGS 8
28706f2543Smrg#define DET_TIMINGS 4
29706f2543Smrg
30706f2543Smrg#ifdef _PARSE_EDID_
31706f2543Smrg
32706f2543Smrg/* header: 0x00 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x00  */
33706f2543Smrg#define HEADER_SECTION 0
34706f2543Smrg#define HEADER_LENGTH 8
35706f2543Smrg
36706f2543Smrg/* vendor section */
37706f2543Smrg#define VENDOR_SECTION (HEADER_SECTION + HEADER_LENGTH)
38706f2543Smrg#define V_MANUFACTURER 0
39706f2543Smrg#define V_PROD_ID (V_MANUFACTURER + 2)
40706f2543Smrg#define V_SERIAL (V_PROD_ID + 2)
41706f2543Smrg#define V_WEEK (V_SERIAL + 4)
42706f2543Smrg#define V_YEAR (V_WEEK + 1)
43706f2543Smrg#define VENDOR_LENGTH (V_YEAR + 1)
44706f2543Smrg
45706f2543Smrg/* EDID version */
46706f2543Smrg#define VERSION_SECTION (VENDOR_SECTION + VENDOR_LENGTH)
47706f2543Smrg#define V_VERSION 0
48706f2543Smrg#define V_REVISION (V_VERSION + 1)
49706f2543Smrg#define VERSION_LENGTH (V_REVISION + 1)
50706f2543Smrg
51706f2543Smrg/* display information */
52706f2543Smrg#define DISPLAY_SECTION (VERSION_SECTION + VERSION_LENGTH)
53706f2543Smrg#define D_INPUT 0
54706f2543Smrg#define D_HSIZE (D_INPUT + 1)
55706f2543Smrg#define D_VSIZE (D_HSIZE + 1)
56706f2543Smrg#define D_GAMMA (D_VSIZE + 1)
57706f2543Smrg#define FEAT_S (D_GAMMA + 1)
58706f2543Smrg#define D_RG_LOW (FEAT_S + 1)
59706f2543Smrg#define D_BW_LOW (D_RG_LOW + 1)
60706f2543Smrg#define D_REDX (D_BW_LOW + 1)
61706f2543Smrg#define D_REDY (D_REDX + 1)
62706f2543Smrg#define D_GREENX (D_REDY + 1)
63706f2543Smrg#define D_GREENY (D_GREENX + 1)
64706f2543Smrg#define D_BLUEX (D_GREENY + 1)
65706f2543Smrg#define D_BLUEY (D_BLUEX + 1)
66706f2543Smrg#define D_WHITEX (D_BLUEY + 1)
67706f2543Smrg#define D_WHITEY (D_WHITEX + 1)
68706f2543Smrg#define DISPLAY_LENGTH (D_WHITEY + 1)
69706f2543Smrg
70706f2543Smrg/* supported VESA and other standard timings */
71706f2543Smrg#define ESTABLISHED_TIMING_SECTION (DISPLAY_SECTION + DISPLAY_LENGTH)
72706f2543Smrg#define E_T1 0
73706f2543Smrg#define E_T2 (E_T1 + 1)
74706f2543Smrg#define E_TMANU (E_T2 + 1)
75706f2543Smrg#define E_TIMING_LENGTH (E_TMANU + 1)
76706f2543Smrg
77706f2543Smrg/* non predefined standard timings supported by display */
78706f2543Smrg#define STD_TIMING_SECTION (ESTABLISHED_TIMING_SECTION + E_TIMING_LENGTH)
79706f2543Smrg#define STD_TIMING_INFO_LEN 2
80706f2543Smrg#define STD_TIMING_INFO_NUM STD_TIMINGS
81706f2543Smrg#define STD_TIMING_LENGTH (STD_TIMING_INFO_LEN * STD_TIMING_INFO_NUM)
82706f2543Smrg
83706f2543Smrg/* detailed timing info of non standard timings */
84706f2543Smrg#define DET_TIMING_SECTION (STD_TIMING_SECTION + STD_TIMING_LENGTH)
85706f2543Smrg#define DET_TIMING_INFO_LEN 18
86706f2543Smrg#define MONITOR_DESC_LEN DET_TIMING_INFO_LEN
87706f2543Smrg#define DET_TIMING_INFO_NUM DET_TIMINGS
88706f2543Smrg#define DET_TIMING_LENGTH (DET_TIMING_INFO_LEN * DET_TIMING_INFO_NUM)
89706f2543Smrg
90706f2543Smrg/* number of EDID sections to follow */
91706f2543Smrg#define NO_EDID (DET_TIMING_SECTION + DET_TIMING_LENGTH)
92706f2543Smrg/* one byte checksum */
93706f2543Smrg#define CHECKSUM (NO_EDID + 1)
94706f2543Smrg
95706f2543Smrg#if (CHECKSUM != (EDID1_LEN - 1))
96706f2543Smrg# error "EDID1 length != 128!"
97706f2543Smrg#endif
98706f2543Smrg
99706f2543Smrg
100706f2543Smrg#define SECTION(x,y) (Uchar *)(x + y)
101706f2543Smrg#define GET_ARRAY(y) ((Uchar *)(c + y))
102706f2543Smrg#define GET(y) *(Uchar *)(c + y)
103706f2543Smrg
104706f2543Smrg/* extract information from vendor section */
105706f2543Smrg#define _PROD_ID(x) x[0] + (x[1] << 8);
106706f2543Smrg#define PROD_ID _PROD_ID(GET_ARRAY(V_PROD_ID))
107706f2543Smrg#define _SERIAL_NO(x) x[0] + (x[1] << 8) + (x[2] << 16) + (x[3] << 24)
108706f2543Smrg#define SERIAL_NO _SERIAL_NO(GET_ARRAY(V_SERIAL))
109706f2543Smrg#define _YEAR(x) (x & 0xFF) + 1990
110706f2543Smrg#define YEAR _YEAR(GET(V_YEAR))
111706f2543Smrg#define WEEK GET(V_WEEK) & 0xFF
112706f2543Smrg#define _L1(x) ((x[0] & 0x7C) >> 2) + '@'
113706f2543Smrg#define _L2(x) ((x[0] & 0x03) << 3) + ((x[1] & 0xE0) >> 5) + '@'
114706f2543Smrg#define _L3(x) (x[1] & 0x1F) + '@';
115706f2543Smrg#define L1 _L1(GET_ARRAY(V_MANUFACTURER))
116706f2543Smrg#define L2 _L2(GET_ARRAY(V_MANUFACTURER))
117706f2543Smrg#define L3 _L3(GET_ARRAY(V_MANUFACTURER))
118706f2543Smrg
119706f2543Smrg/* extract information from version section */
120706f2543Smrg#define VERSION GET(V_VERSION)
121706f2543Smrg#define REVISION GET(V_REVISION)
122706f2543Smrg
123706f2543Smrg/* extract information from display section */
124706f2543Smrg#define _INPUT_TYPE(x) ((x & 0x80) >> 7)
125706f2543Smrg#define INPUT_TYPE _INPUT_TYPE(GET(D_INPUT))
126706f2543Smrg#define _INPUT_VOLTAGE(x) ((x & 0x60) >> 5)
127706f2543Smrg#define INPUT_VOLTAGE _INPUT_VOLTAGE(GET(D_INPUT))
128706f2543Smrg#define _SETUP(x) ((x & 0x10) >> 4)
129706f2543Smrg#define SETUP _SETUP(GET(D_INPUT))
130706f2543Smrg#define _SYNC(x) (x  & 0x0F)
131706f2543Smrg#define SYNC _SYNC(GET(D_INPUT))
132706f2543Smrg#define _DFP(x) (x & 0x01)
133706f2543Smrg#define DFP _DFP(GET(D_INPUT))
134706f2543Smrg#define _BPC(x) ((x & 0x70) >> 4)
135706f2543Smrg#define BPC _BPC(GET(D_INPUT))
136706f2543Smrg#define _DIGITAL_INTERFACE(x) (x & 0x0F)
137706f2543Smrg#define DIGITAL_INTERFACE _DIGITAL_INTERFACE(GET(D_INPUT))
138706f2543Smrg#define _GAMMA(x) (x == 0xff ? 0.0 : ((x + 100.0)/100.0))
139706f2543Smrg#define GAMMA _GAMMA(GET(D_GAMMA))
140706f2543Smrg#define HSIZE_MAX GET(D_HSIZE)
141706f2543Smrg#define VSIZE_MAX GET(D_VSIZE)
142706f2543Smrg#define _DPMS(x) ((x & 0xE0) >> 5)
143706f2543Smrg#define DPMS _DPMS(GET(FEAT_S))
144706f2543Smrg#define _DISPLAY_TYPE(x) ((x & 0x18) >> 3)
145706f2543Smrg#define DISPLAY_TYPE _DISPLAY_TYPE(GET(FEAT_S))
146706f2543Smrg#define _MSC(x) (x & 0x7)
147706f2543Smrg#define MSC _MSC(GET(FEAT_S))
148706f2543Smrg
149706f2543Smrg
150706f2543Smrg/* color characteristics */
151706f2543Smrg#define CC_L(x,y) ((x & (0x03 << y)) >> y)
152706f2543Smrg#define CC_H(x) (x << 2)
153706f2543Smrg#define I_CC(x,y,z) CC_H(y) | CC_L(x,z)
154706f2543Smrg#define F_CC(x) ((x)/1024.0)
155706f2543Smrg#define REDX F_CC(I_CC((GET(D_RG_LOW)),(GET(D_REDX)),6))
156706f2543Smrg#define REDY F_CC(I_CC((GET(D_RG_LOW)),(GET(D_REDY)),4))
157706f2543Smrg#define GREENX F_CC(I_CC((GET(D_RG_LOW)),(GET(D_GREENX)),2))
158706f2543Smrg#define GREENY F_CC(I_CC((GET(D_RG_LOW)),(GET(D_GREENY)),0))
159706f2543Smrg#define BLUEX F_CC(I_CC((GET(D_BW_LOW)),(GET(D_BLUEX)),6))
160706f2543Smrg#define BLUEY F_CC(I_CC((GET(D_BW_LOW)),(GET(D_BLUEY)),4))
161706f2543Smrg#define WHITEX F_CC(I_CC((GET(D_BW_LOW)),(GET(D_WHITEX)),2))
162706f2543Smrg#define WHITEY F_CC(I_CC((GET(D_BW_LOW)),(GET(D_WHITEY)),0))
163706f2543Smrg
164706f2543Smrg/* extract information from standard timing section */
165706f2543Smrg#define T1 GET(E_T1)
166706f2543Smrg#define T2 GET(E_T2)
167706f2543Smrg#define T_MANU GET(E_TMANU)
168706f2543Smrg
169706f2543Smrg/* extract information from estabished timing section */
170706f2543Smrg#define _VALID_TIMING(x) !(((x[0] == 0x01) && (x[1] == 0x01)) \
171706f2543Smrg                        || ((x[0] == 0x00) && (x[1] == 0x00)) \
172706f2543Smrg                        || ((x[0] == 0x20) && (x[1] == 0x20)) )
173706f2543Smrg#define VALID_TIMING _VALID_TIMING(c)
174706f2543Smrg#define _HSIZE1(x) ((x[0] + 31) * 8)
175706f2543Smrg#define HSIZE1 _HSIZE1(c)
176706f2543Smrg#define RATIO(x) ((x[1] & 0xC0) >> 6)
177706f2543Smrg#define RATIO1_1 0
178706f2543Smrg/* EDID Ver. 1.3 redefined this */
179706f2543Smrg#define RATIO16_10 RATIO1_1
180706f2543Smrg#define RATIO4_3 1
181706f2543Smrg#define RATIO5_4 2
182706f2543Smrg#define RATIO16_9 3
183706f2543Smrg#define _VSIZE1(x,y,r) switch(RATIO(x)){ \
184706f2543Smrg  case RATIO1_1: y =  ((v->version > 1 || v->revision > 2) \
185706f2543Smrg		       ? (_HSIZE1(x) * 10) / 16 : _HSIZE1(x)); break; \
186706f2543Smrg  case RATIO4_3: y = _HSIZE1(x) * 3 / 4; break; \
187706f2543Smrg  case RATIO5_4: y = _HSIZE1(x) * 4 / 5; break; \
188706f2543Smrg  case RATIO16_9: y = _HSIZE1(x) * 9 / 16; break; \
189706f2543Smrg  }
190706f2543Smrg#define VSIZE1(x) _VSIZE1(c,x,v)
191706f2543Smrg#define _REFRESH_R(x) (x[1] & 0x3F) + 60
192706f2543Smrg#define REFRESH_R  _REFRESH_R(c)
193706f2543Smrg#define _ID_LOW(x) x[0]
194706f2543Smrg#define ID_LOW _ID_LOW(c)
195706f2543Smrg#define _ID_HIGH(x) (x[1] << 8)
196706f2543Smrg#define ID_HIGH _ID_HIGH(c)
197706f2543Smrg#define STD_TIMING_ID (ID_LOW | ID_HIGH)
198706f2543Smrg#define _NEXT_STD_TIMING(x)  (x = (x + STD_TIMING_INFO_LEN))
199706f2543Smrg#define NEXT_STD_TIMING _NEXT_STD_TIMING(c)
200706f2543Smrg
201706f2543Smrg
202706f2543Smrg/* EDID Ver. >= 1.2 */
203706f2543Smrg/**
204706f2543Smrg * Returns true if the pointer is the start of a monitor descriptor block
205706f2543Smrg * instead of a detailed timing descriptor.
206706f2543Smrg *
207706f2543Smrg * Checking the reserved pad fields for zeroes fails on some monitors with
208706f2543Smrg * broken empty ASCII strings.  Only the first two bytes are reliable.
209706f2543Smrg */
210706f2543Smrg#define _IS_MONITOR_DESC(x) (x[0] == 0 && x[1] == 0)
211706f2543Smrg#define IS_MONITOR_DESC _IS_MONITOR_DESC(c)
212706f2543Smrg#define _PIXEL_CLOCK(x) (x[0] + (x[1] << 8)) * 10000
213706f2543Smrg#define PIXEL_CLOCK _PIXEL_CLOCK(c)
214706f2543Smrg#define _H_ACTIVE(x) (x[2] + ((x[4] & 0xF0) << 4))
215706f2543Smrg#define H_ACTIVE _H_ACTIVE(c)
216706f2543Smrg#define _H_BLANK(x) (x[3] + ((x[4] & 0x0F) << 8))
217706f2543Smrg#define H_BLANK _H_BLANK(c)
218706f2543Smrg#define _V_ACTIVE(x) (x[5] + ((x[7] & 0xF0) << 4))
219706f2543Smrg#define V_ACTIVE _V_ACTIVE(c)
220706f2543Smrg#define _V_BLANK(x) (x[6] + ((x[7] & 0x0F) << 8))
221706f2543Smrg#define V_BLANK _V_BLANK(c)
222706f2543Smrg#define _H_SYNC_OFF(x) (x[8] + ((x[11] & 0xC0) << 2))
223706f2543Smrg#define H_SYNC_OFF _H_SYNC_OFF(c)
224706f2543Smrg#define _H_SYNC_WIDTH(x) (x[9] + ((x[11] & 0x30) << 4))
225706f2543Smrg#define H_SYNC_WIDTH _H_SYNC_WIDTH(c)
226706f2543Smrg#define _V_SYNC_OFF(x) ((x[10] >> 4) + ((x[11] & 0x0C) << 2))
227706f2543Smrg#define V_SYNC_OFF _V_SYNC_OFF(c)
228706f2543Smrg#define _V_SYNC_WIDTH(x) ((x[10] & 0x0F) + ((x[11] & 0x03) << 4))
229706f2543Smrg#define V_SYNC_WIDTH _V_SYNC_WIDTH(c)
230706f2543Smrg#define _H_SIZE(x) (x[12] + ((x[14] & 0xF0) << 4))
231706f2543Smrg#define H_SIZE _H_SIZE(c)
232706f2543Smrg#define _V_SIZE(x) (x[13] + ((x[14] & 0x0F) << 8))
233706f2543Smrg#define V_SIZE _V_SIZE(c)
234706f2543Smrg#define _H_BORDER(x) (x[15])
235706f2543Smrg#define H_BORDER _H_BORDER(c)
236706f2543Smrg#define _V_BORDER(x) (x[16])
237706f2543Smrg#define V_BORDER _V_BORDER(c)
238706f2543Smrg#define _INTERLACED(x) ((x[17] & 0x80) >> 7)
239706f2543Smrg#define INTERLACED _INTERLACED(c)
240706f2543Smrg#define _STEREO(x) ((x[17] & 0x60) >> 5)
241706f2543Smrg#define STEREO _STEREO(c)
242706f2543Smrg#define _STEREO1(x) (x[17] & 0x1)
243706f2543Smrg#define STEREO1 _STEREO(c)
244706f2543Smrg#define _SYNC_T(x) ((x[17] & 0x18) >> 3)
245706f2543Smrg#define SYNC_T _SYNC_T(c)
246706f2543Smrg#define _MISC(x) ((x[17] & 0x06) >> 1)
247706f2543Smrg#define MISC _MISC(c)
248706f2543Smrg
249706f2543Smrg#define _MONITOR_DESC_TYPE(x) x[3]
250706f2543Smrg#define MONITOR_DESC_TYPE _MONITOR_DESC_TYPE(c)
251706f2543Smrg#define SERIAL_NUMBER 0xFF
252706f2543Smrg#define ASCII_STR 0xFE
253706f2543Smrg#define MONITOR_RANGES 0xFD
254706f2543Smrg#define _MIN_V_OFFSET(x) ((!!(x[4] & 0x01)) * 255)
255706f2543Smrg#define _MAX_V_OFFSET(x) ((!!(x[4] & 0x02)) * 255)
256706f2543Smrg#define _MIN_H_OFFSET(x) ((!!(x[4] & 0x04)) * 255)
257706f2543Smrg#define _MAX_H_OFFSET(x) ((!!(x[4] & 0x08)) * 255)
258706f2543Smrg#define _MIN_V(x) x[5]
259706f2543Smrg#define MIN_V (_MIN_V(c) + _MIN_V_OFFSET(c))
260706f2543Smrg#define _MAX_V(x) x[6]
261706f2543Smrg#define MAX_V (_MAX_V(c) + _MAX_V_OFFSET(c))
262706f2543Smrg#define _MIN_H(x) x[7]
263706f2543Smrg#define MIN_H (_MIN_H(c) + _MIN_H_OFFSET(c))
264706f2543Smrg#define _MAX_H(x) x[8]
265706f2543Smrg#define MAX_H (_MAX_H(c) + _MAX_H_OFFSET(c))
266706f2543Smrg#define _MAX_CLOCK(x) x[9]
267706f2543Smrg#define MAX_CLOCK _MAX_CLOCK(c)
268706f2543Smrg#define _HAVE_2ND_GTF(x) (x[10] == 0x02)
269706f2543Smrg#define HAVE_2ND_GTF _HAVE_2ND_GTF(c)
270706f2543Smrg#define _F_2ND_GTF(x) (x[12] * 2)
271706f2543Smrg#define F_2ND_GTF _F_2ND_GTF(c)
272706f2543Smrg#define _C_2ND_GTF(x) (x[13] / 2)
273706f2543Smrg#define C_2ND_GTF _C_2ND_GTF(c)
274706f2543Smrg#define _M_2ND_GTF(x) (x[14] + (x[15] << 8))
275706f2543Smrg#define M_2ND_GTF _M_2ND_GTF(c)
276706f2543Smrg#define _K_2ND_GTF(x) (x[16])
277706f2543Smrg#define K_2ND_GTF _K_2ND_GTF(c)
278706f2543Smrg#define _J_2ND_GTF(x) (x[17] / 2)
279706f2543Smrg#define J_2ND_GTF _J_2ND_GTF(c)
280706f2543Smrg#define _HAVE_CVT(x) (x[10] == 0x04)
281706f2543Smrg#define HAVE_CVT _HAVE_CVT(c)
282706f2543Smrg#define _MAX_CLOCK_KHZ(x) (x[12] >> 2)
283706f2543Smrg#define MAX_CLOCK_KHZ (MAX_CLOCK * 10000) - (_MAX_CLOCK_KHZ(c) * 250)
284706f2543Smrg#define _MAXWIDTH(x) ((x[13] == 0 ? 0 : x[13] + ((x[12] & 0x03) << 8)) * 8)
285706f2543Smrg#define MAXWIDTH _MAXWIDTH(c)
286706f2543Smrg#define _SUPPORTED_ASPECT(x) x[14]
287706f2543Smrg#define SUPPORTED_ASPECT _SUPPORTED_ASPECT(c)
288706f2543Smrg#define  SUPPORTED_ASPECT_4_3   0x80
289706f2543Smrg#define  SUPPORTED_ASPECT_16_9  0x40
290706f2543Smrg#define  SUPPORTED_ASPECT_16_10 0x20
291706f2543Smrg#define  SUPPORTED_ASPECT_5_4   0x10
292706f2543Smrg#define  SUPPORTED_ASPECT_15_9  0x08
293706f2543Smrg#define _PREFERRED_ASPECT(x) ((x[15] & 0xe0) >> 5)
294706f2543Smrg#define PREFERRED_ASPECT _PREFERRED_ASPECT(c)
295706f2543Smrg#define  PREFERRED_ASPECT_4_3   0
296706f2543Smrg#define  PREFERRED_ASPECT_16_9  1
297706f2543Smrg#define  PREFERRED_ASPECT_16_10 2
298706f2543Smrg#define  PREFERRED_ASPECT_5_4   3
299706f2543Smrg#define  PREFERRED_ASPECT_15_9  4
300706f2543Smrg#define _SUPPORTED_BLANKING(x) ((x[15] & 0x18) >> 3)
301706f2543Smrg#define SUPPORTED_BLANKING _SUPPORTED_BLANKING(c)
302706f2543Smrg#define  CVT_STANDARD 0x01
303706f2543Smrg#define  CVT_REDUCED  0x02
304706f2543Smrg#define _SUPPORTED_SCALING(x) ((x[16] & 0xf0) >> 4)
305706f2543Smrg#define SUPPORTED_SCALING _SUPPORTED_SCALING(c)
306706f2543Smrg#define  SCALING_HSHRINK  0x08
307706f2543Smrg#define  SCALING_HSTRETCH 0x04
308706f2543Smrg#define  SCALING_VSHRINK  0x02
309706f2543Smrg#define  SCALING_VSTRETCH 0x01
310706f2543Smrg#define _PREFERRED_REFRESH(x) x[17]
311706f2543Smrg#define PREFERRED_REFRESH _PREFERRED_REFRESH(c)
312706f2543Smrg
313706f2543Smrg#define MONITOR_NAME 0xFC
314706f2543Smrg#define ADD_COLOR_POINT 0xFB
315706f2543Smrg#define WHITEX F_CC(I_CC((GET(D_BW_LOW)),(GET(D_WHITEX)),2))
316706f2543Smrg#define WHITEY F_CC(I_CC((GET(D_BW_LOW)),(GET(D_WHITEY)),0))
317706f2543Smrg#define _WHITEX_ADD(x,y) F_CC(I_CC(((*(x + y))),(*(x + y + 1)),2))
318706f2543Smrg#define _WHITEY_ADD(x,y) F_CC(I_CC(((*(x + y))),(*(x + y + 2)),0))
319706f2543Smrg#define _WHITE_INDEX1(x) x[5]
320706f2543Smrg#define WHITE_INDEX1 _WHITE_INDEX1(c)
321706f2543Smrg#define _WHITE_INDEX2(x) x[10]
322706f2543Smrg#define WHITE_INDEX2 _WHITE_INDEX2(c)
323706f2543Smrg#define WHITEX1 _WHITEX_ADD(c,6)
324706f2543Smrg#define WHITEY1 _WHITEY_ADD(c,6)
325706f2543Smrg#define WHITEX2 _WHITEX_ADD(c,12)
326706f2543Smrg#define WHITEY2 _WHITEY_ADD(c,12)
327706f2543Smrg#define _WHITE_GAMMA1(x) _GAMMA(x[9])
328706f2543Smrg#define WHITE_GAMMA1 _WHITE_GAMMA1(c)
329706f2543Smrg#define _WHITE_GAMMA2(x) _GAMMA(x[14])
330706f2543Smrg#define WHITE_GAMMA2 _WHITE_GAMMA2(c)
331706f2543Smrg#define ADD_STD_TIMINGS 0xFA
332706f2543Smrg#define COLOR_MANAGEMENT_DATA 0xF9
333706f2543Smrg#define CVT_3BYTE_DATA 0xF8
334706f2543Smrg#define ADD_EST_TIMINGS 0xF7
335706f2543Smrg#define ADD_DUMMY 0x10
336706f2543Smrg
337706f2543Smrg#define _NEXT_DT_MD_SECTION(x) (x = (x + DET_TIMING_INFO_LEN))
338706f2543Smrg#define NEXT_DT_MD_SECTION _NEXT_DT_MD_SECTION(c)
339706f2543Smrg
340706f2543Smrg#endif /* _PARSE_EDID_ */
341706f2543Smrg
342706f2543Smrg/* input type */
343706f2543Smrg#define DIGITAL(x) x
344706f2543Smrg
345706f2543Smrg/* DFP */
346706f2543Smrg#define DFP1(x) x
347706f2543Smrg
348706f2543Smrg/* input voltage level */
349706f2543Smrg#define V070 0  /* 0.700V/0.300V */
350706f2543Smrg#define V071 1  /* 0.714V/0.286V */
351706f2543Smrg#define V100 2  /* 1.000V/0.400V */
352706f2543Smrg#define V007 3 /* 0.700V/0.000V */
353706f2543Smrg
354706f2543Smrg/* Signal level setup */
355706f2543Smrg#define SIG_SETUP(x) (x)
356706f2543Smrg
357706f2543Smrg/* sync characteristics */
358706f2543Smrg#define SEP_SYNC(x) (x & 0x08)
359706f2543Smrg#define COMP_SYNC(x) (x & 0x04)
360706f2543Smrg#define SYNC_O_GREEN(x) (x & 0x02)
361706f2543Smrg#define SYNC_SERR(x) (x & 0x01)
362706f2543Smrg
363706f2543Smrg/* DPMS features */
364706f2543Smrg#define DPMS_STANDBY(x) (x & 0x04)
365706f2543Smrg#define DPMS_SUSPEND(x) (x & 0x02)
366706f2543Smrg#define DPMS_OFF(x) (x & 0x01)
367706f2543Smrg
368706f2543Smrg/* display type, analog */
369706f2543Smrg#define DISP_MONO 0
370706f2543Smrg#define DISP_RGB 1
371706f2543Smrg#define DISP_MULTCOLOR 2
372706f2543Smrg
373706f2543Smrg/* display color encodings, digital */
374706f2543Smrg#define DISP_YCRCB444 0x01
375706f2543Smrg#define DISP_YCRCB422 0x02
376706f2543Smrg
377706f2543Smrg/* Msc stuff EDID Ver > 1.1 */
378706f2543Smrg#define STD_COLOR_SPACE(x) (x & 0x4)
379706f2543Smrg#define PREFERRED_TIMING_MODE(x) (x & 0x2)
380706f2543Smrg#define GFT_SUPPORTED(x) (x & 0x1)
381706f2543Smrg#define GTF_SUPPORTED(x) (x & 0x1)
382706f2543Smrg#define CVT_SUPPORTED(x) (x & 0x1)
383706f2543Smrg
384706f2543Smrg/* detailed timing misc */
385706f2543Smrg#define IS_INTERLACED(x)  (x)
386706f2543Smrg#define IS_STEREO(x)  (x)
387706f2543Smrg#define IS_RIGHT_STEREO(x) (x & 0x01)
388706f2543Smrg#define IS_LEFT_STEREO(x) (x & 0x02)
389706f2543Smrg#define IS_4WAY_STEREO(x) (x & 0x03)
390706f2543Smrg#define IS_RIGHT_ON_SYNC(x) IS_RIGHT_STEREO(x)
391706f2543Smrg#define IS_LEFT_ON_SYNC(x) IS_LEFT_STEREO(x)
392706f2543Smrg
393706f2543Smrg
394706f2543Smrgtypedef unsigned int Uint;
395706f2543Smrgtypedef unsigned char Uchar;
396706f2543Smrg
397706f2543Smrgstruct vendor {
398706f2543Smrg  char name[4];
399706f2543Smrg  int prod_id;
400706f2543Smrg  Uint serial;
401706f2543Smrg  int week;
402706f2543Smrg  int year;
403706f2543Smrg};
404706f2543Smrg
405706f2543Smrgstruct edid_version {
406706f2543Smrg  int version;
407706f2543Smrg  int revision;
408706f2543Smrg};
409706f2543Smrg
410706f2543Smrgstruct disp_features {
411706f2543Smrg  unsigned int input_type:1;
412706f2543Smrg  unsigned int input_voltage:2;
413706f2543Smrg  unsigned int input_setup:1;
414706f2543Smrg  unsigned int input_sync:5;
415706f2543Smrg  unsigned int input_dfp:1;
416706f2543Smrg  unsigned int input_bpc:3;
417706f2543Smrg  unsigned int input_interface:4;
418706f2543Smrg  /* 15 bit hole */
419706f2543Smrg  int hsize;
420706f2543Smrg  int vsize;
421706f2543Smrg  float gamma;
422706f2543Smrg  unsigned int dpms:3;
423706f2543Smrg  unsigned int display_type:2;
424706f2543Smrg  unsigned int msc:3;
425706f2543Smrg  float redx;
426706f2543Smrg  float redy;
427706f2543Smrg  float greenx;
428706f2543Smrg  float greeny;
429706f2543Smrg  float bluex;
430706f2543Smrg  float bluey;
431706f2543Smrg  float whitex;
432706f2543Smrg  float whitey;
433706f2543Smrg};
434706f2543Smrg
435706f2543Smrgstruct established_timings {
436706f2543Smrg  Uchar t1;
437706f2543Smrg  Uchar t2;
438706f2543Smrg  Uchar t_manu;
439706f2543Smrg};
440706f2543Smrg
441706f2543Smrgstruct std_timings {
442706f2543Smrg  int hsize;
443706f2543Smrg  int vsize;
444706f2543Smrg  int refresh;
445706f2543Smrg  CARD16 id;
446706f2543Smrg};
447706f2543Smrg
448706f2543Smrgstruct detailed_timings {
449706f2543Smrg  int clock;
450706f2543Smrg  int h_active;
451706f2543Smrg  int h_blanking;
452706f2543Smrg  int v_active;
453706f2543Smrg  int v_blanking;
454706f2543Smrg  int h_sync_off;
455706f2543Smrg  int h_sync_width;
456706f2543Smrg  int v_sync_off;
457706f2543Smrg  int v_sync_width;
458706f2543Smrg  int h_size;
459706f2543Smrg  int v_size;
460706f2543Smrg  int h_border;
461706f2543Smrg  int v_border;
462706f2543Smrg  unsigned int interlaced:1;
463706f2543Smrg  unsigned int stereo:2;
464706f2543Smrg  unsigned int sync:2;
465706f2543Smrg  unsigned int misc:2;
466706f2543Smrg  unsigned int stereo_1:1;
467706f2543Smrg};
468706f2543Smrg
469706f2543Smrg#define DT 0
470706f2543Smrg#define DS_SERIAL 0xFF
471706f2543Smrg#define DS_ASCII_STR 0xFE
472706f2543Smrg#define DS_NAME 0xFC
473706f2543Smrg#define DS_RANGES 0xFD
474706f2543Smrg#define DS_WHITE_P 0xFB
475706f2543Smrg#define DS_STD_TIMINGS 0xFA
476706f2543Smrg#define DS_CMD 0xF9
477706f2543Smrg#define DS_CVT 0xF8
478706f2543Smrg#define DS_EST_III 0xF7
479706f2543Smrg#define DS_DUMMY 0x10
480706f2543Smrg#define DS_UNKOWN 0x100 /* type is an int */
481706f2543Smrg#define DS_VENDOR 0x101
482706f2543Smrg#define DS_VENDOR_MAX 0x110
483706f2543Smrg
484706f2543Smrgstruct monitor_ranges {
485706f2543Smrg  int min_v;
486706f2543Smrg  int max_v;
487706f2543Smrg  int min_h;
488706f2543Smrg  int max_h;
489706f2543Smrg  int max_clock;    /* in mhz */
490706f2543Smrg  int gtf_2nd_f;
491706f2543Smrg  int gtf_2nd_c;
492706f2543Smrg  int gtf_2nd_m;
493706f2543Smrg  int gtf_2nd_k;
494706f2543Smrg  int gtf_2nd_j;
495706f2543Smrg  int max_clock_khz;
496706f2543Smrg  int maxwidth;	    /* in pixels */
497706f2543Smrg  char supported_aspect;
498706f2543Smrg  char preferred_aspect;
499706f2543Smrg  char supported_blanking;
500706f2543Smrg  char supported_scaling;
501706f2543Smrg  int preferred_refresh; /* in hz */
502706f2543Smrg};
503706f2543Smrg
504706f2543Smrgstruct whitePoints{
505706f2543Smrg  int   index;
506706f2543Smrg  float white_x;
507706f2543Smrg  float white_y;
508706f2543Smrg  float white_gamma;
509706f2543Smrg};
510706f2543Smrg
511706f2543Smrgstruct cvt_timings {
512706f2543Smrg    int width;
513706f2543Smrg    int height;
514706f2543Smrg    int rate;
515706f2543Smrg    int rates;
516706f2543Smrg};
517706f2543Smrg
518706f2543Smrg/*
519706f2543Smrg * Be careful when adding new sections; this structure can't grow, it's
520706f2543Smrg * embedded in the middle of xf86Monitor which is ABI.  Sizes below are
521706f2543Smrg * in bytes, for ILP32 systems.  If all else fails just copy the section
522706f2543Smrg * literally like serial and friends.
523706f2543Smrg */
524706f2543Smrgstruct detailed_monitor_section {
525706f2543Smrg  int type;
526706f2543Smrg  union {
527706f2543Smrg    struct detailed_timings d_timings;	/* 56 */
528706f2543Smrg    Uchar serial[13];
529706f2543Smrg    Uchar ascii_data[13];
530706f2543Smrg    Uchar name[13];
531706f2543Smrg    struct monitor_ranges ranges;	/* 56 */
532706f2543Smrg    struct std_timings std_t[5];	/* 80 */
533706f2543Smrg    struct whitePoints wp[2];		/* 32 */
534706f2543Smrg    /* color management data */
535706f2543Smrg    struct cvt_timings cvt[4];		/* 64 */
536706f2543Smrg    Uchar est_iii[6];			/* 6 */
537706f2543Smrg  } section;				/* max: 80 */
538706f2543Smrg};
539706f2543Smrg
540706f2543Smrg/* flags */
541706f2543Smrg#define MONITOR_EDID_COMPLETE_RAWDATA	0x01
542706f2543Smrg/* old, don't use */
543706f2543Smrg#define EDID_COMPLETE_RAWDATA		0x01
544706f2543Smrg#define MONITOR_DISPLAYID		0x02
545706f2543Smrg
546706f2543Smrg/*
547706f2543Smrg * For DisplayID devices, only the scrnIndex, flags, and rawData fields
548706f2543Smrg * are meaningful.  For EDID, they all are.
549706f2543Smrg */
550706f2543Smrgtypedef struct {
551706f2543Smrg  int scrnIndex;
552706f2543Smrg  struct vendor vendor;
553706f2543Smrg  struct edid_version ver;
554706f2543Smrg  struct disp_features features;
555706f2543Smrg  struct established_timings timings1;
556706f2543Smrg  struct std_timings timings2[8];
557706f2543Smrg  struct detailed_monitor_section det_mon[4];
558706f2543Smrg  unsigned long flags;
559706f2543Smrg  int no_sections;
560706f2543Smrg  Uchar *rawData;
561706f2543Smrg} xf86Monitor, *xf86MonPtr;
562706f2543Smrg
563706f2543Smrgextern _X_EXPORT xf86MonPtr ConfiguredMonitor;
564706f2543Smrg
565706f2543Smrg#define EXT_TAG 0
566706f2543Smrg#define EXT_REV 1
567706f2543Smrg#define CEA_EXT   0x02
568706f2543Smrg#define VTB_EXT   0x10
569706f2543Smrg#define DI_EXT    0x40
570706f2543Smrg#define LS_EXT    0x50
571706f2543Smrg#define MI_EXT    0x60
572706f2543Smrg
573706f2543Smrg#define CEA_EXT_MIN_DATA_OFFSET 4
574706f2543Smrg#define CEA_EXT_MAX_DATA_OFFSET 127
575706f2543Smrg#define CEA_EXT_DET_TIMING_NUM 6
576706f2543Smrg
577706f2543Smrg#define IEEE_ID_HDMI    0x000C03
578706f2543Smrg#define CEA_AUDIO_BLK   1
579706f2543Smrg#define CEA_VIDEO_BLK   2
580706f2543Smrg#define CEA_VENDOR_BLK  3
581706f2543Smrg#define CEA_SPEAKER_ALLOC_BLK 4
582706f2543Smrg#define CEA_VESA_DTC_BLK 5
583706f2543Smrg#define VENDOR_SUPPORT_AI(x) ((x) >> 7)
584706f2543Smrg#define VENDOR_SUPPORT_DC_48bit(x)  ( ( (x) >> 6) & 0x01)
585706f2543Smrg#define VENDOR_SUPPORT_DC_36bit(x)  ( ( (x) >> 5) & 0x01)
586706f2543Smrg#define VENDOR_SUPPORT_DC_30bit(x)  ( ( (x) >> 4) & 0x01)
587706f2543Smrg#define VENDOR_SUPPORT_DC_Y444(x)   ( ( (x) >> 3) & 0x01)
588706f2543Smrg#define VENDOR_LATENCY_PRESENT(x)     ( (x) >> 7)
589706f2543Smrg#define VENDOR_LATENCY_PRESENT_I(x) ( ( (x) >> 6) & 0x01)
590706f2543Smrg#define HDMI_MAX_TMDS_UNIT   (5000)
591706f2543Smrg
592706f2543Smrgstruct cea_video_block {
593706f2543Smrg  Uchar video_code;
594706f2543Smrg};
595706f2543Smrg
596706f2543Smrgstruct cea_audio_block_descriptor {
597706f2543Smrg  Uchar audio_code[3];
598706f2543Smrg};
599706f2543Smrg
600706f2543Smrgstruct cea_audio_block {
601706f2543Smrg  struct cea_audio_block_descriptor descriptor[10];
602706f2543Smrg};
603706f2543Smrg
604706f2543Smrgstruct cea_vendor_block_hdmi {
605706f2543Smrg  Uchar  portB:4;
606706f2543Smrg  Uchar  portA:4;
607706f2543Smrg  Uchar  portD:4;
608706f2543Smrg  Uchar  portC:4;
609706f2543Smrg  Uchar  support_flags;
610706f2543Smrg  Uchar  max_tmds_clock;
611706f2543Smrg  Uchar  latency_present;
612706f2543Smrg  Uchar  video_latency;
613706f2543Smrg  Uchar  audio_latency;
614706f2543Smrg  Uchar  interlaced_video_latency;
615706f2543Smrg  Uchar  interlaced_audio_latency;
616706f2543Smrg};
617706f2543Smrg
618706f2543Smrgstruct cea_vendor_block {
619706f2543Smrg  unsigned char ieee_id[3];
620706f2543Smrg  union {
621706f2543Smrg      struct cea_vendor_block_hdmi hdmi;
622706f2543Smrg      /* any other vendor blocks we know about */
623706f2543Smrg  };
624706f2543Smrg};
625706f2543Smrg
626706f2543Smrgstruct cea_speaker_block
627706f2543Smrg{
628706f2543Smrg  Uchar FLR:1;
629706f2543Smrg  Uchar LFE:1;
630706f2543Smrg  Uchar FC:1;
631706f2543Smrg  Uchar RLR:1;
632706f2543Smrg  Uchar RC:1;
633706f2543Smrg  Uchar FLRC:1;
634706f2543Smrg  Uchar RLRC:1;
635706f2543Smrg  Uchar FLRW:1;
636706f2543Smrg  Uchar FLRH:1;
637706f2543Smrg  Uchar TC:1;
638706f2543Smrg  Uchar FCH:1;
639706f2543Smrg  Uchar Resv:5;
640706f2543Smrg  Uchar ResvByte;
641706f2543Smrg};
642706f2543Smrg
643706f2543Smrgstruct cea_data_block {
644706f2543Smrg  Uchar len:5;
645706f2543Smrg  Uchar tag:3;
646706f2543Smrg  union{
647706f2543Smrg    struct cea_video_block video;
648706f2543Smrg    struct cea_audio_block audio;
649706f2543Smrg    struct cea_vendor_block vendor;
650706f2543Smrg    struct cea_speaker_block speaker;
651706f2543Smrg  }u;
652706f2543Smrg};
653706f2543Smrg
654706f2543Smrgstruct cea_ext_body {
655706f2543Smrg  Uchar tag;
656706f2543Smrg  Uchar rev;
657706f2543Smrg  Uchar dt_offset;
658706f2543Smrg  Uchar flags;
659706f2543Smrg  struct cea_data_block data_collection;
660706f2543Smrg};
661706f2543Smrg
662706f2543Smrg#endif /* _EDID_H_ */
663