14642e01fSmrg/*
235c4bbdfSmrg * edid.h: defines to parse an EDID block
305b261ecSmrg *
435c4bbdfSmrg * This file contains all information to interpret a standard EDIC block
535c4bbdfSmrg * transmitted by a display device via DDC (Display Data Channel). So far
635c4bbdfSmrg * there is no information to deal with optional EDID blocks.
705b261ecSmrg * DDC is a Trademark of VESA (Video Electronics Standard Association).
805b261ecSmrg *
905b261ecSmrg * Copyright 1998 by Egbert Eich <Egbert.Eich@Physik.TU-Darmstadt.DE>
1005b261ecSmrg */
1105b261ecSmrg
1205b261ecSmrg#ifndef _EDID_H_
1335c4bbdfSmrg#define _EDID_H_
1405b261ecSmrg
156747b715Smrg#include <X11/Xmd.h>
166747b715Smrg
176747b715Smrg#ifndef _X_EXPORT
1835c4bbdfSmrg#include <X11/Xfuncproto.h>
196747b715Smrg#endif
206747b715Smrg
2105b261ecSmrg/* read complete EDID record */
2205b261ecSmrg#define EDID1_LEN 128
2305b261ecSmrg#define BITS_PER_BYTE 9
2405b261ecSmrg#define NUM BITS_PER_BYTE*EDID1_LEN
2505b261ecSmrg#define HEADER 6
2605b261ecSmrg
2705b261ecSmrg#define STD_TIMINGS 8
2805b261ecSmrg#define DET_TIMINGS 4
2905b261ecSmrg
3005b261ecSmrg#ifdef _PARSE_EDID_
3105b261ecSmrg
3205b261ecSmrg/* header: 0x00 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x00  */
3305b261ecSmrg#define HEADER_SECTION 0
3405b261ecSmrg#define HEADER_LENGTH 8
3505b261ecSmrg
3605b261ecSmrg/* vendor section */
3705b261ecSmrg#define VENDOR_SECTION (HEADER_SECTION + HEADER_LENGTH)
3805b261ecSmrg#define V_MANUFACTURER 0
3905b261ecSmrg#define V_PROD_ID (V_MANUFACTURER + 2)
4005b261ecSmrg#define V_SERIAL (V_PROD_ID + 2)
4105b261ecSmrg#define V_WEEK (V_SERIAL + 4)
4205b261ecSmrg#define V_YEAR (V_WEEK + 1)
4305b261ecSmrg#define VENDOR_LENGTH (V_YEAR + 1)
4405b261ecSmrg
4505b261ecSmrg/* EDID version */
4605b261ecSmrg#define VERSION_SECTION (VENDOR_SECTION + VENDOR_LENGTH)
4705b261ecSmrg#define V_VERSION 0
4805b261ecSmrg#define V_REVISION (V_VERSION + 1)
4905b261ecSmrg#define VERSION_LENGTH (V_REVISION + 1)
5005b261ecSmrg
5105b261ecSmrg/* display information */
5205b261ecSmrg#define DISPLAY_SECTION (VERSION_SECTION + VERSION_LENGTH)
5305b261ecSmrg#define D_INPUT 0
5405b261ecSmrg#define D_HSIZE (D_INPUT + 1)
5505b261ecSmrg#define D_VSIZE (D_HSIZE + 1)
5605b261ecSmrg#define D_GAMMA (D_VSIZE + 1)
5705b261ecSmrg#define FEAT_S (D_GAMMA + 1)
5805b261ecSmrg#define D_RG_LOW (FEAT_S + 1)
5905b261ecSmrg#define D_BW_LOW (D_RG_LOW + 1)
6005b261ecSmrg#define D_REDX (D_BW_LOW + 1)
6105b261ecSmrg#define D_REDY (D_REDX + 1)
6205b261ecSmrg#define D_GREENX (D_REDY + 1)
6305b261ecSmrg#define D_GREENY (D_GREENX + 1)
6405b261ecSmrg#define D_BLUEX (D_GREENY + 1)
6505b261ecSmrg#define D_BLUEY (D_BLUEX + 1)
6605b261ecSmrg#define D_WHITEX (D_BLUEY + 1)
6705b261ecSmrg#define D_WHITEY (D_WHITEX + 1)
6805b261ecSmrg#define DISPLAY_LENGTH (D_WHITEY + 1)
6905b261ecSmrg
7005b261ecSmrg/* supported VESA and other standard timings */
7105b261ecSmrg#define ESTABLISHED_TIMING_SECTION (DISPLAY_SECTION + DISPLAY_LENGTH)
7205b261ecSmrg#define E_T1 0
7305b261ecSmrg#define E_T2 (E_T1 + 1)
7405b261ecSmrg#define E_TMANU (E_T2 + 1)
7535c4bbdfSmrg#define E_TIMING_LENGTH (E_TMANU + 1)
7605b261ecSmrg
7705b261ecSmrg/* non predefined standard timings supported by display */
7805b261ecSmrg#define STD_TIMING_SECTION (ESTABLISHED_TIMING_SECTION + E_TIMING_LENGTH)
7905b261ecSmrg#define STD_TIMING_INFO_LEN 2
8005b261ecSmrg#define STD_TIMING_INFO_NUM STD_TIMINGS
8105b261ecSmrg#define STD_TIMING_LENGTH (STD_TIMING_INFO_LEN * STD_TIMING_INFO_NUM)
8205b261ecSmrg
8305b261ecSmrg/* detailed timing info of non standard timings */
8405b261ecSmrg#define DET_TIMING_SECTION (STD_TIMING_SECTION + STD_TIMING_LENGTH)
8505b261ecSmrg#define DET_TIMING_INFO_LEN 18
8605b261ecSmrg#define MONITOR_DESC_LEN DET_TIMING_INFO_LEN
8705b261ecSmrg#define DET_TIMING_INFO_NUM DET_TIMINGS
8805b261ecSmrg#define DET_TIMING_LENGTH (DET_TIMING_INFO_LEN * DET_TIMING_INFO_NUM)
8905b261ecSmrg
9005b261ecSmrg/* number of EDID sections to follow */
9105b261ecSmrg#define NO_EDID (DET_TIMING_SECTION + DET_TIMING_LENGTH)
9205b261ecSmrg/* one byte checksum */
9335c4bbdfSmrg#define CHECKSUM (NO_EDID + 1)
9405b261ecSmrg
9505b261ecSmrg#if (CHECKSUM != (EDID1_LEN - 1))
9635c4bbdfSmrg#error "EDID1 length != 128!"
9705b261ecSmrg#endif
9805b261ecSmrg
9905b261ecSmrg#define SECTION(x,y) (Uchar *)(x + y)
10005b261ecSmrg#define GET_ARRAY(y) ((Uchar *)(c + y))
10105b261ecSmrg#define GET(y) *(Uchar *)(c + y)
10205b261ecSmrg
10305b261ecSmrg/* extract information from vendor section */
10405b261ecSmrg#define _PROD_ID(x) x[0] + (x[1] << 8);
10505b261ecSmrg#define PROD_ID _PROD_ID(GET_ARRAY(V_PROD_ID))
10605b261ecSmrg#define _SERIAL_NO(x) x[0] + (x[1] << 8) + (x[2] << 16) + (x[3] << 24)
10705b261ecSmrg#define SERIAL_NO _SERIAL_NO(GET_ARRAY(V_SERIAL))
10805b261ecSmrg#define _YEAR(x) (x & 0xFF) + 1990
10905b261ecSmrg#define YEAR _YEAR(GET(V_YEAR))
11005b261ecSmrg#define WEEK GET(V_WEEK) & 0xFF
11105b261ecSmrg#define _L1(x) ((x[0] & 0x7C) >> 2) + '@'
11205b261ecSmrg#define _L2(x) ((x[0] & 0x03) << 3) + ((x[1] & 0xE0) >> 5) + '@'
11305b261ecSmrg#define _L3(x) (x[1] & 0x1F) + '@';
11405b261ecSmrg#define L1 _L1(GET_ARRAY(V_MANUFACTURER))
11505b261ecSmrg#define L2 _L2(GET_ARRAY(V_MANUFACTURER))
11605b261ecSmrg#define L3 _L3(GET_ARRAY(V_MANUFACTURER))
11705b261ecSmrg
11805b261ecSmrg/* extract information from version section */
11905b261ecSmrg#define VERSION GET(V_VERSION)
12005b261ecSmrg#define REVISION GET(V_REVISION)
12105b261ecSmrg
12205b261ecSmrg/* extract information from display section */
12305b261ecSmrg#define _INPUT_TYPE(x) ((x & 0x80) >> 7)
12405b261ecSmrg#define INPUT_TYPE _INPUT_TYPE(GET(D_INPUT))
12505b261ecSmrg#define _INPUT_VOLTAGE(x) ((x & 0x60) >> 5)
12605b261ecSmrg#define INPUT_VOLTAGE _INPUT_VOLTAGE(GET(D_INPUT))
12705b261ecSmrg#define _SETUP(x) ((x & 0x10) >> 4)
12805b261ecSmrg#define SETUP _SETUP(GET(D_INPUT))
12905b261ecSmrg#define _SYNC(x) (x  & 0x0F)
13005b261ecSmrg#define SYNC _SYNC(GET(D_INPUT))
13105b261ecSmrg#define _DFP(x) (x & 0x01)
13205b261ecSmrg#define DFP _DFP(GET(D_INPUT))
1334642e01fSmrg#define _BPC(x) ((x & 0x70) >> 4)
1344642e01fSmrg#define BPC _BPC(GET(D_INPUT))
1354642e01fSmrg#define _DIGITAL_INTERFACE(x) (x & 0x0F)
1364642e01fSmrg#define DIGITAL_INTERFACE _DIGITAL_INTERFACE(GET(D_INPUT))
1374642e01fSmrg#define _GAMMA(x) (x == 0xff ? 0.0 : ((x + 100.0)/100.0))
13805b261ecSmrg#define GAMMA _GAMMA(GET(D_GAMMA))
13905b261ecSmrg#define HSIZE_MAX GET(D_HSIZE)
14005b261ecSmrg#define VSIZE_MAX GET(D_VSIZE)
14105b261ecSmrg#define _DPMS(x) ((x & 0xE0) >> 5)
14205b261ecSmrg#define DPMS _DPMS(GET(FEAT_S))
14305b261ecSmrg#define _DISPLAY_TYPE(x) ((x & 0x18) >> 3)
14405b261ecSmrg#define DISPLAY_TYPE _DISPLAY_TYPE(GET(FEAT_S))
14505b261ecSmrg#define _MSC(x) (x & 0x7)
14605b261ecSmrg#define MSC _MSC(GET(FEAT_S))
14705b261ecSmrg
14805b261ecSmrg/* color characteristics */
14905b261ecSmrg#define CC_L(x,y) ((x & (0x03 << y)) >> y)
15005b261ecSmrg#define CC_H(x) (x << 2)
15105b261ecSmrg#define I_CC(x,y,z) CC_H(y) | CC_L(x,z)
15205b261ecSmrg#define F_CC(x) ((x)/1024.0)
15305b261ecSmrg#define REDX F_CC(I_CC((GET(D_RG_LOW)),(GET(D_REDX)),6))
15405b261ecSmrg#define REDY F_CC(I_CC((GET(D_RG_LOW)),(GET(D_REDY)),4))
15505b261ecSmrg#define GREENX F_CC(I_CC((GET(D_RG_LOW)),(GET(D_GREENX)),2))
15605b261ecSmrg#define GREENY F_CC(I_CC((GET(D_RG_LOW)),(GET(D_GREENY)),0))
15705b261ecSmrg#define BLUEX F_CC(I_CC((GET(D_BW_LOW)),(GET(D_BLUEX)),6))
15805b261ecSmrg#define BLUEY F_CC(I_CC((GET(D_BW_LOW)),(GET(D_BLUEY)),4))
15905b261ecSmrg#define WHITEX F_CC(I_CC((GET(D_BW_LOW)),(GET(D_WHITEX)),2))
16005b261ecSmrg#define WHITEY F_CC(I_CC((GET(D_BW_LOW)),(GET(D_WHITEY)),0))
16105b261ecSmrg
16205b261ecSmrg/* extract information from standard timing section */
16305b261ecSmrg#define T1 GET(E_T1)
16405b261ecSmrg#define T2 GET(E_T2)
16505b261ecSmrg#define T_MANU GET(E_TMANU)
16605b261ecSmrg
167ed6184dfSmrg/* extract information from established timing section */
16805b261ecSmrg#define _VALID_TIMING(x) !(((x[0] == 0x01) && (x[1] == 0x01)) \
16905b261ecSmrg                        || ((x[0] == 0x00) && (x[1] == 0x00)) \
17005b261ecSmrg                        || ((x[0] == 0x20) && (x[1] == 0x20)) )
17105b261ecSmrg#define VALID_TIMING _VALID_TIMING(c)
17205b261ecSmrg#define _HSIZE1(x) ((x[0] + 31) * 8)
17305b261ecSmrg#define HSIZE1 _HSIZE1(c)
17405b261ecSmrg#define RATIO(x) ((x[1] & 0xC0) >> 6)
17505b261ecSmrg#define RATIO1_1 0
17605b261ecSmrg/* EDID Ver. 1.3 redefined this */
17705b261ecSmrg#define RATIO16_10 RATIO1_1
17805b261ecSmrg#define RATIO4_3 1
17905b261ecSmrg#define RATIO5_4 2
18005b261ecSmrg#define RATIO16_9 3
18105b261ecSmrg#define _VSIZE1(x,y,r) switch(RATIO(x)){ \
18205b261ecSmrg  case RATIO1_1: y =  ((v->version > 1 || v->revision > 2) \
18305b261ecSmrg		       ? (_HSIZE1(x) * 10) / 16 : _HSIZE1(x)); break; \
18405b261ecSmrg  case RATIO4_3: y = _HSIZE1(x) * 3 / 4; break; \
18505b261ecSmrg  case RATIO5_4: y = _HSIZE1(x) * 4 / 5; break; \
18605b261ecSmrg  case RATIO16_9: y = _HSIZE1(x) * 9 / 16; break; \
18705b261ecSmrg  }
18805b261ecSmrg#define VSIZE1(x) _VSIZE1(c,x,v)
18905b261ecSmrg#define _REFRESH_R(x) (x[1] & 0x3F) + 60
19005b261ecSmrg#define REFRESH_R  _REFRESH_R(c)
19105b261ecSmrg#define _ID_LOW(x) x[0]
19205b261ecSmrg#define ID_LOW _ID_LOW(c)
19305b261ecSmrg#define _ID_HIGH(x) (x[1] << 8)
19405b261ecSmrg#define ID_HIGH _ID_HIGH(c)
19505b261ecSmrg#define STD_TIMING_ID (ID_LOW | ID_HIGH)
19605b261ecSmrg#define _NEXT_STD_TIMING(x)  (x = (x + STD_TIMING_INFO_LEN))
19705b261ecSmrg#define NEXT_STD_TIMING _NEXT_STD_TIMING(c)
19805b261ecSmrg
19905b261ecSmrg/* EDID Ver. >= 1.2 */
2004642e01fSmrg/**
2014642e01fSmrg * Returns true if the pointer is the start of a monitor descriptor block
2024642e01fSmrg * instead of a detailed timing descriptor.
2034642e01fSmrg *
2044642e01fSmrg * Checking the reserved pad fields for zeroes fails on some monitors with
2054642e01fSmrg * broken empty ASCII strings.  Only the first two bytes are reliable.
2064642e01fSmrg */
2074642e01fSmrg#define _IS_MONITOR_DESC(x) (x[0] == 0 && x[1] == 0)
20805b261ecSmrg#define IS_MONITOR_DESC _IS_MONITOR_DESC(c)
20905b261ecSmrg#define _PIXEL_CLOCK(x) (x[0] + (x[1] << 8)) * 10000
21005b261ecSmrg#define PIXEL_CLOCK _PIXEL_CLOCK(c)
21105b261ecSmrg#define _H_ACTIVE(x) (x[2] + ((x[4] & 0xF0) << 4))
21205b261ecSmrg#define H_ACTIVE _H_ACTIVE(c)
21305b261ecSmrg#define _H_BLANK(x) (x[3] + ((x[4] & 0x0F) << 8))
21405b261ecSmrg#define H_BLANK _H_BLANK(c)
21505b261ecSmrg#define _V_ACTIVE(x) (x[5] + ((x[7] & 0xF0) << 4))
21605b261ecSmrg#define V_ACTIVE _V_ACTIVE(c)
21705b261ecSmrg#define _V_BLANK(x) (x[6] + ((x[7] & 0x0F) << 8))
21805b261ecSmrg#define V_BLANK _V_BLANK(c)
21905b261ecSmrg#define _H_SYNC_OFF(x) (x[8] + ((x[11] & 0xC0) << 2))
22005b261ecSmrg#define H_SYNC_OFF _H_SYNC_OFF(c)
22105b261ecSmrg#define _H_SYNC_WIDTH(x) (x[9] + ((x[11] & 0x30) << 4))
22205b261ecSmrg#define H_SYNC_WIDTH _H_SYNC_WIDTH(c)
22305b261ecSmrg#define _V_SYNC_OFF(x) ((x[10] >> 4) + ((x[11] & 0x0C) << 2))
22405b261ecSmrg#define V_SYNC_OFF _V_SYNC_OFF(c)
22505b261ecSmrg#define _V_SYNC_WIDTH(x) ((x[10] & 0x0F) + ((x[11] & 0x03) << 4))
22605b261ecSmrg#define V_SYNC_WIDTH _V_SYNC_WIDTH(c)
22705b261ecSmrg#define _H_SIZE(x) (x[12] + ((x[14] & 0xF0) << 4))
22805b261ecSmrg#define H_SIZE _H_SIZE(c)
22905b261ecSmrg#define _V_SIZE(x) (x[13] + ((x[14] & 0x0F) << 8))
23005b261ecSmrg#define V_SIZE _V_SIZE(c)
23105b261ecSmrg#define _H_BORDER(x) (x[15])
23205b261ecSmrg#define H_BORDER _H_BORDER(c)
23305b261ecSmrg#define _V_BORDER(x) (x[16])
23405b261ecSmrg#define V_BORDER _V_BORDER(c)
23505b261ecSmrg#define _INTERLACED(x) ((x[17] & 0x80) >> 7)
23605b261ecSmrg#define INTERLACED _INTERLACED(c)
23705b261ecSmrg#define _STEREO(x) ((x[17] & 0x60) >> 5)
23805b261ecSmrg#define STEREO _STEREO(c)
23905b261ecSmrg#define _STEREO1(x) (x[17] & 0x1)
24005b261ecSmrg#define STEREO1 _STEREO(c)
24105b261ecSmrg#define _SYNC_T(x) ((x[17] & 0x18) >> 3)
24205b261ecSmrg#define SYNC_T _SYNC_T(c)
24305b261ecSmrg#define _MISC(x) ((x[17] & 0x06) >> 1)
24405b261ecSmrg#define MISC _MISC(c)
24505b261ecSmrg
24605b261ecSmrg#define _MONITOR_DESC_TYPE(x) x[3]
24705b261ecSmrg#define MONITOR_DESC_TYPE _MONITOR_DESC_TYPE(c)
24805b261ecSmrg#define SERIAL_NUMBER 0xFF
24905b261ecSmrg#define ASCII_STR 0xFE
25005b261ecSmrg#define MONITOR_RANGES 0xFD
2514642e01fSmrg#define _MIN_V_OFFSET(x) ((!!(x[4] & 0x01)) * 255)
2524642e01fSmrg#define _MAX_V_OFFSET(x) ((!!(x[4] & 0x02)) * 255)
2534642e01fSmrg#define _MIN_H_OFFSET(x) ((!!(x[4] & 0x04)) * 255)
2544642e01fSmrg#define _MAX_H_OFFSET(x) ((!!(x[4] & 0x08)) * 255)
25505b261ecSmrg#define _MIN_V(x) x[5]
2564642e01fSmrg#define MIN_V (_MIN_V(c) + _MIN_V_OFFSET(c))
25705b261ecSmrg#define _MAX_V(x) x[6]
2584642e01fSmrg#define MAX_V (_MAX_V(c) + _MAX_V_OFFSET(c))
25905b261ecSmrg#define _MIN_H(x) x[7]
2604642e01fSmrg#define MIN_H (_MIN_H(c) + _MIN_H_OFFSET(c))
26105b261ecSmrg#define _MAX_H(x) x[8]
2624642e01fSmrg#define MAX_H (_MAX_H(c) + _MAX_H_OFFSET(c))
26305b261ecSmrg#define _MAX_CLOCK(x) x[9]
26435c4bbdfSmrg#define MAX_CLOCK _MAX_CLOCK(c)
2655a7dfde8Smrg#define _DEFAULT_GTF(x) (x[10] == 0x00)
2665a7dfde8Smrg#define DEFAULT_GTF _DEFAULT_GTF(c)
2675a7dfde8Smrg#define _RANGE_LIMITS_ONLY(x) (x[10] == 0x01)
2685a7dfde8Smrg#define RANGE_LIMITS_ONLY _RANGE_LIMITS_ONLY(c)
26905b261ecSmrg#define _HAVE_2ND_GTF(x) (x[10] == 0x02)
27005b261ecSmrg#define HAVE_2ND_GTF _HAVE_2ND_GTF(c)
27105b261ecSmrg#define _F_2ND_GTF(x) (x[12] * 2)
27205b261ecSmrg#define F_2ND_GTF _F_2ND_GTF(c)
27305b261ecSmrg#define _C_2ND_GTF(x) (x[13] / 2)
27405b261ecSmrg#define C_2ND_GTF _C_2ND_GTF(c)
27505b261ecSmrg#define _M_2ND_GTF(x) (x[14] + (x[15] << 8))
27605b261ecSmrg#define M_2ND_GTF _M_2ND_GTF(c)
27705b261ecSmrg#define _K_2ND_GTF(x) (x[16])
27805b261ecSmrg#define K_2ND_GTF _K_2ND_GTF(c)
27905b261ecSmrg#define _J_2ND_GTF(x) (x[17] / 2)
28005b261ecSmrg#define J_2ND_GTF _J_2ND_GTF(c)
2814642e01fSmrg#define _HAVE_CVT(x) (x[10] == 0x04)
2824642e01fSmrg#define HAVE_CVT _HAVE_CVT(c)
2834642e01fSmrg#define _MAX_CLOCK_KHZ(x) (x[12] >> 2)
2844642e01fSmrg#define MAX_CLOCK_KHZ (MAX_CLOCK * 10000) - (_MAX_CLOCK_KHZ(c) * 250)
2854642e01fSmrg#define _MAXWIDTH(x) ((x[13] == 0 ? 0 : x[13] + ((x[12] & 0x03) << 8)) * 8)
2864642e01fSmrg#define MAXWIDTH _MAXWIDTH(c)
2874642e01fSmrg#define _SUPPORTED_ASPECT(x) x[14]
2884642e01fSmrg#define SUPPORTED_ASPECT _SUPPORTED_ASPECT(c)
2894642e01fSmrg#define  SUPPORTED_ASPECT_4_3   0x80
2904642e01fSmrg#define  SUPPORTED_ASPECT_16_9  0x40
2914642e01fSmrg#define  SUPPORTED_ASPECT_16_10 0x20
2924642e01fSmrg#define  SUPPORTED_ASPECT_5_4   0x10
2934642e01fSmrg#define  SUPPORTED_ASPECT_15_9  0x08
2944642e01fSmrg#define _PREFERRED_ASPECT(x) ((x[15] & 0xe0) >> 5)
2954642e01fSmrg#define PREFERRED_ASPECT _PREFERRED_ASPECT(c)
2964642e01fSmrg#define  PREFERRED_ASPECT_4_3   0
2974642e01fSmrg#define  PREFERRED_ASPECT_16_9  1
2984642e01fSmrg#define  PREFERRED_ASPECT_16_10 2
2994642e01fSmrg#define  PREFERRED_ASPECT_5_4   3
3004642e01fSmrg#define  PREFERRED_ASPECT_15_9  4
3014642e01fSmrg#define _SUPPORTED_BLANKING(x) ((x[15] & 0x18) >> 3)
3024642e01fSmrg#define SUPPORTED_BLANKING _SUPPORTED_BLANKING(c)
3034642e01fSmrg#define  CVT_STANDARD 0x01
3044642e01fSmrg#define  CVT_REDUCED  0x02
3054642e01fSmrg#define _SUPPORTED_SCALING(x) ((x[16] & 0xf0) >> 4)
3064642e01fSmrg#define SUPPORTED_SCALING _SUPPORTED_SCALING(c)
3074642e01fSmrg#define  SCALING_HSHRINK  0x08
3084642e01fSmrg#define  SCALING_HSTRETCH 0x04
3094642e01fSmrg#define  SCALING_VSHRINK  0x02
3104642e01fSmrg#define  SCALING_VSTRETCH 0x01
3114642e01fSmrg#define _PREFERRED_REFRESH(x) x[17]
3124642e01fSmrg#define PREFERRED_REFRESH _PREFERRED_REFRESH(c)
3134642e01fSmrg
31405b261ecSmrg#define MONITOR_NAME 0xFC
31505b261ecSmrg#define ADD_COLOR_POINT 0xFB
31605b261ecSmrg#define WHITEX F_CC(I_CC((GET(D_BW_LOW)),(GET(D_WHITEX)),2))
31705b261ecSmrg#define WHITEY F_CC(I_CC((GET(D_BW_LOW)),(GET(D_WHITEY)),0))
31805b261ecSmrg#define _WHITEX_ADD(x,y) F_CC(I_CC(((*(x + y))),(*(x + y + 1)),2))
31905b261ecSmrg#define _WHITEY_ADD(x,y) F_CC(I_CC(((*(x + y))),(*(x + y + 2)),0))
32005b261ecSmrg#define _WHITE_INDEX1(x) x[5]
32105b261ecSmrg#define WHITE_INDEX1 _WHITE_INDEX1(c)
32205b261ecSmrg#define _WHITE_INDEX2(x) x[10]
32305b261ecSmrg#define WHITE_INDEX2 _WHITE_INDEX2(c)
32405b261ecSmrg#define WHITEX1 _WHITEX_ADD(c,6)
32505b261ecSmrg#define WHITEY1 _WHITEY_ADD(c,6)
32605b261ecSmrg#define WHITEX2 _WHITEX_ADD(c,12)
32705b261ecSmrg#define WHITEY2 _WHITEY_ADD(c,12)
32805b261ecSmrg#define _WHITE_GAMMA1(x) _GAMMA(x[9])
32935c4bbdfSmrg#define WHITE_GAMMA1 _WHITE_GAMMA1(c)
33005b261ecSmrg#define _WHITE_GAMMA2(x) _GAMMA(x[14])
33105b261ecSmrg#define WHITE_GAMMA2 _WHITE_GAMMA2(c)
33205b261ecSmrg#define ADD_STD_TIMINGS 0xFA
3334642e01fSmrg#define COLOR_MANAGEMENT_DATA 0xF9
3344642e01fSmrg#define CVT_3BYTE_DATA 0xF8
3354642e01fSmrg#define ADD_EST_TIMINGS 0xF7
33605b261ecSmrg#define ADD_DUMMY 0x10
33705b261ecSmrg
33805b261ecSmrg#define _NEXT_DT_MD_SECTION(x) (x = (x + DET_TIMING_INFO_LEN))
33905b261ecSmrg#define NEXT_DT_MD_SECTION _NEXT_DT_MD_SECTION(c)
34005b261ecSmrg
34135c4bbdfSmrg#endif                          /* _PARSE_EDID_ */
34205b261ecSmrg
34305b261ecSmrg/* input type */
34405b261ecSmrg#define DIGITAL(x) x
34505b261ecSmrg
34605b261ecSmrg/* DFP */
34705b261ecSmrg#define DFP1(x) x
34805b261ecSmrg
34905b261ecSmrg/* input voltage level */
35035c4bbdfSmrg#define V070 0                  /* 0.700V/0.300V */
35135c4bbdfSmrg#define V071 1                  /* 0.714V/0.286V */
35235c4bbdfSmrg#define V100 2                  /* 1.000V/0.400V */
35335c4bbdfSmrg#define V007 3                  /* 0.700V/0.000V */
35405b261ecSmrg
35505b261ecSmrg/* Signal level setup */
35605b261ecSmrg#define SIG_SETUP(x) (x)
35705b261ecSmrg
35805b261ecSmrg/* sync characteristics */
35905b261ecSmrg#define SEP_SYNC(x) (x & 0x08)
36005b261ecSmrg#define COMP_SYNC(x) (x & 0x04)
36105b261ecSmrg#define SYNC_O_GREEN(x) (x & 0x02)
36205b261ecSmrg#define SYNC_SERR(x) (x & 0x01)
36305b261ecSmrg
36405b261ecSmrg/* DPMS features */
36505b261ecSmrg#define DPMS_STANDBY(x) (x & 0x04)
36605b261ecSmrg#define DPMS_SUSPEND(x) (x & 0x02)
36705b261ecSmrg#define DPMS_OFF(x) (x & 0x01)
36805b261ecSmrg
3694642e01fSmrg/* display type, analog */
37005b261ecSmrg#define DISP_MONO 0
37105b261ecSmrg#define DISP_RGB 1
37205b261ecSmrg#define DISP_MULTCOLOR 2
37305b261ecSmrg
3744642e01fSmrg/* display color encodings, digital */
3754642e01fSmrg#define DISP_YCRCB444 0x01
3764642e01fSmrg#define DISP_YCRCB422 0x02
3774642e01fSmrg
37805b261ecSmrg/* Msc stuff EDID Ver > 1.1 */
37905b261ecSmrg#define STD_COLOR_SPACE(x) (x & 0x4)
38005b261ecSmrg#define PREFERRED_TIMING_MODE(x) (x & 0x2)
38105b261ecSmrg#define GFT_SUPPORTED(x) (x & 0x1)
3824642e01fSmrg#define GTF_SUPPORTED(x) (x & 0x1)
3834642e01fSmrg#define CVT_SUPPORTED(x) (x & 0x1)
38405b261ecSmrg
38505b261ecSmrg/* detailed timing misc */
38635c4bbdfSmrg#define IS_INTERLACED(x)  (x)
38735c4bbdfSmrg#define IS_STEREO(x)  (x)
38805b261ecSmrg#define IS_RIGHT_STEREO(x) (x & 0x01)
38905b261ecSmrg#define IS_LEFT_STEREO(x) (x & 0x02)
39005b261ecSmrg#define IS_4WAY_STEREO(x) (x & 0x03)
39105b261ecSmrg#define IS_RIGHT_ON_SYNC(x) IS_RIGHT_STEREO(x)
39205b261ecSmrg#define IS_LEFT_ON_SYNC(x) IS_LEFT_STEREO(x)
39305b261ecSmrg
39405b261ecSmrgtypedef unsigned int Uint;
39505b261ecSmrgtypedef unsigned char Uchar;
39605b261ecSmrg
39705b261ecSmrgstruct vendor {
39835c4bbdfSmrg    char name[4];
39935c4bbdfSmrg    int prod_id;
40035c4bbdfSmrg    Uint serial;
40135c4bbdfSmrg    int week;
40235c4bbdfSmrg    int year;
40305b261ecSmrg};
40405b261ecSmrg
40505b261ecSmrgstruct edid_version {
40635c4bbdfSmrg    int version;
40735c4bbdfSmrg    int revision;
40805b261ecSmrg};
40905b261ecSmrg
41005b261ecSmrgstruct disp_features {
41135c4bbdfSmrg    unsigned int input_type:1;
41235c4bbdfSmrg    unsigned int input_voltage:2;
41335c4bbdfSmrg    unsigned int input_setup:1;
41435c4bbdfSmrg    unsigned int input_sync:5;
41535c4bbdfSmrg    unsigned int input_dfp:1;
41635c4bbdfSmrg    unsigned int input_bpc:3;
41735c4bbdfSmrg    unsigned int input_interface:4;
41835c4bbdfSmrg    /* 15 bit hole */
41935c4bbdfSmrg    int hsize;
42035c4bbdfSmrg    int vsize;
42135c4bbdfSmrg    float gamma;
42235c4bbdfSmrg    unsigned int dpms:3;
42335c4bbdfSmrg    unsigned int display_type:2;
42435c4bbdfSmrg    unsigned int msc:3;
42535c4bbdfSmrg    float redx;
42635c4bbdfSmrg    float redy;
42735c4bbdfSmrg    float greenx;
42835c4bbdfSmrg    float greeny;
42935c4bbdfSmrg    float bluex;
43035c4bbdfSmrg    float bluey;
43135c4bbdfSmrg    float whitex;
43235c4bbdfSmrg    float whitey;
43305b261ecSmrg};
43405b261ecSmrg
43505b261ecSmrgstruct established_timings {
43635c4bbdfSmrg    Uchar t1;
43735c4bbdfSmrg    Uchar t2;
43835c4bbdfSmrg    Uchar t_manu;
43905b261ecSmrg};
44005b261ecSmrg
44105b261ecSmrgstruct std_timings {
44235c4bbdfSmrg    int hsize;
44335c4bbdfSmrg    int vsize;
44435c4bbdfSmrg    int refresh;
44535c4bbdfSmrg    CARD16 id;
44605b261ecSmrg};
44705b261ecSmrg
44805b261ecSmrgstruct detailed_timings {
44935c4bbdfSmrg    int clock;
45035c4bbdfSmrg    int h_active;
45135c4bbdfSmrg    int h_blanking;
45235c4bbdfSmrg    int v_active;
45335c4bbdfSmrg    int v_blanking;
45435c4bbdfSmrg    int h_sync_off;
45535c4bbdfSmrg    int h_sync_width;
45635c4bbdfSmrg    int v_sync_off;
45735c4bbdfSmrg    int v_sync_width;
45835c4bbdfSmrg    int h_size;
45935c4bbdfSmrg    int v_size;
46035c4bbdfSmrg    int h_border;
46135c4bbdfSmrg    int v_border;
46235c4bbdfSmrg    unsigned int interlaced:1;
46335c4bbdfSmrg    unsigned int stereo:2;
46435c4bbdfSmrg    unsigned int sync:2;
46535c4bbdfSmrg    unsigned int misc:2;
46635c4bbdfSmrg    unsigned int stereo_1:1;
46705b261ecSmrg};
46805b261ecSmrg
46905b261ecSmrg#define DT 0
47005b261ecSmrg#define DS_SERIAL 0xFF
47105b261ecSmrg#define DS_ASCII_STR 0xFE
47205b261ecSmrg#define DS_NAME 0xFC
47305b261ecSmrg#define DS_RANGES 0xFD
47405b261ecSmrg#define DS_WHITE_P 0xFB
47505b261ecSmrg#define DS_STD_TIMINGS 0xFA
4764642e01fSmrg#define DS_CMD 0xF9
4774642e01fSmrg#define DS_CVT 0xF8
4784642e01fSmrg#define DS_EST_III 0xF7
47905b261ecSmrg#define DS_DUMMY 0x10
48035c4bbdfSmrg#define DS_UNKOWN 0x100         /* type is an int */
4814642e01fSmrg#define DS_VENDOR 0x101
4824642e01fSmrg#define DS_VENDOR_MAX 0x110
48305b261ecSmrg
4845a7dfde8Smrg/*
4855a7dfde8Smrg * Display range limit Descriptor of EDID version1, reversion 4
4865a7dfde8Smrg */
4875a7dfde8Smrgtypedef enum {
4885a7dfde8Smrg	DR_DEFAULT_GTF,
4895a7dfde8Smrg	DR_LIMITS_ONLY,
4905a7dfde8Smrg	DR_SECONDARY_GTF,
4915a7dfde8Smrg	DR_CVT_SUPPORTED = 4,
4925a7dfde8Smrg} DR_timing_flags;
4935a7dfde8Smrg
49405b261ecSmrgstruct monitor_ranges {
49535c4bbdfSmrg    int min_v;
49635c4bbdfSmrg    int max_v;
49735c4bbdfSmrg    int min_h;
49835c4bbdfSmrg    int max_h;
49935c4bbdfSmrg    int max_clock;              /* in mhz */
50035c4bbdfSmrg    int gtf_2nd_f;
50135c4bbdfSmrg    int gtf_2nd_c;
50235c4bbdfSmrg    int gtf_2nd_m;
50335c4bbdfSmrg    int gtf_2nd_k;
50435c4bbdfSmrg    int gtf_2nd_j;
50535c4bbdfSmrg    int max_clock_khz;
50635c4bbdfSmrg    int maxwidth;               /* in pixels */
50735c4bbdfSmrg    char supported_aspect;
50835c4bbdfSmrg    char preferred_aspect;
50935c4bbdfSmrg    char supported_blanking;
51035c4bbdfSmrg    char supported_scaling;
51135c4bbdfSmrg    int preferred_refresh;      /* in hz */
5125a7dfde8Smrg    DR_timing_flags display_range_timing_flags;
51305b261ecSmrg};
51405b261ecSmrg
51535c4bbdfSmrgstruct whitePoints {
51635c4bbdfSmrg    int index;
51735c4bbdfSmrg    float white_x;
51835c4bbdfSmrg    float white_y;
51935c4bbdfSmrg    float white_gamma;
52005b261ecSmrg};
52105b261ecSmrg
5224642e01fSmrgstruct cvt_timings {
5234642e01fSmrg    int width;
5244642e01fSmrg    int height;
5254642e01fSmrg    int rate;
5264642e01fSmrg    int rates;
5274642e01fSmrg};
5284642e01fSmrg
5294642e01fSmrg/*
5304642e01fSmrg * Be careful when adding new sections; this structure can't grow, it's
5314642e01fSmrg * embedded in the middle of xf86Monitor which is ABI.  Sizes below are
5324642e01fSmrg * in bytes, for ILP32 systems.  If all else fails just copy the section
5334642e01fSmrg * literally like serial and friends.
5344642e01fSmrg */
53505b261ecSmrgstruct detailed_monitor_section {
53635c4bbdfSmrg    int type;
53735c4bbdfSmrg    union {
53835c4bbdfSmrg        struct detailed_timings d_timings;      /* 56 */
53935c4bbdfSmrg        Uchar serial[13];
54035c4bbdfSmrg        Uchar ascii_data[13];
54135c4bbdfSmrg        Uchar name[13];
5425a7dfde8Smrg        struct monitor_ranges ranges;   /* 60 */
54335c4bbdfSmrg        struct std_timings std_t[5];    /* 80 */
54435c4bbdfSmrg        struct whitePoints wp[2];       /* 32 */
54535c4bbdfSmrg        /* color management data */
54635c4bbdfSmrg        struct cvt_timings cvt[4];      /* 64 */
54735c4bbdfSmrg        Uchar est_iii[6];       /* 6 */
54835c4bbdfSmrg    } section;                  /* max: 80 */
54905b261ecSmrg};
55005b261ecSmrg
5514642e01fSmrg/* flags */
5526747b715Smrg#define MONITOR_EDID_COMPLETE_RAWDATA	0x01
5536747b715Smrg/* old, don't use */
5546747b715Smrg#define EDID_COMPLETE_RAWDATA		0x01
5554642e01fSmrg
5566747b715Smrg/*
5576747b715Smrg * For DisplayID devices, only the scrnIndex, flags, and rawData fields
5586747b715Smrg * are meaningful.  For EDID, they all are.
5596747b715Smrg */
56005b261ecSmrgtypedef struct {
56135c4bbdfSmrg    int scrnIndex;
56235c4bbdfSmrg    struct vendor vendor;
56335c4bbdfSmrg    struct edid_version ver;
56435c4bbdfSmrg    struct disp_features features;
56535c4bbdfSmrg    struct established_timings timings1;
56635c4bbdfSmrg    struct std_timings timings2[8];
56735c4bbdfSmrg    struct detailed_monitor_section det_mon[4];
56835c4bbdfSmrg    unsigned long flags;
56935c4bbdfSmrg    int no_sections;
57035c4bbdfSmrg    Uchar *rawData;
57105b261ecSmrg} xf86Monitor, *xf86MonPtr;
57205b261ecSmrg
5736747b715Smrgextern _X_EXPORT xf86MonPtr ConfiguredMonitor;
5746747b715Smrg
5756747b715Smrg#define EXT_TAG 0
5766747b715Smrg#define EXT_REV 1
5776747b715Smrg#define CEA_EXT   0x02
5786747b715Smrg#define VTB_EXT   0x10
5796747b715Smrg#define DI_EXT    0x40
5806747b715Smrg#define LS_EXT    0x50
5816747b715Smrg#define MI_EXT    0x60
5826747b715Smrg
5836747b715Smrg#define CEA_EXT_MIN_DATA_OFFSET 4
5846747b715Smrg#define CEA_EXT_MAX_DATA_OFFSET 127
5856747b715Smrg#define CEA_EXT_DET_TIMING_NUM 6
5866747b715Smrg
5876747b715Smrg#define IEEE_ID_HDMI    0x000C03
5886747b715Smrg#define CEA_AUDIO_BLK   1
5896747b715Smrg#define CEA_VIDEO_BLK   2
5906747b715Smrg#define CEA_VENDOR_BLK  3
5916747b715Smrg#define CEA_SPEAKER_ALLOC_BLK 4
5926747b715Smrg#define CEA_VESA_DTC_BLK 5
5936747b715Smrg#define VENDOR_SUPPORT_AI(x) ((x) >> 7)
5946747b715Smrg#define VENDOR_SUPPORT_DC_48bit(x)  ( ( (x) >> 6) & 0x01)
5956747b715Smrg#define VENDOR_SUPPORT_DC_36bit(x)  ( ( (x) >> 5) & 0x01)
5966747b715Smrg#define VENDOR_SUPPORT_DC_30bit(x)  ( ( (x) >> 4) & 0x01)
5976747b715Smrg#define VENDOR_SUPPORT_DC_Y444(x)   ( ( (x) >> 3) & 0x01)
5986747b715Smrg#define VENDOR_LATENCY_PRESENT(x)     ( (x) >> 7)
5996747b715Smrg#define VENDOR_LATENCY_PRESENT_I(x) ( ( (x) >> 6) & 0x01)
6006747b715Smrg#define HDMI_MAX_TMDS_UNIT   (5000)
6016747b715Smrg
6026747b715Smrgstruct cea_video_block {
60335c4bbdfSmrg    Uchar video_code;
6046747b715Smrg};
6056747b715Smrg
6066747b715Smrgstruct cea_audio_block_descriptor {
60735c4bbdfSmrg    Uchar audio_code[3];
6086747b715Smrg};
6096747b715Smrg
6106747b715Smrgstruct cea_audio_block {
61135c4bbdfSmrg    struct cea_audio_block_descriptor descriptor[10];
6126747b715Smrg};
6136747b715Smrg
6146747b715Smrgstruct cea_vendor_block_hdmi {
61535c4bbdfSmrg    Uchar portB:4;
61635c4bbdfSmrg    Uchar portA:4;
61735c4bbdfSmrg    Uchar portD:4;
61835c4bbdfSmrg    Uchar portC:4;
61935c4bbdfSmrg    Uchar support_flags;
62035c4bbdfSmrg    Uchar max_tmds_clock;
62135c4bbdfSmrg    Uchar latency_present;
62235c4bbdfSmrg    Uchar video_latency;
62335c4bbdfSmrg    Uchar audio_latency;
62435c4bbdfSmrg    Uchar interlaced_video_latency;
62535c4bbdfSmrg    Uchar interlaced_audio_latency;
6266747b715Smrg};
6276747b715Smrg
6286747b715Smrgstruct cea_vendor_block {
62935c4bbdfSmrg    unsigned char ieee_id[3];
63035c4bbdfSmrg    union {
63135c4bbdfSmrg        struct cea_vendor_block_hdmi hdmi;
63235c4bbdfSmrg        /* any other vendor blocks we know about */
63335c4bbdfSmrg    };
6346747b715Smrg};
6356747b715Smrg
63635c4bbdfSmrgstruct cea_speaker_block {
63735c4bbdfSmrg    Uchar FLR:1;
63835c4bbdfSmrg    Uchar LFE:1;
63935c4bbdfSmrg    Uchar FC:1;
64035c4bbdfSmrg    Uchar RLR:1;
64135c4bbdfSmrg    Uchar RC:1;
64235c4bbdfSmrg    Uchar FLRC:1;
64335c4bbdfSmrg    Uchar RLRC:1;
64435c4bbdfSmrg    Uchar FLRW:1;
64535c4bbdfSmrg    Uchar FLRH:1;
64635c4bbdfSmrg    Uchar TC:1;
64735c4bbdfSmrg    Uchar FCH:1;
64835c4bbdfSmrg    Uchar Resv:5;
64935c4bbdfSmrg    Uchar ResvByte;
6506747b715Smrg};
6516747b715Smrg
6526747b715Smrgstruct cea_data_block {
65335c4bbdfSmrg    Uchar len:5;
65435c4bbdfSmrg    Uchar tag:3;
65535c4bbdfSmrg    union {
65635c4bbdfSmrg        struct cea_video_block video;
65735c4bbdfSmrg        struct cea_audio_block audio;
65835c4bbdfSmrg        struct cea_vendor_block vendor;
65935c4bbdfSmrg        struct cea_speaker_block speaker;
66035c4bbdfSmrg    } u;
6616747b715Smrg};
6626747b715Smrg
6636747b715Smrgstruct cea_ext_body {
66435c4bbdfSmrg    Uchar tag;
66535c4bbdfSmrg    Uchar rev;
66635c4bbdfSmrg    Uchar dt_offset;
66735c4bbdfSmrg    Uchar flags;
66835c4bbdfSmrg    struct cea_data_block data_collection;
6696747b715Smrg};
67005b261ecSmrg
67135c4bbdfSmrg#endif                          /* _EDID_H_ */
672