1 /* $NetBSD: sbic.c,v 1.38 2026/08/06 01:23:44 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Van Jacobson of Lawrence Berkeley Laboratory. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 35 */ 36 37 /* 38 * Changes Copyright (c) 1996 Steve Woodford 39 * Original Copyright (c) 1994 Christian E. Hopps 40 * 41 * This code is derived from software contributed to Berkeley by 42 * Van Jacobson of Lawrence Berkeley Laboratory. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by the University of 55 * California, Berkeley and its contributors. 56 * 4. Neither the name of the University nor the names of its contributors 57 * may be used to endorse or promote products derived from this software 58 * without specific prior written permission. 59 * 60 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 61 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 63 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 66 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 67 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 68 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 69 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 70 * SUCH DAMAGE. 71 * 72 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 73 */ 74 75 /* 76 * Steve Woodford (SCW), Apr, 1996 77 * MVME147S WD33C93 Scsi Bus Interface Controller driver, 78 * 79 * Basically a de-loused and tidied up version of the Amiga AMD 33C93 driver. 80 * 81 * The original driver used features which required at least a WD33C93A 82 * chip. The '147 has the original WD33C93 chip (no 'A' suffix). 83 * 84 * This version of the driver is pretty well generic, so should work with 85 * any flavour of WD33C93 chip. 86 */ 87 88 #include <sys/cdefs.h> 89 __KERNEL_RCSID(0, "$NetBSD: sbic.c,v 1.38 2026/08/06 01:23:44 thorpej Exp $"); 90 91 #include "opt_ddb.h" 92 93 #include <sys/param.h> 94 #include <sys/systm.h> 95 #include <sys/device.h> 96 #include <sys/kernel.h> /* For hz */ 97 #include <sys/disklabel.h> 98 #include <sys/buf.h> 99 100 #include <dev/scsipi/scsi_all.h> 101 #include <dev/scsipi/scsipi_all.h> 102 #include <dev/scsipi/scsiconf.h> 103 104 #include <uvm/uvm_extern.h> 105 106 #include <mvme68k/dev/dmavar.h> 107 #include <mvme68k/dev/sbicreg.h> 108 #include <mvme68k/dev/sbicvar.h> 109 110 111 /* 112 * Since I can't find this in any other header files 113 */ 114 #define SCSI_PHASE(reg) (reg&0x07) 115 116 /* 117 * SCSI delays 118 * In u-seconds, primarily for state changes on the SPC. 119 */ 120 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 121 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 122 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 123 124 /* 125 * Convenience macro for waiting for a particular sbic event 126 */ 127 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 128 129 int sbicicmd (struct sbic_softc *, void *, int, void *, int); 130 int sbicgo (struct sbic_softc *, struct scsipi_xfer *); 131 int sbicdmaok (struct sbic_softc *, struct scsipi_xfer *); 132 int sbicwait (sbic_regmap_p, u_char, int , int); 133 int sbiccheckdmap (void *, u_long, u_long); 134 u_char sbicselectbus (struct sbic_softc *); 135 int sbicxfout (sbic_regmap_p, int, void *); 136 int sbicxfin (sbic_regmap_p, int, void *); 137 int sbicfromscsiperiod (struct sbic_softc *, int); 138 int sbictoscsiperiod (struct sbic_softc *, int); 139 int sbicpoll (struct sbic_softc *); 140 int sbicnextstate (struct sbic_softc *, u_char, u_char); 141 int sbicmsgin (struct sbic_softc *); 142 int sbicabort (struct sbic_softc *, const char *); 143 void sbicxfdone (struct sbic_softc *); 144 void sbicerror (struct sbic_softc *, u_char); 145 void sbicreset (struct sbic_softc *); 146 void sbic_scsidone (struct sbic_acb *, int); 147 void sbic_sched (struct sbic_softc *); 148 void sbic_save_ptrs (struct sbic_softc *); 149 void sbic_load_ptrs (struct sbic_softc *); 150 151 /* 152 * Synch xfer parameters, and timing conversions 153 */ 154 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 155 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 156 int sbic_cmd_wait = SBIC_CMD_WAIT; 157 int sbic_data_wait = SBIC_DATA_WAIT; 158 int sbic_init_wait = SBIC_INIT_WAIT; 159 160 /* 161 * was broken before.. now if you want this you get it for all drives 162 * on sbic controllers. 163 */ 164 u_char sbic_inhibit_sync[8]; 165 int sbic_enable_reselect = 1; /* Allow Disconnect / Reselect */ 166 int sbic_no_dma = 0; /* Use PIO transfers instead of DMA */ 167 int sbic_parallel_operations = 1; /* Allow command queues */ 168 169 /* 170 * Some useful stuff for debugging purposes 171 */ 172 #ifdef DEBUG 173 int sbicdma_ops = 0; /* total DMA operations */ 174 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 175 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 176 int sbicdma_saves = 0; 177 178 #define QPRINTF(a) if (sbic_debug > 1) printf a 179 180 int sbic_debug = 0; /* Debug all chip related things */ 181 int sync_debug = 0; /* Debug all Synchronous Scsi related things */ 182 int reselect_debug = 0; /* Debug all reselection related things */ 183 int data_pointer_debug = 0; /* Debug Data Pointer related things */ 184 185 void sbictimeout(struct sbic_softc *dev); 186 187 #else 188 #define QPRINTF(a) /* */ 189 #endif 190 191 192 /* 193 * default minphys routine for sbic based controllers 194 */ 195 void 196 sbic_minphys(struct buf *bp) 197 { 198 /* 199 * No max transfer at this level. 200 */ 201 minphys(bp); 202 } 203 204 205 /* 206 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 207 */ 208 void 209 sbic_save_ptrs(struct sbic_softc *dev) 210 { 211 sbic_regmap_p regs; 212 struct sbic_acb *acb; 213 int count, asr, s; 214 215 /* 216 * Only need to save pointers if DMA was active... 217 */ 218 if (dev->sc_cur == NULL || (dev->sc_flags & SBICF_INDMA) == 0) 219 return; 220 221 regs = dev->sc_sbicp; 222 223 s = splbio(); 224 225 /* 226 * Wait until WD chip is idle 227 */ 228 do { 229 GET_SBIC_asr(regs, asr); 230 if (asr & SBIC_ASR_DBR) { 231 printf("%s: asr %02x canceled!\n", __func__, asr); 232 splx(s); 233 return; 234 } 235 } while(asr & (SBIC_ASR_BSY|SBIC_ASR_CIP)); 236 237 238 /* 239 * Save important state. 240 * must be done before dmastop 241 */ 242 acb = dev->sc_nexus; 243 acb->sc_dmacmd = dev->sc_dmacmd; 244 245 /* 246 * Fetch the residual count 247 */ 248 SBIC_TC_GET(regs, count); 249 250 /* 251 * Shut down DMA 252 */ 253 dev->sc_dmastop(dev); 254 255 /* 256 * No longer in DMA 257 */ 258 dev->sc_flags &= ~SBICF_INDMA; 259 260 /* 261 * Ensure the WD chip is back in polled I/O mode, with nothing to 262 * transfer. 263 */ 264 SBIC_TC_PUT(regs, 0); 265 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 266 267 /* 268 * Update current count... 269 */ 270 acb->sc_tcnt = count; 271 272 /* 273 * Work out how many bytes were actually transferred 274 */ 275 count = dev->sc_tcnt - count; 276 dev->sc_tcnt = acb->sc_tcnt; 277 278 /* 279 * Fixup partial xfers 280 */ 281 acb->sc_kv.dc_addr += count; 282 acb->sc_kv.dc_count -= count; 283 acb->sc_pa.dc_addr += count; 284 acb->sc_pa.dc_count -= count >> 1; 285 286 #ifdef DEBUG 287 if (data_pointer_debug) 288 printf("save at (%p,%x):%x\n", 289 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 290 sbicdma_saves++; 291 #endif 292 293 splx(s); 294 } 295 296 297 /* 298 * DOES NOT RESTART DMA!!! 299 */ 300 void 301 sbic_load_ptrs(struct sbic_softc *dev) 302 { 303 struct sbic_acb *acb = dev->sc_nexus; 304 int s; 305 306 if (acb->sc_kv.dc_count == 0) { 307 /* 308 * No data to xfer 309 */ 310 return; 311 } 312 313 s = splbio(); 314 315 /* 316 * Reset the Scatter-Gather chain 317 */ 318 dev->sc_last = dev->sc_cur = &acb->sc_pa; 319 320 /* 321 * Restore the Transfer Count and DMA specific data 322 */ 323 dev->sc_tcnt = acb->sc_tcnt; 324 dev->sc_dmacmd = acb->sc_dmacmd; 325 326 #ifdef DEBUG 327 sbicdma_ops++; 328 #endif 329 330 /* 331 * Need to fixup new segment? 332 */ 333 if (dev->sc_tcnt == 0) { 334 /* 335 * sc_tcnt == 0 implies end of segment 336 */ 337 char *vaddr, *paddr; 338 int count; 339 340 /* 341 * do kvm to pa mappings 342 */ 343 vaddr = acb->sc_kv.dc_addr; 344 paddr = acb->sc_pa.dc_addr = (char *)kvtop((void *)vaddr); 345 346 for (count = (PAGE_SIZE - ((int)vaddr & PGOFSET)); 347 count < acb->sc_kv.dc_count && 348 (char *)kvtop((void *)(vaddr + count + 4)) == 349 paddr + count + 4; 350 count += PAGE_SIZE) 351 ; /* Do nothing */ 352 353 /* 354 * If it's all contiguous... 355 */ 356 if (count > acb->sc_kv.dc_count) { 357 count = acb->sc_kv.dc_count; 358 #ifdef DEBUG 359 sbicdma_hits++; 360 #endif 361 } 362 #ifdef DEBUG 363 else 364 sbicdma_misses++; 365 #endif 366 367 acb->sc_tcnt = count; 368 acb->sc_pa.dc_count = count >> 1; 369 370 #ifdef DEBUG 371 if (data_pointer_debug) 372 printf("DMA recalc:kv(%p,%x)pa(%p,%lx)\n", 373 acb->sc_kv.dc_addr, 374 acb->sc_kv.dc_count, 375 acb->sc_pa.dc_addr, 376 acb->sc_tcnt); 377 #endif 378 379 } 380 381 splx(s); 382 } 383 384 /* 385 * used by specific sbic controller 386 * 387 * it appears that the higher level code does nothing with LUN's 388 * so I will too. I could plug it in, however so could they 389 * in scsi_scsipi_cmd(). 390 */ 391 void 392 sbic_scsi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 393 void *arg) 394 { 395 struct scsipi_xfer *xs; 396 struct scsipi_periph *periph; 397 struct sbic_softc *dev = device_private(chan->chan_adapter->adapt_dev); 398 struct sbic_acb *acb; 399 int flags, s; 400 401 switch (req) { 402 case ADAPTER_REQ_RUN_XFER: 403 xs = arg; 404 periph = xs->xs_periph; 405 flags = xs->xs_control; 406 407 if (flags & XS_CTL_DATA_UIO) 408 panic("sbic: scsi data uio requested"); 409 410 if (dev->sc_nexus && (flags & XS_CTL_POLL)) 411 panic("sbic_scsicmd: busy"); 412 413 s = splbio(); 414 415 if ((acb = dev->free_list.tqh_first) != NULL) 416 TAILQ_REMOVE(&dev->free_list, acb, chain); 417 418 splx(s); 419 420 if (acb == NULL) { 421 #ifdef DEBUG 422 printf("%s: unable to queue request for target %d\n", 423 __func__, periph->periph_target); 424 #ifdef DDB 425 Debugger(); 426 #endif 427 #endif 428 xs->error = XS_RESOURCE_SHORTAGE; 429 scsipi_done(xs); 430 return; 431 } 432 433 if (flags & XS_CTL_DATA_IN) 434 acb->flags = ACB_ACTIVE | ACB_DATAIN; 435 else 436 acb->flags = ACB_ACTIVE; 437 438 acb->xs = xs; 439 acb->clen = xs->cmdlen; 440 acb->sc_kv.dc_addr = xs->data; 441 acb->sc_kv.dc_count = xs->datalen; 442 acb->pa_addr = xs->data ? 443 (char *)kvtop((void *)xs->data) : 0; 444 memcpy(&acb->cmd, xs->cmd, xs->cmdlen); 445 446 if (flags & XS_CTL_POLL) { 447 /* 448 * This has major side effects 449 * -- it locks up the machine 450 */ 451 int stat; 452 453 s = splbio(); 454 455 dev->sc_flags |= SBICF_ICMD; 456 457 do { 458 /* 459 * If we already had a nexus, while away 460 * the time until idle... 461 * This is likely only to happen if 462 * a reselection occurs between 463 * here and our earlier check for 464 * ICMD && sc_nexus(which would 465 * have resulted in a panic() had it been true). 466 */ 467 while (dev->sc_nexus) 468 sbicpoll(dev); 469 470 /* 471 * Fix up the new nexus 472 */ 473 dev->sc_nexus = acb; 474 dev->sc_xs = xs; 475 dev->target = periph->periph_target; 476 dev->lun = periph->periph_lun; 477 478 stat = sbicicmd(dev, &acb->cmd, acb->clen, 479 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 480 481 } while (dev->sc_nexus != acb); 482 483 sbic_scsidone(acb, stat); 484 485 splx(s); 486 487 return; 488 } 489 490 s = splbio(); 491 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 492 493 /* 494 * If nothing is active, try to start it now. 495 */ 496 if (dev->sc_nexus == NULL) 497 sbic_sched(dev); 498 499 splx(s); 500 501 return; 502 503 case ADAPTER_REQ_GROW_RESOURCES: 504 /* XXX Not supported. */ 505 return; 506 507 case ADAPTER_REQ_SET_XFER_MODE: 508 /* XXX Not supported. */ 509 return; 510 } 511 } 512 513 /* 514 * attempt to start the next available command 515 */ 516 void 517 sbic_sched(struct sbic_softc *dev) 518 { 519 struct scsipi_xfer *xs; 520 struct scsipi_periph *periph = NULL; /* Gag the compiler */ 521 struct sbic_acb *acb; 522 int flags, stat; 523 524 /* 525 * XXXSCW 526 * I'll keep this test here, even though I can't see any obvious way 527 * in which sbic_sched() could be called with sc_nexus non NULL 528 */ 529 if (dev->sc_nexus) 530 return; /* a command is current active */ 531 532 /* 533 * Loop through the ready list looking for work to do... 534 */ 535 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 536 int i, j; 537 538 periph = acb->xs->xs_periph; 539 i = periph->periph_target; 540 j = 1 << periph->periph_lun; 541 542 /* 543 * We've found a potential command, but is the target/lun busy? 544 */ 545 if ((dev->sc_tinfo[i].lubusy & j) == 0) { 546 /* 547 * Nope, it's not busy, so we can use it. 548 */ 549 dev->sc_tinfo[i].lubusy |= j; 550 TAILQ_REMOVE(&dev->ready_list, acb, chain); 551 dev->sc_nexus = acb; 552 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 553 break; 554 } 555 } 556 557 if (acb == NULL) { 558 QPRINTF(("sbicsched: no work\n")); 559 return; /* did not find an available command */ 560 } 561 562 #ifdef DEBUG 563 if (data_pointer_debug > 1) 564 printf("sbic_sched(%d,%d)\n", periph->periph_target, 565 periph->periph_lun); 566 #endif 567 568 dev->sc_xs = xs = acb->xs; 569 flags = xs->xs_control; 570 571 if (flags & XS_CTL_RESET) 572 sbicreset(dev); 573 574 dev->sc_stat[0] = -1; 575 dev->target = periph->periph_target; 576 dev->lun = periph->periph_lun; 577 578 if (flags & XS_CTL_POLL || (!sbic_parallel_operations && 579 (sbicdmaok(dev, xs) == 0)) ) 580 stat = sbicicmd(dev, &acb->cmd, acb->clen, 581 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 582 else if (sbicgo(dev, xs) == 0 && xs->error != XS_SELTIMEOUT) 583 return; 584 else 585 stat = dev->sc_stat[0]; 586 587 sbic_scsidone(acb, stat); 588 } 589 590 void 591 sbic_scsidone(struct sbic_acb *acb, int stat) 592 { 593 struct scsipi_xfer *xs = acb->xs; 594 struct scsipi_periph *periph = xs->xs_periph; 595 struct sbic_softc *dev = 596 device_private(periph->periph_channel->chan_adapter->adapt_dev); 597 int dosched = 0; 598 599 #ifdef DIAGNOSTIC 600 if (acb == NULL || xs == NULL) { 601 printf("sbic_scsidone -- (%d,%d) no scsipi_xfer\n", 602 dev->target, dev->lun); 603 #ifdef DDB 604 Debugger(); 605 #endif 606 return; 607 } 608 #endif 609 610 611 #ifdef DEBUG 612 if (data_pointer_debug > 1) 613 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", 614 periph->periph_target, periph->periph_lun, 615 dev->target, dev->lun, stat); 616 617 if (xs->xs_periph->periph_target == dev->sc_channel.chan_id) 618 panic("target == hostid"); 619 #endif 620 621 xs->status = stat; 622 xs->resid = 0; /* XXXX */ 623 if (xs->error == XS_NOERROR) { 624 if (stat == SCSI_CHECK || stat == SCSI_BUSY) 625 xs->error = XS_BUSY; 626 } 627 628 629 /* 630 * Remove the ACB from whatever queue it's on. We have to do a bit of 631 * a hack to figure out which queue it's on. Note that it is *not* 632 * necessary to cdr down the ready queue, but we must cdr down the 633 * nexus queue and see if it's there, so we can mark the unit as no 634 * longer busy. This code is sickening, but it works. 635 */ 636 if (acb == dev->sc_nexus ) { 637 638 dev->sc_nexus = NULL; 639 dev->sc_xs = NULL; 640 641 dev->sc_tinfo[periph->periph_target].lubusy &= 642 ~(1 << periph->periph_lun); 643 644 if (dev->ready_list.tqh_first) 645 dosched = 1; /* start next command */ 646 647 } else if (dev->ready_list.tqh_last == &acb->chain.tqe_next) { 648 649 TAILQ_REMOVE(&dev->ready_list, acb, chain); 650 651 } else { 652 653 struct sbic_acb *a; 654 655 for (a = dev->nexus_list.tqh_first; a != NULL; 656 a = a->chain.tqe_next) { 657 if (a == acb) { 658 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 659 dev->sc_tinfo[periph->periph_target].lubusy &= 660 ~(1 << periph->periph_lun); 661 break; 662 } 663 } 664 665 if (a != NULL) 666 ; 667 else if ( acb->chain.tqe_next ) { 668 TAILQ_REMOVE(&dev->ready_list, acb, chain); 669 } else { 670 printf("%s: can't find matching acb\n", 671 device_xname(dev->sc_dev)); 672 #ifdef DDB 673 Debugger(); 674 #endif 675 } 676 } 677 678 /* 679 * Put it on the free list. 680 */ 681 acb->flags = ACB_FREE; 682 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 683 684 dev->sc_tinfo[periph->periph_target].cmds++; 685 686 scsipi_done(xs); 687 688 if (dosched) 689 sbic_sched(dev); 690 } 691 692 int 693 sbicdmaok(struct sbic_softc *dev, struct scsipi_xfer *xs) 694 { 695 696 if (sbic_no_dma || xs->datalen == 0 || 697 xs->datalen & 0x03 || (int)xs->data & 0x03) 698 return 0; 699 700 /* 701 * controller supports DMA to any addresses? 702 */ 703 if ((dev->sc_flags & SBICF_BADDMA) == 0) 704 return 1; 705 706 /* 707 * this address is ok for DMA? 708 */ 709 if (sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0) 710 return 1; 711 712 return 0; 713 } 714 715 int 716 sbicwait(sbic_regmap_p regs, u_char until, int timeo, int line) 717 { 718 u_char val; 719 720 if (timeo == 0) 721 timeo = 1000000; /* some large value.. */ 722 723 GET_SBIC_asr(regs, val); 724 725 while ((val & until) == 0) { 726 727 if (timeo-- == 0) { 728 int csr; 729 GET_SBIC_csr(regs, csr); 730 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", 731 line, val, csr); 732 #if defined(DDB) && defined(DEBUG) 733 Debugger(); 734 #endif 735 return val; /* Maybe I should abort */ 736 break; 737 } 738 739 DELAY(1); 740 GET_SBIC_asr(regs, val); 741 } 742 743 return val; 744 } 745 746 int 747 sbicabort(struct sbic_softc *dev, const char *where) 748 { 749 sbic_regmap_p regs = dev->sc_sbicp; 750 u_char csr, asr; 751 752 GET_SBIC_asr(regs, asr); 753 GET_SBIC_csr(regs, csr); 754 755 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 756 device_xname(dev->sc_dev), where, csr, asr); 757 758 /* 759 * Clean up chip itself 760 */ 761 if (dev->sc_flags & SBICF_SELECTED) { 762 763 while (asr & SBIC_ASR_DBR) { 764 /* 765 * sbic is jammed w/data. need to clear it 766 * But we don't know what direction it needs to go 767 */ 768 GET_SBIC_data(regs, asr); 769 printf("%s: abort %s: clearing data buffer 0x%02x\n", 770 device_xname(dev->sc_dev), where, asr); 771 GET_SBIC_asr(regs, asr); 772 if (asr & SBIC_ASR_DBR) 773 /* Not the read direction, then */ 774 SET_SBIC_data(regs, asr); 775 GET_SBIC_asr(regs, asr); 776 } 777 778 WAIT_CIP(regs); 779 780 printf("%s: sbicabort - sending ABORT command\n", 781 device_xname(dev->sc_dev)); 782 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 783 WAIT_CIP(regs); 784 785 GET_SBIC_asr(regs, asr); 786 787 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 788 /* 789 * ok, get more drastic.. 790 */ 791 printf("%s: sbicabort - asr %x, trying to reset\n", 792 device_xname(dev->sc_dev), asr); 793 sbicreset(dev); 794 dev->sc_flags &= ~SBICF_SELECTED; 795 return SBIC_STATE_ERROR; 796 } 797 798 printf("%s: sbicabort - sending DISC command\n", 799 device_xname(dev->sc_dev)); 800 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 801 802 do { 803 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 804 GET_SBIC_asr(regs, asr); 805 GET_SBIC_csr (regs, csr); 806 QPRINTF(("csr: 0x%02x, asr: 0x%02x\n", csr, asr)); 807 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 808 (csr != SBIC_CSR_CMD_INVALID)); 809 810 /* 811 * lets just hope it worked.. 812 */ 813 dev->sc_flags &= ~SBICF_SELECTED; 814 } 815 816 return SBIC_STATE_ERROR; 817 } 818 819 820 /* 821 * Initialize driver-private structures 822 */ 823 void 824 sbicinit(struct sbic_softc *dev) 825 { 826 u_int i; 827 828 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 829 830 struct sbic_acb *acb; 831 832 TAILQ_INIT(&dev->ready_list); 833 TAILQ_INIT(&dev->nexus_list); 834 TAILQ_INIT(&dev->free_list); 835 callout_init(&dev->sc_timo_ch, 0); 836 837 dev->sc_nexus = NULL; 838 dev->sc_xs = NULL; 839 840 acb = dev->sc_acb; 841 memset(acb, 0, sizeof(dev->sc_acb)); 842 843 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 844 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 845 acb++; 846 } 847 848 memset(dev->sc_tinfo, 0, sizeof(dev->sc_tinfo)); 849 850 #ifdef DEBUG 851 /* 852 * make sure timeout is really not needed 853 */ 854 callout_reset(&dev->sc_timo_ch, 30 * hz, 855 (void *)sbictimeout, dev); 856 #endif 857 858 } else 859 panic("sbic: reinitializing driver!"); 860 861 dev->sc_flags |= SBICF_ALIVE; 862 dev->sc_flags &= ~SBICF_SELECTED; 863 864 /* 865 * initialize inhibit array 866 * Never enable Sync, since it just doesn't work on mvme147 :( 867 */ 868 for (i = 0; i < 8; ++i) 869 sbic_inhibit_sync[i] = 1; 870 871 sbicreset(dev); 872 } 873 874 void 875 sbicreset(struct sbic_softc *dev) 876 { 877 sbic_regmap_p regs = dev->sc_sbicp; 878 u_int my_id, s; 879 u_char csr; 880 881 s = splbio(); 882 883 my_id = dev->sc_channel.chan_id & SBIC_ID_MASK; 884 885 if (dev->sc_clkfreq < 110) 886 my_id |= SBIC_ID_FS_8_10; 887 else if (dev->sc_clkfreq < 160) 888 my_id |= SBIC_ID_FS_12_15; 889 else if (dev->sc_clkfreq < 210) 890 my_id |= SBIC_ID_FS_16_20; 891 892 SET_SBIC_myid(regs, my_id); 893 894 /* 895 * Reset the chip 896 */ 897 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 898 DELAY(25); 899 900 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 901 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 902 __USE(csr); 903 904 /* 905 * Set up various chip parameters 906 */ 907 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 908 909 /* 910 * don't allow Selection (SBIC_RID_ES) 911 * until we can handle target mode!! 912 */ 913 SET_SBIC_rselid(regs, SBIC_RID_ER); 914 915 /* 916 * Asynchronous for now 917 */ 918 SET_SBIC_syn(regs, 0); 919 920 /* 921 * Anything else was zeroed by reset 922 */ 923 splx(s); 924 925 dev->sc_flags &= ~SBICF_SELECTED; 926 } 927 928 void 929 sbicerror(struct sbic_softc *dev, u_char csr) 930 { 931 struct scsipi_xfer *xs = dev->sc_xs; 932 933 #ifdef DIAGNOSTIC 934 if (xs == NULL) 935 panic("sbicerror: dev->sc_xs == NULL"); 936 #endif 937 938 if ( xs->xs_control & XS_CTL_SILENT ) 939 return; 940 941 printf("%s: csr == 0x%02x\n", device_xname(dev->sc_dev), csr); 942 } 943 944 /* 945 * select the bus, return when selected or error. 946 * 947 * Returns the current CSR following selection and optionally MSG out phase. 948 * i.e. the returned CSR *should* indicate CMD phase... 949 * If the return value is 0, some error happened. 950 */ 951 u_char 952 sbicselectbus(struct sbic_softc *dev) 953 { 954 sbic_regmap_p regs = dev->sc_sbicp; 955 u_char target = dev->target, lun = dev->lun, asr, csr, id; 956 957 /* 958 * if we're already selected, return (XXXX panic maybe?) 959 */ 960 if (dev->sc_flags & SBICF_SELECTED) 961 return 0; 962 963 QPRINTF(("sbicselectbus %d: ", target)); 964 965 /* 966 * issue select 967 */ 968 SET_SBIC_selid(regs, target); 969 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250, dev->sc_clkfreq)); 970 971 GET_SBIC_asr(regs, asr); 972 973 if (asr & (SBIC_ASR_INT|SBIC_ASR_BSY)) { 974 /* 975 * This means we got ourselves reselected upon 976 */ 977 QPRINTF(("WD busy (reselect?)\n")); 978 return 0; 979 } 980 981 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 982 983 /* 984 * wait for select (merged from separate function may need 985 * cleanup) 986 */ 987 WAIT_CIP(regs); 988 989 do { 990 991 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 992 993 if (asr & SBIC_ASR_LCI) { 994 QPRINTF(("late LCI: asr %02x\n", asr)); 995 return 0; 996 } 997 998 /* 999 * Clear interrupt 1000 */ 1001 GET_SBIC_csr (regs, csr); 1002 1003 QPRINTF(("%02x ", csr)); 1004 1005 /* 1006 * Reselected from under our feet? 1007 */ 1008 if (csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 1009 QPRINTF(("got reselected, asr %02x\n", asr)); 1010 /* 1011 * We need to handle this now so we don't lock up later 1012 */ 1013 sbicnextstate(dev, csr, asr); 1014 1015 return 0; 1016 } 1017 1018 /* 1019 * Whoops! 1020 */ 1021 if (csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 1022 panic("sbicselectbus: target issued select!"); 1023 return 0; 1024 } 1025 1026 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) && 1027 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && 1028 csr != SBIC_CSR_SEL_TIMEO); 1029 1030 /* 1031 * Anyone at home? 1032 */ 1033 if (csr == SBIC_CSR_SEL_TIMEO) { 1034 dev->sc_xs->error = XS_SELTIMEOUT; 1035 QPRINTF(("Selection Timeout\n")); 1036 return 0; 1037 } 1038 1039 QPRINTF(("Selection Complete\n")); 1040 1041 /* 1042 * Assume we're now selected 1043 */ 1044 GET_SBIC_selid(regs, id); 1045 dev->target = id; 1046 dev->lun = lun; 1047 dev->sc_flags |= SBICF_SELECTED; 1048 1049 /* 1050 * Enable (or not) reselection 1051 * XXXSCW This is probably not necessary since we don't use use the 1052 * Select-and-Xfer-with-ATN command to initiate a selection... 1053 */ 1054 if (!sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1055 SET_SBIC_rselid (regs, 0); 1056 else 1057 SET_SBIC_rselid (regs, SBIC_RID_ER); 1058 1059 /* 1060 * We only really need to do anything when the target goes to MSG out 1061 * If the device ignored ATN, it's probably old and brain-dead, 1062 * but we'll try to support it anyhow. 1063 * If it doesn't support message out, it definitely doesn't 1064 * support synchronous transfers, so no point in even asking... 1065 */ 1066 if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) { 1067 /* 1068 * Send identify message (SCSI-2 requires an identify msg) 1069 */ 1070 if (sbic_inhibit_sync[id] && 1071 dev->sc_sync[id].state == SYNC_START) { 1072 /* 1073 * Handle drives that don't want to be asked 1074 * whether to go sync at all. 1075 */ 1076 dev->sc_sync[id].offset = 0; 1077 dev->sc_sync[id].period = sbic_min_period; 1078 dev->sc_sync[id].state = SYNC_DONE; 1079 } 1080 1081 /* 1082 * Do we need to negotiate Synchronous Xfers for this target? 1083 */ 1084 if (dev->sc_sync[id].state != SYNC_START) { 1085 /* 1086 * Nope, we've already negotiated. 1087 * Now see if we should allow the target to 1088 * disconnect/reselect... 1089 */ 1090 if (dev->sc_xs->xs_control & XS_CTL_POLL || 1091 dev->sc_flags & SBICF_ICMD || 1092 !sbic_enable_reselect) 1093 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1094 else 1095 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1096 1097 } else { 1098 /* 1099 * try to initiate a sync transfer. 1100 * So compose the sync message we're going 1101 * to send to the target 1102 */ 1103 #ifdef DEBUG 1104 if (sync_debug) 1105 printf("\nSending sync request " 1106 "to target %d ... ", id); 1107 #endif 1108 /* 1109 * setup scsi message sync message request 1110 */ 1111 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1112 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1113 dev->sc_msg[2] = 3; 1114 dev->sc_msg[3] = MSG_SYNC_REQ; 1115 dev->sc_msg[4] = sbictoscsiperiod(dev, sbic_min_period); 1116 dev->sc_msg[5] = sbic_max_offset; 1117 1118 sbicxfout(regs, 6, dev->sc_msg); 1119 1120 dev->sc_sync[id].state = SYNC_SENT; 1121 #ifdef DEBUG 1122 if (sync_debug) 1123 printf ("sent\n"); 1124 #endif 1125 } 1126 1127 /* 1128 * There's one interrupt still to come: the change to 1129 * CMD phase... 1130 */ 1131 SBIC_WAIT(regs, SBIC_ASR_INT , 0); 1132 GET_SBIC_csr(regs, csr); 1133 } 1134 1135 /* 1136 * set sync or async 1137 */ 1138 if (dev->sc_sync[target].state == SYNC_DONE) { 1139 #ifdef DEBUG 1140 if (sync_debug) 1141 printf("select(%d): sync reg = 0x%02x\n", target, 1142 SBIC_SYN(dev->sc_sync[target].offset, 1143 dev->sc_sync[target].period)); 1144 #endif 1145 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[target].offset, 1146 dev->sc_sync[target].period)); 1147 } else { 1148 #ifdef DEBUG 1149 if (sync_debug) 1150 printf("select(%d): sync reg = 0x%02x\n", target, 1151 SBIC_SYN(0,sbic_min_period)); 1152 #endif 1153 SET_SBIC_syn(regs, SBIC_SYN(0, sbic_min_period)); 1154 } 1155 1156 return csr; 1157 } 1158 1159 /* 1160 * Information Transfer *to* a Scsi Target. 1161 * 1162 * Note: Don't expect there to be an interrupt immediately after all 1163 * the data is transferred out. The WD spec sheet says that the Transfer- 1164 * Info command for non-MSG_IN phases only completes when the target 1165 * next asserts 'REQ'. That is, when the SCSI bus changes to a new state. 1166 * 1167 * This can have a nasty effect on commands which take a relatively long 1168 * time to complete, for example a START/STOP unit command may remain in 1169 * CMD phase until the disk has spun up. Only then will the target change 1170 * to STATUS phase. This is really only a problem for immediate commands 1171 * since we don't allow disconnection for them (yet). 1172 */ 1173 int 1174 sbicxfout(sbic_regmap_p regs, int len, void *bp) 1175 { 1176 int wait = sbic_data_wait; 1177 u_char asr, *buf = bp; 1178 1179 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1180 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1181 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1182 1183 /* 1184 * sigh.. WD-PROTO strikes again.. sending the command in one go 1185 * causes the chip to lock up if talking to certain (misbehaving?) 1186 * targets. Anyway, this procedure should work for all targets, but 1187 * it's slightly slower due to the overhead 1188 */ 1189 WAIT_CIP (regs); 1190 1191 SBIC_TC_PUT (regs, 0); 1192 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1193 SBIC_TC_PUT (regs, (unsigned)len); 1194 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1195 1196 /* 1197 * Loop for each byte transferred 1198 */ 1199 do { 1200 1201 GET_SBIC_asr(regs, asr); 1202 1203 if (asr & SBIC_ASR_DBR) { 1204 if (len) { 1205 SET_SBIC_data (regs, *buf); 1206 buf++; 1207 len--; 1208 } else { 1209 SET_SBIC_data (regs, 0); 1210 } 1211 wait = sbic_data_wait; 1212 } 1213 1214 } while (len && (asr & SBIC_ASR_INT) == 0 && wait-- > 0); 1215 1216 #ifdef DEBUG 1217 QPRINTF(("sbicxfout done: %d bytes remaining (wait:%d)\n", len, wait)); 1218 #endif 1219 1220 /* 1221 * Normally, an interrupt will be pending when this routing returns. 1222 */ 1223 return len; 1224 } 1225 1226 /* 1227 * Information Transfer *from* a Scsi Target 1228 * returns # bytes left to read 1229 */ 1230 int 1231 sbicxfin(sbic_regmap_p regs, int len, void *bp) 1232 { 1233 int wait = sbic_data_wait; 1234 u_char *buf = bp; 1235 u_char asr; 1236 #ifdef DEBUG 1237 u_char *obp = bp; 1238 #endif 1239 1240 WAIT_CIP(regs); 1241 1242 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1243 SBIC_TC_PUT(regs, (unsigned int)len); 1244 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1245 1246 /* 1247 * Loop for each byte transferred 1248 */ 1249 do { 1250 1251 GET_SBIC_asr(regs, asr); 1252 1253 if (asr & SBIC_ASR_DBR) { 1254 if (len) { 1255 GET_SBIC_data (regs, *buf); 1256 buf++; 1257 len--; 1258 } else { 1259 u_char foo; 1260 GET_SBIC_data (regs, foo); 1261 __USE(foo); 1262 } 1263 wait = sbic_data_wait; 1264 } 1265 1266 } while ((asr & SBIC_ASR_INT) == 0 && wait-- > 0); 1267 1268 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1269 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1270 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1271 1272 SBIC_TC_PUT (regs, 0); 1273 1274 /* 1275 * this leaves with one csr to be read 1276 */ 1277 return len; 1278 } 1279 1280 /* 1281 * SCSI 'immediate' command: issue a command to some SCSI device 1282 * and get back an 'immediate' response (i.e., do programmed xfer 1283 * to get the response data). 'cbuf' is a buffer containing a scsi 1284 * command of length clen bytes. 'buf' is a buffer of length 'len' 1285 * bytes for data. The transfer direction is determined by the device 1286 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1287 * command must supply no data. 1288 * 1289 * Note that although this routine looks like it can handle disconnect/ 1290 * reselect, the fact is that it can't. There is still some work to be 1291 * done to clean this lot up. 1292 */ 1293 int 1294 sbicicmd(struct sbic_softc *dev, void *cbuf, int clen, void *buf, int len) 1295 { 1296 sbic_regmap_p regs = dev->sc_sbicp; 1297 struct sbic_acb *acb = dev->sc_nexus; 1298 u_char csr, asr; 1299 int still_busy = SBIC_STATE_RUNNING; 1300 1301 /* 1302 * Make sure pointers are OK 1303 */ 1304 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1305 dev->sc_tcnt = acb->sc_tcnt = 0; 1306 1307 acb->sc_dmacmd = 0; 1308 acb->sc_pa.dc_count = 0; /* No DMA */ 1309 acb->sc_kv.dc_addr = buf; 1310 acb->sc_kv.dc_count = len; 1311 1312 #ifdef DEBUG 1313 if (data_pointer_debug > 1) 1314 printf("sbicicmd(%d,%d):%d\n", 1315 dev->target, dev->lun, acb->sc_kv.dc_count); 1316 #endif 1317 1318 /* 1319 * set the sbic into non-DMA mode 1320 */ 1321 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1322 1323 dev->sc_stat[0] = 0xff; 1324 dev->sc_msg[0] = 0xff; 1325 1326 /* 1327 * We're stealing the SCSI bus 1328 */ 1329 dev->sc_flags |= SBICF_ICMD; 1330 1331 do { 1332 GET_SBIC_asr(regs, asr); 1333 1334 /* 1335 * select the SCSI bus (it's an error if bus isn't free) 1336 */ 1337 if ((dev->sc_flags & SBICF_SELECTED) == 0 && 1338 still_busy != SBIC_STATE_DISCONNECT) { 1339 if ((csr = sbicselectbus(dev)) == 0) { 1340 dev->sc_flags &= ~SBICF_ICMD; 1341 return -1; 1342 } 1343 } else if ((asr & (SBIC_ASR_BSY | SBIC_ASR_INT)) == 1344 SBIC_ASR_INT) 1345 GET_SBIC_csr(regs, csr); 1346 else 1347 csr = 0; 1348 1349 if (csr) { 1350 1351 QPRINTF((">ASR:0x%02x CSR:0x%02x< ", asr, csr)); 1352 1353 switch (csr) { 1354 1355 case SBIC_CSR_S_XFERRED: 1356 case SBIC_CSR_DISC: 1357 case SBIC_CSR_DISC_1: 1358 { 1359 u_char phase; 1360 1361 dev->sc_flags &= ~SBICF_SELECTED; 1362 GET_SBIC_cmd_phase(regs, phase); 1363 1364 if (phase == 0x60) { 1365 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1366 still_busy = SBIC_STATE_DONE; /* done */ 1367 } else { 1368 #ifdef DEBUG 1369 if (reselect_debug > 1) 1370 printf("sbicicmd: " 1371 "handling disconnect\n"); 1372 #endif 1373 still_busy = SBIC_STATE_DISCONNECT; 1374 } 1375 break; 1376 } 1377 1378 case SBIC_CSR_XFERRED | CMD_PHASE: 1379 case SBIC_CSR_MIS | CMD_PHASE: 1380 case SBIC_CSR_MIS_1 | CMD_PHASE: 1381 case SBIC_CSR_MIS_2 | CMD_PHASE: 1382 1383 if (sbicxfout(regs, clen, cbuf)) 1384 still_busy = sbicabort(dev, 1385 "icmd sending cmd"); 1386 break; 1387 1388 case SBIC_CSR_XFERRED | STATUS_PHASE: 1389 case SBIC_CSR_MIS | STATUS_PHASE: 1390 case SBIC_CSR_MIS_1 | STATUS_PHASE: 1391 case SBIC_CSR_MIS_2 | STATUS_PHASE: 1392 1393 /* 1394 * The sbic does the status/cmd-complete 1395 * reading ok, so do this with its 1396 * hi-level commands. 1397 */ 1398 #ifdef DEBUG 1399 if (sbic_debug) 1400 printf("SBICICMD status phase " 1401 "(bsy=%d)\n", still_busy); 1402 #endif 1403 SET_SBIC_cmd_phase(regs, 0x46); 1404 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1405 break; 1406 1407 default: 1408 still_busy = sbicnextstate(dev, csr, asr); 1409 break; 1410 } 1411 1412 /* 1413 * make sure the last command was taken, 1414 * ie. we're not hunting after an ignored command.. 1415 */ 1416 GET_SBIC_asr(regs, asr); 1417 1418 /* 1419 * tapes may take a loooong time.. 1420 */ 1421 while (asr & SBIC_ASR_BSY) { 1422 1423 if (asr & SBIC_ASR_DBR) { 1424 int i; 1425 1426 printf("sbicicmd: " 1427 "Waiting while sbic is jammed, " 1428 "CSR:%02x,ASR:%02x\n", csr, asr); 1429 #ifdef DDB 1430 Debugger(); 1431 #endif 1432 /* 1433 * SBIC is jammed 1434 * DUNNO which direction 1435 * Try old direction 1436 */ 1437 GET_SBIC_data(regs, i); 1438 GET_SBIC_asr(regs, asr); 1439 1440 if (asr & SBIC_ASR_DBR) 1441 /* Wants us to write */ 1442 SET_SBIC_data(regs, i); 1443 } 1444 1445 GET_SBIC_asr(regs, asr); 1446 } 1447 } 1448 1449 /* 1450 * wait for last command to complete 1451 */ 1452 if (asr & SBIC_ASR_LCI) { 1453 printf("sbicicmd: last command ignored\n"); 1454 } else if (still_busy >= SBIC_STATE_RUNNING) /* Bsy */ 1455 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1456 1457 /* 1458 * do it again 1459 */ 1460 } while (still_busy >= SBIC_STATE_RUNNING && dev->sc_stat[0] == 0xff); 1461 1462 /* 1463 * Sometimes we need to do an extra read of the CSR 1464 */ 1465 GET_SBIC_csr(regs, csr); 1466 1467 #ifdef DEBUG 1468 if (data_pointer_debug > 1) 1469 printf("sbicicmd done(%d,%d):%d =%d=\n", dev->target, dev->lun, 1470 acb->sc_kv.dc_count, dev->sc_stat[0]); 1471 #endif 1472 1473 dev->sc_flags &= ~SBICF_ICMD; 1474 1475 return dev->sc_stat[0]; 1476 } 1477 1478 /* 1479 * Finish SCSI xfer command: After the completion interrupt from 1480 * a read/write operation, sequence through the final phases in 1481 * programmed i/o. This routine is a lot like sbicicmd except we 1482 * skip (and don't allow) the select, cmd out and data in/out phases. 1483 */ 1484 void 1485 sbicxfdone(struct sbic_softc *dev) 1486 { 1487 sbic_regmap_p regs = dev->sc_sbicp; 1488 u_char phase, csr; 1489 int s; 1490 1491 QPRINTF(("{")); 1492 s = splbio(); 1493 1494 /* 1495 * have the sbic complete on its own 1496 */ 1497 SBIC_TC_PUT(regs, 0); 1498 SET_SBIC_cmd_phase(regs, 0x46); 1499 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1500 1501 do { 1502 1503 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1504 GET_SBIC_csr(regs, csr); 1505 QPRINTF(("%02x:", csr)); 1506 1507 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 1508 (csr != SBIC_CSR_S_XFERRED)); 1509 1510 dev->sc_flags &= ~SBICF_SELECTED; 1511 1512 GET_SBIC_cmd_phase (regs, phase); 1513 QPRINTF(("}%02x", phase)); 1514 1515 if (phase == 0x60) 1516 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1517 else 1518 sbicerror(dev, csr); 1519 1520 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1521 1522 splx(s); 1523 } 1524 1525 /* 1526 * No DMA chains 1527 */ 1528 int 1529 sbicgo(struct sbic_softc *dev, struct scsipi_xfer *xs) 1530 { 1531 struct sbic_acb *acb = dev->sc_nexus; 1532 sbic_regmap_p regs = dev->sc_sbicp; 1533 int i, dmaflags, count, usedma; 1534 u_char csr, asr, *addr; 1535 1536 dev->target = xs->xs_periph->periph_target; 1537 dev->lun = xs->xs_periph->periph_lun; 1538 1539 usedma = sbicdmaok(dev, xs); 1540 1541 #ifdef DEBUG 1542 if (data_pointer_debug > 1) 1543 printf("sbicgo(%d,%d): usedma=%d\n", 1544 dev->target, dev->lun, usedma); 1545 #endif 1546 1547 /* 1548 * select the SCSI bus (it's an error if bus isn't free) 1549 */ 1550 if ((csr = sbicselectbus(dev)) == 0) 1551 return 0; /* Not done: needs to be rescheduled */ 1552 1553 dev->sc_stat[0] = 0xff; 1554 1555 /* 1556 * Calculate DMA chains now 1557 */ 1558 if (acb->flags & ACB_DATAIN) 1559 dmaflags = DMAGO_READ; 1560 else 1561 dmaflags = 0; 1562 1563 addr = acb->sc_kv.dc_addr; 1564 count = acb->sc_kv.dc_count; 1565 1566 if (count && ((char *)kvtop((void *)addr) != acb->sc_pa.dc_addr)) { 1567 printf("sbic: DMA buffer mapping changed %p->%x\n", 1568 acb->sc_pa.dc_addr, kvtop((void *)addr)); 1569 #ifdef DDB 1570 Debugger(); 1571 #endif 1572 } 1573 1574 #ifdef DEBUG 1575 ++sbicdma_ops; /* count total DMA operations */ 1576 #endif 1577 1578 /* 1579 * Allocate the DMA chain 1580 * Mark end of segment... 1581 */ 1582 acb->sc_tcnt = dev->sc_tcnt = 0; 1583 acb->sc_pa.dc_count = 0; 1584 1585 sbic_load_ptrs(dev); 1586 1587 /* 1588 * Enable interrupts but don't do any DMA 1589 * enintr() also enables interrupts for the sbic 1590 */ 1591 dev->sc_enintr(dev); 1592 1593 if (usedma) { 1594 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1595 acb->sc_pa.dc_count, dmaflags); 1596 #ifdef DEBUG 1597 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1598 #endif 1599 } else 1600 dev->sc_dmacmd = 0; /* Don't use DMA */ 1601 1602 acb->sc_dmacmd = dev->sc_dmacmd; 1603 1604 #ifdef DEBUG 1605 if (data_pointer_debug > 1) { 1606 printf("sbicgo dmago:%d(%p:%lx) dmacmd=0x%02x\n", dev->target, 1607 dev->sc_cur->dc_addr, 1608 dev->sc_tcnt, 1609 dev->sc_dmacmd); 1610 } 1611 #endif 1612 1613 /* 1614 * Lets cycle a while then let the interrupt handler take over. 1615 */ 1616 GET_SBIC_asr(regs, asr); 1617 1618 do { 1619 1620 QPRINTF(("go ")); 1621 1622 /* 1623 * Handle the new phase 1624 */ 1625 i = sbicnextstate(dev, csr, asr); 1626 #if 0 1627 WAIT_CIP(regs); 1628 #endif 1629 if (i == SBIC_STATE_RUNNING) { 1630 GET_SBIC_asr(regs, asr); 1631 1632 if (asr & SBIC_ASR_LCI) 1633 printf("sbicgo: LCI asr:%02x csr:%02x\n", 1634 asr, csr); 1635 1636 if (asr & SBIC_ASR_INT) 1637 GET_SBIC_csr(regs, csr); 1638 } 1639 1640 } while (i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1641 1642 if (i == SBIC_STATE_DONE) { 1643 if (dev->sc_stat[0] == 0xff) 1644 #if 0 1645 printf("sbicgo: done & stat = 0xff\n"); 1646 #else 1647 ; 1648 #endif 1649 else 1650 return 1; /* Did we really finish that fast? */ 1651 } 1652 1653 return 0; 1654 } 1655 1656 1657 int 1658 sbicintr(struct sbic_softc *dev) 1659 { 1660 sbic_regmap_p regs = dev->sc_sbicp; 1661 u_char asr, csr; 1662 int i; 1663 1664 /* 1665 * pending interrupt? 1666 */ 1667 GET_SBIC_asr (regs, asr); 1668 if ((asr & SBIC_ASR_INT) == 0) 1669 return 0; 1670 1671 GET_SBIC_csr(regs, csr); 1672 1673 do { 1674 1675 QPRINTF(("intr[0x%x]", csr)); 1676 1677 i = sbicnextstate(dev, csr, asr); 1678 #if 0 1679 WAIT_CIP(regs); 1680 #endif 1681 if (i == SBIC_STATE_RUNNING) { 1682 GET_SBIC_asr(regs, asr); 1683 1684 if (asr & SBIC_ASR_LCI) 1685 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1686 1687 if (asr & SBIC_ASR_INT) 1688 GET_SBIC_csr(regs, csr); 1689 } 1690 1691 } while (i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1692 1693 QPRINTF(("intr done. state=%d, asr=0x%02x\n", i, asr)); 1694 1695 return 1; 1696 } 1697 1698 /* 1699 * Run commands and wait for disconnect. 1700 * This is only ever called when a command is in progress, when we 1701 * want to busy wait for it to finish. 1702 */ 1703 int 1704 sbicpoll(struct sbic_softc *dev) 1705 { 1706 sbic_regmap_p regs = dev->sc_sbicp; 1707 u_char asr, csr = SBIC_CSR_RESET; /* XXX: Quell un-init warning */ 1708 int i; 1709 1710 /* 1711 * Wait for the next interrupt 1712 */ 1713 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1714 1715 do { 1716 GET_SBIC_asr (regs, asr); 1717 1718 if (asr & SBIC_ASR_INT) 1719 GET_SBIC_csr(regs, csr); 1720 1721 QPRINTF(("poll[0x%x]", csr)); 1722 1723 /* 1724 * Handle it 1725 */ 1726 i = sbicnextstate(dev, csr, asr); 1727 1728 WAIT_CIP(regs); 1729 GET_SBIC_asr(regs, asr); 1730 1731 /* 1732 * tapes may take a loooong time.. 1733 */ 1734 while (asr & SBIC_ASR_BSY) { 1735 u_char z = 0; 1736 1737 if (asr & SBIC_ASR_DBR) { 1738 printf("sbipoll: Waiting while sbic is jammed," 1739 " CSR:%02x,ASR:%02x\n", csr, asr); 1740 #ifdef DDB 1741 Debugger(); 1742 #endif 1743 /* 1744 * SBIC is jammed 1745 * DUNNO which direction 1746 * Try old direction 1747 */ 1748 GET_SBIC_data(regs, z); 1749 GET_SBIC_asr(regs, asr); 1750 1751 if (asr & SBIC_ASR_DBR) /* Wants us to write */ 1752 SET_SBIC_data(regs, z); 1753 } 1754 1755 GET_SBIC_asr(regs, asr); 1756 } 1757 1758 if (asr & SBIC_ASR_LCI) 1759 printf("sbicpoll: LCI asr:%02x csr:%02x\n", asr,csr); 1760 else if (i == SBIC_STATE_RUNNING) /* BSY */ 1761 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1762 1763 } while (i == SBIC_STATE_RUNNING); 1764 1765 return 1; 1766 } 1767 1768 /* 1769 * Handle a single msgin 1770 */ 1771 int 1772 sbicmsgin(struct sbic_softc *dev) 1773 { 1774 sbic_regmap_p regs = dev->sc_sbicp; 1775 int recvlen = 1; 1776 u_char asr, csr, *tmpaddr, *msgaddr; 1777 1778 tmpaddr = msgaddr = dev->sc_msg; 1779 1780 tmpaddr[0] = 0xff; 1781 tmpaddr[1] = 0xff; 1782 1783 GET_SBIC_asr(regs, asr); 1784 1785 #ifdef DEBUG 1786 if (reselect_debug > 1) 1787 printf("sbicmsgin asr=%02x\n", asr); 1788 #endif 1789 1790 GET_SBIC_selid (regs, csr); 1791 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1792 1793 SBIC_TC_PUT(regs, 0); 1794 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1795 1796 do { 1797 while (recvlen--) { 1798 1799 /* 1800 * Fetch the next byte of the message 1801 */ 1802 RECV_BYTE(regs, *tmpaddr); 1803 1804 /* 1805 * get the command completion interrupt, or we 1806 * can't send a new command (LCI) 1807 */ 1808 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1809 GET_SBIC_csr(regs, csr); 1810 1811 #ifdef DEBUG 1812 if (reselect_debug > 1) 1813 printf("sbicmsgin: got %02x csr %02x\n", 1814 *tmpaddr, csr); 1815 #endif 1816 1817 tmpaddr++; 1818 1819 if (recvlen) { 1820 /* 1821 * Clear ACK, and wait for the interrupt 1822 * for the next byte 1823 */ 1824 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1825 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1826 GET_SBIC_csr(regs, csr); 1827 } 1828 } 1829 1830 if (msgaddr[0] == 0xff) { 1831 printf("sbicmsgin: sbic swallowed our message\n"); 1832 break; 1833 } 1834 1835 #ifdef DEBUG 1836 if (sync_debug) { 1837 GET_SBIC_asr(regs, asr); 1838 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", 1839 csr, asr, msgaddr[0]); 1840 } 1841 #endif 1842 /* 1843 * test whether this is a reply to our sync 1844 * request 1845 */ 1846 if (MSG_ISIDENTIFY(msgaddr[0])) { 1847 1848 /* 1849 * Got IFFY msg -- ack it 1850 */ 1851 QPRINTF(("IFFY")); 1852 1853 } else if (msgaddr[0] == MSG_REJECT && 1854 dev->sc_sync[dev->target].state == SYNC_SENT) { 1855 1856 /* 1857 * Target probably rejected our Sync negotiation. 1858 */ 1859 QPRINTF(("REJECT of SYN")); 1860 1861 #ifdef DEBUG 1862 if (sync_debug) 1863 printf("target %d rejected sync, going async\n", 1864 dev->target); 1865 #endif 1866 1867 dev->sc_sync[dev->target].period = sbic_min_period; 1868 dev->sc_sync[dev->target].offset = 0; 1869 dev->sc_sync[dev->target].state = SYNC_DONE; 1870 SET_SBIC_syn(regs, 1871 SBIC_SYN(dev->sc_sync[dev->target].offset, 1872 dev->sc_sync[dev->target].period)); 1873 1874 } else if (msgaddr[0] == MSG_REJECT) { 1875 1876 /* 1877 * we'll never REJECt a REJECT message.. 1878 */ 1879 QPRINTF(("REJECT")); 1880 1881 } else if (msgaddr[0] == MSG_SAVE_DATA_PTR) { 1882 1883 /* 1884 * don't reject this either. 1885 */ 1886 QPRINTF(("MSG_SAVE_DATA_PTR")); 1887 1888 } else if (msgaddr[0] == MSG_RESTORE_PTR) { 1889 1890 /* 1891 * don't reject this either. 1892 */ 1893 QPRINTF(("MSG_RESTORE_PTR")); 1894 1895 } else if (msgaddr[0] == MSG_DISCONNECT) { 1896 1897 /* 1898 * Target is disconnecting... 1899 */ 1900 QPRINTF(("DISCONNECT")); 1901 1902 #ifdef DEBUG 1903 if (reselect_debug > 1 && msgaddr[0] == MSG_DISCONNECT) 1904 printf("sbicmsgin: got disconnect msg %s\n", 1905 (dev->sc_flags & SBICF_ICMD) ? 1906 "rejecting" : ""); 1907 #endif 1908 1909 if (dev->sc_flags & SBICF_ICMD) { 1910 /* 1911 * We're in immediate mode. Prevent disconnects. 1912 * prepare to reject the message, NACK 1913 */ 1914 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1915 WAIT_CIP(regs); 1916 } 1917 1918 } else if (msgaddr[0] == MSG_CMD_COMPLETE) { 1919 1920 /* 1921 * !! KLUDGE ALERT !! quite a few drives don't seem to 1922 * really like the current way of sending the 1923 * sync-handshake together with the ident-message, and 1924 * they react by sending command-complete and 1925 * disconnecting right after returning the valid sync 1926 * handshake. So, all I can do is reselect the drive, 1927 * and hope it won't disconnect again. I don't think 1928 * this is valid behavior, but I can't help fixing a 1929 * problem that apparently exists. 1930 * 1931 * Note: we should not get here on `normal' command 1932 * completion, as that condition is handled by the 1933 * high-level sel&xfer resume command used to walk 1934 * thru status/cc-phase. 1935 */ 1936 QPRINTF(("CMD_COMPLETE")); 1937 1938 #ifdef DEBUG 1939 if (sync_debug) 1940 printf("GOT MSG %d! target %d acting weird.." 1941 " waiting for disconnect...\n", 1942 msgaddr[0], dev->target); 1943 #endif 1944 1945 /* 1946 * Check to see if sbic is handling this 1947 */ 1948 GET_SBIC_asr(regs, asr); 1949 1950 /* 1951 * XXXSCW: I'm not convinced of this, 1952 * we haven't negated ACK yet... 1953 */ 1954 if (asr & SBIC_ASR_BSY) 1955 return SBIC_STATE_RUNNING; 1956 1957 /* 1958 * Let's try this: Assume it works and set status to 00 1959 */ 1960 dev->sc_stat[0] = 0; 1961 1962 } else if (msgaddr[0] == MSG_EXT_MESSAGE && 1963 tmpaddr == &(msgaddr[1])) { 1964 1965 /* 1966 * Target is sending us an extended message. 1967 * We'll assume it's the response to our Sync. 1968 * negotiation. 1969 */ 1970 QPRINTF(("ExtMSG\n")); 1971 1972 /* 1973 * Read in whole extended message. 1974 * First, negate ACK to accept 1975 * the MSG_EXT_MESSAGE byte... 1976 */ 1977 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1978 1979 /* 1980 * Wait for the interrupt for the next byte (length) 1981 */ 1982 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1983 GET_SBIC_csr(regs, csr); 1984 1985 #ifdef DEBUG 1986 QPRINTF(("CLR ACK csr %02x\n", csr)); 1987 #endif 1988 1989 /* 1990 * Read the length byte 1991 */ 1992 RECV_BYTE(regs, *tmpaddr); 1993 1994 /* 1995 * Wait for command completion IRQ 1996 */ 1997 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1998 GET_SBIC_csr(regs, csr); 1999 2000 /* 2001 * Reload the loop counter 2002 */ 2003 recvlen = *tmpaddr++; 2004 2005 QPRINTF(("Recving ext msg, csr %02x len %02x\n", 2006 csr, recvlen)); 2007 2008 } else if (msgaddr[0] == MSG_EXT_MESSAGE && 2009 msgaddr[1] == 3 && 2010 msgaddr[2] == MSG_SYNC_REQ ) { 2011 2012 /* 2013 * We've received the complete Extended Message Sync. 2014 * Request... 2015 */ 2016 QPRINTF(("SYN")); 2017 2018 /* 2019 * Compute the required Transfer Period for 2020 * the WD chip... 2021 */ 2022 dev->sc_sync[dev->target].period = 2023 sbicfromscsiperiod(dev, msgaddr[3]); 2024 dev->sc_sync[dev->target].offset = msgaddr[4]; 2025 dev->sc_sync[dev->target].state = SYNC_DONE; 2026 2027 /* 2028 * Put the WD chip in synchronous mode 2029 */ 2030 SET_SBIC_syn(regs, 2031 SBIC_SYN(dev->sc_sync[dev->target].offset, 2032 dev->sc_sync[dev->target].period)); 2033 #ifdef DEBUG 2034 if (sync_debug) 2035 printf("msgin(%d): sync reg = 0x%02x\n", 2036 dev->target, 2037 SBIC_SYN(dev->sc_sync[dev->target].offset, 2038 dev->sc_sync[dev->target].period)); 2039 #endif 2040 2041 printf("%s: target %d now synchronous, " 2042 "period=%dns, offset=%d.\n", 2043 device_xname(dev->sc_dev), dev->target, 2044 msgaddr[3] * 4, msgaddr[4]); 2045 2046 } else { 2047 2048 /* 2049 * We don't support whatever this message is... 2050 */ 2051 #ifdef DEBUG 2052 if (sbic_debug || sync_debug) 2053 printf("sbicmsgin: Rejecting message 0x%02x\n", 2054 msgaddr[0]); 2055 #endif 2056 2057 /* 2058 * prepare to reject the message, NACK 2059 */ 2060 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2061 WAIT_CIP(regs); 2062 } 2063 2064 /* 2065 * Negate ACK to complete the transfer 2066 */ 2067 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2068 2069 /* 2070 * Wait for the interrupt for the next byte, or phase change. 2071 * Only read the CSR if we have more data to transfer. 2072 * XXXSCW: We should really verify that we're still in 2073 * MSG IN phase before blindly going back around this loop, 2074 * but that would mean we read the CSR... <sigh> 2075 */ 2076 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2077 if (recvlen > 0) 2078 GET_SBIC_csr(regs, csr); 2079 2080 } while (recvlen > 0); 2081 2082 /* 2083 * Should still have one CSR to read 2084 */ 2085 return SBIC_STATE_RUNNING; 2086 } 2087 2088 2089 /* 2090 * sbicnextstate() 2091 * return: 2092 * SBIC_STATE_DONE == done 2093 * SBIC_STATE_RUNNING == working 2094 * SBIC_STATE_DISCONNECT == disconnected 2095 * SBIC_STATE_ERROR == error 2096 */ 2097 int 2098 sbicnextstate(struct sbic_softc *dev, u_char csr, u_char asr) 2099 { 2100 sbic_regmap_p regs = dev->sc_sbicp; 2101 struct sbic_acb *acb = dev->sc_nexus; 2102 2103 QPRINTF(("next[%02x,%02x]: ",asr,csr)); 2104 2105 switch (csr) { 2106 2107 case SBIC_CSR_XFERRED | CMD_PHASE: 2108 case SBIC_CSR_MIS | CMD_PHASE: 2109 case SBIC_CSR_MIS_1 | CMD_PHASE: 2110 case SBIC_CSR_MIS_2 | CMD_PHASE: 2111 if ( sbicxfout(regs, acb->clen, &acb->cmd) ) 2112 goto abort; 2113 break; 2114 2115 case SBIC_CSR_XFERRED | STATUS_PHASE: 2116 case SBIC_CSR_MIS | STATUS_PHASE: 2117 case SBIC_CSR_MIS_1 | STATUS_PHASE: 2118 case SBIC_CSR_MIS_2 | STATUS_PHASE: 2119 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2120 2121 /* 2122 * this should be the normal i/o completion case. 2123 * get the status & cmd complete msg then let the 2124 * device driver look at what happened. 2125 */ 2126 sbicxfdone(dev); 2127 2128 #ifdef DEBUG 2129 dev->sc_dmatimo = 0; 2130 if (data_pointer_debug > 1) 2131 printf("next dmastop: %d(%p:%lx)\n", 2132 dev->target, 2133 dev->sc_cur->dc_addr, 2134 dev->sc_tcnt); 2135 #endif 2136 /* 2137 * Stop the DMA chip 2138 */ 2139 dev->sc_dmastop(dev); 2140 2141 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2142 2143 /* 2144 * Indicate to the upper layers that the command is done 2145 */ 2146 sbic_scsidone(acb, dev->sc_stat[0]); 2147 2148 return SBIC_STATE_DONE; 2149 2150 case SBIC_CSR_XFERRED | DATA_OUT_PHASE: 2151 case SBIC_CSR_XFERRED | DATA_IN_PHASE: 2152 case SBIC_CSR_MIS | DATA_OUT_PHASE: 2153 case SBIC_CSR_MIS | DATA_IN_PHASE: 2154 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: 2155 case SBIC_CSR_MIS_1 | DATA_IN_PHASE: 2156 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: 2157 case SBIC_CSR_MIS_2 | DATA_IN_PHASE: 2158 /* 2159 * Verify that we expected to transfer data... 2160 */ 2161 if (acb->sc_kv.dc_count <= 0) { 2162 printf("next: DATA phase with xfer count == %d, " 2163 "asr:0x%02x csr:0x%02x\n", 2164 acb->sc_kv.dc_count, asr, csr); 2165 goto abort; 2166 } 2167 2168 /* 2169 * Should we transfer using PIO or DMA ? 2170 */ 2171 if (dev->sc_xs->xs_control & XS_CTL_POLL || 2172 dev->sc_flags & SBICF_ICMD || 2173 acb->sc_dmacmd == 0 ) { 2174 2175 /* 2176 * Do PIO transfer 2177 */ 2178 int i; 2179 2180 #ifdef DEBUG 2181 if (data_pointer_debug > 1) 2182 printf("next PIO: %d(%p:%x)\n", dev->target, 2183 acb->sc_kv.dc_addr, 2184 acb->sc_kv.dc_count); 2185 #endif 2186 2187 if (SBIC_PHASE(csr) == DATA_IN_PHASE) 2188 /* 2189 * data in 2190 */ 2191 i = sbicxfin(regs, acb->sc_kv.dc_count, 2192 acb->sc_kv.dc_addr); 2193 else 2194 /* 2195 * data out 2196 */ 2197 i = sbicxfout(regs, acb->sc_kv.dc_count, 2198 acb->sc_kv.dc_addr); 2199 2200 acb->sc_kv.dc_addr += (acb->sc_kv.dc_count - i); 2201 acb->sc_kv.dc_count = i; 2202 2203 /* 2204 * Update current count... 2205 */ 2206 acb->sc_tcnt = dev->sc_tcnt = i; 2207 2208 dev->sc_flags &= ~SBICF_INDMA; 2209 2210 } else { 2211 2212 /* 2213 * Do DMA transfer 2214 * set next DMA addr and dec count 2215 */ 2216 sbic_save_ptrs(dev); 2217 sbic_load_ptrs(dev); 2218 2219 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2220 SBIC_MACHINE_DMA_MODE); 2221 2222 #ifdef DEBUG 2223 dev->sc_dmatimo = 1; 2224 if (data_pointer_debug > 1) 2225 printf("next DMA: %d(%p:%lx)\n", dev->target, 2226 dev->sc_cur->dc_addr, 2227 dev->sc_tcnt); 2228 #endif 2229 /* 2230 * Start the DMA chip going 2231 */ 2232 dev->sc_tcnt = dev->sc_dmanext(dev); 2233 2234 /* 2235 * Tell the WD chip how much to transfer 2236 * this time around 2237 */ 2238 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2239 2240 /* 2241 * Start the transfer 2242 */ 2243 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2244 2245 /* 2246 * Indicate that we're in DMA mode 2247 */ 2248 dev->sc_flags |= SBICF_INDMA; 2249 } 2250 break; 2251 2252 case SBIC_CSR_XFERRED | MESG_IN_PHASE: 2253 case SBIC_CSR_MIS | MESG_IN_PHASE: 2254 case SBIC_CSR_MIS_1 | MESG_IN_PHASE: 2255 case SBIC_CSR_MIS_2 | MESG_IN_PHASE: 2256 sbic_save_ptrs(dev); 2257 2258 /* 2259 * Handle a single message in... 2260 */ 2261 return sbicmsgin(dev); 2262 2263 case SBIC_CSR_MSGIN_W_ACK: 2264 /* 2265 * We should never see this since it's handled in 'sbicmsgin()' 2266 * but just for the sake of paranoia... 2267 */ 2268 /* Dunno what I'm ACKing */ 2269 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2270 printf("Acking unknown msgin CSR:%02x",csr); 2271 break; 2272 2273 case SBIC_CSR_XFERRED | MESG_OUT_PHASE: 2274 case SBIC_CSR_MIS | MESG_OUT_PHASE: 2275 case SBIC_CSR_MIS_1 | MESG_OUT_PHASE: 2276 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE: 2277 /* 2278 * We only ever handle a message out phase here for sending a 2279 * REJECT message. 2280 */ 2281 sbic_save_ptrs(dev); 2282 2283 #ifdef DEBUG 2284 if (sync_debug) 2285 printf("sending REJECT msg to last msg.\n"); 2286 #endif 2287 2288 SEND_BYTE(regs, MSG_REJECT); 2289 WAIT_CIP(regs); 2290 break; 2291 2292 case SBIC_CSR_DISC: 2293 case SBIC_CSR_DISC_1: 2294 /* 2295 * Try to schedule another target 2296 */ 2297 sbic_save_ptrs(dev); 2298 2299 dev->sc_flags &= ~SBICF_SELECTED; 2300 2301 #ifdef DEBUG 2302 if (reselect_debug > 1) 2303 printf("sbicnext target %d disconnected\n", 2304 dev->target); 2305 #endif 2306 2307 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2308 2309 ++dev->sc_tinfo[dev->target].dconns; 2310 2311 dev->sc_nexus = NULL; 2312 dev->sc_xs = NULL; 2313 2314 if (acb->xs->xs_control & XS_CTL_POLL || 2315 dev->sc_flags & SBICF_ICMD || 2316 !sbic_parallel_operations ) 2317 return SBIC_STATE_DISCONNECT; 2318 2319 QPRINTF(("sbicnext: calling sbic_sched\n")); 2320 2321 sbic_sched(dev); 2322 2323 QPRINTF(("sbicnext: sbic_sched returned\n")); 2324 2325 return SBIC_STATE_DISCONNECT; 2326 2327 case SBIC_CSR_RSLT_NI: 2328 case SBIC_CSR_RSLT_IFY: 2329 { 2330 /* 2331 * A reselection. 2332 * Note that since we don't enable Advanced Features (assuming 2333 * the WD chip is at least the 'A' revision), we're only ever 2334 * likely to see the 'SBIC_CSR_RSLT_NI' status. But for the 2335 * hell of it, we'll handle it anyway, for all the extra code 2336 * it needs... 2337 */ 2338 u_char newtarget, newlun; 2339 2340 GET_SBIC_rselid(regs, newtarget); 2341 2342 /* 2343 * check SBIC_RID_SIV? 2344 */ 2345 newtarget &= SBIC_RID_MASK; 2346 2347 if (csr == SBIC_CSR_RSLT_IFY) { 2348 2349 /* 2350 * Read Identify msg to avoid lockup 2351 */ 2352 GET_SBIC_data(regs, newlun); 2353 WAIT_CIP(regs); 2354 newlun &= SBIC_TLUN_MASK; 2355 2356 } else { 2357 2358 /* 2359 * Need to read Identify message the hard way, assuming 2360 * the target even sends us one... 2361 */ 2362 for (newlun = 255; newlun; --newlun) { 2363 GET_SBIC_asr(regs, asr); 2364 if (asr & SBIC_ASR_INT) 2365 break; 2366 delay(10); 2367 } 2368 2369 /* 2370 * If we didn't get an interrupt, something's up 2371 */ 2372 if ((asr & SBIC_ASR_INT) == 0) { 2373 printf("%s: Reselect without identify?" 2374 " asr %x\n", device_xname(dev->sc_dev), asr); 2375 newlun = 0; /* XXXX */ 2376 } else { 2377 /* 2378 * We got an interrupt, verify that 2379 * it's a change to message in phase, 2380 * and if so read the message. 2381 */ 2382 GET_SBIC_csr(regs,csr); 2383 2384 if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2385 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2386 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) { 2387 /* 2388 * Yup, gone to message in. 2389 * Fetch the target LUN 2390 */ 2391 sbicmsgin(dev); 2392 newlun = dev->sc_msg[0] & 0x07; 2393 2394 } else { 2395 /* 2396 * Whoops! Target didn't go to 2397 * message in phase!! 2398 */ 2399 printf("RSLT_NI - " 2400 "not MESG_IN_PHASE %x\n", csr); 2401 newlun = 0; /* XXXSCW */ 2402 } 2403 } 2404 } 2405 2406 /* 2407 * Ok, we have the identity of the reselecting target. 2408 */ 2409 #ifdef DEBUG 2410 if (reselect_debug > 1 || 2411 (reselect_debug && csr == SBIC_CSR_RSLT_NI)) { 2412 printf("sbicnext: reselect %s from targ %d lun %d\n", 2413 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", 2414 newtarget, newlun); 2415 } 2416 #endif 2417 2418 if (dev->sc_nexus) { 2419 /* 2420 * Whoops! We've been reselected with 2421 * a command in progress! 2422 * The best we can do is to put the current command 2423 * back on the ready list and hope for the best. 2424 */ 2425 #ifdef DEBUG 2426 if (reselect_debug > 1) { 2427 printf("%s: reselect %s with active command\n", 2428 device_xname(dev->sc_dev), 2429 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2430 } 2431 #endif 2432 2433 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, 2434 chain); 2435 2436 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2437 2438 dev->sc_nexus = NULL; 2439 dev->sc_xs = NULL; 2440 } 2441 2442 /* 2443 * Reload sync values for this target 2444 */ 2445 if (dev->sc_sync[newtarget].state == SYNC_DONE) 2446 SET_SBIC_syn(regs, 2447 SBIC_SYN(dev->sc_sync[newtarget].offset, 2448 dev->sc_sync[newtarget].period)); 2449 else 2450 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2451 2452 /* 2453 * Loop through the nexus list until we find the saved entry 2454 * for the reselecting target... 2455 */ 2456 for (acb = dev->nexus_list.tqh_first; acb; 2457 acb = acb->chain.tqe_next) { 2458 2459 if ( acb->xs->xs_periph->periph_target == newtarget && 2460 acb->xs->xs_periph->periph_lun == newlun) { 2461 /* 2462 * We've found the saved entry. Dequeue it, and 2463 * make it current again. 2464 */ 2465 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2466 2467 dev->sc_nexus = acb; 2468 dev->sc_xs = acb->xs; 2469 dev->sc_flags |= SBICF_SELECTED; 2470 dev->target = newtarget; 2471 dev->lun = newlun; 2472 break; 2473 } 2474 } 2475 2476 if (acb == NULL) { 2477 printf("%s: reselect %s targ %d not in nexus_list %p\n", 2478 device_xname(dev->sc_dev), 2479 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2480 &dev->nexus_list.tqh_first); 2481 panic("bad reselect in sbic"); 2482 } 2483 2484 if (csr == SBIC_CSR_RSLT_IFY) 2485 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2486 break; 2487 } 2488 default: 2489 abort: 2490 /* 2491 * Something unexpected happened -- deal with it. 2492 */ 2493 printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr); 2494 2495 #ifdef DDB 2496 Debugger(); 2497 #endif 2498 2499 #ifdef DEBUG 2500 dev->sc_dmatimo = 0; 2501 if (data_pointer_debug > 1) 2502 printf("next dmastop: %d(%p:%lx)\n", dev->target, 2503 dev->sc_cur->dc_addr, 2504 dev->sc_tcnt); 2505 #endif 2506 2507 dev->sc_dmastop(dev); 2508 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2509 if (dev->sc_xs) 2510 sbicerror(dev, csr); 2511 sbicabort(dev, "next"); 2512 2513 if (dev->sc_flags & SBICF_INDMA) { 2514 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2515 2516 #ifdef DEBUG 2517 dev->sc_dmatimo = 0; 2518 if (data_pointer_debug > 1) 2519 printf("next dmastop: %d(%p:%lx)\n", 2520 dev->target, 2521 dev->sc_cur->dc_addr, 2522 dev->sc_tcnt); 2523 #endif 2524 sbic_scsidone(acb, -1); 2525 } 2526 2527 return SBIC_STATE_ERROR; 2528 } 2529 2530 return SBIC_STATE_RUNNING; 2531 } 2532 2533 2534 /* 2535 * Check if DMA can not be used with specified buffer 2536 */ 2537 int 2538 sbiccheckdmap(void *bp, u_long len, u_long mask) 2539 { 2540 u_char *buffer; 2541 u_long phy_buf; 2542 u_long phy_len; 2543 2544 buffer = bp; 2545 2546 if (len == 0) 2547 return 1; 2548 2549 while (len) { 2550 2551 phy_buf = kvtop((void *)buffer); 2552 phy_len = PAGE_SIZE - ((int)buffer & PGOFSET); 2553 2554 if (len < phy_len) 2555 phy_len = len; 2556 2557 if (phy_buf & mask) 2558 return 1; 2559 2560 buffer += phy_len; 2561 len -= phy_len; 2562 } 2563 2564 return 0; 2565 } 2566 2567 int 2568 sbictoscsiperiod(struct sbic_softc *dev, int a) 2569 { 2570 unsigned int fs; 2571 2572 /* 2573 * cycle = DIV / (2 * CLK) 2574 * DIV = FS + 2 2575 * best we can do is 200ns at 20 MHz, 2 cycles 2576 */ 2577 2578 GET_SBIC_myid(dev->sc_sbicp, fs); 2579 2580 fs = (fs >> 6) + 2; /* DIV */ 2581 2582 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2583 2584 if (a < 2) 2585 a = 8; /* map to Cycles */ 2586 2587 return (fs * a) >> 2; /* in 4 ns units */ 2588 } 2589 2590 int 2591 sbicfromscsiperiod(struct sbic_softc *dev, int p) 2592 { 2593 unsigned int fs, ret; 2594 2595 /* 2596 * Just the inverse of the above 2597 */ 2598 GET_SBIC_myid(dev->sc_sbicp, fs); 2599 2600 fs = (fs >> 6) + 2; /* DIV */ 2601 2602 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2603 2604 ret = p << 2; /* in ns units */ 2605 ret = ret / fs; /* in Cycles */ 2606 2607 if (ret < sbic_min_period) 2608 return(sbic_min_period); 2609 2610 /* 2611 * verify rounding 2612 */ 2613 if (sbictoscsiperiod(dev, ret) < p) 2614 ret++; 2615 2616 return (ret >= 8) ? 0 : ret; 2617 } 2618 2619 #ifdef DEBUG 2620 void 2621 sbictimeout(struct sbic_softc *dev) 2622 { 2623 int s, asr; 2624 2625 s = splbio(); 2626 2627 if (dev->sc_dmatimo) { 2628 2629 if (dev->sc_dmatimo > 1) { 2630 2631 printf("%s: DMA timeout #%d\n", device_xname(dev->sc_dev), 2632 dev->sc_dmatimo - 1); 2633 2634 GET_SBIC_asr(dev->sc_sbicp, asr); 2635 2636 if (asr & SBIC_ASR_INT) { 2637 /* 2638 * We need to service a missed IRQ 2639 */ 2640 sbicintr(dev); 2641 } else { 2642 (void)sbicabort(dev, "timeout"); 2643 splx(s); 2644 return; 2645 } 2646 } 2647 2648 dev->sc_dmatimo++; 2649 } 2650 2651 splx(s); 2652 2653 callout_reset(&dev->sc_timo_ch, 30 * hz, (void *)sbictimeout, dev); 2654 } 2655 #endif 2656
Indexes created Sun Oct 25 00:26:45 UTC 2026