1 /* $NetBSD: am18xx_platform.c,v 1.2 2026/07/30 15:08:08 yurix Exp $ */ 2 3 /*- 4 * Copyright (c) 2026 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Yuri Honegger. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Platform code for the TI AM18XX family of SOCs (AM1808, AM1810). In linux 34 * land and in the device trees, this platform is sometimes also called DA830 35 * and DA850 (Davinci 8XX) because their silicon has a lot in common. 36 */ 37 38 #include "opt_console.h" 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: am18xx_platform.c,v 1.2 2026/07/30 15:08:08 yurix Exp $"); 42 43 #include <uvm/uvm_extern.h> 44 45 #include <dev/fdt/fdt_platform.h> 46 #include <dev/fdt/fdtvar.h> 47 #include <dev/ic/comreg.h> 48 49 #include <arch/evbarm/fdt/platform.h> 50 #include <arm/fdt/arm_fdtvar.h> 51 52 #define AM18XX_IO_VBASE KERNEL_IO_VBASE 53 #define AM18XX_IO_PBASE 0x01c00000 54 #define AM18XX_IO_SIZE 0x00400000 55 #define AM18XX_INTC_VBASE (AM18XX_IO_VBASE + AM18XX_IO_SIZE) 56 #define AM18XX_INTC_PBASE 0xfffee000 57 #define AM18XX_INTC_SIZE 0x2000 58 59 #define AM18XX_TIMER1_BASE 0x01C21000 60 #define AM18XX_TIMER1_SIZE 0x1000 61 #define AM18XX_TIMER1_TIM12 0x10 62 #define AM18XX_TIMER1_TIM34 0x14 63 #define AM18XX_TIMER1_PRD12 0x18 64 #define AM18XX_TIMER1_PRD34 0x1C 65 #define AM18XX_TIMER1_TCR 0x20 66 #define AM18XX_TIMER1_TGCR 0x24 67 #define AM18XX_TIMER1_WDTCR 0x28 68 69 #define AM18XX_TIMER_TCR_ENAMODE12_CONTINUOUS 0x80 70 #define AM18XX_TIMER_TGCR_TIMMODE32_UNCHAINED 0x4 71 #define AM18XX_TIMER_TGCR_TIMMODE64_WATCHDOG 0x8 72 #define AM18XX_TIMER_TGCR_TIM12EN 1 73 #define AM18XX_TIMER_TGCR_TIM34EN 2 74 #define AM18XX_TIMER_WDTCR_WDEN 1 75 #define AM18XX_TIMER_WDTCR_KEY0 0xa5c60000 76 #define AM18XX_TIMER_WDTCR_KEY1 0xda7e0000 77 78 79 void am18xx_platform_early_putchar(char); 80 81 extern struct arm32_bus_dma_tag arm_generic_dma_tag; 82 extern struct bus_space arm_generic_bs_tag; 83 84 void __noasan 85 am18xx_platform_early_putchar(char c) 86 { 87 #ifdef CONSADDR 88 #define CONSADDR_VA (CONSADDR - AM18XX_IO_PBASE + KERNEL_IO_VBASE) 89 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() 90 ? (volatile uint32_t *)CONSADDR_VA 91 : (volatile uint32_t *)CONSADDR; 92 93 while ((le32toh(uartaddr[com_lsr]) & LSR_TXRDY) == 0) 94 continue; 95 96 uartaddr[com_data] = htole32(c); 97 #endif 98 } 99 100 101 static const struct pmap_devmap * 102 am18xx_platform_devmap(void) 103 { 104 static const struct pmap_devmap devmap[] = { 105 /* input/output registers */ 106 DEVMAP_ENTRY(AM18XX_IO_VBASE, 107 AM18XX_IO_PBASE, 108 AM18XX_IO_SIZE), 109 /* interrupt controller */ 110 DEVMAP_ENTRY(AM18XX_INTC_VBASE, 111 AM18XX_INTC_PBASE, 112 AM18XX_INTC_SIZE), 113 DEVMAP_ENTRY_END 114 }; 115 116 return devmap; 117 } 118 119 static void 120 am18xx_platform_init_attach_args(struct fdt_attach_args *faa) 121 { 122 faa->faa_bst = &arm_generic_bs_tag; 123 faa->faa_dmat = &arm_generic_dma_tag; 124 } 125 126 static void 127 am18xx_platform_delay(u_int n) 128 { 129 /* Use Timer1 for delay. Timer0 is used*/ 130 static bus_space_tag_t bst = &arm_generic_bs_tag; 131 static bus_space_handle_t bsh = 0; 132 133 if (bsh == 0) { 134 /* map Timer1 */ 135 bus_space_map(bst, AM18XX_TIMER1_BASE, AM18XX_TIMER1_SIZE, 136 0, &bsh); 137 138 /* disable counter to allow changing mode */ 139 bus_space_write_4(bst, bsh, AM18XX_TIMER1_TCR, 0); 140 /* set mode to 32-bit unchained */ 141 bus_space_write_4(bst, bsh, AM18XX_TIMER1_TGCR, 142 AM18XX_TIMER_TGCR_TIMMODE32_UNCHAINED | 143 AM18XX_TIMER_TGCR_TIM12EN); 144 /* load period registers with maximum period */ 145 bus_space_write_4(bst, bsh, AM18XX_TIMER1_PRD12, 0xFFFFFFFF); 146 /* enable timer */ 147 bus_space_write_4(bst, bsh, AM18XX_TIMER1_TCR, 148 AM18XX_TIMER_TCR_ENAMODE12_CONTINUOUS); 149 150 } 151 152 /* 153 * The counter is driven by PLL0_AUXCLK, which is taken from OSCIN. 154 * On the EV3, that is 24MHz. 155 * 156 * n is in microseconds (us) 157 * 158 * TODO: The frequency is board-dependent and we should get it from the 159 * device tree. 160 */ 161 long ticks = n * (24000000 / 1000000); 162 163 uint32_t prev, cur; 164 prev = bus_space_read_4(bst, bsh, AM18XX_TIMER1_TIM12); 165 while (ticks > 0) { 166 cur = bus_space_read_4(bst, bsh, AM18XX_TIMER1_TIM12); 167 if (cur >= prev) 168 ticks -= (cur - prev); 169 else 170 ticks -= (UINT32_MAX - cur + prev); 171 prev = cur; 172 } 173 } 174 175 /* 176 * To reset the AM1808, you have to crash the watchdog. 177 */ 178 static void 179 am18xx_platform_reset(void) 180 { 181 /* map TIMER1 */ 182 bus_space_tag_t bst = &arm_generic_bs_tag; 183 bus_space_handle_t bsh = 0; 184 bus_space_map(bst, AM18XX_TIMER1_BASE, AM18XX_TIMER1_SIZE, 0, &bsh); 185 186 /* disable counter to allow changing mode */ 187 bus_space_write_4(bst, bsh, AM18XX_TIMER1_TCR, 0); 188 /* set mode to watchdog unchained */ 189 bus_space_write_4(bst, bsh, AM18XX_TIMER1_TGCR, 190 AM18XX_TIMER_TGCR_TIMMODE64_WATCHDOG | 191 AM18XX_TIMER_TGCR_TIM12EN | 192 AM18XX_TIMER_TGCR_TIM34EN); 193 /* set counter and reload registers */ 194 bus_space_write_4(bst, bsh, AM18XX_TIMER1_TIM12, 0); 195 bus_space_write_4(bst, bsh, AM18XX_TIMER1_TIM34, 0); 196 bus_space_write_4(bst, bsh, AM18XX_TIMER1_PRD12, 0); 197 bus_space_write_4(bst, bsh, AM18XX_TIMER1_PRD34, 0); 198 199 /* execute the watchdog enable sequence */ 200 bus_space_write_4(bst, bsh, AM18XX_TIMER1_WDTCR, 201 AM18XX_TIMER_WDTCR_KEY0 | AM18XX_TIMER_WDTCR_WDEN); 202 bus_space_write_4(bst, bsh, AM18XX_TIMER1_WDTCR, 203 AM18XX_TIMER_WDTCR_KEY1 | AM18XX_TIMER_WDTCR_WDEN); 204 /* trigger a reset by writing an invalid value to WDTCR*/ 205 bus_space_write_4(bst, bsh, AM18XX_TIMER1_WDTCR, 0xaffe); 206 207 /* NOTREACHED */ 208 } 209 210 static const struct fdt_platform am18xx_platform = { 211 .fp_devmap = am18xx_platform_devmap, 212 .fp_bootstrap = arm_fdt_cpu_bootstrap, 213 .fp_init_attach_args = am18xx_platform_init_attach_args, 214 .fp_uart_freq = NULL, 215 .fp_delay = am18xx_platform_delay, 216 .fp_reset = am18xx_platform_reset, 217 }; 218 219 /* The device tree name for the AM1808 is da850 (davinci 850) */ 220 FDT_PLATFORM(am18xx, "ti,da850", &am18xx_platform); 221
Indexes created Sun Oct 25 00:26:45 UTC 2026