Tidy up how __sigaction14_sigtramp.c is added to SRCS.

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

No need for double semi-colon

Indent END the same as ENTRY.

NFCI.

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Looks like libc is too big to be able to use j. use a longer distance jump

branches: 1.2.16;
Switch to new ABI (return values now in a0/a1; v0/v1 are no more)

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Annotate the RISC-V signal trampoline with CFI attributes.

KNF

Adapt to the jmpbuf changes.

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

revert previously. we want riscv32 to have 128 bit long double...
shall fix the compiler instead.

risc32 doesn't want long double specific versions

Cargo cult follow the other 128bit long double architecture (sparc64).

branches: 1.1.16;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Trailing whitespace

Provide a definition of quiet NaN for RISC-V, and a reference to where
it comes from.

branches: 1.1.16;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

libc/arch: Fix copy-paste; or1k, powerpc64, riscv are not powerpc ;)

build the generic 128bit long double code.

branches: 1.1.16;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Consistently pass 0 as first and ignored argument to sigprocmask in the
setjmp implementations.

NFCI.

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Consistently use the 'mv' instrucation (which is itself an alias) instead
of the (old) alternative alias 'move'.

Switch to new ABI (return values now in a0/a1; v0/v1 are no more)

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Adapt to new assembler. jump->tail[call] auipc/lo12 changes.

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Create a new header lwp_private.h to contain _lwp_getprivate_fast,
_lwp_gettcb_fast, _lwp_settcb and remove them from mcontext.h, so that:
1. we don't need special hacks to hide them
2. we can include <lwp.h> where needed to get the necessary prototypes
without redefining them locally.

branches: 1.1.28;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Consistently use the 'mv' instrucation (which is itself an alias) instead
of the (old) alternative alias 'move'.

Switch to new ABI (return values now in a0/a1; v0/v1 are no more)

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Call libc's fpgetround.

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Trailing whitespace

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

riscv: Nix shifting around FRRM and FSRM in libc too.

These read and write the floating-point rounding mode directly, not
the whole floating-point control and status register.

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Trailing whitespace

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

riscv: More shiftiness reduction around FCSR in libc.

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Trailing whitespace

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Do the '#if FCSR_FMASK == 0' thing that fpgetmask.c does for consistency.

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Trailing whitespace

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

riscv: Nix shifting around FRRM and FSRM in libc too.

These read and write the floating-point rounding mode directly, not
the whole floating-point control and status register.

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Trailing whitespace

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

riscv: More shiftiness reduction around FCSR in libc.

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Trailing whitespace

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

makecontext: correct the type to setup register based arguments.

Use __greg_t rather than int for register based arguments. This fixes
various atf tests.

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Trailing whitespace

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Adapt to new assembler. jump->tail[call] auipc/lo12 changes.

Switch to new ABI (return values now in a0/a1; v0/v1 are no more)

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Adapt to new assembler. jump->tail[call] auipc/lo12 changes.

Switch to new ABI (return values now in a0/a1; v0/v1 are no more)

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Merge all MD __sigaction14_sigtramp.c copies into one:
- sparc and sparc64 were not using version 0 sigcontext when there were
no arguments in the signal version. This was probably a bug.
- vax is using +1 the version numbers of the other archs.
- Only hppa was defining __LIBC12_SOURCE__ so it was getting a working
sigcontext before. all the other ports that supported sigcontext had
the compat code disabled.
[pointed out by thorpej, thanks!]
If we want to remove sigcontext support from userland at least now there
is less work to do so.

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Annotate the RISC-V signal trampoline with CFI attributes.

Change MIPS to RISC-V.

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Switch to new ABI (return values now in a0/a1; v0/v1 are no more)

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Rename "syscall" to "_syscall" and provide "syscall" as a weak alias.

branches: 1.2.16;
Switch to new ABI (return values now in a0/a1; v0/v1 are no more)

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Switch to new ABI (return values now in a0/a1; v0/v1 are no more)

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Consistently use the 'mv' instrucation (which is itself an alias) instead
of the (old) alternative alias 'move'.

Use lla instead doing the pcrel relocs ourselves.

Adapt to new assembler. jump->tail[call] auipc/lo12 changes.

Switch to new ABI (return values now in a0/a1; v0/v1 are no more)

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Adapt to new assembler. jump->tail[call] auipc/lo12 changes.

Switch to new ABI (return values now in a0/a1; v0/v1 are no more)

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Mark exect(3) obsolete and bind it to plain execve(2) on all platforms

The original exect(2) from BSD4.2 was enabling bit for tracing
(single-step mode) and calling execve(2). The purpose of it was to generate
a signal for a tracer once the application will change its image to a new
program.

This approach no longer works as:
- exect(2) traces (single-steps) libc and it requires hundreds or
thousands steps before entering a new image
- it's vax and x86 specific code
- this functionality has been moved to the kernel - once a process is
traced it will generate SIGTRAP with si_code TRAP_EXEC and route it to
its debugger
- the side effects and unportability make this interface unusable
- there are no known users of this interface
- it apparently never worked better since day0 of NetBSD ("day0 bug")

Users are requested to move to other execve(2) variants. Calling current
execve(2) as it is the most similar behavior to this one from BSD4.2.

Discussed several times on mailing lists and in PR/51700.

Add warning to exect(3) telling about marking this function obsolete.

This function is prepared to be removed in next libc major bump.

Sponsored by <The NetBSD Foundation>

branches: 1.1.2; 1.1.4;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Switch to new ABI (return values now in a0/a1; v0/v1 are no more)

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

Switch to new ABI (return values now in a0/a1; v0/v1 are no more)

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Switch to new ABI (return values now in a0/a1; v0/v1 are no more)

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Consistently use the 'mv' instrucation (which is itself an alias) instead
of the (old) alternative alias 'move'.

Use lla instead doing the pcrel relocs ourselves.

Adapt to new assembler. jump->tail[call] auipc/lo12 changes.

Switch to new ABI (return values now in a0/a1; v0/v1 are no more)

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)