| History log of /src/sys/arch/aarch64/aarch64/idle_machdep.S |
| Revision | | Date | Author | Comments |
| 1.13 |
| 30-Dec-2024 |
jmcneill | aarch64: Allow for alternate cpu_idle() implementations
|
| 1.12 |
| 29-May-2022 |
ryo | ESR_EL1 and FAR_EL1 are not required in interrupt trapframe and their values are meaningless.
To identify it as an interrupt trap frame, store -1 and 0.
|
| 1.11 |
| 10-Oct-2021 |
skrll | KNF
|
| 1.10 |
| 30-Aug-2021 |
jmcneill | Ensure that all memory accesses prior to executing WFI have been completed
by adding a DSB SY before stopping execution and entering a low power
state. From the ARM Cortex-A Series Programmer's Guide for ARMv8-A:
"ARM recommends the use of a Data Synchronization Barrier (DSB) instruction
before WFI or WFE, to ensure that pending memory transactions complete before
changing state."
|
| 1.9 |
| 23-Feb-2021 |
ryo | Just a few optimizations.
- in cpu_idle(), ci_intr_depth is always 0, so there is no need to fetch for increment or conditional branch.
- curcpu() is immutable in idle lwp, there is no need to consider KPREEMPT. Therefore, get curcpu() first and keep using it.
- add more comment.
|
| 1.8 |
| 21-Feb-2021 |
jmcneill | When waking from cpu_idle(), only call dosoftints if ci_intr_depth == 0
|
| 1.7 |
| 11-Feb-2021 |
ryo | include "opt_gprof.h" so that _PROF_PROLOGUE works properly in ENTRY() macro in *.S files
|
| 1.6 |
| 12-Aug-2020 |
skrll | branches: 1.6.2;
Part II of ad's aarch64 performance improvements (cpu_switch.S bugs are
all mine)
- Use tpidr_el1 to hold curlwp and not curcpu, because curlwp is accessed
much more often by MI code. It also makes curlwp preemption safe and
allows aarch64_curlwp() to be a const function (curcpu must be volatile).
- Make ASTs operate per-LWP rather than per-CPU, otherwise sometimes LWPs
can see spurious ASTs (which doesn't cause a problem, it just means some
time may be wasted).
- Use plain stores to set/clear ASTs. Make sure ASTs are always set on the
same CPU as the target LWP, and delivered via IPI if posted from a remote
CPU so that they are resolved quickly.
- Add some cache line padding to struct cpu_info, to match x86.
- Add a memory barrier in a couple of places where ci_curlwp is set. This
is needed whenever an LWP that is resuming on the CPU could hold an
adaptive mutex. The barrier needs to drain the CPU's store buffer, so
that the update to ci_curlwp becomes globally visible before the LWP can
resume and call mutex_exit(). By my reading of the ARM docs it looks like
the instruction I used will do the right thing, but I'm not 100% sure.
|
| 1.5 |
| 27-Jan-2019 |
dholland | restore accidentally-removed rcsid
|
| 1.4 |
| 27-Jan-2019 |
pgoyette | Merge the [pgoyette-compat] branch
|
| 1.3 |
| 12-Dec-2018 |
ryo | - need to save/restore interrupt mask when entering/exiting to/from cpu_switchto_softint().
- when call dosoftints from cpu_idle, interrupts should be disabled.
rarely, lwp stack had been exhausted when high interrupts.
reported by alnsn@. thanks.
|
| 1.2 |
| 01-Apr-2018 |
ryo | branches: 1.2.2;
Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)
- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)
|
| 1.1 |
| 10-Aug-2014 |
matt | branches: 1.1.4; 1.1.28;
Preliminary files for AARCH64 (64-bit ARM) support.
Enough for a distribution build.
|
| 1.1.28.2 |
| 26-Dec-2018 |
pgoyette | Sync with HEAD, resolve a few conflicts
|
| 1.1.28.1 |
| 07-Apr-2018 |
pgoyette | Sync with HEAD. 77 conflicts resolved - all of them $NetBSD$
|
| 1.1.4.2 |
| 20-Aug-2014 |
tls | Rebase to HEAD as of a few days ago.
|
| 1.1.4.1 |
| 10-Aug-2014 |
tls | file idle_machdep.S was added on branch tls-maxphys on 2014-08-20 00:02:39 +0000
|
| 1.2.2.1 |
| 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.6.2.1 |
| 03-Apr-2021 |
thorpej | Sync with HEAD.
|
