| History log of /src/sys/arch/aarch64/include/machdep.h |
| Revision | | Date | Author | Comments |
| 1.19 |
| 07-Feb-2024 |
msaitoh | Remove ryo@'s mail addresses.
|
| 1.18 |
| 30-Aug-2021 |
jmcneill | Add FIQ support.
|
| 1.17 |
| 06-Sep-2020 |
ryo | Fix panic caused by modload. http://mail-index.netbsd.org/port-arm/2020/08/30/msg006960.html
The address space reserved for modules may not be mapped in L1-L3.
|
| 1.16 |
| 06-Aug-2020 |
ryo | revert the changes of http://mail-index.netbsd.org/source-changes/2020/08/03/msg120183.html
This change is overengineered.
bus_space_{peek,poke}_N does not have to be reentrant nor available for interrupt context.
requested by skrll@
|
| 1.15 |
| 03-Aug-2020 |
ryo | Fix a problem in which a fault occured in an interrupt handler during copyin/copyout was erroneously detected as being occured by copyin.
- keep idepth in faultbuf and compare it to avoid unnecessary fault recovery
- make cpu_set_onfault() nestable to use bus_space_{peek,poke}()
in hardware interrupt handlers during copyin & copyout.
|
| 1.14 |
| 08-Jul-2020 |
ryo | Determination of A64,A32,T32 for disasm is now done in strrdisasm() instead of the caller.
correctly disassemble by processor state if defined DEBUG_DUMP_ON_USERFAULT or DEBUG_DDB_ON_USERFAULT.
|
| 1.13 |
| 01-Jul-2020 |
ryo | - On some systems with a different cache line size (and DIC,IDC) per CPU, trap "mrs Xt,ctr_el0" instruction
to return the minimum cache line size of the system to userland.
- add CLIDR_EL1 and CTR_EL0 to struct aarch64_sysctl_cpu_id.
On most systems, cache line size is the same for all CPUs, so this mechanism won't be required.
Rather, this is primarily for errata support, which will be committed later.
|
| 1.12 |
| 29-Jun-2020 |
riastradh | Draft fpu_kern_enter/leave on aarch64.
|
| 1.11 |
| 23-May-2020 |
ryo | Not only the kernel thread, but also the userland PAC keys
(APIA,APIB,APDA,APDB,APGA) are now randomly initialized at exec, and switched
when context switch.
userland programs are able to perform pointer authentication on ARMv8.3+PAC cpu.
reviewd by maxv@, thanks.
|
| 1.10 |
| 15-Feb-2020 |
skrll | Various updates and improvements to cpu start up on arm/aarch64
- start sharing more code around the AP startup messaging.
- call arm_cpu_topology_set early so that ci_core_id is available for
drivers, e.g. bcm2835_intr.c
- both arm and aarch64 now have
- a static cpu_info_store array
- the same arm_cpu_{hatched,mbox}
|
| 1.9 |
| 18-Dec-2019 |
riastradh | branches: 1.9.2;
New function cpu_startup_hook on arm.
Called at end of cpu_startup. Can be defined in, e.g., evbarm to do
additional stuff after cpu_startup. Defined as a weak alias to a
function that does nothing, so optional.
ok jmcneill
|
| 1.8 |
| 16-Jul-2019 |
skrll | branches: 1.8.2;
Add vaddr_t initarm(void *);
Missed in previous commit.
|
| 1.7 |
| 06-Apr-2019 |
thorpej | Overhaul the API used to fetch and store individual memory cells in
userspace. The old fetch(9) and store(9) APIs (fubyte(), fuword(),
subyte(), suword(), etc.) are retired and replaced with new ufetch(9)
and ustore(9) APIs that can return proper error codes, etc. and are
implemented consistently across all platforms. The interrupt-safe
variants are no longer supported (and several of the existing attempts
at fuswintr(), etc. were buggy and not actually interrupt-safe).
Also augmement the ucas(9) API, making it consistently available on
all plaforms, supporting uniprocessor and multiprocessor systems, even
those that do not have CAS or LL/SC primitives.
Welcome to NetBSD 8.99.37.
|
| 1.6 |
| 18-Oct-2018 |
skrll | Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.
The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors. AP startup is
performed in less steps and more code is written in C.
The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.
Various kernels have been converted to use this code and tested. Some
boards were provided by TNF. Thanks!
The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.
Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively
|
| 1.5 |
| 15-Sep-2018 |
jakllsch | make kernel-groveling crash(8) work on aarch64
|
| 1.4 |
| 05-Aug-2018 |
skrll | Refactor code to split aarch{32,64} kernel page tables and VM setup. This
will help re-build the kernel page tables on aarch64 with correct section
mappings.
|
| 1.3 |
| 19-Jul-2018 |
christos | Implement TRAP_SIGDEBUG for aarch64...
ptraced programs die with:
data_abort_handler, 257: pid 199.1 (a.out): signal 11 (trap 0x82000006) @pc 0, addr 0x0, error=Instruction Abort (EL0)
|
| 1.2 |
| 09-Jul-2018 |
ryo | add MULTIPROCESSOR support
|
| 1.1 |
| 01-Apr-2018 |
ryo | branches: 1.1.2; 1.1.4;
Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)
- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)
|
| 1.1.4.2 |
| 13-Apr-2020 |
martin | Mostly merge changes from HEAD upto 20200411
|
| 1.1.4.1 |
| 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.1.2.6 |
| 20-Oct-2018 |
pgoyette | Sync with head
|
| 1.1.2.5 |
| 30-Sep-2018 |
pgoyette | Ssync with HEAD
|
| 1.1.2.4 |
| 06-Sep-2018 |
pgoyette | Sync with HEAD
Resolve a couple of conflicts (result of the uimin/uimax changes)
|
| 1.1.2.3 |
| 28-Jul-2018 |
pgoyette | Sync with HEAD
|
| 1.1.2.2 |
| 07-Apr-2018 |
pgoyette | Sync with HEAD. 77 conflicts resolved - all of them $NetBSD$
|
| 1.1.2.1 |
| 01-Apr-2018 |
pgoyette | file machdep.h was added on branch pgoyette-compat on 2018-04-07 04:12:11 +0000
|
| 1.8.2.1 |
| 12-Feb-2020 |
martin | Pull up following revision(s) (requested by riastradh in ticket #705):
sys/arch/aarch64/aarch64/aarch64_machdep.c: revision 1.35
sys/stand/efiboot/efifdt.c: revision 1.20
sys/stand/efiboot/efifdt.h: revision 1.7
sys/arch/aarch64/include/machdep.h: revision 1.9
sys/stand/efiboot/efiboot.h: revision 1.11
sys/arch/arm/arm32/arm32_machdep.c: revision 1.129
sys/arch/arm/include/arm32/machdep.h: revision 1.30
sys/stand/efiboot/exec.c: revision 1.12
sys/arch/evbarm/fdt/fdt_machdep.c: revision 1.65
sys/stand/efiboot/version: revision 1.14
sys/stand/efiboot/boot.c: revision 1.19
New function cpu_startup_hook on arm.
Called at end of cpu_startup. Can be defined in, e.g., evbarm to do
additional stuff after cpu_startup. Defined as a weak alias to a
function that does nothing, so optional.
ok jmcneill
Implement rndseed support in efiboot and fdt arm.
The EFI environment variable `rndseed' specifies the path to the
random seed. It is loaded only for fdt platforms at the moment.
Since the rndseed (an rndsave_t object as defined in <sys/rndio.h>)
is 536 bytes long (for hysterical raisins), and to avoid having to
erase parts of the fdt tree, we load it into a physical page whose
address is passed in the fdt tree, rather than passing the content of
the file as an fdt node directly; the kernel then reserves the page
from uvm, and maps it into kva to call rnd_seed.
For now, the only kernel that does use efiboot with fdt is evbarm,
which knows to handle the rndseed. Any new kernels that use efiboot
with fdt must do the same; otherwise uvm may hand out the page with
the secret key on it for a normal page allocation in the kernel --
which should be OK if there are no kernel memory disclosure bugs, but
would lead to worse consequences than simply loading the seed late in
userland with /etc/rc.d/random_seed otherwise.
ok jmcneill
|
| 1.9.2.1 |
| 29-Feb-2020 |
ad | Sync with head.
|
