| History log of /src/sys/arch/aarch64/include/param.h |
| Revision | | Date | Author | Comments |
| 1.16 |
| 31-May-2021 |
simonb | Include "opt_param.h" (ifdef _KERNEL_OPT) everywhere that MSGBUFSIZE is
referenced since some sources include <machine/param.h>.
|
| 1.15 |
| 24-Jan-2021 |
jmcneill | branches: 1.15.4;
Use 32K as the default NFSv3 read and write data sizes on aarch64, matching
i386 and amd64.
|
| 1.14 |
| 01-Feb-2020 |
skrll | branches: 1.14.6;
G/C
|
| 1.13 |
| 24-Nov-2019 |
rin | branches: 1.13.2;
PR port-arm/54702
Add support for earmv6hf binaries on COMPAT_NETBSD32 for aarch64:
- Emulate ARMv6 instructions with cache operations register (c7), that
are deprecated since ARMv7, and disabled on ARMv8 with LP64 kernel.
- ep_machine_arch (default: earmv7hf) is copied from executables, as we
do for mips64. "uname -p" reports earmv6hf if compiled for earmv6hf;
configure scripts etc can determine the appropriate architecture.
Many thanks to ryo@ for helping me to add support of Thumb-mode,
as well as providing exhaustive test cases:
https://github.com/ryo/mcr_test/
We've confirmed:
- Emulation works in Thumb-mode.
- T32 16-bit length illegal instruction results in SIGILL, even if
it is located nearby a boundary b/w mapped and unmapped pages.
- T32 32-bit instruction results in SIGSEGV if it is located across
a boundary b/w mapped and unmapped pages.
XXX
pullup to netbsd-9
|
| 1.12 |
| 19-Oct-2019 |
jmcneill | Increase aarch64 MAXCPUS to 256.
|
| 1.11 |
| 19-Jan-2019 |
skrll | branches: 1.11.4;
Increase MSGBUFSIZE
|
| 1.10 |
| 07-Jan-2019 |
jdolecek | move DEV_BSIZE, DEV_BSHIFT out of MD param.h, they are same on all ports
also move BLKDEV_IOSIZE, MAXPHYS, but allow override since some ports
have different value (powerpc uses NBPG for BLKDEV_IOSIZE, sun2/sun3
have lower MAXPHYS)
|
| 1.9 |
| 04-Jan-2019 |
rin | ALIGNBYTES32 should be (8 - 1), not (4 - 1) for EABI:
https://nxr.netbsd.org/xref/src/sys/arch/arm/include/cdefs.h#56
Now, sshd for earmv7hf works without problems.
Also fix other users of cmsg(3) API hopefully.
|
| 1.8 |
| 06-Dec-2018 |
skrll | Expose CACHE_LINE_SIZE (and COHERENCY_UNIT) so that fstat can work
|
| 1.7 |
| 18-Nov-2018 |
skrll | Add CPU_THUNDERX which sets COHERENCY_UNIT and CACHE_LINE_SIZE to 128
|
| 1.6 |
| 15-Nov-2018 |
riastradh | Respect the __HIDE_DELAY kludge like on other ports.
|
| 1.5 |
| 14-Nov-2018 |
jakllsch | Switch to NKMEMPAGES_MAX_UNLIMITED.
This aligns aarch64 with our other modern 64-bit ports. Significantly
improves file caching utilization on aarch64 systems with copious RAM.
|
| 1.4 |
| 12-Oct-2018 |
ryo | add initial support of COMPAT_NETBSD32 on AArch64.
arm ELF32 EABI binaries could be execute in AArch32 state on AArch64. A32 THUMB mode is not supported yet.
|
| 1.3 |
| 28-Apr-2018 |
jmcneill | branches: 1.3.2;
Increase default MSGBUFSIZE to match arm32 defaults
|
| 1.2 |
| 01-Apr-2018 |
ryo | Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)
- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)
|
| 1.1 |
| 10-Aug-2014 |
matt | branches: 1.1.4; 1.1.28;
Preliminary files for AARCH64 (64-bit ARM) support.
Enough for a distribution build.
|
| 1.1.28.7 |
| 26-Jan-2019 |
pgoyette | Sync with HEAD
|
| 1.1.28.6 |
| 18-Jan-2019 |
pgoyette | Synch with HEAD
|
| 1.1.28.5 |
| 26-Dec-2018 |
pgoyette | Sync with HEAD, resolve a few conflicts
|
| 1.1.28.4 |
| 26-Nov-2018 |
pgoyette | Sync with HEAD, resolve a couple of conflicts
|
| 1.1.28.3 |
| 20-Oct-2018 |
pgoyette | Sync with head
|
| 1.1.28.2 |
| 02-May-2018 |
pgoyette | Synch with HEAD
|
| 1.1.28.1 |
| 07-Apr-2018 |
pgoyette | Sync with HEAD. 77 conflicts resolved - all of them $NetBSD$
|
| 1.1.4.2 |
| 20-Aug-2014 |
tls | Rebase to HEAD as of a few days ago.
|
| 1.1.4.1 |
| 10-Aug-2014 |
tls | file param.h was added on branch tls-maxphys on 2014-08-20 00:02:39 +0000
|
| 1.3.2.3 |
| 13-Apr-2020 |
martin | Mostly merge changes from HEAD upto 20200411
|
| 1.3.2.2 |
| 08-Apr-2020 |
martin | Merge changes from current as of 20200406
|
| 1.3.2.1 |
| 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.11.4.1 |
| 23-Oct-2019 |
martin | Pull up following revision(s) (requested by jmcneill in ticket #359):
sys/arch/aarch64/aarch64/locore.S: revision 1.42
sys/arch/aarch64/aarch64/locore.S: revision 1.43
sys/arch/aarch64/aarch64/locore.S: revision 1.44
sys/arch/arm/fdt/cpu_fdt.c: revision 1.28
sys/arch/aarch64/include/cpu.h: revision 1.14
sys/arch/aarch64/include/param.h: revision 1.12
sys/arch/arm/arm32/cpu.c: revision 1.133
sys/arch/arm/arm32/cpu.c: revision 1.134
sys/arch/arm/include/cpu.h: revision 1.101
sys/arch/arm/acpi/cpu_acpi.c: revision 1.7
sys/arch/aarch64/aarch64/cpu.c: revision 1.23
sys/arch/aarch64/aarch64/cpu.c: revision 1.24
sys/arch/aarch64/aarch64/cpu.c: revision 1.25
Increase aarch64 MAXCPUS to 256.
-
Invalidate dcache before polling AP hatched status
-
Avoid overlap between BP and last AP stack. AP stacks are now in order of
increasing address order.
Spotted by and idea from mlelstv.
-
Use separate cacheline aligned arrays for mbox and hatched as before.
-
cpu_hatched_p only for MULTIPROCESSOR
|
| 1.13.2.1 |
| 29-Feb-2020 |
ad | Sync with head.
|
| 1.14.6.1 |
| 03-Apr-2021 |
thorpej | Sync with HEAD.
|
| 1.15.4.1 |
| 17-Jun-2021 |
thorpej | Sync w/ HEAD.
|
