| History log of /src/sys/arch/aarch64/include/proc.h |
| Revision | | Date | Author | Comments |
| 1.8 |
| 12-Aug-2020 |
skrll | Part II of ad's aarch64 performance improvements (cpu_switch.S bugs are
all mine)
- Use tpidr_el1 to hold curlwp and not curcpu, because curlwp is accessed
much more often by MI code. It also makes curlwp preemption safe and
allows aarch64_curlwp() to be a const function (curcpu must be volatile).
- Make ASTs operate per-LWP rather than per-CPU, otherwise sometimes LWPs
can see spurious ASTs (which doesn't cause a problem, it just means some
time may be wasted).
- Use plain stores to set/clear ASTs. Make sure ASTs are always set on the
same CPU as the target LWP, and delivered via IPI if posted from a remote
CPU so that they are resolved quickly.
- Add some cache line padding to struct cpu_info, to match x86.
- Add a memory barrier in a couple of places where ci_curlwp is set. This
is needed whenever an LWP that is resuming on the CPU could hold an
adaptive mutex. The barrier needs to drain the CPU's store buffer, so
that the update to ci_curlwp becomes globally visible before the LWP can
resume and call mutex_exit(). By my reading of the ARM docs it looks like
the instruction I used will do the right thing, but I'm not 100% sure.
|
| 1.7 |
| 23-May-2020 |
ryo | Not only the kernel thread, but also the userland PAC keys
(APIA,APIB,APDA,APDB,APGA) are now randomly initialized at exec, and switched
when context switch.
userland programs are able to perform pointer authentication on ARMv8.3+PAC cpu.
reviewd by maxv@, thanks.
|
| 1.6 |
| 12-Apr-2020 |
maxv | Add support for Pointer Authentication (PAC).
We use the "pac-ret" option, to sign the return instruction pointer on
function entry, and authenticate it on function exit. This acts as a
mitigation against ROP.
The authentication uses a per-lwp (secret) I-A key stored in the 128bit
APIAKey register and part of the lwp context. During lwp creation, the
kernel generates a random key, and during context switches, it installs
the key of the target lwp on the CPU.
Userland cannot read the APIAKey register directly. However, it can sign
its pointers with it, because the register is architecturally shared
between userland and the kernel. Although part of the CPU design, it is
a bit of an undesired behavior, because it allows to forge valid kernel
pointers from userland. To avoid that, we don't share the key with
userland, and rather switch it in EL0<->EL1 transitions. This means that
when userland executes, a different key is loaded in APIAKey than the one
the kernel uses. For now the userland key is a fixed 128bit zero value.
The DDB stack unwinder is changed to strip the authentication code from
the pointers in lr.
Two problems are known:
* Currently the idlelwps' keys are not really secret. This is because
the RNG is not yet available when we spawn these lwps. Not overly
important, but would be nice to fix with UEFI RNG.
* The key switching in EL0<->EL1 transitions is not the most optimized
code on the planet. Instead of checking aarch64_pac_enabled, it would
be better to hot-patch the code at boot time, but there currently is
no hot-patch support on aarch64.
Tested on Qemu.
|
| 1.5 |
| 24-Nov-2019 |
rin | branches: 1.5.6;
part of PR port-arm/54702
Having md_march32 unconditionally in struct mdproc, in order to
make libkvm happy.
XXX
pullup to netbsd-9
|
| 1.4 |
| 24-Nov-2019 |
rin | PR port-arm/54702
Add support for earmv6hf binaries on COMPAT_NETBSD32 for aarch64:
- Emulate ARMv6 instructions with cache operations register (c7), that
are deprecated since ARMv7, and disabled on ARMv8 with LP64 kernel.
- ep_machine_arch (default: earmv7hf) is copied from executables, as we
do for mips64. "uname -p" reports earmv6hf if compiled for earmv6hf;
configure scripts etc can determine the appropriate architecture.
Many thanks to ryo@ for helping me to add support of Thumb-mode,
as well as providing exhaustive test cases:
https://github.com/ryo/mcr_test/
We've confirmed:
- Emulation works in Thumb-mode.
- T32 16-bit length illegal instruction results in SIGILL, even if
it is located nearby a boundary b/w mapped and unmapped pages.
- T32 32-bit instruction results in SIGSEGV if it is located across
a boundary b/w mapped and unmapped pages.
XXX
pullup to netbsd-9
|
| 1.3 |
| 27-Dec-2018 |
mrg | make savecore for arm64 basically work.
- move MD lwp "md_ktf" member into struct pcb. the pcb is used by
the gdb "bsd-kvm" target code to find the stack of each thread
and needs to be available in a well known location.
- implement aarch64_nbsd_supply_pcb() in GDB. makes basic gdb work
on a crash dump.
- remove '#if L_MD_KTF + 8 == L_MD_CPACR' conditional code, as there
is no more L_MD_KTF.
with this gdb has minimal working functionality with "target kvm",
and crash can at least "ps" on a crash dump.
ok skrll.
|
| 1.2 |
| 01-Apr-2018 |
ryo | branches: 1.2.2;
Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)
- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)
|
| 1.1 |
| 10-Aug-2014 |
matt | branches: 1.1.4; 1.1.28;
Preliminary files for AARCH64 (64-bit ARM) support.
Enough for a distribution build.
|
| 1.1.28.2 |
| 18-Jan-2019 |
pgoyette | Synch with HEAD
|
| 1.1.28.1 |
| 07-Apr-2018 |
pgoyette | Sync with HEAD. 77 conflicts resolved - all of them $NetBSD$
|
| 1.1.4.2 |
| 20-Aug-2014 |
tls | Rebase to HEAD as of a few days ago.
|
| 1.1.4.1 |
| 10-Aug-2014 |
tls | file proc.h was added on branch tls-maxphys on 2014-08-20 00:02:39 +0000
|
| 1.2.2.3 |
| 21-Apr-2020 |
martin | Sync with HEAD
|
| 1.2.2.2 |
| 08-Apr-2020 |
martin | Merge changes from current as of 20200406
|
| 1.2.2.1 |
| 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.5.6.1 |
| 20-Apr-2020 |
bouyer | Sync with HEAD
|
