Major update of algor.
Now uses generic mips bus_space.h bus_dma.h isa_machdep.h pci_machdep.h
Now uses evbmips versions of cpu.c isadma_bounce.c mcclock_isa.c

Remove all the __P() from sys (excluding sys/dist)
Diff checked with grep and MK1 eyeball.
i386 and amd64 GENERIC and sys still build.

branches: 1.8.8; 1.8.14;
Remove clause 3 and 4 from TNF licenses

branches: 1.7.40; 1.7.42; 1.7.44;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

branches: 1.6.26;
merge ktrace-lwp.

branches: 1.5.16;
add __KERNEL_RCSID()

branches: 1.4.6; 1.4.22;
Implement bus_space_mmap().

branches: 1.3.2;
When the old PCI address map is in use, disable I/O space. Also disable
I/O space on PBC revs < B2.

If a bus doens't want to use an extent, don't force it to.

A port to the Algorithmics MIPS evaluation boards. We currently
support the P-5064, which has a QED RM5xxx CPU soldered on.

There is some skeletal support for the P-4032 (an older board, which
had an R4xxx CPU). There are some placeholders for the P-6032, which
is their newest board, but no real code yet (the P-6032 has a different
PCI controller, the Algorithmics BONITO).

There are still some (apprently softintr-related) problems with the
algor kernel, but it works well-enough to self-host.

Kudos to Allegro Networks for loaning me a P-5064 board on which to do
the port.

Major update of algor.
Now uses generic mips bus_space.h bus_dma.h isa_machdep.h pci_machdep.h
Now uses evbmips versions of cpu.c isadma_bounce.c mcclock_isa.c

Remove all the __P() from sys (excluding sys/dist)
Diff checked with grep and MK1 eyeball.
i386 and amd64 GENERIC and sys still build.

branches: 1.7.8; 1.7.14;
Remove clause 3 and 4 from TNF licenses

branches: 1.6.40; 1.6.42; 1.6.44;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

branches: 1.5.26;
merge ktrace-lwp.

branches: 1.4.16;
add __KERNEL_RCSID()

branches: 1.3.4; 1.3.20;
Fix typo in mmap hander.

Implement bus_space_mmap().

branches: 1.1.2;
A port to the Algorithmics MIPS evaluation boards. We currently
support the P-5064, which has a QED RM5xxx CPU soldered on.

There is some skeletal support for the P-4032 (an older board, which
had an R4xxx CPU). There are some placeholders for the P-6032, which
is their newest board, but no real code yet (the P-6032 has a different
PCI controller, the Algorithmics BONITO).

There are still some (apprently softintr-related) problems with the
algor kernel, but it works well-enough to self-host.

Kudos to Allegro Networks for loaning me a P-5064 board on which to do
the port.

Use {,e}isabus_attach().

s/sharable/shareable in comments and documentation.

Merge thorpej-cfargs2.

branches: 1.27.8;
Merge thorpej-cfargs branch:

Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.

Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
actually needed.
- Don't be explicit about what interface attribute is attaching if
the device only has one. (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
situations, making is visibly easier to see when indirect config is
in play, and allowing for future change in semantics. (As of now,
this is just a wrapper around config_match(), but that is an
implementation detail.)

Remove unnecessary or redundant interface attributes where they're not
needed.

There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)

...and a sentinel value CFARG_EOL.

Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.

Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance. This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).

branches: 1.26.2;
malloc(9) -> kmem(9)

branches: 1.25.8;
in many device attach paths, allocate memory with M_WAITOK instead of M_NOWAIT
and remove code to handle failures that can no longer happen.

branches: 1.24.54;
Allow algor kernels to be built under either algor/algor64 or
evbmips-el/evbmips64-el. Note that MAXMAPARITITONS and majors numbers
differ between the two ports which is why two kernels are still needed.

Major update of algor.
Now uses generic mips bus_space.h bus_dma.h isa_machdep.h pci_machdep.h
Now uses evbmips versions of cpu.c isadma_bounce.c mcclock_isa.c

#include <sys/bus.h> instead of <machine/bus.h>.

Define, and hook into the isa_chipset_tag_t, pcib_isa_detach_hook().

Change about 4500 of the K&R function definitions to ANSI ones.
There are still about 1600 left, but they have ',' or /* ... */
in the actual variable definitions - which my awk script doesn't handle.
There are also many that need () -> (void).
(The script does handle misordered arguments.)

branches: 1.19.8; 1.19.14;
Remove clause 3 and 4 from TNF licenses

branches: 1.18.62; 1.18.64; 1.18.66;
According to the i8259 manual, EOI, R, and SL bits belong to OCW2 register
so rename them OCW3_* -> OCW2_*.

branches: 1.17.4; 1.17.6; 1.17.8; 1.17.12;
merge ktrace-lwp.

branches: 1.16.12;
Phase out the use of a string as first "attach args" member to control
which bustype should be attached with a specific call to config_found()
(from a "mainbus" or a bus bridge).
Do it for isa/eisa/mca and pci/agp for now. These buses all attach to
an mi interface attribute "isabus", "eisabus" etc., and the autoconf
framework now allows to specify an interface attribute on config_found()
and config_search(), which limits the search of matching config data
to these which attach to that specific attribute.
So we basically have to call config_found_ia(..., "foobus", ...) where
such a bus is attached.
As a consequence, where a "mainbus" or alike also attaches other
devices (eg CPUs) which do not attach to a specific attribute yet,
we need at least pass an attribute name (different from "foobus") so
that the foo bus is not found at these places. This made some minor
changes necessary which are not obviously related to the mentioned buses.

pass string length (= boundary info) to pci_devinfo so that we do not run over
the end of memory region

Fix uninitialized error in pcib_print().

branches: 1.13.2;
Use aprint_normal() for cfprint() routines.

Fix script-o's in last.

Use CFATTACH_DECL().

Declare all cfattach structures const.

branches: 1.9.2; 1.9.8;
Check in work-in-progress of P-6032 support. This is not tested,
but is meant for back-up purposes.

Fill in one P-6032 snippet.

More ISA interrupt rototilling. I get *some* interrupts on a:

we1 at isa0 port 0x300-0x31f iomem 0xcc000-0xcffff irq 10
we1: WD8013WC Ethernet (16-bit)
we1: Ethernet address 00:00:c0:94:f6:72

...but still nothing on the PCIC.

Rototill ISA interrupt code. In particular, I have remembered most
of the horror that is the 8259 PIC.

PCMCIA interrupts still not working yet, but getting closer.

Yet more interrupt cleanup -- the platform mater interrupt establish
function now just takes an "irq", which is an index into the irqmap
table for that platform.

Hand off intr evcnt responsiblity in a reasonable way on the 5064.

Check in work-in-progress of generic ISA interrupt support. The
goal here is to get the P-5064 PCMCIA slots working, and serve as
the basis for P-6032 interrupt support.

PCMCIA interrupt auto-detection not working -- more work to be
done here.

The P-4032 has no ISA bridge/bus, so remove all P-4032 conditionals.

A port to the Algorithmics MIPS evaluation boards. We currently
support the P-5064, which has a QED RM5xxx CPU soldered on.

There is some skeletal support for the P-4032 (an older board, which
had an R4xxx CPU). There are some placeholders for the P-6032, which
is their newest board, but no real code yet (the P-6032 has a different
PCI controller, the Algorithmics BONITO).

There are still some (apprently softintr-related) problems with the
algor kernel, but it works well-enough to self-host.

Kudos to Allegro Networks for loaning me a P-5064 board on which to do
the port.

Allow algor kernels to be built under either algor/algor64 or
evbmips-el/evbmips64-el. Note that MAXMAPARITITONS and majors numbers
differ between the two ports which is why two kernels are still needed.

Major update of algor.
Now uses generic mips bus_space.h bus_dma.h isa_machdep.h pci_machdep.h
Now uses evbmips versions of cpu.c isadma_bounce.c mcclock_isa.c

Fix fallout of pci_attach_args constification. This should be the last
one for algor.

branches: 1.3.26; 1.3.32;
Split device_t and softc for ATA devices, as well as wd(4). Other
cosmetic changes where appropriate.

branches: 1.2.8; 1.2.40; 1.2.102; 1.2.122; 1.2.126;
Only call through the function pointer if it's not NULL.

A port to the Algorithmics MIPS evaluation boards. We currently
support the P-5064, which has a QED RM5xxx CPU soldered on.

There is some skeletal support for the P-4032 (an older board, which
had an R4xxx CPU). There are some placeholders for the P-6032, which
is their newest board, but no real code yet (the P-6032 has a different
PCI controller, the Algorithmics BONITO).

There are still some (apprently softintr-related) problems with the
algor kernel, but it works well-enough to self-host.

Kudos to Allegro Networks for loaning me a P-5064 board on which to do
the port.

PCI Extended Configuration stuff written by nonaka@:
- Add PCI Extended Configuration Space support into x86.
- Check register offset of pci_conf_read() in MD part. It returns (pcireg_t)-1
if it isn't accessible.
- Decode Extended Capability in PCI Extended Configuration Space.
Currently the following extended capabilities are decoded:
- Advanced Error Reporting
- Virtual Channel
- Device Serial Number
- Power Budgeting
- Root Complex Link Declaration
- Root Complex Event Collector Association
- Access Control Services
- Alternative Routing-ID Interpretation
- Address Translation Services
- Single Root IO Virtualization
- Page Request
- TPH Requester
- Latency Tolerance Reporting
- Secondary PCI Express
- Process Address Space ID
- LN Requester
- L1 PM Substates
The following extended capabilities are not decoded yet:
- Root Complex Internal Link Control
- Multi-Function Virtual Channel
- RCRB Header
- Vendor Unique
- Configuration Access Correction
- Multiple Root IO Virtualization
- Multicast
- Resizable BAR
- Dynamic Power Allocation
- Protocol Multiplexing
- Downstream Port Containment
- Precision Time Management
- M-PCIe
- Function Reading Status Queueing
- Readiness Time Reporting
- Designated Vendor-Specific

branches: 1.9.14;
split device_t/softc for all remaining drivers.
replace "struct device *" with "device_t".
use device_xname(), device_unit(), etc.

branches: 1.8.2; 1.8.12;
#include <sys/bus.h> instead of <machine/bus.h>.

Remove clause 3 and 4 from TNF licenses

branches: 1.6.74; 1.6.76; 1.6.78;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

branches: 1.4.16;
add __KERNEL_RCSID()

branches: 1.3.8; 1.3.24;
When the old PCI address map is in use, disable I/O space. Also disable
I/O space on PBC revs < B2.

Read the PCI memory space base and the PCI DMA window base from the
V3 PBC, and use them in the bus mem tag and the bus dma tag on the
P-4032. This allows us to get much further when PMON has configured
the PBC using the old-style PCI address map.

A port to the Algorithmics MIPS evaluation boards. We currently
support the P-5064, which has a QED RM5xxx CPU soldered on.

There is some skeletal support for the P-4032 (an older board, which
had an R4xxx CPU). There are some placeholders for the P-6032, which
is their newest board, but no real code yet (the P-6032 has a different
PCI controller, the Algorithmics BONITO).

There are still some (apprently softintr-related) problems with the
algor kernel, but it works well-enough to self-host.

Kudos to Allegro Networks for loaning me a P-5064 board on which to do
the port.

Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

branches: 1.1.8; 1.1.40;
A port to the Algorithmics MIPS evaluation boards. We currently
support the P-5064, which has a QED RM5xxx CPU soldered on.

There is some skeletal support for the P-4032 (an older board, which
had an R4xxx CPU). There are some placeholders for the P-6032, which
is their newest board, but no real code yet (the P-6032 has a different
PCI controller, the Algorithmics BONITO).

There are still some (apprently softintr-related) problems with the
algor kernel, but it works well-enough to self-host.

Kudos to Allegro Networks for loaning me a P-5064 board on which to do
the port.

Remove clause 3 and 4 from TNF licenses

branches: 1.3.8; 1.3.126; 1.3.128; 1.3.130;
When the old PCI address map is in use, disable I/O space. Also disable
I/O space on PBC revs < B2.

Read the PCI memory space base and the PCI DMA window base from the
V3 PBC, and use them in the bus mem tag and the bus dma tag on the
P-4032. This allows us to get much further when PMON has configured
the PBC using the old-style PCI address map.

A port to the Algorithmics MIPS evaluation boards. We currently
support the P-5064, which has a QED RM5xxx CPU soldered on.

There is some skeletal support for the P-4032 (an older board, which
had an R4xxx CPU). There are some placeholders for the P-6032, which
is their newest board, but no real code yet (the P-6032 has a different
PCI controller, the Algorithmics BONITO).

There are still some (apprently softintr-related) problems with the
algor kernel, but it works well-enough to self-host.

Kudos to Allegro Networks for loaning me a P-5064 board on which to do
the port.