branches: 1.1.2;
acpicpu: Add support for ACPI P-states and T-states on Arm.

arm64: acpi: Honour DMA memory address limit for named components.

branches: 1.4.26;
Make Arm MD ACPI code big endian friendly.

Add support for multiple GICv3 ITS domains.

Single mappings are translated to OutputBase, not InputBase

branches: 1.1.2; 1.1.6; 1.1.10;
Add support for decoding PCI ID mappings using IO remapping tables (IORT).

arm64: acpi: Honour DMA memory address limit for named components.

branches: 1.2.30;
Add support for multiple GICv3 ITS domains.

branches: 1.1.2; 1.1.6; 1.1.10;
Add support for decoding PCI ID mappings using IO remapping tables (IORT).

arm: ACPI: Fix EFI_MEMORY_UC memory type.

The UEFI specification says that EFI_MEMORY_UC should be treated as
Device-nGnRnE (UEFI 2.10, 2.3.6.1 AArch64 Platforms - Memory types).

arm64: acpi: Honour DMA memory address limit for named components.

branches: 1.26.8;
Use "non-posted" instead of "strongly ordered" to describe nGnRnE mappings

Rename the following defines:
- _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED to BUS_SPACE_MAP_NONPOSTED
- PMAP_DEV_SO to PMAP_DEV_NP
- LX_BLKPAG_ATTR_DEVICE_MEM_SO to LX_BLKPAG_ATTR_DEVICE_MEM_NP
Rename the following option:
- AARCH64_DEVICE_MEM_STRONGLY_ORDERED to AARCH64_DEVICE_MEM_NONPOSTED

arm: ACPI: Add support for simple sharing of platform interrupts

Allow sharing of platform interrupts provided that the type, ipl, and
mpsafe-ness are the same.

acpi: DMA: Use acpi_resource_parse_any to parse _DMA resources

_DMA resources really should be marked ResourceProducer, so use
acpi_resource_parse_any to pick these up.

Merge thorpej-cfargs2.

branches: 1.22.8;
Merge thorpej-cfargs branch:

Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.

Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
actually needed.
- Don't be explicit about what interface attribute is attaching if
the device only has one. (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
situations, making is visibly easier to see when indirect config is
in play, and allowing for future change in semantics. (As of now,
this is just a wrapper around config_match(), but that is an
implementation detail.)

Remove unnecessary or redundant interface attributes where they're not
needed.

There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)

...and a sentinel value CFARG_EOL.

Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.

Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance. This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).

branches: 1.21.2;
Add MI support for attaching drivers to arbitrary System Description
Tables.

branches: 1.20.2;
Trailing whitespace

Provide a properly constrained 32-bit DMA tag to ACPI.

branches: 1.18.2;
Rely on 32/64-bit overflow to calculate translation offsets. Store this
as a separate ar_xbase field in acpi_mem instead of having separate
ar_offset and ar_decode fields.

Create bus_dma tags for each device node based on _CCA and _DMA properties
found by walking up the device node tree. These tags encode range
restrictions, address translations, and whether or not the device is
cache coherent.

The DMA restrictions may not be defined in the direct parent of a device,
so search up the tree for a module device.

If a device node is a child of a module device, and the module device declares DMA range restrictions, use them.

Allow MD code to provide custom bus_dma tags on a per-node basis. On Arm
this is required to return non-coherent bus_dma tags for device nodes with
_CCA=0

Do not use Early Write Acknowledge for PCIe I/O and config space.

Implement acpi_md_intr_mask and acpi_md_intr_unmask

Add acpi_intr_mask() and acpi_intr_unmask() which, following the pre-existing
ACPI software layering model, are wrappers around acpi_md_intr_mask() and
acpi_md_intr_unmask(), which in turn are wrappers around intr_mask() and
intr_unmask().

XXX ARM and IA64 implementations of acpi_md_intr_mask() and
acpi_md_intr_unmask() are just stubs for now.

Use same style test as acpi_md_OsWritable

Correct the test for writeable memory. There aren't any users of this at
this point.

Always map ACPI table memory as normal memory. Always map device memory as device memory.

acpi_md_OsMapMemory can be used for both normal and device memory. Use the
UEFI memory map to determine how to map a given region.

branches: 1.6.4; 1.6.6;
Add MD functions for establishing and disestablishing interrupt handlers.

Support building kernels with ACPI and no PCI.

Don't make assumptions about the order of MADT subtables. Ensure that we
attach CPUs before the interrupt controller driver.

branches: 1.3.2;
Fix size calculation in acpi_md_OsUnmapMemory

Add ARM ACPI PCI support.

Add ARM MD ACPI implementation.

Use "non-posted" instead of "strongly ordered" to describe nGnRnE mappings

Rename the following defines:
- _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED to BUS_SPACE_MAP_NONPOSTED
- PMAP_DEV_SO to PMAP_DEV_NP
- LX_BLKPAG_ATTR_DEVICE_MEM_SO to LX_BLKPAG_ATTR_DEVICE_MEM_NP
Rename the following option:
- AARCH64_DEVICE_MEM_STRONGLY_ORDERED to AARCH64_DEVICE_MEM_NONPOSTED

Trailing whitespace

<sys/extent.h> not needed here.

Use sys/cpu.h so that curcpu defined in terms of curlwp->l_cpu works too.

branches: 1.1.2; 1.1.6;
Add support for Arm N1 SDP PCIe host controller.

The N1 SDP has a few bugs that we need to work around:
- PCIe root port config space lives in a non-standard location.
- Access to PCIe config space of devices that do not exist results in
an sync SError. Firmware creates a "known devices" table at a fixed
physical address that we use to filter PCI conf access to only known
devices.

This change splits the Arm ACPI PCI quirks into separate files for each
host controller, and allows per-segment quirks to be applied.

These changes exposed some bugs in the MI ACPI layer related to
multi-segment support. The MI ACPI PCI code was using a shared PCI
chipset tag to access devices, and these accesses can happen before our
PCI host bridge drivers are attached! The global chipset tag is now gone,
and an MD callback can provide a custom tag on a per-segment basis.

Use "non-posted" instead of "strongly ordered" to describe nGnRnE mappings

Rename the following defines:
- _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED to BUS_SPACE_MAP_NONPOSTED
- PMAP_DEV_SO to PMAP_DEV_NP
- LX_BLKPAG_ATTR_DEVICE_MEM_SO to LX_BLKPAG_ATTR_DEVICE_MEM_NP
Rename the following option:
- AARCH64_DEVICE_MEM_STRONGLY_ORDERED to AARCH64_DEVICE_MEM_NONPOSTED

<sys/extent.h> not needed here.

Use sys/cpu.h so that curcpu defined in terms of curlwp->l_cpu works too.

branches: 1.2.2; 1.2.6;
Map and read MCFG space directly instead of going through acpimcfg to
simplify access through our tiny config space window.

Add support for NXP Layerscape PCIe Gen4 (not ECAM compliant)

arm: acpi: Improve legacy INTx support.

For devices on a bus with no direct _PRT, use the raw intr pin with the
parent bridge's slot number to derive a pin number that can be used to
lookup the pin -> irq mapping in the parent bus's _PRT.

Remove unneeded struct acpi_pci_intr forward declaration.

Install the shared PCI INTx interrupt handler at IPL_VM to workaround a
possible interrupt storm at boot. Need to revisit this.

arm: acpi: Add support for SMCCC based PCI config access.

<sys/extent.h> not needed here.

Use sys/cpu.h so that curcpu defined in terms of curlwp->l_cpu works too.

Add support for multiple GICv3 ITS domains.

Add support for NXP Layerscape PCIe Gen4 (not ECAM compliant)

Add support for sharing legacy PCI interrupt sources.

Add support for Arm N1 SDP PCIe host controller.

The N1 SDP has a few bugs that we need to work around:
- PCIe root port config space lives in a non-standard location.
- Access to PCIe config space of devices that do not exist results in
an sync SError. Firmware creates a "known devices" table at a fixed
physical address that we use to filter PCI conf access to only known
devices.

This change splits the Arm ACPI PCI quirks into separate files for each
host controller, and allows per-segment quirks to be applied.

These changes exposed some bugs in the MI ACPI layer related to
multi-segment support. The MI ACPI PCI code was using a shared PCI
chipset tag to access devices, and these accesses can happen before our
PCI host bridge drivers are attached! The global chipset tag is now gone,
and an MD callback can provide a custom tag on a per-segment basis.

branches: 1.12.2;
Amazon Graviton maxdevs quirk no longer required as of pci.c r1.155

More Amazon Graviton quirks:
- Ignore devno > 0 on the PCIe root port.
- Fixup PCIe bridge bus number register on the root port.
- Move quirk handling to acpipchb so it can be applied before the bus
is configured.

Add quirks for Amazon Graviton PCIe root ports. Configuration space for the
root port is found in a child AMZN0001 resource, not the MCFG table.

branches: 1.9.4; 1.9.6;
Add support for decoding PCI ID mappings using IO remapping tables (IORT).

Add intr_establish_xname support to arm and expose it to intrctl

Match _PRT by segment and bus

Add support for multiple PCI segments.

Add MSI-X support

Do not add PCI link references until the bus has been mapped

Add support for PCI MSI using ARM GICv2m.

branches: 1.2.2;
Add support for PCI Segment Groups.

Add ARM ACPI PCI support.

arm: acpi: Add support for SMCCC based PCI config access.

Add support for NXP Layerscape PCIe Gen4 (not ECAM compliant)

Add support for Arm N1 SDP PCIe host controller.

The N1 SDP has a few bugs that we need to work around:
- PCIe root port config space lives in a non-standard location.
- Access to PCIe config space of devices that do not exist results in
an sync SError. Firmware creates a "known devices" table at a fixed
physical address that we use to filter PCI conf access to only known
devices.

This change splits the Arm ACPI PCI quirks into separate files for each
host controller, and allows per-segment quirks to be applied.

These changes exposed some bugs in the MI ACPI layer related to
multi-segment support. The MI ACPI PCI code was using a shared PCI
chipset tag to access devices, and these accesses can happen before our
PCI host bridge drivers are attached! The global chipset tag is now gone,
and an MD callback can provide a custom tag on a per-segment basis.

branches: 1.5.2;
Amazon Graviton maxdevs quirk no longer required as of pci.c r1.155

More Amazon Graviton quirks:
- Ignore devno > 0 on the PCIe root port.
- Fixup PCIe bridge bus number register on the root port.
- Move quirk handling to acpipchb so it can be applied before the bus
is configured.

Add quirks for Amazon Graviton PCIe root ports. Configuration space for the
root port is found in a child AMZN0001 resource, not the MCFG table.

branches: 1.2.2; 1.2.6; 1.2.8;
Add support for PCI Segment Groups.

Add ARM ACPI PCI support.

Use "non-posted" instead of "strongly ordered" to describe nGnRnE mappings

Rename the following defines:
- _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED to BUS_SPACE_MAP_NONPOSTED
- PMAP_DEV_SO to PMAP_DEV_NP
- LX_BLKPAG_ATTR_DEVICE_MEM_SO to LX_BLKPAG_ATTR_DEVICE_MEM_NP
Rename the following option:
- AARCH64_DEVICE_MEM_STRONGLY_ORDERED to AARCH64_DEVICE_MEM_NONPOSTED

Trailing whitespace

Make Arm MD ACPI code big endian friendly.

<sys/extent.h> not needed here.

Use sys/cpu.h so that curcpu defined in terms of curlwp->l_cpu works too.

branches: 1.2.4;
Enable MSI and MSI-X support on N1SDP

branches: 1.1.2;
Add support for Arm N1 SDP PCIe host controller.

The N1 SDP has a few bugs that we need to work around:
- PCIe root port config space lives in a non-standard location.
- Access to PCIe config space of devices that do not exist results in
an sync SError. Firmware creates a "known devices" table at a fixed
physical address that we use to filter PCI conf access to only known
devices.

This change splits the Arm ACPI PCI quirks into separate files for each
host controller, and allows per-segment quirks to be applied.

These changes exposed some bugs in the MI ACPI layer related to
multi-segment support. The MI ACPI PCI code was using a shared PCI
chipset tag to access devices, and these accesses can happen before our
PCI host bridge drivers are attached! The global chipset tag is now gone,
and an MD callback can provide a custom tag on a per-segment basis.

fix indentation

arm: acpi: Add support for SMCCC based PCI config access.

Use device_setprop_bool() for "force_console".

Refactor the "platform" defitions into fdt_platform.h

acpi: Try PSCI before UEFI RT for shutdown/reset.

BSA says that an OS can use either UEFI RT or PSCI, and that the RT
implementation should just call PSCI.

Given the amount of implementation issues with UEFI RT, let's try PSCI
first, because it's nice to be able to reboot and poweroff even with
buggy firmware.

aarch64: Add NUMA awareness for ACPI systems with SRAT tables.

On an Ampere Altra w/ hemisphere mode enabled:

[ 1.0000000] cpu0: package 16, core 0, smt 0, numa 0
[...]
[ 1.0000000] cpu32: package 22, core 0, smt 0, numa 1

[ 1.000004] SRAT: 2 NUMA nodes
[ 1.000004] SRAT: node 0 memory range 0 (0x88300000 - 0x88400000 flags 1)
[ 1.000004] SRAT: node 0 memory range 1 (0x90000000 - 0x100000000 flags 1)
[ 1.000004] SRAT: node 0 memory range 2 (0x80000000000 - 0x80080000000 flags 1)
[ 1.000004] SRAT: node 0 memory range 3 (0x80100000000 - 0x81000000000 flags 1)
[ 1.000004] SRAT: node 1 memory range 0 (0xc0000000000 - 0xc1000000000 flags 1)

branches: 1.36.6;
Rename ARM_PLATFORM to FDT_PLATFORM and make it available outside arm.

Add support for FIFOs and hardware flow-control to plcom driver.
Add a PLCOM_TYPE_GENERIC_UART variant to match SBSA requirements.

typo in comment

Use the ACPICA define ACPI_DBG2_16550_WITH_GAS

More SPCR cleanup:

- For 16550 style UARTs, always honour GAS if BitWidth != 0
- Use BitWidth instead of AccessWidth to determine register stride
- For baud rate ID of 0, assume 115200 until we have a way of probing
the baud rate configured by firmware.

It seems that there are three 16550 types for SPCR:

- 0x0000: Fully 16550-compatible (1-byte I/O)
- 0x0001: 16550 subset compatible with DBGP Revision 1 (4-byte MMIO)
- 0x0012: 16550-compatible with parameters defined in GAS

So assume reg_width for types 0 and 1, and only look at GAS for type 12h.

baud_rate is signed now

SPCR_BAUD_DEFAULT maps better to -1 than 0

Suggested by jmcneill@

acpi: call smccc_probe() after PSCI init

Arm: Add support for SMC Calling Convention

Arm DEN0028 defines a calling mechanism used with Secure Monitor Call (SMC)
and Hypervisor Call (HVC) instructions. To discover SMCCC, we must:

1) Find the PSCI conduit (either via ACPI FADT, or Device Tree)
2) Use PSCI_VERSION to determine whether PSCI_FEATURES is supported
3) Call PSCI_FEATURES with SMCCC_VERSION to determine the implementation
version.

- Define a device call for PCI bus instances to fetch a direct child's
device handle given the device's device/function #s (extracted from
a pcitag_t). Use it to associate the handle with the child device
at config_found() time.
- Implement this device call for ACPI and OpenFirmware.
- Enable the OpenFirmware variant for evbarm FDT, macppc, ofppc, sparc64.
- Obsolete acpi_device_register(); it is no longer needed.
- Obsolete setting the OpenFirmware handle in PCI devices in the
sparc64 device_register(); it is no longer needed.

branches: 1.25.2; 1.25.4;
Merge thorpej-cfargs branch:

Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.

Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
actually needed.
- Don't be explicit about what interface attribute is attaching if
the device only has one. (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
situations, making is visibly easier to see when indirect config is
in play, and allowing for future change in semantics. (As of now,
this is just a wrapper around config_match(), but that is an
implementation detail.)

Remove unnecessary or redundant interface attributes where they're not
needed.

There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)

...and a sentinel value CFARG_EOL.

Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.

Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance. This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).

branches: 1.24.2;
Reset serial terminal to default state at boot.

UEFI may leave the serial console in an undesireable state (incorrect
foreground and background colour, etc) when exiting. Send ANSI escape
sequences when setting up the early console attachments to turn off
character attributes and erase from the cursor to the end of the screen.

Call acpi_device_register() / fdtbus_device_register() as approrpriate.

acpi: Cleanup SPCR setup and style fixes.

branches: 1.21.2;
Support early FB console attachment when booting with a devicetree
(non-ACPI mode). Inform the pciconf code about the framebuffer to
prevent pciconf from changing resources out from under us when framebuffer
memory is in VRAM.

Get rid of a4x bus_space tag from fdtbus_attach_args. The only consumer
of this was various com(4) glue so modify all of that to use the new
com_init_regs_stride instead.

Make Arm MD ACPI code big endian friendly.

Use vcons for simplefb preattach to speed up early console messages.

Use a unique name for the acpi ARM_PLATFORM definition

Ignore AccessWidth (PL011 and SBSA console always needs 32-bit access)

branches: 1.15.2;
Add early fb console support

Finish the job

Provide a 64-bit dma tag and use a coherent tag unless CCA=0

branches: 1.12.2;
fix build without options MULTIPROCESSOR

Use SPCR to force console selection for com@acpi. This is needed because
we may use a non-standard bus_space tag (a4x) to attach the console early,
which breaks com_is_console.

Force a matching com@puc by seg/bus/dev/func to be the console device if specified in SPCR

Replace SPCR_INTERFACE_TYPE_* defines with ACPI_DBG2_* from acpica. Suggested by msaitoh@

Add support for SPCR 16550 and 16450 interface types

Allow building when plcom isn't used.

Retire fdt_putchar and ap_early_put_char in favour of uartputc.

Add support for EFI runtime services on aarch64.

branches: 1.4.2;
Fix BCM2835 console support.

Handle more plcom-style console types

Don't rely on PSCI node in FDT to reboot

Add ACPI platform glue and basic device drivers (CPU, GIC, Generic Timer,
SBSA UART).

Support early FB console attachment when booting with a devicetree
(non-ACPI mode). Inform the pciconf code about the framebuffer to
prevent pciconf from changing resources out from under us when framebuffer
memory is in VRAM.

branches: 1.2.6;
Do not attach simplefb if the width or height are invalid

branches: 1.1.2; 1.1.4;
Use vcons for simplefb preattach to speed up early console messages.

Support early FB console attachment when booting with a devicetree
(non-ACPI mode). Inform the pciconf code about the framebuffer to
prevent pciconf from changing resources out from under us when framebuffer
memory is in VRAM.

branches: 1.1.2; 1.1.10;
Use vcons for simplefb preattach to speed up early console messages.

Make Arm MD ACPI code big endian friendly.

branches: 1.1.2; 1.1.6;
Add helper functions used for parsing ACPI tables before the ACPICA
subsystem can be brought online. ARM64 needs this primarily for
initializing the SBSA UART via SPCR table, reading ARM boot flags from the
FADT, counting CPUs, etc.

branches: 1.1.2; 1.1.6;
Add helper functions used for parsing ACPI tables before the ACPICA
subsystem can be brought online. ARM64 needs this primarily for
initializing the SBSA UART via SPCR table, reading ARM boot flags from the
FADT, counting CPUs, etc.

acpi: i2c: only claim child devices with a _CRS or _ADR method

acpi_enter_i2c_devs is too aggressive with claiming child device nodes.
Restrict it to devices with either a _CRS or _ADR method. A driver is
free to claim more if appropriate.

Fixes missing HKEY (LEN0268) device on Thinkpad T14s Gen 6 (X1E).

branches: 1.32.8;
Use "non-posted" instead of "strongly ordered" to describe nGnRnE mappings

Rename the following defines:
- _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED to BUS_SPACE_MAP_NONPOSTED
- PMAP_DEV_SO to PMAP_DEV_NP
- LX_BLKPAG_ATTR_DEVICE_MEM_SO to LX_BLKPAG_ATTR_DEVICE_MEM_NP
Rename the following option:
- AARCH64_DEVICE_MEM_STRONGLY_ORDERED to AARCH64_DEVICE_MEM_NONPOSTED

Add a PCI resource manager and use it on Arm ACPI platforms.

The Arm ACPI code relied on PCI_NETBSD_CONFIGURE to configure devices that
were not enabled by system firmware. This is not safe to do unless the
firmware explicitly permits it using a device specific method defined in
the PCI firmware spec.

Introduce a new PCI resource manager that discovers what has already been
configured by firmware and allocates from the remaining space. This will
ensure that devices setup by firmware are untouched and only will program
BARs of devices that are not enabled at boot time.

The current implementation assumes that the parent PCI-PCI bridge's
are already configured. A worthwhile improvement in the future would be
to support programming windows for bridges that are not fully configured.

Add "nopcimsi" boot option to force legacy INTx only mode.

acpipchb: Add a kernel cmdline option to skip PCI resource assignment.

Passing "nopciconf" to the kernel will force acpipchb to skip PCI
resource assignment.

Disable MSI if the linux,pcie-nomsi flag is present

arm: acpi: Add support for SMCCC based PCI config access.

Merge thorpej-cfargs2.

branches: 1.25.4;
Pass along our devhandle to the PCI bus instance we attach.

branches: 1.24.2; 1.24.4;
Merge thorpej-cfargs branch:

Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.

Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
actually needed.
- Don't be explicit about what interface attribute is attaching if
the device only has one. (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
situations, making is visibly easier to see when indirect config is
in play, and allowing for future change in semantics. (As of now,
this is just a wrapper around config_match(), but that is an
implementation detail.)

Remove unnecessary or redundant interface attributes where they're not
needed.

There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)

...and a sentinel value CFARG_EOL.

Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.

Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance. This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).

branches: 1.23.2;
acpipchb is a bus, so claim all child ACPI device nodes

Style fixes. NFC.

branches: 1.21.2;
Trailing whitespace

<sys/extent.h> not needed here.

Use sys/cpu.h so that curcpu defined in terms of curlwp->l_cpu works too.

Try to get the starting bus number from _CRS before falling back to _BBN.
There are apparently cases where the first bus in _CRS does not match the
value of _BBN, and the consensus is that _CRS should take precedence.

Provide a properly constrained 32-bit DMA tag to ACPI.

Add support for Arm N1 SDP PCIe host controller.

The N1 SDP has a few bugs that we need to work around:
- PCIe root port config space lives in a non-standard location.
- Access to PCIe config space of devices that do not exist results in
an sync SError. Firmware creates a "known devices" table at a fixed
physical address that we use to filter PCI conf access to only known
devices.

This change splits the Arm ACPI PCI quirks into separate files for each
host controller, and allows per-segment quirks to be applied.

These changes exposed some bugs in the MI ACPI layer related to
multi-segment support. The MI ACPI PCI code was using a shared PCI
chipset tag to access devices, and these accesses can happen before our
PCI host bridge drivers are attached! The global chipset tag is now gone,
and an MD callback can provide a custom tag on a per-segment basis.

branches: 1.15.2;
Allow MD code to provide custom bus_dma tags on a per-node basis. On Arm
this is required to return non-coherent bus_dma tags for device nodes with
_CCA=0

Do not use Early Write Acknowledge for PCIe I/O and config space.

Amazon Graviton maxdevs quirk no longer required as of pci.c r1.155

Fix detection of root port resources for Graviton and remove no longer required bridge fixup

More Amazon Graviton quirks:
- Ignore devno > 0 on the PCIe root port.
- Fixup PCIe bridge bus number register on the root port.
- Move quirk handling to acpipchb so it can be applied before the bus
is configured.

Add quirks for Amazon Graviton PCIe root ports. Configuration space for the
root port is found in a child AMZN0001 resource, not the MCFG table.

branches: 1.9.2;
Honour _CRS mem ranges and translation offsets instead of assuming 1:1
mappings. Tested on Overdrive 1000.

Provide a 64-bit dma tag and use a coherent tag unless CCA=0

branches: 1.7.4;
On second thought, get rid of "bs_base" from struct bus_space and use a
custom bs_map for acpipchb instead.

Add support for PCI I/O space.

Restore acpi_pci_ignore_boot_config lost in previous commit

Add intr_establish_xname support to arm and expose it to intrctl

Only configure PCI bus if _DSM rev 1 func 5 ("Ignore PCI boot configuration") returns 1

branches: 1.2.2;
Add support for PCI Segment Groups.

Add ARM ACPI PCI support.

arm: acpi: Early return when a CPU is not configured

arm64: Enable support for low power idle CPU states on ACPI platforms.

The ACPI CPU driver parses the _LPI package on each CPU and builds a
table of supported low power states. A custom cpu_idle() implementation
is registered that uses the time previously spent idle to select an
entry method for low power on the next idle entry.

A boot option, "nolpi", can be used to ignore _LPI and use the normal
WFI idle method.

This decreases the battery discharge rate on my Snapdragon X1E laptop from
~17W to ~10W when idle.

aarch64: Add NUMA awareness for ACPI systems with SRAT tables.

On an Ampere Altra w/ hemisphere mode enabled:

[ 1.0000000] cpu0: package 16, core 0, smt 0, numa 0
[...]
[ 1.0000000] cpu32: package 22, core 0, smt 0, numa 1

[ 1.000004] SRAT: 2 NUMA nodes
[ 1.000004] SRAT: node 0 memory range 0 (0x88300000 - 0x88400000 flags 1)
[ 1.000004] SRAT: node 0 memory range 1 (0x90000000 - 0x100000000 flags 1)
[ 1.000004] SRAT: node 0 memory range 2 (0x80000000000 - 0x80080000000 flags 1)
[ 1.000004] SRAT: node 0 memory range 3 (0x80100000000 - 0x81000000000 flags 1)
[ 1.000004] SRAT: node 1 memory range 0 (0xc0000000000 - 0xc1000000000 flags 1)

branches: 1.15.2;
kern/58195: arm: Support drvctl -d and -r for cpufeaturebus

This is required for detaching and re-attaching the vmt(4) driver on aarch64.

tprof: armv8: Only attach to known PMU types.

Improve error handling.

Hypervisors can return a PMCR.N of 0.

arm64: acpi: Set capacity_dmips_mhz for CPUs

The GICC structure describes a relative power efficiency for each
processor. Use this value as-is for the capacity_dmips_mhz value of a
cpu. This makes the assumption that "more efficient" means "slower".

Fix primary CPU detection in cpu_acpi_tprof_intr_establish

fit in 80 columns

Provide and use a sev() macro for the sev instruction.

While here use the correct barrier to ensure completion of memory accesses
before a couple of the sev() calls.

branches: 1.8.6;
Various updates and improvements to cpu start up on arm/aarch64

- start sharing more code around the AP startup messaging.
- call arm_cpu_topology_set early so that ci_core_id is available for
drivers, e.g. bcm2835_intr.c
- both arm and aarch64 now have
- a static cpu_info_store array
- the same arm_cpu_{hatched,mbox}

branches: 1.7.2;
Increase aarch64 MAXCPUS to 256.

branches: 1.6.2; 1.6.4;
fix build without options MULTIPROCESSOR

Add CPU performance counter support

branches: 1.4.2;
Store the ACPI Processor UID in struct cpu_info

Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.

The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors. AP startup is
performed in less steps and more code is written in C.

The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.

Various kernels have been converted to use this code and tested. Some
boards were provided by TNF. Thanks!

The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.

Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively

Only attach to usable processors

Add ACPI platform glue and basic device drivers (CPU, GIC, Generic Timer,
SBSA UART).

arm: acpi: Add support for SMCCC based PCI config access.

acpicpu: Add support for ACPI P-states and T-states on Arm.

branches: 1.11.2;
Support early FB console attachment when booting with a devicetree
(non-ACPI mode). Inform the pciconf code about the framebuffer to
prevent pciconf from changing resources out from under us when framebuffer
memory is in VRAM.

Add support for NXP Layerscape PCIe Gen4 (not ECAM compliant)

Add support for Arm N1 SDP PCIe host controller.

The N1 SDP has a few bugs that we need to work around:
- PCIe root port config space lives in a non-standard location.
- Access to PCIe config space of devices that do not exist results in
an sync SError. Firmware creates a "known devices" table at a fixed
physical address that we use to filter PCI conf access to only known
devices.

This change splits the Arm ACPI PCI quirks into separate files for each
host controller, and allows per-segment quirks to be applied.

These changes exposed some bugs in the MI ACPI layer related to
multi-segment support. The MI ACPI PCI code was using a shared PCI
chipset tag to access devices, and these accesses can happen before our
PCI host bridge drivers are attached! The global chipset tag is now gone,
and an MD callback can provide a custom tag on a per-segment basis.

branches: 1.8.2;
Add support for Amazon's Graviton MSI controller.

Graviton has a GICv3 with a modified GICv2m (!) for MSIs. Instead of
sending messages to a fixed address with the SPI as data, the Graviton's
GICv2m uses a different address for each vector with "don't care" as data.

Use vcons for simplefb preattach to speed up early console messages.

branches: 1.6.4; 1.6.6;
Add support for decoding PCI ID mappings using IO remapping tables (IORT).

Support building kernels with ACPI and no PCI.

Add driver for ARM Server Base System Architecture (SBSA)-compliant
generic watchdog timers.

Add GICv3 ACPI attachment glue.

branches: 1.2.2;
Add ARM ACPI PCI support.

Add ACPI platform glue and basic device drivers (CPU, GIC, Generic Timer,
SBSA UART).

gicv2: Fix truncation of GICC / GICD base addresses above 4GB.

branches: 1.7.6;
Merge thorpej-cfargs2.

branches: 1.6.8;
Merge thorpej-cfargs branch:

Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.

Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
actually needed.
- Don't be explicit about what interface attribute is attaching if
the device only has one. (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
situations, making is visibly easier to see when indirect config is
in play, and allowing for future change in semantics. (As of now,
this is just a wrapper around config_match(), but that is an
implementation detail.)

Remove unnecessary or redundant interface attributes where they're not
needed.

There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)

...and a sentinel value CFARG_EOL.

Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.

Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance. This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).

branches: 1.5.4;
Skip v2m probe if armgic fails to attach

Add support for Amazon's Graviton MSI controller.

Graviton has a GICv3 with a modified GICv2m (!) for MSIs. Instead of
sending messages to a fixed address with the SPI as data, the Graviton's
GICv2m uses a different address for each vector with "don't care" as data.

branches: 1.3.4; 1.3.6;
Support building kernels with ACPI and no PCI.

Add support for PCI MSI using ARM GICv2m.

branches: 1.1.2;
Add ACPI platform glue and basic device drivers (CPU, GIC, Generic Timer,
SBSA UART).

branches: 1.1.2; 1.1.10;
Add support for Amazon's Graviton MSI controller.

Graviton has a GICv3 with a modified GICv2m (!) for MSIs. Instead of
sending messages to a fixed address with the SPI as data, the Graviton's
GICv2m uses a different address for each vector with "don't care" as data.

branches: 1.1.2; 1.1.10;
Add support for Amazon's Graviton MSI controller.

Graviton has a GICv3 with a modified GICv2m (!) for MSIs. Instead of
sending messages to a fixed address with the SPI as data, the Graviton's
GICv2m uses a different address for each vector with "don't care" as data.

Future-proof ID_AA64PFR0_EL1.GIC test -- any value other than 0 means that
the GIC CPU interface is supported.

branches: 1.7.6;
Add support for multiple GICv3 ITS domains.

Only attach the first ITS for now

branches: 1.5.2;
Add support for Amazon's Graviton MSI controller.

Graviton has a GICv3 with a modified GICv2m (!) for MSIs. Instead of
sending messages to a fixed address with the SPI as data, the Graviton's
GICv2m uses a different address for each vector with "don't care" as data.

Redistributors with virtual LPI support have larger register spaces. Take
this into consideration when scanning LPI regions.

branches: 1.3.2; 1.3.6; 1.3.8;
Support building kernels with ACPI and no PCI.

Add GICv3 ITS support

Add GICv3 ACPI attachment glue.

Merge thorpej-cfargs2.

branches: 1.4.8;
Merge thorpej-cfargs branch:

Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.

Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
actually needed.
- Don't be explicit about what interface attribute is attaching if
the device only has one. (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
situations, making is visibly easier to see when indirect config is
in play, and allowing for future change in semantics. (As of now,
this is just a wrapper around config_match(), but that is an
implementation detail.)

Remove unnecessary or redundant interface attributes where they're not
needed.

There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)

...and a sentinel value CFARG_EOL.

Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.

Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance. This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).

branches: 1.3.2; 1.3.14;
Catch up with constant name change.

Use intr_establish_xname

branches: 1.1.2;
Add ACPI platform glue and basic device drivers (CPU, GIC, Generic Timer,
SBSA UART).

Add support for FIFOs and hardware flow-control to plcom driver.
Add a PLCOM_TYPE_GENERIC_UART variant to match SBSA requirements.

Enable HW FIFO

branches: 1.2.4;
Use acpi_intr_establish

branches: 1.1.2;
Add ACPI platform glue and basic device drivers (CPU, GIC, Generic Timer,
SBSA UART).

branches: 1.2.2; 1.2.6;
Avoid overflow when calculating watchdog offset.

Add driver for ARM Server Base System Architecture (SBSA)-compliant
generic watchdog timers.