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History log of /src/sys/arch/arm/acpi
RevisionDateAuthorComments
 1.1 07-Dec-2020  jmcneill branches: 1.1.2;
acpicpu: Add support for ACPI P-states and T-states on Arm.
 1.1.2.2 14-Dec-2020  thorpej Sync w/ HEAD.
 1.1.2.1 07-Dec-2020  thorpej file acpi_cpu_md.c was added on branch thorpej-futex on 2020-12-14 14:37:47 +0000
 1.5 09-Dec-2024  jmcneill arm64: acpi: Honour DMA memory address limit for named components.
 1.4 13-Sep-2020  jmcneill branches: 1.4.26;
Make Arm MD ACPI code big endian friendly.
 1.3 13-Feb-2020  jmcneill Add support for multiple GICv3 ITS domains.
 1.2 07-Feb-2020  jmcneill Single mappings are translated to OutputBase, not InputBase
 1.1 08-Dec-2018  jmcneill branches: 1.1.2; 1.1.6; 1.1.10;
Add support for decoding PCI ID mappings using IO remapping tables (IORT).
 1.1.10.1 29-Feb-2020  ad Sync with head.
 1.1.6.3 08-Apr-2020  martin Merge changes from current as of 20200406
 1.1.6.2 10-Jun-2019  christos Sync with HEAD
 1.1.6.1 08-Dec-2018  christos file acpi_iort.c was added on branch phil-wifi on 2019-06-10 22:05:50 +0000
 1.1.2.2 26-Dec-2018  pgoyette Sync with HEAD, resolve a few conflicts
 1.1.2.1 08-Dec-2018  pgoyette file acpi_iort.c was added on branch pgoyette-compat on 2018-12-26 14:01:32 +0000
 1.4.26.1 02-Aug-2025  perseant Sync with HEAD
 1.3 09-Dec-2024  jmcneill arm64: acpi: Honour DMA memory address limit for named components.
 1.2 13-Feb-2020  jmcneill branches: 1.2.30;
Add support for multiple GICv3 ITS domains.
 1.1 08-Dec-2018  jmcneill branches: 1.1.2; 1.1.6; 1.1.10;
Add support for decoding PCI ID mappings using IO remapping tables (IORT).
 1.1.10.1 29-Feb-2020  ad Sync with head.
 1.1.6.3 08-Apr-2020  martin Merge changes from current as of 20200406
 1.1.6.2 10-Jun-2019  christos Sync with HEAD
 1.1.6.1 08-Dec-2018  christos file acpi_iort.h was added on branch phil-wifi on 2019-06-10 22:05:50 +0000
 1.1.2.2 26-Dec-2018  pgoyette Sync with HEAD, resolve a few conflicts
 1.1.2.1 08-Dec-2018  pgoyette file acpi_iort.h was added on branch pgoyette-compat on 2018-12-26 14:01:32 +0000
 1.2.30.1 02-Aug-2025  perseant Sync with HEAD
 1.28 30-Dec-2024  jmcneill arm: ACPI: Fix EFI_MEMORY_UC memory type.

The UEFI specification says that EFI_MEMORY_UC should be treated as
Device-nGnRnE (UEFI 2.10, 2.3.6.1 AArch64 Platforms - Memory types).
 1.27 09-Dec-2024  jmcneill arm64: acpi: Honour DMA memory address limit for named components.
 1.26 15-Oct-2022  jmcneill branches: 1.26.8;
Use "non-posted" instead of "strongly ordered" to describe nGnRnE mappings

Rename the following defines:
- _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED to BUS_SPACE_MAP_NONPOSTED
- PMAP_DEV_SO to PMAP_DEV_NP
- LX_BLKPAG_ATTR_DEVICE_MEM_SO to LX_BLKPAG_ATTR_DEVICE_MEM_NP
Rename the following option:
- AARCH64_DEVICE_MEM_STRONGLY_ORDERED to AARCH64_DEVICE_MEM_NONPOSTED
 1.25 08-Aug-2021  jmcneill arm: ACPI: Add support for simple sharing of platform interrupts

Allow sharing of platform interrupts provided that the type, ipl, and
mpsafe-ness are the same.
 1.24 07-Aug-2021  jmcneill acpi: DMA: Use acpi_resource_parse_any to parse _DMA resources

_DMA resources really should be marked ResourceProducer, so use
acpi_resource_parse_any to pick these up.
 1.23 07-Aug-2021  thorpej Merge thorpej-cfargs2.
 1.22 24-Apr-2021  thorpej branches: 1.22.8;
Merge thorpej-cfargs branch:

Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.

Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
actually needed.
- Don't be explicit about what interface attribute is attaching if
the device only has one. (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
situations, making is visibly easier to see when indirect config is
in play, and allowing for future change in semantics. (As of now,
this is just a wrapper around config_match(), but that is an
implementation detail.)

Remove unnecessary or redundant interface attributes where they're not
needed.

There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)

...and a sentinel value CFARG_EOL.

Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.

Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance. This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).
 1.21 13-Dec-2020  jmcneill branches: 1.21.2;
Add MI support for attaching drivers to arbitrary System Description
Tables.
 1.20 24-Oct-2020  skrll branches: 1.20.2;
Trailing whitespace
 1.19 21-Jan-2020  jmcneill Provide a properly constrained 32-bit DMA tag to ACPI.
 1.18 31-Dec-2019  jmcneill branches: 1.18.2;
Rely on 32/64-bit overflow to calculate translation offsets. Store this
as a separate ar_xbase field in acpi_mem instead of having separate
ar_offset and ar_decode fields.
 1.17 31-Dec-2019  jmcneill Create bus_dma tags for each device node based on _CCA and _DMA properties
found by walking up the device node tree. These tags encode range
restrictions, address translations, and whether or not the device is
cache coherent.
 1.16 31-Dec-2019  jmcneill The DMA restrictions may not be defined in the direct parent of a device,
so search up the tree for a module device.
 1.15 30-Dec-2019  jmcneill If a device node is a child of a module device, and the module device declares DMA range restrictions, use them.
 1.14 29-Dec-2019  jmcneill Allow MD code to provide custom bus_dma tags on a per-node basis. On Arm
this is required to return non-coherent bus_dma tags for device nodes with
_CCA=0
 1.13 28-Dec-2019  jmcneill Do not use Early Write Acknowledge for PCIe I/O and config space.
 1.12 23-Dec-2019  jmcneill Implement acpi_md_intr_mask and acpi_md_intr_unmask
 1.11 22-Dec-2019  thorpej Add acpi_intr_mask() and acpi_intr_unmask() which, following the pre-existing
ACPI software layering model, are wrappers around acpi_md_intr_mask() and
acpi_md_intr_unmask(), which in turn are wrappers around intr_mask() and
intr_unmask().

XXX ARM and IA64 implementations of acpi_md_intr_mask() and
acpi_md_intr_unmask() are just stubs for now.
 1.10 12-Aug-2019  skrll Use same style test as acpi_md_OsWritable
 1.9 12-Aug-2019  skrll Correct the test for writeable memory. There aren't any users of this at
this point.
 1.8 01-Aug-2019  jmcneill Always map ACPI table memory as normal memory. Always map device memory as device memory.
 1.7 01-Aug-2019  jmcneill acpi_md_OsMapMemory can be used for both normal and device memory. Use the
UEFI memory map to determine how to map a given region.
 1.6 16-Nov-2018  jmcneill branches: 1.6.4; 1.6.6;
Add MD functions for establishing and disestablishing interrupt handlers.
 1.5 12-Nov-2018  jmcneill Support building kernels with ACPI and no PCI.
 1.4 21-Oct-2018  jmcneill Don't make assumptions about the order of MADT subtables. Ensure that we
attach CPUs before the interrupt controller driver.
 1.3 16-Oct-2018  jmcneill branches: 1.3.2;
Fix size calculation in acpi_md_OsUnmapMemory
 1.2 15-Oct-2018  jmcneill Add ARM ACPI PCI support.
 1.1 12-Oct-2018  jmcneill Add ARM MD ACPI implementation.
 1.3.2.3 26-Nov-2018  pgoyette Sync with HEAD, resolve a couple of conflicts
 1.3.2.2 20-Oct-2018  pgoyette Sync with head
 1.3.2.1 16-Oct-2018  pgoyette file acpi_machdep.c was added on branch pgoyette-compat on 2018-10-20 06:58:24 +0000
 1.6.6.3 29-Dec-2019  martin Pull up following revision(s) (requested by jmcneill in ticket #586):

sys/arch/arm/nvidia/tegra_pcie.c: revision 1.27
sys/arch/aarch64/aarch64/pmap.c: revision 1.57
sys/arch/aarch64/aarch64/locore.S: revision 1.48
sys/arch/aarch64/include/armreg.h: revision 1.29
sys/arch/aarch64/aarch64/pmap.c: revision 1.58
sys/arch/aarch64/aarch64/locore.S: revision 1.49
sys/arch/arm/acpi/acpipchb.c: revision 1.14
sys/arch/aarch64/aarch64/genassym.cf: revision 1.16
sys/arch/arm/acpi/acpi_machdep.c: revision 1.13
sys/arch/aarch64/include/pmap.h: revision 1.27
sys/arch/aarch64/aarch64/genassym.cf: revision 1.17
sys/arch/aarch64/include/pmap.h: revision 1.28
sys/arch/arm/fdt/pcihost_fdtvar.h: revision 1.3
sys/arch/arm/include/bus_defs.h: revision 1.14
sys/arch/aarch64/aarch64/bus_space.c: revision 1.9
sys/arch/arm/fdt/pcihost_fdt.c: revision 1.12
sys/arch/aarch64/conf/files.aarch64: revision 1.15
sys/arch/aarch64/conf/files.aarch64: revision 1.16
sys/arch/arm/rockchip/rk3399_pcie.c: revision 1.9

Enable early write acknowledge for device memory mappings.

Do not use Early Write Acknowledge for PCIe I/O and config space.
 1.6.6.2 12-Aug-2019  martin Pull up following revision(s) (requested by skrll in ticket #48):

sys/arch/arm/acpi/acpi_machdep.c: revision 1.9
sys/arch/arm/acpi/acpi_machdep.c: revision 1.10

Correct the test for writeable memory. There aren't any users of this at
this point.

Use same style test as acpi_md_OsWritable
 1.6.6.1 04-Aug-2019  martin Pull up following revision(s) (requested by jmcneill in ticket #3):

sys/stand/efiboot/efiacpi.c: revision 1.4
sys/stand/efiboot/efifdt.c: revision 1.18
sys/stand/efiboot/version: revision 1.12
sys/arch/arm/acpi/acpi_machdep.c: revision 1.7
sys/arch/arm/acpi/acpi_machdep.c: revision 1.8

Add full UEFI memory map to the /chosen node.

-

acpi_md_OsMapMemory can be used for both normal and device memory. Use the
UEFI memory map to determine how to map a given region.

Always map ACPI table memory as normal memory. Always map device memory as device memory.
 1.6.4.4 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.6.4.3 08-Apr-2020  martin Merge changes from current as of 20200406
 1.6.4.2 10-Jun-2019  christos Sync with HEAD
 1.6.4.1 16-Nov-2018  christos file acpi_machdep.c was added on branch phil-wifi on 2019-06-10 22:05:50 +0000
 1.18.2.1 25-Jan-2020  ad Sync with head.
 1.20.2.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.21.2.2 17-Apr-2021  thorpej acpi_md_gtdt_probe(): Fix paste-o in interface attribute name.
 1.21.2.1 02-Apr-2021  thorpej config_found_ia() -> config_found() w/ CFARG_IATTR.
 1.22.8.1 04-Aug-2021  thorpej Adapt to CFARGS().
 1.26.8.1 02-Aug-2025  perseant Sync with HEAD
 1.5 15-Oct-2022  jmcneill Use "non-posted" instead of "strongly ordered" to describe nGnRnE mappings

Rename the following defines:
- _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED to BUS_SPACE_MAP_NONPOSTED
- PMAP_DEV_SO to PMAP_DEV_NP
- LX_BLKPAG_ATTR_DEVICE_MEM_SO to LX_BLKPAG_ATTR_DEVICE_MEM_NP
Rename the following option:
- AARCH64_DEVICE_MEM_STRONGLY_ORDERED to AARCH64_DEVICE_MEM_NONPOSTED
 1.4 24-Oct-2020  skrll Trailing whitespace
 1.3 17-Jun-2020  thorpej <sys/extent.h> not needed here.
 1.2 15-Jun-2020  ad Use sys/cpu.h so that curcpu defined in terms of curlwp->l_cpu works too.
 1.1 17-Jan-2020  jmcneill branches: 1.1.2; 1.1.6;
Add support for Arm N1 SDP PCIe host controller.

The N1 SDP has a few bugs that we need to work around:
- PCIe root port config space lives in a non-standard location.
- Access to PCIe config space of devices that do not exist results in
an sync SError. Firmware creates a "known devices" table at a fixed
physical address that we use to filter PCI conf access to only known
devices.

This change splits the Arm ACPI PCI quirks into separate files for each
host controller, and allows per-segment quirks to be applied.

These changes exposed some bugs in the MI ACPI layer related to
multi-segment support. The MI ACPI PCI code was using a shared PCI
chipset tag to access devices, and these accesses can happen before our
PCI host bridge drivers are attached! The global chipset tag is now gone,
and an MD callback can provide a custom tag on a per-segment basis.
 1.1.6.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.1.6.1 17-Jan-2020  martin file acpi_pci_graviton.c was added on branch phil-wifi on 2020-04-08 14:07:27 +0000
 1.1.2.2 17-Jan-2020  ad Sync with head.
 1.1.2.1 17-Jan-2020  ad file acpi_pci_graviton.c was added on branch ad-namecache on 2020-01-17 21:47:23 +0000
 1.5 15-Oct-2022  jmcneill Use "non-posted" instead of "strongly ordered" to describe nGnRnE mappings

Rename the following defines:
- _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED to BUS_SPACE_MAP_NONPOSTED
- PMAP_DEV_SO to PMAP_DEV_NP
- LX_BLKPAG_ATTR_DEVICE_MEM_SO to LX_BLKPAG_ATTR_DEVICE_MEM_NP
Rename the following option:
- AARCH64_DEVICE_MEM_STRONGLY_ORDERED to AARCH64_DEVICE_MEM_NONPOSTED
 1.4 17-Jun-2020  thorpej <sys/extent.h> not needed here.
 1.3 15-Jun-2020  ad Use sys/cpu.h so that curcpu defined in terms of curlwp->l_cpu works too.
 1.2 02-Feb-2020  jmcneill branches: 1.2.2; 1.2.6;
Map and read MCFG space directly instead of going through acpimcfg to
simplify access through our tiny config space window.
 1.1 01-Feb-2020  jmcneill Add support for NXP Layerscape PCIe Gen4 (not ECAM compliant)
 1.2.6.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.2.6.1 02-Feb-2020  martin file acpi_pci_layerscape_gen4.c was added on branch phil-wifi on 2020-04-08 14:07:27 +0000
 1.2.2.2 29-Feb-2020  ad Sync with head.
 1.2.2.1 02-Feb-2020  ad file acpi_pci_layerscape_gen4.c was added on branch ad-namecache on 2020-02-29 20:18:17 +0000
 1.22 13-Aug-2022  jmcneill arm: acpi: Improve legacy INTx support.

For devices on a bus with no direct _PRT, use the raw intr pin with the
parent bridge's slot number to derive a pin number that can be used to
lookup the pin -> irq mapping in the parent bus's _PRT.
 1.21 21-Dec-2021  skrll Remove unneeded struct acpi_pci_intr forward declaration.
 1.20 08-Aug-2021  jmcneill Install the shared PCI INTx interrupt handler at IPL_VM to workaround a
possible interrupt storm at boot. Need to revisit this.
 1.19 07-Aug-2021  jmcneill arm: acpi: Add support for SMCCC based PCI config access.
 1.18 17-Jun-2020  thorpej <sys/extent.h> not needed here.
 1.17 15-Jun-2020  ad Use sys/cpu.h so that curcpu defined in terms of curlwp->l_cpu works too.
 1.16 13-Feb-2020  jmcneill Add support for multiple GICv3 ITS domains.
 1.15 01-Feb-2020  jmcneill Add support for NXP Layerscape PCIe Gen4 (not ECAM compliant)
 1.14 23-Jan-2020  jmcneill Add support for sharing legacy PCI interrupt sources.
 1.13 17-Jan-2020  jmcneill Add support for Arm N1 SDP PCIe host controller.

The N1 SDP has a few bugs that we need to work around:
- PCIe root port config space lives in a non-standard location.
- Access to PCIe config space of devices that do not exist results in
an sync SError. Firmware creates a "known devices" table at a fixed
physical address that we use to filter PCI conf access to only known
devices.

This change splits the Arm ACPI PCI quirks into separate files for each
host controller, and allows per-segment quirks to be applied.

These changes exposed some bugs in the MI ACPI layer related to
multi-segment support. The MI ACPI PCI code was using a shared PCI
chipset tag to access devices, and these accesses can happen before our
PCI host bridge drivers are attached! The global chipset tag is now gone,
and an MD callback can provide a custom tag on a per-segment basis.
 1.12 15-Oct-2019  jmcneill branches: 1.12.2;
Amazon Graviton maxdevs quirk no longer required as of pci.c r1.155
 1.11 14-Oct-2019  jmcneill More Amazon Graviton quirks:
- Ignore devno > 0 on the PCIe root port.
- Fixup PCIe bridge bus number register on the root port.
- Move quirk handling to acpipchb so it can be applied before the bus
is configured.
 1.10 14-Oct-2019  jmcneill Add quirks for Amazon Graviton PCIe root ports. Configuration space for the
root port is found in a child AMZN0001 resource, not the MCFG table.
 1.9 08-Dec-2018  jmcneill branches: 1.9.4; 1.9.6;
Add support for decoding PCI ID mappings using IO remapping tables (IORT).
 1.8 16-Nov-2018  jmcneill Add intr_establish_xname support to arm and expose it to intrctl
 1.7 03-Nov-2018  jmcneill Match _PRT by segment and bus
 1.6 02-Nov-2018  jmcneill Add support for multiple PCI segments.
 1.5 31-Oct-2018  jmcneill Add MSI-X support
 1.4 21-Oct-2018  jmcneill Do not add PCI link references until the bus has been mapped
 1.3 21-Oct-2018  jmcneill Add support for PCI MSI using ARM GICv2m.
 1.2 19-Oct-2018  jmcneill branches: 1.2.2;
Add support for PCI Segment Groups.
 1.1 15-Oct-2018  jmcneill Add ARM ACPI PCI support.
 1.2.2.4 26-Dec-2018  pgoyette Sync with HEAD, resolve a few conflicts
 1.2.2.3 26-Nov-2018  pgoyette Sync with HEAD, resolve a couple of conflicts
 1.2.2.2 20-Oct-2018  pgoyette Sync with head
 1.2.2.1 19-Oct-2018  pgoyette file acpi_pci_machdep.c was added on branch pgoyette-compat on 2018-10-20 06:58:24 +0000
 1.9.6.1 15-Oct-2019  martin Pull up following revision(s) (requested by jmcneill in ticket #332):

sys/arch/arm/acpi/acpipchb.c: revision 1.10
sys/arch/arm/acpi/acpipchb.c: revision 1.11
sys/arch/arm/acpi/acpipchb.c: revision 1.12
sys/arch/arm/acpi/acpi_pci_machdep.h: revision 1.3
sys/arch/arm/acpi/acpi_pci_machdep.h: revision 1.4
sys/arch/arm/acpi/acpi_pci_machdep.c: revision 1.10
sys/arch/arm/acpi/acpi_pci_machdep.c: revision 1.11

Add quirks for Amazon Graviton PCIe root ports. Configuration space for the
root port is found in a child AMZN0001 resource, not the MCFG table.

-

More Amazon Graviton quirks:
- Ignore devno > 0 on the PCIe root port.
- Fixup PCIe bridge bus number register on the root port.
- Move quirk handling to acpipchb so it can be applied before the bus
is configured.

-

Fix detection of root port resources for Graviton and remove no longer required bridge fixup
 1.9.4.4 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.9.4.3 08-Apr-2020  martin Merge changes from current as of 20200406
 1.9.4.2 10-Jun-2019  christos Sync with HEAD
 1.9.4.1 08-Dec-2018  christos file acpi_pci_machdep.c was added on branch phil-wifi on 2019-06-10 22:05:50 +0000
 1.12.2.3 29-Feb-2020  ad Sync with head.
 1.12.2.2 25-Jan-2020  ad Sync with head.
 1.12.2.1 17-Jan-2020  ad Sync with head.
 1.8 07-Aug-2021  jmcneill arm: acpi: Add support for SMCCC based PCI config access.
 1.7 01-Feb-2020  jmcneill Add support for NXP Layerscape PCIe Gen4 (not ECAM compliant)
 1.6 17-Jan-2020  jmcneill Add support for Arm N1 SDP PCIe host controller.

The N1 SDP has a few bugs that we need to work around:
- PCIe root port config space lives in a non-standard location.
- Access to PCIe config space of devices that do not exist results in
an sync SError. Firmware creates a "known devices" table at a fixed
physical address that we use to filter PCI conf access to only known
devices.

This change splits the Arm ACPI PCI quirks into separate files for each
host controller, and allows per-segment quirks to be applied.

These changes exposed some bugs in the MI ACPI layer related to
multi-segment support. The MI ACPI PCI code was using a shared PCI
chipset tag to access devices, and these accesses can happen before our
PCI host bridge drivers are attached! The global chipset tag is now gone,
and an MD callback can provide a custom tag on a per-segment basis.
 1.5 15-Oct-2019  jmcneill branches: 1.5.2;
Amazon Graviton maxdevs quirk no longer required as of pci.c r1.155
 1.4 14-Oct-2019  jmcneill More Amazon Graviton quirks:
- Ignore devno > 0 on the PCIe root port.
- Fixup PCIe bridge bus number register on the root port.
- Move quirk handling to acpipchb so it can be applied before the bus
is configured.
 1.3 14-Oct-2019  jmcneill Add quirks for Amazon Graviton PCIe root ports. Configuration space for the
root port is found in a child AMZN0001 resource, not the MCFG table.
 1.2 19-Oct-2018  jmcneill branches: 1.2.2; 1.2.6; 1.2.8;
Add support for PCI Segment Groups.
 1.1 15-Oct-2018  jmcneill Add ARM ACPI PCI support.
 1.2.8.1 15-Oct-2019  martin Pull up following revision(s) (requested by jmcneill in ticket #332):

sys/arch/arm/acpi/acpipchb.c: revision 1.10
sys/arch/arm/acpi/acpipchb.c: revision 1.11
sys/arch/arm/acpi/acpipchb.c: revision 1.12
sys/arch/arm/acpi/acpi_pci_machdep.h: revision 1.3
sys/arch/arm/acpi/acpi_pci_machdep.h: revision 1.4
sys/arch/arm/acpi/acpi_pci_machdep.c: revision 1.10
sys/arch/arm/acpi/acpi_pci_machdep.c: revision 1.11

Add quirks for Amazon Graviton PCIe root ports. Configuration space for the
root port is found in a child AMZN0001 resource, not the MCFG table.

-

More Amazon Graviton quirks:
- Ignore devno > 0 on the PCIe root port.
- Fixup PCIe bridge bus number register on the root port.
- Move quirk handling to acpipchb so it can be applied before the bus
is configured.

-

Fix detection of root port resources for Graviton and remove no longer required bridge fixup
 1.2.6.3 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.2.6.2 10-Jun-2019  christos Sync with HEAD
 1.2.6.1 19-Oct-2018  christos file acpi_pci_machdep.h was added on branch phil-wifi on 2019-06-10 22:05:50 +0000
 1.2.2.2 20-Oct-2018  pgoyette Sync with head
 1.2.2.1 19-Oct-2018  pgoyette file acpi_pci_machdep.h was added on branch pgoyette-compat on 2018-10-20 06:58:24 +0000
 1.5.2.2 29-Feb-2020  ad Sync with head.
 1.5.2.1 17-Jan-2020  ad Sync with head.
 1.7 15-Oct-2022  jmcneill Use "non-posted" instead of "strongly ordered" to describe nGnRnE mappings

Rename the following defines:
- _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED to BUS_SPACE_MAP_NONPOSTED
- PMAP_DEV_SO to PMAP_DEV_NP
- LX_BLKPAG_ATTR_DEVICE_MEM_SO to LX_BLKPAG_ATTR_DEVICE_MEM_NP
Rename the following option:
- AARCH64_DEVICE_MEM_STRONGLY_ORDERED to AARCH64_DEVICE_MEM_NONPOSTED
 1.6 24-Oct-2020  skrll Trailing whitespace
 1.5 13-Sep-2020  jmcneill Make Arm MD ACPI code big endian friendly.
 1.4 17-Jun-2020  thorpej <sys/extent.h> not needed here.
 1.3 15-Jun-2020  ad Use sys/cpu.h so that curcpu defined in terms of curlwp->l_cpu works too.
 1.2 13-Feb-2020  jmcneill branches: 1.2.4;
Enable MSI and MSI-X support on N1SDP
 1.1 17-Jan-2020  jmcneill branches: 1.1.2;
Add support for Arm N1 SDP PCIe host controller.

The N1 SDP has a few bugs that we need to work around:
- PCIe root port config space lives in a non-standard location.
- Access to PCIe config space of devices that do not exist results in
an sync SError. Firmware creates a "known devices" table at a fixed
physical address that we use to filter PCI conf access to only known
devices.

This change splits the Arm ACPI PCI quirks into separate files for each
host controller, and allows per-segment quirks to be applied.

These changes exposed some bugs in the MI ACPI layer related to
multi-segment support. The MI ACPI PCI code was using a shared PCI
chipset tag to access devices, and these accesses can happen before our
PCI host bridge drivers are attached! The global chipset tag is now gone,
and an MD callback can provide a custom tag on a per-segment basis.
 1.1.2.3 29-Feb-2020  ad Sync with head.
 1.1.2.2 17-Jan-2020  ad Sync with head.
 1.1.2.1 17-Jan-2020  ad file acpi_pci_n1sdp.c was added on branch ad-namecache on 2020-01-17 21:47:23 +0000
 1.2.4.2 08-Apr-2020  martin Merge changes from current as of 20200406
 1.2.4.1 13-Feb-2020  martin file acpi_pci_n1sdp.c was added on branch phil-wifi on 2020-04-08 14:07:27 +0000
 1.2 15-Oct-2022  jmcneill fix indentation
 1.1 07-Aug-2021  jmcneill arm: acpi: Add support for SMCCC based PCI config access.
 1.40 04-Oct-2025  thorpej Use device_setprop_bool() for "force_console".
 1.39 06-Sep-2025  thorpej Refactor the "platform" defitions into fdt_platform.h
 1.38 08-Dec-2024  jmcneill acpi: Try PSCI before UEFI RT for shutdown/reset.

BSA says that an OS can use either UEFI RT or PSCI, and that the RT
implementation should just call PSCI.

Given the amount of implementation issues with UEFI RT, let's try PSCI
first, because it's nice to be able to reboot and poweroff even with
buggy firmware.
 1.37 30-Jun-2024  jmcneill aarch64: Add NUMA awareness for ACPI systems with SRAT tables.

On an Ampere Altra w/ hemisphere mode enabled:

[ 1.0000000] cpu0: package 16, core 0, smt 0, numa 0
[...]
[ 1.0000000] cpu32: package 22, core 0, smt 0, numa 1

[ 1.000004] SRAT: 2 NUMA nodes
[ 1.000004] SRAT: node 0 memory range 0 (0x88300000 - 0x88400000 flags 1)
[ 1.000004] SRAT: node 0 memory range 1 (0x90000000 - 0x100000000 flags 1)
[ 1.000004] SRAT: node 0 memory range 2 (0x80000000000 - 0x80080000000 flags 1)
[ 1.000004] SRAT: node 0 memory range 3 (0x80100000000 - 0x81000000000 flags 1)
[ 1.000004] SRAT: node 1 memory range 0 (0xc0000000000 - 0xc1000000000 flags 1)
 1.36 07-Apr-2023  skrll branches: 1.36.6;
Rename ARM_PLATFORM to FDT_PLATFORM and make it available outside arm.
 1.35 24-Jan-2023  mlelstv Add support for FIFOs and hardware flow-control to plcom driver.
Add a PLCOM_TYPE_GENERIC_UART variant to match SBSA requirements.
 1.34 16-Nov-2022  skrll typo in comment
 1.33 06-Sep-2022  skrll Use the ACPICA define ACPI_DBG2_16550_WITH_GAS
 1.32 24-Oct-2021  jmcneill More SPCR cleanup:

- For 16550 style UARTs, always honour GAS if BitWidth != 0
- Use BitWidth instead of AccessWidth to determine register stride
- For baud rate ID of 0, assume 115200 until we have a way of probing
the baud rate configured by firmware.
 1.31 23-Oct-2021  jmcneill It seems that there are three 16550 types for SPCR:

- 0x0000: Fully 16550-compatible (1-byte I/O)
- 0x0001: 16550 subset compatible with DBGP Revision 1 (4-byte MMIO)
- 0x0012: 16550-compatible with parameters defined in GAS

So assume reg_width for types 0 and 1, and only look at GAS for type 12h.
 1.30 21-Oct-2021  jmcneill baud_rate is signed now
 1.29 20-Oct-2021  jakllsch SPCR_BAUD_DEFAULT maps better to -1 than 0

Suggested by jmcneill@
 1.28 07-Aug-2021  jmcneill acpi: call smccc_probe() after PSCI init
 1.27 06-Aug-2021  jmcneill Arm: Add support for SMC Calling Convention

Arm DEN0028 defines a calling mechanism used with Secure Monitor Call (SMC)
and Hypervisor Call (HVC) instructions. To discover SMCCC, we must:

1) Find the PSCI conduit (either via ACPI FADT, or Device Tree)
2) Use PSCI_VERSION to determine whether PSCI_FEATURES is supported
3) Call PSCI_FEATURES with SMCCC_VERSION to determine the implementation
version.
 1.26 12-May-2021  thorpej - Define a device call for PCI bus instances to fetch a direct child's
device handle given the device's device/function #s (extracted from
a pcitag_t). Use it to associate the handle with the child device
at config_found() time.
- Implement this device call for ACPI and OpenFirmware.
- Enable the OpenFirmware variant for evbarm FDT, macppc, ofppc, sparc64.
- Obsolete acpi_device_register(); it is no longer needed.
- Obsolete setting the OpenFirmware handle in PCI devices in the
sparc64 device_register(); it is no longer needed.
 1.25 24-Apr-2021  thorpej branches: 1.25.2; 1.25.4;
Merge thorpej-cfargs branch:

Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.

Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
actually needed.
- Don't be explicit about what interface attribute is attaching if
the device only has one. (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
situations, making is visibly easier to see when indirect config is
in play, and allowing for future change in semantics. (As of now,
this is just a wrapper around config_match(), but that is an
implementation detail.)

Remove unnecessary or redundant interface attributes where they're not
needed.

There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)

...and a sentinel value CFARG_EOL.

Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.

Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance. This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).
 1.24 12-Feb-2021  jmcneill branches: 1.24.2;
Reset serial terminal to default state at boot.

UEFI may leave the serial console in an undesireable state (incorrect
foreground and background colour, etc) when exiting. Send ANSI escape
sequences when setting up the early console attachments to turn off
character attributes and erase from the cursor to the end of the screen.
 1.23 04-Feb-2021  thorpej Call acpi_device_register() / fdtbus_device_register() as approrpriate.
 1.22 06-Dec-2020  jmcneill acpi: Cleanup SPCR setup and style fixes.
 1.21 10-Oct-2020  jmcneill branches: 1.21.2;
Support early FB console attachment when booting with a devicetree
(non-ACPI mode). Inform the pciconf code about the framebuffer to
prevent pciconf from changing resources out from under us when framebuffer
memory is in VRAM.
 1.20 28-Sep-2020  jmcneill Get rid of a4x bus_space tag from fdtbus_attach_args. The only consumer
of this was various com(4) glue so modify all of that to use the new
com_init_regs_stride instead.
 1.19 13-Sep-2020  jmcneill Make Arm MD ACPI code big endian friendly.
 1.18 22-Sep-2019  jmcneill Use vcons for simplefb preattach to speed up early console messages.
 1.17 19-Aug-2019  jmcneill Use a unique name for the acpi ARM_PLATFORM definition
 1.16 02-Aug-2019  jmcneill Ignore AccessWidth (PL011 and SBSA console always needs 32-bit access)
 1.15 24-Jul-2019  jmcneill branches: 1.15.2;
Add early fb console support
 1.14 22-Jun-2019  jmcneill Finish the job
 1.13 19-Jun-2019  jmcneill Provide a 64-bit dma tag and use a coherent tag unless CCA=0
 1.12 23-May-2019  ryo branches: 1.12.2;
fix build without options MULTIPROCESSOR
 1.11 21-Dec-2018  jmcneill Use SPCR to force console selection for com@acpi. This is needed because
we may use a non-standard bus_space tag (a4x) to attach the console early,
which breaks com_is_console.
 1.10 28-Nov-2018  jmcneill Force a matching com@puc by seg/bus/dev/func to be the console device if specified in SPCR
 1.9 28-Nov-2018  jmcneill Replace SPCR_INTERFACE_TYPE_* defines with ACPI_DBG2_* from acpica. Suggested by msaitoh@
 1.8 27-Nov-2018  jmcneill Add support for SPCR 16550 and 16450 interface types
 1.7 24-Nov-2018  rjs Allow building when plcom isn't used.
 1.6 30-Oct-2018  skrll Retire fdt_putchar and ap_early_put_char in favour of uartputc.
 1.5 28-Oct-2018  jmcneill Add support for EFI runtime services on aarch64.
 1.4 19-Oct-2018  jmcneill branches: 1.4.2;
Fix BCM2835 console support.
 1.3 15-Oct-2018  jmcneill Handle more plcom-style console types
 1.2 13-Oct-2018  jmcneill Don't rely on PSCI node in FDT to reboot
 1.1 12-Oct-2018  jmcneill Add ACPI platform glue and basic device drivers (CPU, GIC, Generic Timer,
SBSA UART).
 1.4.2.4 26-Dec-2018  pgoyette Sync with HEAD, resolve a few conflicts
 1.4.2.3 26-Nov-2018  pgoyette Sync with HEAD, resolve a couple of conflicts
 1.4.2.2 20-Oct-2018  pgoyette Sync with head
 1.4.2.1 19-Oct-2018  pgoyette file acpi_platform.c was added on branch pgoyette-compat on 2018-10-20 06:58:24 +0000
 1.12.2.3 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.12.2.2 10-Jun-2019  christos Sync with HEAD
 1.12.2.1 23-May-2019  christos file acpi_platform.c was added on branch phil-wifi on 2019-06-10 22:05:50 +0000
 1.15.2.2 23-Sep-2019  martin Pull up following revision(s) (requested by jmcneill in ticket #231):

sys/arch/arm/acpi/acpi_platform.c: revision 1.18
sys/arch/arm/acpi/files.acpi: revision 1.7
sys/arch/arm/acpi/acpi_simplefb.c: revision 1.1
sys/arch/arm/acpi/acpi_simplefb.h: revision 1.1

Use vcons for simplefb preattach to speed up early console messages.
 1.15.2.1 04-Aug-2019  martin Pull up following revision(s) (requested by jmcneill in ticket #17):

sys/arch/arm/acpi/acpi_platform.c: revision 1.16

Ignore AccessWidth (PL011 and SBSA console always needs 32-bit access)
 1.21.2.2 03-Apr-2021  thorpej Sync with HEAD.
 1.21.2.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.24.2.1 03-Apr-2021  thorpej - FDT device enumeration now sets the device handle using CFARG_DEVHANDLE.
- fdtbus_device_register() is now obsolete, so G/C it.
- of_device_register() is now obsolete, so G/C it.
 1.25.4.1 31-May-2021  cjep sync with head
 1.25.2.1 13-May-2021  thorpej Sync with HEAD.
 1.36.6.2 02-Aug-2025  perseant Sync with HEAD
 1.36.6.1 01-Jul-2024  perseant Sync with HEAD.
 1.3 10-Oct-2020  jmcneill Support early FB console attachment when booting with a devicetree
(non-ACPI mode). Inform the pciconf code about the framebuffer to
prevent pciconf from changing resources out from under us when framebuffer
memory is in VRAM.
 1.2 24-Jan-2020  jmcneill branches: 1.2.6;
Do not attach simplefb if the width or height are invalid
 1.1 22-Sep-2019  jmcneill branches: 1.1.2; 1.1.4;
Use vcons for simplefb preattach to speed up early console messages.
 1.1.4.1 25-Jan-2020  ad Sync with head.
 1.1.2.2 23-Sep-2019  martin Pull up following revision(s) (requested by jmcneill in ticket #231):

sys/arch/arm/acpi/acpi_platform.c: revision 1.18
sys/arch/arm/acpi/files.acpi: revision 1.7
sys/arch/arm/acpi/acpi_simplefb.c: revision 1.1
sys/arch/arm/acpi/acpi_simplefb.h: revision 1.1

Use vcons for simplefb preattach to speed up early console messages.
 1.1.2.1 22-Sep-2019  martin file acpi_simplefb.c was added on branch netbsd-9 on 2019-09-23 07:06:31 +0000
 1.2.6.2 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.2.6.1 24-Jan-2020  martin file acpi_simplefb.c was added on branch phil-wifi on 2020-04-13 08:03:32 +0000
 1.2 10-Oct-2020  jmcneill Support early FB console attachment when booting with a devicetree
(non-ACPI mode). Inform the pciconf code about the framebuffer to
prevent pciconf from changing resources out from under us when framebuffer
memory is in VRAM.
 1.1 22-Sep-2019  jmcneill branches: 1.1.2; 1.1.10;
Use vcons for simplefb preattach to speed up early console messages.
 1.1.10.2 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.1.10.1 22-Sep-2019  martin file acpi_simplefb.h was added on branch phil-wifi on 2020-04-13 08:03:32 +0000
 1.1.2.2 23-Sep-2019  martin Pull up following revision(s) (requested by jmcneill in ticket #231):

sys/arch/arm/acpi/acpi_platform.c: revision 1.18
sys/arch/arm/acpi/files.acpi: revision 1.7
sys/arch/arm/acpi/acpi_simplefb.c: revision 1.1
sys/arch/arm/acpi/acpi_simplefb.h: revision 1.1

Use vcons for simplefb preattach to speed up early console messages.
 1.1.2.1 22-Sep-2019  martin file acpi_simplefb.h was added on branch netbsd-9 on 2019-09-23 07:06:31 +0000
 1.2 13-Sep-2020  jmcneill Make Arm MD ACPI code big endian friendly.
 1.1 12-Oct-2018  jmcneill branches: 1.1.2; 1.1.6;
Add helper functions used for parsing ACPI tables before the ACPICA
subsystem can be brought online. ARM64 needs this primarily for
initializing the SBSA UART via SPCR table, reading ARM boot flags from the
FADT, counting CPUs, etc.
 1.1.6.2 10-Jun-2019  christos Sync with HEAD
 1.1.6.1 12-Oct-2018  christos file acpi_table.c was added on branch phil-wifi on 2019-06-10 22:05:50 +0000
 1.1.2.2 20-Oct-2018  pgoyette Sync with head
 1.1.2.1 12-Oct-2018  pgoyette file acpi_table.c was added on branch pgoyette-compat on 2018-10-20 06:58:24 +0000
 1.1 12-Oct-2018  jmcneill branches: 1.1.2; 1.1.6;
Add helper functions used for parsing ACPI tables before the ACPICA
subsystem can be brought online. ARM64 needs this primarily for
initializing the SBSA UART via SPCR table, reading ARM boot flags from the
FADT, counting CPUs, etc.
 1.1.6.2 10-Jun-2019  christos Sync with HEAD
 1.1.6.1 12-Oct-2018  christos file acpi_table.h was added on branch phil-wifi on 2019-06-10 22:05:50 +0000
 1.1.2.2 20-Oct-2018  pgoyette Sync with head
 1.1.2.1 12-Oct-2018  pgoyette file acpi_table.h was added on branch pgoyette-compat on 2018-10-20 06:58:24 +0000
 1.33 11-Jan-2025  jmcneill acpi: i2c: only claim child devices with a _CRS or _ADR method

acpi_enter_i2c_devs is too aggressive with claiming child device nodes.
Restrict it to devices with either a _CRS or _ADR method. A driver is
free to claim more if appropriate.

Fixes missing HKEY (LEN0268) device on Thinkpad T14s Gen 6 (X1E).
 1.32 15-Oct-2022  jmcneill branches: 1.32.8;
Use "non-posted" instead of "strongly ordered" to describe nGnRnE mappings

Rename the following defines:
- _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED to BUS_SPACE_MAP_NONPOSTED
- PMAP_DEV_SO to PMAP_DEV_NP
- LX_BLKPAG_ATTR_DEVICE_MEM_SO to LX_BLKPAG_ATTR_DEVICE_MEM_NP
Rename the following option:
- AARCH64_DEVICE_MEM_STRONGLY_ORDERED to AARCH64_DEVICE_MEM_NONPOSTED
 1.31 14-Oct-2022  jmcneill Add a PCI resource manager and use it on Arm ACPI platforms.

The Arm ACPI code relied on PCI_NETBSD_CONFIGURE to configure devices that
were not enabled by system firmware. This is not safe to do unless the
firmware explicitly permits it using a device specific method defined in
the PCI firmware spec.

Introduce a new PCI resource manager that discovers what has already been
configured by firmware and allocates from the remaining space. This will
ensure that devices setup by firmware are untouched and only will program
BARs of devices that are not enabled at boot time.

The current implementation assumes that the parent PCI-PCI bridge's
are already configured. A worthwhile improvement in the future would be
to support programming windows for bridges that are not fully configured.
 1.30 13-Aug-2022  jmcneill Add "nopcimsi" boot option to force legacy INTx only mode.
 1.29 13-Aug-2022  jmcneill acpipchb: Add a kernel cmdline option to skip PCI resource assignment.

Passing "nopciconf" to the kernel will force acpipchb to skip PCI
resource assignment.
 1.28 10-Aug-2021  jmcneill Disable MSI if the linux,pcie-nomsi flag is present
 1.27 07-Aug-2021  jmcneill arm: acpi: Add support for SMCCC based PCI config access.
 1.26 07-Aug-2021  thorpej Merge thorpej-cfargs2.
 1.25 12-May-2021  thorpej branches: 1.25.4;
Pass along our devhandle to the PCI bus instance we attach.
 1.24 24-Apr-2021  thorpej branches: 1.24.2; 1.24.4;
Merge thorpej-cfargs branch:

Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.

Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
actually needed.
- Don't be explicit about what interface attribute is attaching if
the device only has one. (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
situations, making is visibly easier to see when indirect config is
in play, and allowing for future change in semantics. (As of now,
this is just a wrapper around config_match(), but that is an
implementation detail.)

Remove unnecessary or redundant interface attributes where they're not
needed.

There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)

...and a sentinel value CFARG_EOL.

Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.

Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance. This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).
 1.23 26-Jan-2021  jmcneill branches: 1.23.2;
acpipchb is a bus, so claim all child ACPI device nodes
 1.22 06-Dec-2020  jmcneill Style fixes. NFC.
 1.21 24-Oct-2020  skrll branches: 1.21.2;
Trailing whitespace
 1.20 17-Jun-2020  thorpej <sys/extent.h> not needed here.
 1.19 15-Jun-2020  ad Use sys/cpu.h so that curcpu defined in terms of curlwp->l_cpu works too.
 1.18 08-May-2020  jmcneill Try to get the starting bus number from _CRS before falling back to _BBN.
There are apparently cases where the first bus in _CRS does not match the
value of _BBN, and the consensus is that _CRS should take precedence.
 1.17 21-Jan-2020  jmcneill Provide a properly constrained 32-bit DMA tag to ACPI.
 1.16 17-Jan-2020  jmcneill Add support for Arm N1 SDP PCIe host controller.

The N1 SDP has a few bugs that we need to work around:
- PCIe root port config space lives in a non-standard location.
- Access to PCIe config space of devices that do not exist results in
an sync SError. Firmware creates a "known devices" table at a fixed
physical address that we use to filter PCI conf access to only known
devices.

This change splits the Arm ACPI PCI quirks into separate files for each
host controller, and allows per-segment quirks to be applied.

These changes exposed some bugs in the MI ACPI layer related to
multi-segment support. The MI ACPI PCI code was using a shared PCI
chipset tag to access devices, and these accesses can happen before our
PCI host bridge drivers are attached! The global chipset tag is now gone,
and an MD callback can provide a custom tag on a per-segment basis.
 1.15 29-Dec-2019  jmcneill branches: 1.15.2;
Allow MD code to provide custom bus_dma tags on a per-node basis. On Arm
this is required to return non-coherent bus_dma tags for device nodes with
_CCA=0
 1.14 28-Dec-2019  jmcneill Do not use Early Write Acknowledge for PCIe I/O and config space.
 1.13 15-Oct-2019  jmcneill Amazon Graviton maxdevs quirk no longer required as of pci.c r1.155
 1.12 15-Oct-2019  jmcneill Fix detection of root port resources for Graviton and remove no longer required bridge fixup
 1.11 14-Oct-2019  jmcneill More Amazon Graviton quirks:
- Ignore devno > 0 on the PCIe root port.
- Fixup PCIe bridge bus number register on the root port.
- Move quirk handling to acpipchb so it can be applied before the bus
is configured.
 1.10 14-Oct-2019  jmcneill Add quirks for Amazon Graviton PCIe root ports. Configuration space for the
root port is found in a child AMZN0001 resource, not the MCFG table.
 1.9 25-Jun-2019  jmcneill branches: 1.9.2;
Honour _CRS mem ranges and translation offsets instead of assuming 1:1
mappings. Tested on Overdrive 1000.
 1.8 19-Jun-2019  jmcneill Provide a 64-bit dma tag and use a coherent tag unless CCA=0
 1.7 19-Nov-2018  jmcneill branches: 1.7.4;
On second thought, get rid of "bs_base" from struct bus_space and use a
custom bs_map for acpipchb instead.
 1.6 18-Nov-2018  jmcneill Add support for PCI I/O space.
 1.5 16-Nov-2018  jmcneill Restore acpi_pci_ignore_boot_config lost in previous commit
 1.4 16-Nov-2018  jmcneill Add intr_establish_xname support to arm and expose it to intrctl
 1.3 21-Oct-2018  jmcneill Only configure PCI bus if _DSM rev 1 func 5 ("Ignore PCI boot configuration") returns 1
 1.2 19-Oct-2018  jmcneill branches: 1.2.2;
Add support for PCI Segment Groups.
 1.1 15-Oct-2018  jmcneill Add ARM ACPI PCI support.
 1.2.2.3 26-Nov-2018  pgoyette Sync with HEAD, resolve a couple of conflicts
 1.2.2.2 20-Oct-2018  pgoyette Sync with head
 1.2.2.1 19-Oct-2018  pgoyette file acpipchb.c was added on branch pgoyette-compat on 2018-10-20 06:58:24 +0000
 1.7.4.3 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.7.4.2 10-Jun-2019  christos Sync with HEAD
 1.7.4.1 19-Nov-2018  christos file acpipchb.c was added on branch phil-wifi on 2019-06-10 22:05:50 +0000
 1.9.2.2 29-Dec-2019  martin Pull up following revision(s) (requested by jmcneill in ticket #586):

sys/arch/arm/nvidia/tegra_pcie.c: revision 1.27
sys/arch/aarch64/aarch64/pmap.c: revision 1.57
sys/arch/aarch64/aarch64/locore.S: revision 1.48
sys/arch/aarch64/include/armreg.h: revision 1.29
sys/arch/aarch64/aarch64/pmap.c: revision 1.58
sys/arch/aarch64/aarch64/locore.S: revision 1.49
sys/arch/arm/acpi/acpipchb.c: revision 1.14
sys/arch/aarch64/aarch64/genassym.cf: revision 1.16
sys/arch/arm/acpi/acpi_machdep.c: revision 1.13
sys/arch/aarch64/include/pmap.h: revision 1.27
sys/arch/aarch64/aarch64/genassym.cf: revision 1.17
sys/arch/aarch64/include/pmap.h: revision 1.28
sys/arch/arm/fdt/pcihost_fdtvar.h: revision 1.3
sys/arch/arm/include/bus_defs.h: revision 1.14
sys/arch/aarch64/aarch64/bus_space.c: revision 1.9
sys/arch/arm/fdt/pcihost_fdt.c: revision 1.12
sys/arch/aarch64/conf/files.aarch64: revision 1.15
sys/arch/aarch64/conf/files.aarch64: revision 1.16
sys/arch/arm/rockchip/rk3399_pcie.c: revision 1.9

Enable early write acknowledge for device memory mappings.

Do not use Early Write Acknowledge for PCIe I/O and config space.
 1.9.2.1 15-Oct-2019  martin Pull up following revision(s) (requested by jmcneill in ticket #332):

sys/arch/arm/acpi/acpipchb.c: revision 1.10
sys/arch/arm/acpi/acpipchb.c: revision 1.11
sys/arch/arm/acpi/acpipchb.c: revision 1.12
sys/arch/arm/acpi/acpi_pci_machdep.h: revision 1.3
sys/arch/arm/acpi/acpi_pci_machdep.h: revision 1.4
sys/arch/arm/acpi/acpi_pci_machdep.c: revision 1.10
sys/arch/arm/acpi/acpi_pci_machdep.c: revision 1.11

Add quirks for Amazon Graviton PCIe root ports. Configuration space for the
root port is found in a child AMZN0001 resource, not the MCFG table.

-

More Amazon Graviton quirks:
- Ignore devno > 0 on the PCIe root port.
- Fixup PCIe bridge bus number register on the root port.
- Move quirk handling to acpipchb so it can be applied before the bus
is configured.

-

Fix detection of root port resources for Graviton and remove no longer required bridge fixup
 1.15.2.2 25-Jan-2020  ad Sync with head.
 1.15.2.1 17-Jan-2020  ad Sync with head.
 1.21.2.2 03-Apr-2021  thorpej Sync with HEAD.
 1.21.2.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.23.2.1 23-Mar-2021  thorpej Convert config_found_ia() call sites where the device only carries
a single interface attribute to bare config_found() calls.
 1.24.4.1 31-May-2021  cjep sync with head
 1.24.2.1 13-May-2021  thorpej Sync with HEAD.
 1.25.4.1 04-Aug-2021  thorpej Adapt to CFARGS().
 1.32.8.1 02-Aug-2025  perseant Sync with HEAD
 1.18 30-Jan-2025  jmcneill arm: acpi: Early return when a CPU is not configured
 1.17 30-Dec-2024  jmcneill arm64: Enable support for low power idle CPU states on ACPI platforms.

The ACPI CPU driver parses the _LPI package on each CPU and builds a
table of supported low power states. A custom cpu_idle() implementation
is registered that uses the time previously spent idle to select an
entry method for low power on the next idle entry.

A boot option, "nolpi", can be used to ignore _LPI and use the normal
WFI idle method.

This decreases the battery discharge rate on my Snapdragon X1E laptop from
~17W to ~10W when idle.
 1.16 30-Jun-2024  jmcneill aarch64: Add NUMA awareness for ACPI systems with SRAT tables.

On an Ampere Altra w/ hemisphere mode enabled:

[ 1.0000000] cpu0: package 16, core 0, smt 0, numa 0
[...]
[ 1.0000000] cpu32: package 22, core 0, smt 0, numa 1

[ 1.000004] SRAT: 2 NUMA nodes
[ 1.000004] SRAT: node 0 memory range 0 (0x88300000 - 0x88400000 flags 1)
[ 1.000004] SRAT: node 0 memory range 1 (0x90000000 - 0x100000000 flags 1)
[ 1.000004] SRAT: node 0 memory range 2 (0x80000000000 - 0x80080000000 flags 1)
[ 1.000004] SRAT: node 0 memory range 3 (0x80100000000 - 0x81000000000 flags 1)
[ 1.000004] SRAT: node 1 memory range 0 (0xc0000000000 - 0xc1000000000 flags 1)
 1.15 09-May-2024  pho branches: 1.15.2;
kern/58195: arm: Support drvctl -d and -r for cpufeaturebus

This is required for detaching and re-attaching the vmt(4) driver on aarch64.
 1.14 16-May-2022  jmcneill tprof: armv8: Only attach to known PMU types.
 1.13 25-Nov-2021  skrll Improve error handling.

Hypervisors can return a PMCR.N of 0.
 1.12 24-Nov-2021  jmcneill arm64: acpi: Set capacity_dmips_mhz for CPUs

The GICC structure describes a relative power efficiency for each
processor. Use this value as-is for the capacity_dmips_mhz value of a
cpu. This makes the assumption that "more efficient" means "slower".
 1.11 17-Oct-2021  jmcneill Fix primary CPU detection in cpu_acpi_tprof_intr_establish
 1.10 23-Jan-2021  jmcneill fit in 80 columns
 1.9 03-Dec-2020  skrll Provide and use a sev() macro for the sev instruction.

While here use the correct barrier to ensure completion of memory accesses
before a couple of the sev() calls.
 1.8 15-Feb-2020  skrll branches: 1.8.6;
Various updates and improvements to cpu start up on arm/aarch64

- start sharing more code around the AP startup messaging.
- call arm_cpu_topology_set early so that ci_core_id is available for
drivers, e.g. bcm2835_intr.c
- both arm and aarch64 now have
- a static cpu_info_store array
- the same arm_cpu_{hatched,mbox}
 1.7 19-Oct-2019  jmcneill branches: 1.7.2;
Increase aarch64 MAXCPUS to 256.
 1.6 23-May-2019  ryo branches: 1.6.2; 1.6.4;
fix build without options MULTIPROCESSOR
 1.5 05-Dec-2018  jmcneill Add CPU performance counter support
 1.4 19-Oct-2018  jmcneill branches: 1.4.2;
Store the ACPI Processor UID in struct cpu_info
 1.3 18-Oct-2018  skrll Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.

The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors. AP startup is
performed in less steps and more code is written in C.

The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.

Various kernels have been converted to use this code and tested. Some
boards were provided by TNF. Thanks!

The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.

Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively
 1.2 16-Oct-2018  jmcneill Only attach to usable processors
 1.1 12-Oct-2018  jmcneill Add ACPI platform glue and basic device drivers (CPU, GIC, Generic Timer,
SBSA UART).
 1.4.2.3 26-Dec-2018  pgoyette Sync with HEAD, resolve a few conflicts
 1.4.2.2 20-Oct-2018  pgoyette Sync with head
 1.4.2.1 19-Oct-2018  pgoyette file cpu_acpi.c was added on branch pgoyette-compat on 2018-10-20 06:58:24 +0000
 1.6.4.1 23-Oct-2019  martin Pull up following revision(s) (requested by jmcneill in ticket #359):

sys/arch/aarch64/aarch64/locore.S: revision 1.42
sys/arch/aarch64/aarch64/locore.S: revision 1.43
sys/arch/aarch64/aarch64/locore.S: revision 1.44
sys/arch/arm/fdt/cpu_fdt.c: revision 1.28
sys/arch/aarch64/include/cpu.h: revision 1.14
sys/arch/aarch64/include/param.h: revision 1.12
sys/arch/arm/arm32/cpu.c: revision 1.133
sys/arch/arm/arm32/cpu.c: revision 1.134
sys/arch/arm/include/cpu.h: revision 1.101
sys/arch/arm/acpi/cpu_acpi.c: revision 1.7
sys/arch/aarch64/aarch64/cpu.c: revision 1.23
sys/arch/aarch64/aarch64/cpu.c: revision 1.24
sys/arch/aarch64/aarch64/cpu.c: revision 1.25

Increase aarch64 MAXCPUS to 256.

-

Invalidate dcache before polling AP hatched status

-

Avoid overlap between BP and last AP stack. AP stacks are now in order of
increasing address order.

Spotted by and idea from mlelstv.

-

Use separate cacheline aligned arrays for mbox and hatched as before.

-

cpu_hatched_p only for MULTIPROCESSOR
 1.6.2.4 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.6.2.3 08-Apr-2020  martin Merge changes from current as of 20200406
 1.6.2.2 10-Jun-2019  christos Sync with HEAD
 1.6.2.1 23-May-2019  christos file cpu_acpi.c was added on branch phil-wifi on 2019-06-10 22:05:50 +0000
 1.7.2.1 29-Feb-2020  ad Sync with head.
 1.8.6.2 03-Apr-2021  thorpej Sync with HEAD.
 1.8.6.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.15.2.2 02-Aug-2025  perseant Sync with HEAD
 1.15.2.1 01-Jul-2024  perseant Sync with HEAD.
 1.13 07-Aug-2021  jmcneill arm: acpi: Add support for SMCCC based PCI config access.
 1.12 07-Dec-2020  jmcneill acpicpu: Add support for ACPI P-states and T-states on Arm.
 1.11 10-Oct-2020  jmcneill branches: 1.11.2;
Support early FB console attachment when booting with a devicetree
(non-ACPI mode). Inform the pciconf code about the framebuffer to
prevent pciconf from changing resources out from under us when framebuffer
memory is in VRAM.
 1.10 01-Feb-2020  jmcneill Add support for NXP Layerscape PCIe Gen4 (not ECAM compliant)
 1.9 17-Jan-2020  jmcneill Add support for Arm N1 SDP PCIe host controller.

The N1 SDP has a few bugs that we need to work around:
- PCIe root port config space lives in a non-standard location.
- Access to PCIe config space of devices that do not exist results in
an sync SError. Firmware creates a "known devices" table at a fixed
physical address that we use to filter PCI conf access to only known
devices.

This change splits the Arm ACPI PCI quirks into separate files for each
host controller, and allows per-segment quirks to be applied.

These changes exposed some bugs in the MI ACPI layer related to
multi-segment support. The MI ACPI PCI code was using a shared PCI
chipset tag to access devices, and these accesses can happen before our
PCI host bridge drivers are attached! The global chipset tag is now gone,
and an MD callback can provide a custom tag on a per-segment basis.
 1.8 14-Oct-2019  jmcneill branches: 1.8.2;
Add support for Amazon's Graviton MSI controller.

Graviton has a GICv3 with a modified GICv2m (!) for MSIs. Instead of
sending messages to a fixed address with the SPI as data, the Graviton's
GICv2m uses a different address for each vector with "don't care" as data.
 1.7 22-Sep-2019  jmcneill Use vcons for simplefb preattach to speed up early console messages.
 1.6 08-Dec-2018  jmcneill branches: 1.6.4; 1.6.6;
Add support for decoding PCI ID mappings using IO remapping tables (IORT).
 1.5 12-Nov-2018  jmcneill Support building kernels with ACPI and no PCI.
 1.4 24-Oct-2018  jmcneill Add driver for ARM Server Base System Architecture (SBSA)-compliant
generic watchdog timers.
 1.3 21-Oct-2018  jmcneill Add GICv3 ACPI attachment glue.
 1.2 15-Oct-2018  jmcneill branches: 1.2.2;
Add ARM ACPI PCI support.
 1.1 12-Oct-2018  jmcneill Add ACPI platform glue and basic device drivers (CPU, GIC, Generic Timer,
SBSA UART).
 1.2.2.4 26-Dec-2018  pgoyette Sync with HEAD, resolve a few conflicts
 1.2.2.3 26-Nov-2018  pgoyette Sync with HEAD, resolve a couple of conflicts
 1.2.2.2 20-Oct-2018  pgoyette Sync with head
 1.2.2.1 15-Oct-2018  pgoyette file files.acpi was added on branch pgoyette-compat on 2018-10-20 06:58:24 +0000
 1.6.6.2 15-Oct-2019  martin Pull up following revision(s) (requested by jmcneill in ticket #334):

sys/arch/arm/cortex/gic_v2m.c: revision 1.7
sys/arch/arm/acpi/gicv3_acpi.c: revision 1.5
sys/arch/arm/acpi/files.acpi: revision 1.8
sys/arch/arm/acpi/gic_acpi.c: revision 1.4
sys/arch/arm/cortex/files.cortex: revision 1.13
sys/arch/arm/acpi/gic_v2m_acpi.c: revision 1.1
sys/arch/arm/acpi/gic_v2m_acpi.h: revision 1.1
sys/arch/arm/cortex/gic_v2m.h: revision 1.2

Add support for Amazon's Graviton MSI controller.

Graviton has a GICv3 with a modified GICv2m (!) for MSIs. Instead of
sending messages to a fixed address with the SPI as data, the Graviton's
GICv2m uses a different address for each vector with "don't care" as data.
 1.6.6.1 23-Sep-2019  martin Pull up following revision(s) (requested by jmcneill in ticket #231):

sys/arch/arm/acpi/acpi_platform.c: revision 1.18
sys/arch/arm/acpi/files.acpi: revision 1.7
sys/arch/arm/acpi/acpi_simplefb.c: revision 1.1
sys/arch/arm/acpi/acpi_simplefb.h: revision 1.1

Use vcons for simplefb preattach to speed up early console messages.
 1.6.4.4 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.6.4.3 08-Apr-2020  martin Merge changes from current as of 20200406
 1.6.4.2 10-Jun-2019  christos Sync with HEAD
 1.6.4.1 08-Dec-2018  christos file files.acpi was added on branch phil-wifi on 2019-06-10 22:05:50 +0000
 1.8.2.2 29-Feb-2020  ad Sync with head.
 1.8.2.1 17-Jan-2020  ad Sync with head.
 1.11.2.1 14-Dec-2020  thorpej Sync w/ HEAD.
 1.8 25-Nov-2023  jmcneill gicv2: Fix truncation of GICC / GICD base addresses above 4GB.
 1.7 07-Aug-2021  thorpej branches: 1.7.6;
Merge thorpej-cfargs2.
 1.6 24-Apr-2021  thorpej branches: 1.6.8;
Merge thorpej-cfargs branch:

Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.

Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
actually needed.
- Don't be explicit about what interface attribute is attaching if
the device only has one. (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
situations, making is visibly easier to see when indirect config is
in play, and allowing for future change in semantics. (As of now,
this is just a wrapper around config_match(), but that is an
implementation detail.)

Remove unnecessary or redundant interface attributes where they're not
needed.

There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)

...and a sentinel value CFARG_EOL.

Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.

Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance. This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).
 1.5 27-Jul-2020  jmcneill branches: 1.5.4;
Skip v2m probe if armgic fails to attach
 1.4 14-Oct-2019  jmcneill Add support for Amazon's Graviton MSI controller.

Graviton has a GICv3 with a modified GICv2m (!) for MSIs. Instead of
sending messages to a fixed address with the SPI as data, the Graviton's
GICv2m uses a different address for each vector with "don't care" as data.
 1.3 12-Nov-2018  jmcneill branches: 1.3.4; 1.3.6;
Support building kernels with ACPI and no PCI.
 1.2 21-Oct-2018  jmcneill Add support for PCI MSI using ARM GICv2m.
 1.1 12-Oct-2018  jmcneill branches: 1.1.2;
Add ACPI platform glue and basic device drivers (CPU, GIC, Generic Timer,
SBSA UART).
 1.1.2.3 26-Nov-2018  pgoyette Sync with HEAD, resolve a couple of conflicts
 1.1.2.2 20-Oct-2018  pgoyette Sync with head
 1.1.2.1 12-Oct-2018  pgoyette file gic_acpi.c was added on branch pgoyette-compat on 2018-10-20 06:58:24 +0000
 1.3.6.1 15-Oct-2019  martin Pull up following revision(s) (requested by jmcneill in ticket #334):

sys/arch/arm/cortex/gic_v2m.c: revision 1.7
sys/arch/arm/acpi/gicv3_acpi.c: revision 1.5
sys/arch/arm/acpi/files.acpi: revision 1.8
sys/arch/arm/acpi/gic_acpi.c: revision 1.4
sys/arch/arm/cortex/files.cortex: revision 1.13
sys/arch/arm/acpi/gic_v2m_acpi.c: revision 1.1
sys/arch/arm/acpi/gic_v2m_acpi.h: revision 1.1
sys/arch/arm/cortex/gic_v2m.h: revision 1.2

Add support for Amazon's Graviton MSI controller.

Graviton has a GICv3 with a modified GICv2m (!) for MSIs. Instead of
sending messages to a fixed address with the SPI as data, the Graviton's
GICv2m uses a different address for each vector with "don't care" as data.
 1.3.4.3 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.3.4.2 10-Jun-2019  christos Sync with HEAD
 1.3.4.1 12-Nov-2018  christos file gic_acpi.c was added on branch phil-wifi on 2019-06-10 22:05:50 +0000
 1.5.4.1 21-Mar-2021  thorpej Give config_found() the same variadic arguments treatment as
config_search(). This commit only adds the CFARG_EOL sentinel
to the existing config_found() calls. Conversion of config_found_sm_loc()
and config_found_ia() call sites will be in subsequent commits.
 1.6.8.1 04-Aug-2021  thorpej Adapt to CFARGS().
 1.7.6.1 29-Nov-2023  martin Pull up following revision(s) (requested by jmcneill in ticket #482):

sys/arch/arm/acpi/gic_acpi.c: revision 1.8

gicv2: Fix truncation of GICC / GICD base addresses above 4GB.
 1.1 14-Oct-2019  jmcneill branches: 1.1.2; 1.1.10;
Add support for Amazon's Graviton MSI controller.

Graviton has a GICv3 with a modified GICv2m (!) for MSIs. Instead of
sending messages to a fixed address with the SPI as data, the Graviton's
GICv2m uses a different address for each vector with "don't care" as data.
 1.1.10.2 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.1.10.1 14-Oct-2019  martin file gic_v2m_acpi.c was added on branch phil-wifi on 2020-04-13 08:03:32 +0000
 1.1.2.2 15-Oct-2019  martin Pull up following revision(s) (requested by jmcneill in ticket #334):

sys/arch/arm/cortex/gic_v2m.c: revision 1.7
sys/arch/arm/acpi/gicv3_acpi.c: revision 1.5
sys/arch/arm/acpi/files.acpi: revision 1.8
sys/arch/arm/acpi/gic_acpi.c: revision 1.4
sys/arch/arm/cortex/files.cortex: revision 1.13
sys/arch/arm/acpi/gic_v2m_acpi.c: revision 1.1
sys/arch/arm/acpi/gic_v2m_acpi.h: revision 1.1
sys/arch/arm/cortex/gic_v2m.h: revision 1.2

Add support for Amazon's Graviton MSI controller.

Graviton has a GICv3 with a modified GICv2m (!) for MSIs. Instead of
sending messages to a fixed address with the SPI as data, the Graviton's
GICv2m uses a different address for each vector with "don't care" as data.
 1.1.2.1 14-Oct-2019  martin file gic_v2m_acpi.c was added on branch netbsd-9 on 2019-10-15 19:40:34 +0000
 1.1 14-Oct-2019  jmcneill branches: 1.1.2; 1.1.10;
Add support for Amazon's Graviton MSI controller.

Graviton has a GICv3 with a modified GICv2m (!) for MSIs. Instead of
sending messages to a fixed address with the SPI as data, the Graviton's
GICv2m uses a different address for each vector with "don't care" as data.
 1.1.10.2 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.1.10.1 14-Oct-2019  martin file gic_v2m_acpi.h was added on branch phil-wifi on 2020-04-13 08:03:32 +0000
 1.1.2.2 15-Oct-2019  martin Pull up following revision(s) (requested by jmcneill in ticket #334):

sys/arch/arm/cortex/gic_v2m.c: revision 1.7
sys/arch/arm/acpi/gicv3_acpi.c: revision 1.5
sys/arch/arm/acpi/files.acpi: revision 1.8
sys/arch/arm/acpi/gic_acpi.c: revision 1.4
sys/arch/arm/cortex/files.cortex: revision 1.13
sys/arch/arm/acpi/gic_v2m_acpi.c: revision 1.1
sys/arch/arm/acpi/gic_v2m_acpi.h: revision 1.1
sys/arch/arm/cortex/gic_v2m.h: revision 1.2

Add support for Amazon's Graviton MSI controller.

Graviton has a GICv3 with a modified GICv2m (!) for MSIs. Instead of
sending messages to a fixed address with the SPI as data, the Graviton's
GICv2m uses a different address for each vector with "don't care" as data.
 1.1.2.1 14-Oct-2019  martin file gic_v2m_acpi.h was added on branch netbsd-9 on 2019-10-15 19:40:34 +0000
 1.8 23-Dec-2020  jmcneill Future-proof ID_AA64PFR0_EL1.GIC test -- any value other than 0 means that
the GIC CPU interface is supported.
 1.7 13-Feb-2020  jmcneill branches: 1.7.6;
Add support for multiple GICv3 ITS domains.
 1.6 17-Jan-2020  jmcneill Only attach the first ITS for now
 1.5 14-Oct-2019  jmcneill branches: 1.5.2;
Add support for Amazon's Graviton MSI controller.

Graviton has a GICv3 with a modified GICv2m (!) for MSIs. Instead of
sending messages to a fixed address with the SPI as data, the Graviton's
GICv2m uses a different address for each vector with "don't care" as data.
 1.4 12-Sep-2019  jmcneill Redistributors with virtual LPI support have larger register spaces. Take
this into consideration when scanning LPI regions.
 1.3 12-Nov-2018  jmcneill branches: 1.3.2; 1.3.6; 1.3.8;
Support building kernels with ACPI and no PCI.
 1.2 09-Nov-2018  jmcneill Add GICv3 ITS support
 1.1 21-Oct-2018  jmcneill Add GICv3 ACPI attachment glue.
 1.3.8.2 15-Oct-2019  martin Pull up following revision(s) (requested by jmcneill in ticket #334):

sys/arch/arm/cortex/gic_v2m.c: revision 1.7
sys/arch/arm/acpi/gicv3_acpi.c: revision 1.5
sys/arch/arm/acpi/files.acpi: revision 1.8
sys/arch/arm/acpi/gic_acpi.c: revision 1.4
sys/arch/arm/cortex/files.cortex: revision 1.13
sys/arch/arm/acpi/gic_v2m_acpi.c: revision 1.1
sys/arch/arm/acpi/gic_v2m_acpi.h: revision 1.1
sys/arch/arm/cortex/gic_v2m.h: revision 1.2

Add support for Amazon's Graviton MSI controller.

Graviton has a GICv3 with a modified GICv2m (!) for MSIs. Instead of
sending messages to a fixed address with the SPI as data, the Graviton's
GICv2m uses a different address for each vector with "don't care" as data.
 1.3.8.1 22-Sep-2019  martin Pull up following revision(s) (requested by jmcneill in ticket #227):

sys/arch/arm/acpi/gicv3_acpi.c: revision 1.4

Redistributors with virtual LPI support have larger register spaces. Take
this into consideration when scanning LPI regions.
 1.3.6.4 13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.3.6.3 08-Apr-2020  martin Merge changes from current as of 20200406
 1.3.6.2 10-Jun-2019  christos Sync with HEAD
 1.3.6.1 12-Nov-2018  christos file gicv3_acpi.c was added on branch phil-wifi on 2019-06-10 22:05:50 +0000
 1.3.2.2 26-Nov-2018  pgoyette Sync with HEAD, resolve a couple of conflicts
 1.3.2.1 12-Nov-2018  pgoyette file gicv3_acpi.c was added on branch pgoyette-compat on 2018-11-26 01:52:17 +0000
 1.5.2.2 29-Feb-2020  ad Sync with head.
 1.5.2.1 17-Jan-2020  ad Sync with head.
 1.7.6.1 03-Jan-2021  thorpej Sync w/ HEAD.
 1.5 07-Aug-2021  thorpej Merge thorpej-cfargs2.
 1.4 24-Apr-2021  thorpej branches: 1.4.8;
Merge thorpej-cfargs branch:

Simplify and make extensible the config_search() / config_found() /
config_attach() interfaces: rather than having different variants for
which arguments you want pass along, just have a single call that
takes a variadic list of tag-value arguments.

Adjust all call sites:
- Simplify wherever possible; don't pass along arguments that aren't
actually needed.
- Don't be explicit about what interface attribute is attaching if
the device only has one. (More simplification.)
- Add a config_probe() function to be used in indirect configuiration
situations, making is visibly easier to see when indirect config is
in play, and allowing for future change in semantics. (As of now,
this is just a wrapper around config_match(), but that is an
implementation detail.)

Remove unnecessary or redundant interface attributes where they're not
needed.

There are currently 5 "cfargs" defined:
- CFARG_SUBMATCH (submatch function for direct config)
- CFARG_SEARCH (search function for indirect config)
- CFARG_IATTR (interface attribte)
- CFARG_LOCATORS (locators array)
- CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles)

...and a sentinel value CFARG_EOL.

Add some extra sanity checking to ensure that interface attributes
aren't ambiguous.

Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark
ports to associate those device handles with device_t instance. This
will trickle trough to more places over time (need back-end for pre-OFW
Sun OBP; any others?).
 1.3 29-Apr-2019  christos branches: 1.3.2; 1.3.14;
Catch up with constant name change.
 1.2 16-Nov-2018  jmcneill Use intr_establish_xname
 1.1 12-Oct-2018  jmcneill branches: 1.1.2;
Add ACPI platform glue and basic device drivers (CPU, GIC, Generic Timer,
SBSA UART).
 1.1.2.3 26-Nov-2018  pgoyette Sync with HEAD, resolve a couple of conflicts
 1.1.2.2 20-Oct-2018  pgoyette Sync with head
 1.1.2.1 12-Oct-2018  pgoyette file gtmr_acpi.c was added on branch pgoyette-compat on 2018-10-20 06:58:24 +0000
 1.3.14.1 21-Mar-2021  thorpej Give config_found() the same variadic arguments treatment as
config_search(). This commit only adds the CFARG_EOL sentinel
to the existing config_found() calls. Conversion of config_found_sm_loc()
and config_found_ia() call sites will be in subsequent commits.
 1.3.2.2 10-Jun-2019  christos Sync with HEAD
 1.3.2.1 29-Apr-2019  christos file gtmr_acpi.c was added on branch phil-wifi on 2019-06-10 22:05:50 +0000
 1.4.8.1 04-Aug-2021  thorpej Adapt to CFARGS().
 1.4 24-Jan-2023  mlelstv Add support for FIFOs and hardware flow-control to plcom driver.
Add a PLCOM_TYPE_GENERIC_UART variant to match SBSA requirements.
 1.3 25-Apr-2020  jmcneill Enable HW FIFO
 1.2 16-Nov-2018  jmcneill branches: 1.2.4;
Use acpi_intr_establish
 1.1 12-Oct-2018  jmcneill branches: 1.1.2;
Add ACPI platform glue and basic device drivers (CPU, GIC, Generic Timer,
SBSA UART).
 1.1.2.3 26-Nov-2018  pgoyette Sync with HEAD, resolve a couple of conflicts
 1.1.2.2 20-Oct-2018  pgoyette Sync with head
 1.1.2.1 12-Oct-2018  pgoyette file plcom_acpi.c was added on branch pgoyette-compat on 2018-10-20 06:58:24 +0000
 1.2.4.2 10-Jun-2019  christos Sync with HEAD
 1.2.4.1 16-Nov-2018  christos file plcom_acpi.c was added on branch phil-wifi on 2019-06-10 22:05:50 +0000
 1.2 24-Oct-2018  jmcneill branches: 1.2.2; 1.2.6;
Avoid overflow when calculating watchdog offset.
 1.1 24-Oct-2018  jmcneill Add driver for ARM Server Base System Architecture (SBSA)-compliant
generic watchdog timers.
 1.2.6.2 10-Jun-2019  christos Sync with HEAD
 1.2.6.1 24-Oct-2018  christos file sbsawdt_acpi.c was added on branch phil-wifi on 2019-06-10 22:05:50 +0000
 1.2.2.2 26-Nov-2018  pgoyette Sync with HEAD, resolve a couple of conflicts
 1.2.2.1 24-Oct-2018  pgoyette file sbsawdt_acpi.c was added on branch pgoyette-compat on 2018-11-26 01:52:17 +0000

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