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History log of /src/sys/arch/arm/acpi/acpi_pci_graviton.c
RevisionDateAuthorComments
 1.5  15-Oct-2022  jmcneill Use "non-posted" instead of "strongly ordered" to describe nGnRnE mappings

Rename the following defines:
- _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED to BUS_SPACE_MAP_NONPOSTED
- PMAP_DEV_SO to PMAP_DEV_NP
- LX_BLKPAG_ATTR_DEVICE_MEM_SO to LX_BLKPAG_ATTR_DEVICE_MEM_NP
Rename the following option:
- AARCH64_DEVICE_MEM_STRONGLY_ORDERED to AARCH64_DEVICE_MEM_NONPOSTED
 1.4  24-Oct-2020  skrll Trailing whitespace
 1.3  17-Jun-2020  thorpej <sys/extent.h> not needed here.
 1.2  15-Jun-2020  ad Use sys/cpu.h so that curcpu defined in terms of curlwp->l_cpu works too.
 1.1  17-Jan-2020  jmcneill branches: 1.1.2; 1.1.6;
Add support for Arm N1 SDP PCIe host controller.

The N1 SDP has a few bugs that we need to work around:
- PCIe root port config space lives in a non-standard location.
- Access to PCIe config space of devices that do not exist results in
an sync SError. Firmware creates a "known devices" table at a fixed
physical address that we use to filter PCI conf access to only known
devices.

This change splits the Arm ACPI PCI quirks into separate files for each
host controller, and allows per-segment quirks to be applied.

These changes exposed some bugs in the MI ACPI layer related to
multi-segment support. The MI ACPI PCI code was using a shared PCI
chipset tag to access devices, and these accesses can happen before our
PCI host bridge drivers are attached! The global chipset tag is now gone,
and an MD callback can provide a custom tag on a per-segment basis.
 1.1.6.2  08-Apr-2020  martin Merge changes from current as of 20200406
 1.1.6.1  17-Jan-2020  martin file acpi_pci_graviton.c was added on branch phil-wifi on 2020-04-08 14:07:27 +0000
 1.1.2.2  17-Jan-2020  ad Sync with head.
 1.1.2.1  17-Jan-2020  ad file acpi_pci_graviton.c was added on branch ad-namecache on 2020-01-17 21:47:23 +0000

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