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History log of /src/sys/arch/arm/arm/cpufunc_asm_arm9.S
RevisionDateAuthorComments
 1.12  20-Oct-2022  skrll Trailing whitespace.
 1.11  30-Mar-2014  matt Allow for 8KB page size. Add ARM_MMU_EXTENDED support.
Add missing END()
 1.10  18-Aug-2013  matt Move parts of cpu.h that are not needed by MI code in <arm/locore.h>
Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h>
Use <arm/asm.h> instead of <machine/arm.h>
 1.9  22-Sep-2012  matt branches: 1.9.2;
Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead
but add a second argument to it to indicate whether the TLB/caches need to be
flushed. Default cortex to pmap_needs_fixup = 1. But check the MMFR3 field
to see if the fixed can be skipped.
Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1)
or enabeld (bit = 0).

With these changes, the A9 MMU can use traverse caches to do MMU tablewalks
Also, make sure all memory has the shareable bit for the A9.
 1.8  07-Sep-2012  matt branches: 1.8.2;
Switch cortex_a9 back to need_ptesync = 1
Add code to disable the L2 cache on cortex-a9 (for now).
Add evcnt for all the fault types.
Move cache info in a structure and have one for the pcache and one for scache.
Probe L1/L2 caches properly for ARMv7
 1.7  03-Jan-2010  uebayasi branches: 1.7.12; 1.7.20;
s/These is/These are/
 1.6  17-Oct-2007  garbled branches: 1.6.20; 1.6.38;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
 1.5  15-Sep-2007  scw ARM cpu_switchto() has been partially broken since yamt-idlelwp was merged
as its cache/tlb management smarts relied too heavily on pre-merge context-
switch behaviour. See PR kern/36548 for one manifestation of the breakage.

To address this:
- Ditch the shadow pmap variables in the PCB (pagedir, l1vec, dacr, cstate)
as it was too easy for them to get out of sync with the pmap.
- Re-write (and fix) the convoluted cpuswitch.S cache/tlb ASM code in C.
It's only slightly less efficient, but is much more readable/maintainable.
- Document cpufuncs.cf_context_switch() as being C-callable.
- pmap_activate() becomes a no-op if the lwp's vmspace is already active.
(Good performance win, since pmap_activate() is now invoked on every
context-switch, even though ARM's cpu_switchto() already does all the
grunt work)

XXX: Some CPU-specific armXX_context_switch() implementations (arm67,
arm7tdmi, arm8) always flush the I+D caches. This should not be necessary.
Someone with access to hardware (acorn32?) needs to deal with this.
 1.4  11-Dec-2005  christos branches: 1.4.30; 1.4.38; 1.4.46; 1.4.48; 1.4.50; 1.4.52;
merge ktrace-lwp.
 1.3  26-Jan-2004  rearnsha branches: 1.3.16;
Switch the ARM9 to using the Dcache in write-back mode. Avoid an
unknown problem with dcache_inv_range by using a wbinv for now
(similarly for ARM10).

When setting the ARM9 system control register, use the computed
cpuctrlmask value (not 0xffffffff) so that the clocking-mode bits are
not reset to FastBus mode (which isn't very fast).
 1.2  29-Jan-2002  rearnsha branches: 1.2.18;
Fix copying and disclaimer (ARM != Causality).
 1.1  10-Nov-2001  thorpej branches: 1.1.2; 1.1.4; 1.1.6;
Split all the model/version-specific cpufuncs into separate files
corresponding to the model/version.
 1.1.6.3  11-Feb-2002  jdolecek Sync w/ -current.
 1.1.6.2  10-Jan-2002  thorpej Sync kqueue branch with -current.
 1.1.6.1  10-Nov-2001  thorpej file cpufunc_asm_arm9.S was added on branch kqueue on 2002-01-10 19:37:46 +0000
 1.1.4.2  28-Feb-2002  nathanw Catch up to -current.
 1.1.4.1  10-Nov-2001  nathanw file cpufunc_asm_arm9.S was added on branch nathanw_sa on 2002-02-28 04:07:16 +0000
 1.1.2.2  12-Nov-2001  thorpej Sync the thorpej-mips-cache branch with -current.
 1.1.2.1  10-Nov-2001  thorpej file cpufunc_asm_arm9.S was added on branch thorpej-mips-cache on 2001-11-12 21:16:27 +0000
 1.2.18.3  21-Sep-2004  skrll Fix the sync with head I botched.
 1.2.18.2  18-Sep-2004  skrll Sync with HEAD.
 1.2.18.1  03-Aug-2004  skrll Sync with HEAD
 1.3.16.1  27-Oct-2007  yamt sync with head.
 1.4.52.1  06-Nov-2007  matt sync with HEAD
 1.4.50.1  01-Jan-2008  chris Sync with HEAD.
 1.4.48.1  02-Oct-2007  joerg Sync with HEAD.
 1.4.46.1  01-Nov-2007  rjs Sync with HEAD.
 1.4.38.1  03-Oct-2007  garbled Sync with HEAD
 1.4.30.1  09-Oct-2007  ad Sync with head.
 1.6.38.1  15-Feb-2014  matt Merge armv7 support from HEAD, specifically support for the BCM5301X
and BCM56340 evbarm kernels.
 1.6.20.1  11-Mar-2010  yamt sync with head
 1.7.20.1  28-Nov-2012  matt Merge improved arm support (especially Cortex) from HEAD
including OMAP and BCM53xx support.
 1.7.12.2  22-May-2014  yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
 1.7.12.1  30-Oct-2012  yamt sync with head
 1.8.2.2  20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.8.2.1  20-Nov-2012  tls Resync to 2012-11-19 00:00:00 UTC
 1.9.2.2  18-May-2014  rmind sync with head
 1.9.2.1  28-Aug-2013  rmind sync with head

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