branches: 1.1.2;
file arm1136_pmc.c was initially added on branch matt-nb4-arm.

Remove the advertising clause from Microsoft's licenses.

Thanks to Scott Hanselman at Microsoft for turning the wheels to get this
approved!

KNF #includes

Remove some unnecessary ones while I'm here.

Trailing whitespace

Merge the [pgoyette-compat] branch

Remove the kernel PMC code. Sent yesterday on tech-kern@.

This change:

* Removes "options PERFCTRS", the associated includes, and the associated
ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is
good.

* Removes the PMC code of ARM XSCALE.

* Removes all the pmc.h files. They were all empty, except for ARM XSCALE.

* Reorders the x86 PMC code not to rely on the legacy pmc.h file. The
definitions are put in sysarch.h.

* Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control
and sys_pmc_get_info syscalls. They are marked as OBSOL in kern,
netbsd32 and rump.

* Removes the pmc_evid_t and pmc_ctr_t types.

* Removes all the associated man pages. The sets are marked as obsolete.

branches: 1.4.28; 1.4.30;
Mark unused inline functions as such.

branches: 1.3.14; 1.3.30; 1.3.40; 1.3.46;
Fix a typo in the delay loop time delta calculation.

From Irme Desk <imre.deak@teleca.com>.

branches: 1.2.2; 1.2.4;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.1.2; 1.1.18; 1.1.20; 1.1.22;
file arm11_pmc.c was initially added on branch matt-armv6.

Remove the advertising clause from Microsoft's licenses.

Thanks to Scott Hanselman at Microsoft for turning the wheels to get this
approved!

Explicitly disable overflow interrupts before enabling the cycle counter.

branches: 1.44.4;
Rework Arm (32bit and 64bit) AP startup so that cpu_hatch doesn't sleep.

The AP initialisation code in cpu_init_secondary_processor will read and
initialise the required system registers and state for the BP to attach
and report.

Rework the interrupt handler code for this new sequence. Thankfully,
this removes a bunch of code for bcm2836mp.

The VFP detection handler on <= armv7 relies on the global undefined
handler being in place until the BP attaches vfp. That is, after the
APs have been spun up.

gicv3_its.c has a serialisation issue which is protected against in
the gicv3_its_cpu_init, which is called from cpu_hatch, with a spin
lock. The serialisation issue needs addressing more completely.

Tested on RPI3, Apple M1, QEMU, and lx2k

Fixes PR port-arm/56264:
diagnostic assertion "l->l_stat == LSONPROC" failed on RPI3

Mirror changes to passing pages to UVM into aarch64_machdep.c

Two fixes for loading free pages into UVM

- Only consider a boot_physmem (inner loop) range that has its end
(bp_end) after the bootconfig.dram (outer loop) range start (start).
This was harmless as a later condition correctly checks there is only
something to do if start < bp_end.

- Stop processing boot_physmem ranges if all the bootconfig.dram range has
been passed to UVM. This fixes a boot problem for simon@

Copy a comment over and do the VPRINTF before the uvm_page_physload in
the same way as aarch64_machdep.c as well.

branches: 1.42.2;
G/C

branches: 1.41.4;
Switch earmv6{,hf}eb to BE8 in kernel side.

My strategy here is to define _ARM_ARCH_BE8 macro in arm/cdefs.h, if
__ARMEB__ && _ARM_ARCH_6.

Use this macro to determine whether system is compiled for and running on
BE8 mode or not.

Note that, for __ARMEB__, some conditions become compile-time constants
determined by _ARM_ARCH_BE8 macro, e.g., whether BE8 or BE32 are accepted
as a userland binary, or unaligned memory access is possible or not.

branches: 1.40.2;
Wrap a long comment

Add support for KASAN on ARMv[67]

Thanks to maxv for many pointers and reviews.

KNF

Various updates and improvements to cpu start up on arm/aarch64

- start sharing more code around the AP startup messaging.
- call arm_cpu_topology_set early so that ci_core_id is available for
drivers, e.g. bcm2835_intr.c
- both arm and aarch64 now have
- a static cpu_info_store array
- the same arm_cpu_{hatched,mbox}

cpu_hatch is too late to report AP topology, do it at attach time instead

branches: 1.35.2;
Some more CPU topology stuff:

- Use cegger@'s ACPI SRAT parsing code to figure out NUMA node ID for each
CPU as it is attached.

- For scheduler experiments with SMT, flag CPUs with the lowest numbered SMT
IDs as "primaries", link back to the primaries from secondaries, and build
a circular list of CPUs in each package with identical SMT IDs.

- No need for package/core/smt/numa IDs to be anything other than a u_int.

Take the basic CPU topology information we already collect, and use it
to make circular lists of CPU siblings in the same core, and in the
same package. Nothing fancy, just enough to have a bit of fun in the
scheduler trying out different tactics.

branches: 1.33.4;
Flush the BP cache just before starting APs so that cache coherency starts
with a correct view.

Merge the [pgoyette-compat] branch

Make sure ci_{smt,core,package}_id are all filled in appropriately.

Previously the BP was missed and __SHIFTOUT wasn't used.

Simplify

Read mpidr and cpuid from the secondary processor itself instead of the
boot processor. While here, add Cortex-A15 r4p0 to supported list.

Start CPUs more like aarch64 by using a cpu_mpidr array (if populated)
to map MPIDRs to an index for each CPU.

Towards big.LITTLE support.

Tidyup VERBOSE_INIT_ARM output

Fix a commit

Fix VPRINTF

Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.

The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors. AP startup is
performed in less steps and more code is written in C.

The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.

Various kernels have been converted to use this code and tested. Some
boards were provided by TNF. Thanks!

The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.

Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively

Use __nothing

G/C

Sprinkle #include "opt_cputypes.h"

Define and use VPRINTF

branches: 1.19.4; 1.19.6;
Consistency around the user trapframe for all LWPs and there's no need to
keep assigning it in kernel entry points.

switch all ports to use uvm_init.c:uvm_md_init()

uvm_setpagesize() is now subsumed within this funciton.

branches: 1.17.2;
#if 0 a KASSERT for now as it doesn't apply to Raspberry Pi 3

KASSERT in cpu_hatch that AUXCTL.SMP is set for Cortex CPUs.

Deal with 4GB overflow in arm32_kvminit.c

Fix 4GB wraparound math.

If not using LPAE, if memory ends at 4GB ignore the last page so physical_end
doesn't wrap to 0.

use IPL_NONE for CPU attach message serialization mutex

serialize printing of secondary cpu info

branches: 1.10.2;
Fix the stacks used by the other CPU to not overlap with the boot cpu's stacks.

Sprinkle #include "opt_multiprocessor.h"

add memory access barrier

branches: 1.7.4;
Various MP changes.

Further cpu_info inits in cpu_hatch

branches: 1.5.2;
Move parts of cpu.h that are not needed by MI code in <arm/locore.h>
Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h>
Use <arm/asm.h> instead of <machine/arm.h>

branches: 1.4.2;
Add printfs around initializing the vector_page.

Include opt_{ddb,kgdb} and fix KGDB build

branches: 1.2.2; 1.2.4;
Change the semantics of the boot_physmem array to select a freelist to use
with uvm_page_physload. Reduces duplication of work.

branches: 1.1.2;
Make cpu_reset, most of initarm and the kvm init code common.
Add MP hooks for cpu_need_resced
Add idlestck which is allocated in arm32_kvminit

Remove the advertising clause from Microsoft's licenses.

Thanks to Scott Hanselman at Microsoft for turning the wheels to get this
approved!

Update to support EFI runtime outside the kernel virtual address space
by creating an EFI RT pmap that can be activated / deactivated when
required.

Adds support for EFI RT to ARM_MMU_EXTENDED (ASID) 32-bit Arm machines.

On Arm64 the usage of pmapboot_enter is reduced and the mappings are
created much later in the boot process -- now in cpu_startup_hook.
Backward compatiblity for KVA mapped RT from old bootaa64.efi is
maintained.

Adding support to other platforms should be easier as a result.

-DKERNEL_BASE_VOFFSET= has annoyed me for the last time...

Introduce KERNEL_VOFFSET_RUNTIME which prevents the addition of
-DKERNEL_BASE_VOFFSET= to the command line and use it on the
__HAVE_GENERIC_START kernels which do runtime calculation of the
offset.

branches: 1.67.2;
Move evbarm/fdt/fdt_memory.[ch] to sys/dev/fdt and simplify the api and
some operations. This allows other architectures to use it.

branches: 1.66.2;
Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.

Some KASAN fixes and tweaks

- don't access BSS variables when __md_early
- centralise the INIT_ARM_STACK_{SHIFT,SIZE} defines and create a new
INIT_ARM_TOTAL_STACK
- Only create L1PT entries in kasan_md_shadow_map_page if
arm32_kernel_vm_init hasn't created the L2PTs (and their L1PT entries)
- Add some comments to explain what's going on

Add support for KASAN on ARMv[67]

Thanks to maxv for many pointers and reviews.

Style and share a debug string

Use howmany()

Whitespace

Avoid unbounded stack usage warning

KNF #includes

Remove some unnecessary ones while I'm here.

KNF

grammar in a comment

G/C L1_TABLE_SIZE_REAL

branches: 1.55.4;
Really go back to pre-whitespace change (1.52) arm32_kernel_vm_init

Revert the part of the previous Whitespace commit which clearly was
functional.

This will probably come back with other changes and a proper commit
message.

Whitespace

Make sure the start stacks are covered by the new translation tables.
They *might* get placed after ARM_BOOTSTRAP_LxPT by the linker.

AP startup uses VA sp in cpu_init_secondary_processor

Misc style

Slight update to comment and KNF it while I'm here

Fix typo in VPRINTF

On second/third thoughts we can use the pages before the kernel
everywhere.

Clean up around cpu_ttb and fix a bunch of builds

Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.

The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors. AP startup is
performed in less steps and more code is written in C.

The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.

Various kernels have been converted to use this code and tested. Some
boards were provided by TNF. Thanks!

The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.

Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively

Use __nothing

Provide and use kern_vtopdiff in KERN_{VTOPHYS,PHYSTOV}. A step towards
generic arm.

#ifdef VERBOSE_INIT_ARM some format strings only used in that case.

Define and use VPRINTF

branches: 1.41.2; 1.41.4;
FDTise RapberryPI support. Thanks for jmcneill for a lot of help with this.

The kernel image that the RPI firmware boots is now netbsd.img in the
kernel build directory.

XXX fdtbus_get_reg needs reworking

Now that we can... mark kernel text as non-writable on MMUs that support
it.

Report an error if compiled with MULTIPROCESSOR support but without
__HAVE_CPU_UAREA_ALLOC_IDLELWP

Fix VERBOSE_INIT_ARM build

branches: 1.37.2;
In the ARM_MMU_EXTENDED case make sure the kernel mappings are marked with
XN (eXecute Never) appropriately.

The XN logic is inconsistent and could do with changing to XN always set
and cleared for VM_PROT_EXECUTE (or the inverse) everywhere.

Trailing whitespace.

pmap_directbase is a failed experiment, nuke it.

Support directmapped systems with >1GB that start memory at 0x80000000.

Deal with 2GB of ram or memory ending at or above 4GB.

branches: 1.32.2;
Sprinkle #include "opt_multiprocessor.h"

Remove unnecessary #include

branches: 1.30.2;
Fix build failed with GUMSTIX(pxa2x0). build test only now.

When figuring out the physical size for direct-mapped systems, round up
to L1_SS_SIZE.

Add a kernel for the CUBIETRUCK (CUBIEBOARD3). Allow direct mapping of all
memory (but for now allow the memory mapped above KERNEL_BASE to used for
poolpages).

If using arm32_kvminit, don't bother mapping msgbuf since it's already mapped.

branches: 1.26.2;
Remove unnecessary { } around code block. No functional change.

ARM_MMU_EXTENDED support.

rearrange some printfs.
when using the extended mmu, make sure to disable ttbr0 until there is an
activated pmap.

If we are going to map all of physical memory, we don't need to allocate
l2 page tables for the kernel.

branches: 1.22.2;
Fix typo: VERBOSE_INIT_ARM, not VERBOSE_ARM_INIT. From
Dennis Ferguson in PR#48163.

branches: 1.21.2;
Fix inverted logic for mapping exception vector.

Add a ARM_HAS_VBAR option which forces the use of the VBAR register. This
allows much code to deal with vector_page mappings to be eliminated. On a
BEAGLEBONE kernel, this saves 8KB of text and instructions that never have
to be executed. (The PJ4B has VBAR but doesn't implement the security
extensions it is part of so a method was needed to allow it use VBAR with
relying on the default test for the security extensions.)

Add support for the VBAR (vector base address register) to remap the vectors
into the kernel text segment. This register is available on arm1176 and
all cortex processors since they all have the arm security (trustzone)
extension. We avoid having to specially map either vector page (0x00000000
or 0xffff0000) and use VBAR to both to page0rel in the text segment. These
vector group differs from the normal page0, that since it's in the kernel,
it can branch directly to the exception routine, instead of loading the
address into the PC. This should result in a tiny improvement in speed since
we eliminate a TLB mapping the vector page and a load on every exception.

XXX Add __HAVE_ARM_TRUSTZONE cpp define and use that to eliminate all code
have to do with manipulating the vector page.

Actually use zero_p now that we pass it in.

Add a zero flag to valloc_pages so that we can *not* zero the msgbuf so it
will be preserved across boots.

Correct one of the kernel_size calculations.

if __HAVE_MM_MD_DIRECT_MAPPED_PHYS is defined, make sure mapallmem_p is true.

branches: 1.14.2; 1.14.4;
Compare pointer against NULL not 0.

Make sure when mapping all the kernel, start at KERNEL_BASE, not kernel_base.

Make sure that start.S and machdep.c don't disagree wrt L1 page table
location during bootstrap.

slop wasn't sloppy enough in the kernel_size calculation. Add in the L2
page tables required as well.

Should fix the dockstar boot problem reported by Andy Ruhl on port-arm.

http://mail-index.netbsd.org/port-arm/2012/09/20/msg001471.html

Comments.

Print the message buffer VAs and number of pages. Other minor cosmetics.

Fix two off-by-one loops. Saves a whole two pages.

More VERBOSE_INIT_ARM output tweaks.

Typo in comment.

Print the system vectors in order so I don't get confused.

Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead
but add a second argument to it to indicate whether the TLB/caches need to be
flushed. Default cortex to pmap_needs_fixup = 1. But check the MMFR3 field
to see if the fixed can be skipped.
Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1)
or enabeld (bit = 0).

With these changes, the A9 MMU can use traverse caches to do MMU tablewalks
Also, make sure all memory has the shareable bit for the A9.

branches: 1.3.2;
Before setting the new TTB wbinv the caches.

Print TTBR/TTBR1/TTBCR registers

Make cpu_reset, most of initarm and the kvm init code common.
Add MP hooks for cpu_need_resced
Add idlestck which is allocated in arm32_kvminit

Refactor the "platform" defitions into fdt_platform.h

Move the at-shutdown call to resettodr() from cpu_reboot() to kern_reboot().

It's a small step, but it's a step.

Rename ARM_PLATFORM to FDT_PLATFORM and make it available outside arm.

Support remaining common boot options.

arm32: Refactor splhigh and restore in dosoftints.

No functional change intended. splhigh always returns ci->ci_cpl,
which should not be changing at this point. Makes the bracketing by
splhigh/splx clearer.

No need to call arm_fdt_platform twice.

Support 'boot -1' on arm

Rework Arm (32bit and 64bit) AP startup so that cpu_hatch doesn't sleep.

The AP initialisation code in cpu_init_secondary_processor will read and
initialise the required system registers and state for the BP to attach
and report.

Rework the interrupt handler code for this new sequence. Thankfully,
this removes a bunch of code for bcm2836mp.

The VFP detection handler on <= armv7 relies on the global undefined
handler being in place until the BP attaches vfp. That is, after the
APs have been spun up.

gicv3_its.c has a serialisation issue which is protected against in
the gicv3_its_cpu_init, which is called from cpu_hatch, with a spin
lock. The serialisation issue needs addressing more completely.

Tested on RPI3, Apple M1, QEMU, and lx2k

Fixes PR port-arm/56264:
diagnostic assertion "l->l_stat == LSONPROC" failed on RPI3

Whitespace in a comment

Switch earmv6{,hf}eb to BE8 in kernel side.

My strategy here is to define _ARM_ARCH_BE8 macro in arm/cdefs.h, if
__ARMEB__ && _ARM_ARCH_6.

Use this macro to determine whether system is compiled for and running on
BE8 mode or not.

Note that, for __ARMEB__, some conditions become compile-time constants
determined by _ARM_ARCH_BE8 macro, e.g., whether BE8 or BE32 are accepted
as a userland binary, or unaligned memory access is possible or not.

branches: 1.138.2;
Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.

Use C rather than assembly

Add support for KASAN on ARMv[67]

Thanks to maxv for many pointers and reviews.

Add support for installing modules that were loaded by the bootloader.

KNF

PMAP_DEBUG has been deleted on arm

branches: 1.132.4;
Various updates and improvements to cpu start up on arm/aarch64

- start sharing more code around the AP startup messaging.
- call arm_cpu_topology_set early so that ci_core_id is available for
drivers, e.g. bcm2835_intr.c
- both arm and aarch64 now have
- a static cpu_info_store array
- the same arm_cpu_{hatched,mbox}

KNF. One #include <sys/atomic.h> is enough

branches: 1.130.2;
s/sucess/success/ in comment.

New function cpu_startup_hook on arm.

Called at end of cpu_startup. Can be defined in, e.g., evbarm to do
additional stuff after cpu_startup. Defined as a weak alias to a
function that does nothing, so optional.

ok jmcneill

branches: 1.128.2;
Fix a printf

Report hatched value after the atomic_or so the VERBOSE_INIT_ARM output
doesn't get mangled.

We start a cpu and wait for it before progressing now.

Wrong long lined comment

Start CPUs more like aarch64 by using a cpu_mpidr array (if populated)
to map MPIDRs to an index for each CPU.

Towards big.LITTLE support.

Fix build for non-generic start kernels

Provide generic start code that assumes the MMU is off and caches are
disabled as per the linux booting protocol for ARMv6 and ARMv7 boards.
u-boot image type should be changed to 'linux' for correct behaviour.

The new start code builds a minimal "bootstrap" L1PT with cached access
disabled and uses the same table for all processors. AP startup is
performed in less steps and more code is written in C.

The bootstrap tables and stack are placed into an (orphaned) section
"_init_memory" which is given to uvm when it is no longer used.

Various kernels have been converted to use this code and tested. Some
boards were provided by TNF. Thanks!

The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS
kernels. The GENERIC kernel will also work on RPI2 using u-boot.

Thanks to martin@ and aymeric@ for testing on parallella and nanosoc
respectively

Use __nothing

Add optional ap_startup callback to struct arm_platform. This allows for
late (post-UVM init) initialization of platform specific stuff.

Use banner

G/C

Add prefixes to struct arm_platform{,_info} members.

No functional change.

Refactor code to split aarch{32,64} kernel page tables and VM setup. This
will help re-build the kernel page tables on aarch64 with correct section
mappings.

Define and use VPRINTF

branches: 1.115.2; 1.115.4;
Allow architectures to define a macro PROC_MACHINE_ARCH(P) and
PROC_MACHINE_ARCH32(P) to override the value for sysctl hw.machine_arch
(native and netbsd32 commpat resp.).

Use these for arm and mips instead of the (not working, noisy, in case
of arm) sysctl override and #ifdef __mips__ in architecture neutral
code.

Consistency around the user trapframe for all LWPs and there's no need to
keep assigning it in kernel entry points.

Trailing whitespace

apply some #if (ARM_MMU_V6 + ARM_MMU_V7) != 0.
now this builds on pre v6-only.

Provide a mm_md_page_color and fix some kernel builds

branches: 1.110.2;
* fix checking physical address range. on some arm devices, physical memory doesn't start from 0x00000000.
* allow /dev/mem to read/write memory mapped I/O area depending on kauth.

Handle boot option -x (alias 'debug') and set AB_DEBUG in boothowto.

branches: 1.108.2;
Add a machdep.unaligned_sigbus sysctl (just like alpha does), but on
arm it is readonly (depends on architecture version).

Sprinkle #include "opt_multiprocessor.h"

Remove katelib.h and references to it.

{Read,Write}{Word,Byte} macros are provided in the files that still use
them. Someone(tm) should convert them to bus_space(9)

branches: 1.105.2;
Implement MI IPI interface with cross-call support.

Add a kernel for the CUBIETRUCK (CUBIEBOARD3). Allow direct mapping of all
memory (but for now allow the memory mapped above KERNEL_BASE to used for
poolpages).

If using arm32_kvminit, don't bother mapping msgbuf since it's already mapped.

branches: 1.102.2;
Various MP changes.

Add most of the cpu_* variables to <arm/locore.h>
Add and initialize cpu_synchprim_present

Ensure that the top level sysctl nodes (kern, vfs, net, ...) exist before
the sysctl link sets are processed, and remove redundancy.

Shaves >13kB off of an amd64 GENERIC, not to mention >1k duplicate
lines of code.

Add hw.printfataltraps sysctl. Always print fatal traps for init. For all
other processes, only do so if cpu_printfataltraps is true.

Support an optional MARCH ELF tag.
Store the MACHINE_ARCH of the executable in mdproc and override sysctl
so that value returned.

Add a machdep.hwdiv_present sysctl (cortex A7 and A15 have hwdiv instructions)

Move parts of cpu.h that are not needed by MI code in <arm/locore.h>
Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h>
Use <arm/asm.h> instead of <machine/arm.h>

Fix tpyo.

branches: 1.94.2;
Add a ARM_HAS_VBAR option which forces the use of the VBAR register. This
allows much code to deal with vector_page mappings to be eliminated. On a
BEAGLEBONE kernel, this saves 8KB of text and instructions that never have
to be executed. (The PJ4B has VBAR but doesn't implement the security
extensions it is part of so a method was needed to allow it use VBAR with
relying on the default test for the security extensions.)

Add support for the VBAR (vector base address register) to remap the vectors
into the kernel text segment. This register is available on arm1176 and
all cortex processors since they all have the arm security (trustzone)
extension. We avoid having to specially map either vector page (0x00000000
or 0xffff0000) and use VBAR to both to page0rel in the text segment. These
vector group differs from the normal page0, that since it's in the kernel,
it can branch directly to the exception routine, instead of loading the
address into the PC. This should result in a tiny improvement in speed since
we eliminate a TLB mapping the vector page and a load on every exception.

XXX Add __HAVE_ARM_TRUSTZONE cpp define and use that to eliminate all code
have to do with manipulating the vector page.

Add a machdep.cpu_arch sysctl

Add simple sysctls for cpu_id, fpu_id, neon_present, simd_present,
simdex_present.
Add struct sysctls to return the isar, mmfr, pfr, and mvfr sets.

Add a machdep.fpu_present sysctl for ld.elf_so to use in ld.so.conf to load
libc_vfp.so.

Add -d as a synonym for getting into DDB to match other ports.

reset todr clock on shutdown

add mm_md_direct_mapped_phys

Rename pcb_sp/PCB_SP to pcb_ksp/PCB_KSP so that ipsec.c will compile.

split device_t/softc for all remaining drivers.
replace "struct device *" with "device_t".
use device_xname(), device_unit(), etc.

Rename kcpuset_copybits() to kcpuset_export_u32() and thus be more specific
about the interface.

branches: 1.83.2;
Make cpu_reset, most of initarm and the kvm init code common.
Add MP hooks for cpu_need_resced
Add idlestck which is allocated in arm32_kvminit

Move the standard definitions of the {UND,IRQ,FIQ,ABT}_STACK_SIZE to
<arm32/machdep.h>
Move the extern for cpu_reset_address to the same file.
Add cpu_reset_address_paddr.
Kill cpu_reset_v4_MMU_disable.
if cpu_reset_address is NULL, then the MMU will be disabled.

small rototill.
pcb_flags is dead. PCB_NOALIGNFLT is now in stored l_md.md_flags as
MDLWP_NOALIGNFLT. This avoids a few loads of the PCB in exception handling.
pcb_tf has been moved to l_md.md_tf. Again this avoids a lot of pcb
references just to access or set this. It also means that pcb doesn't
need to accessed by MI code.
Move pcb_onfault to after the pcb union.
Add pcb_sp macro to make code prettier.
Add lwp_settrapframe(l, tf) to set the l_md.md_tf field.
Use lwp_trapframe to access it (was process_frame but that name was changed
in a previous commit).
Kill off curpcb in acorn26.
Kill the checks for curlwp being NULL.
Move TRAP_USERMODE from arm32/fault.c to frame.h and a __PROG26 version.
Replace tests for usermode with that macro.

Kill curpcb/ci_curpcb. Use device_t in cpu_info.
Add ci_softc (where ci_curpcb was so cpu_info doesn't change).

Fix more -fno-common fallout.
Move more variables to common locations.

Make the result from SOFTIPLMASK match the comment.

"Wouldn't hurt" from matt@

Fix racy softint dispatch that lead to KASSERT(si->si_active) in
softint_execute

Discussed with matt@. "Looks good to me"

branches: 1.76.2; 1.76.8;
dependant -> dependent

Welcome to 5.99.53! Merge rmind-uvmplock branch:

- Reorganize locking in UVM and provide extra serialisation for pmap(9).
New lock order: [vmpage-owner-lock] -> pmap-lock.

- Simplify locking in some pmap(9) modules by removing P->V locking.

- Use lock object on vmobjlock (and thus vnode_t::v_interlock) to share
the locks amongst UVM objects where necessary (tmpfs, layerfs, unionfs).

- Rewrite and optimise x86 TLB shootdown code, make it simpler and cleaner.
Add TLBSTATS option for x86 to collect statistics about TLB shootdowns.

- Unify /dev/mem et al in MI code and provide required locking (removes
kernel-lock on some ports). Also, avoid cache-aliasing issues.

Thanks to Andrew Doran and Joerg Sonnenberger, as their initial patches
formed the core changes of this branch.

branches: 1.74.6;
As md(4) no longer has "needs-count" there is no "md.h" anymore.
Remove the inclusion of this file.

Acorn32 now always builds load_memory_disc_from_floppy(). This should
not be a problem as all configs have md(4).

Observed by: Masao Uebayashi <uebayasi@netbsd.org>

branches: 1.73.2;
Remove separate mb_map. The nmbclusters is computed at boot time based
on the amount of physical memory and limited by NMBCLUSTERS if present.
Architectures without direct mapping also limit it based on the kmem_map
size, which is used as backing store. On i386 and ARM, the maximum KVA
used for mbuf clusters is limited to 64MB by default.

The old default limits and limits based on GATEWAY have been removed.
key_registered_sb_max is hard-wired to a value derived from 2048
clusters.

branches: 1.72.2;
Define an empty module_init_md function so that kernels with 'options
MODULAR' can be built (at least in shark). Still not working due to
some relocations resolving to too far away symbols though.

Replace l_addr with uvm_lwp_getuarea() in various MD code, mostly cpu_lwp_fork().

- Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr.
- Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb().
- Amend assembly in ports where it accesses PCB via struct user.
- Rename L_ADDR to L_PCB in few places. Reduce sys/user.h inclusions.

Kill proc0paddr. Use lwp0.l_addr instead.

Use lwp_getpcb() on ARM (and acorn26/32), clean from struct user usage.

Add a flags argument to pmap_kenter_pa(9).
Patch showed on tech-kern@ http://mail-index.netbsd.org/tech-kern/2009/11/04/msg006434.html
No objections.

Remove all declarations of physmem from sys/arch. Add an include of
<sys/systm.h> to the one file that did not already contain it.
This now means that physmem can be changed by updating systm.h and uvm_page.c
(excluding fixing printfs)

ansify function definitions

Change about 4500 of the K&R function definitions to ANSI ones.
There are still about 1600 left, but they have ',' or /* ... */
in the actual variable definitions - which my awk script doesn't handle.
There are also many that need () -> (void).
(The script does handle misordered arguments.)

Remove all the __P() from sys (excluding sys/dist)
Diff checked with grep and MK1 eyeball.
i386 and amd64 GENERIC and sys still build.

branches: 1.62.2;
Remove the implementation of cpu_intr_p() from here now that it's in
arm/arm_machdep.h. Should fix builds on arm32 platforms. Thanks to
Matt Fleming for reporting the problem.

cpu_info_store, machine, and machine_arch can all be shared by acorn26 and
arm32, so share them.

acorn26 and arm32 have identical versions of cpu_need_resched(). Unify them.
Similarly, with a small tweak acorn26 can use the same cpu_intr_p() as arm32,
so those can be unified too.

Fix __HAVE_FAST_SOFTINTS (boolean dyslexia strikes again).
Add some KASSERTS to make sure assumptions are valid.

branches: 1.58.2; 1.58.8;
Commit missing part of __HAVE_FAST_SOFTINTS support.

branches: 1.57.2;
Replce exec_map with a pool. Proposed on tech-kern@, reviewed by chs@.

branches: 1.56.2; 1.56.4;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.55.6; 1.55.8; 1.55.10;
With the removal of IPKDB on arm, the undefined stack is only used to
bounce into SVC32 mode, there is no per-process data stored on it.

We can therefore use the undefined stack setup by the platform machdep.c
as a system wide undefined stack.

This removes the need for a per-process undefined stack, and the processor
mode switching overhead it causes in cpu_switchto.

The space freed in the USPACE is used to increase the per process kernel
stack size.

Remove arm support for IPKDB.

It hasn't worked since arm was broken out from arm32 in Jan 2001, and
no-one has noticed or cared to fix it.

move the arm32 cpu_intr_p() function into arm32_machdep.c
from arm_machdep.c. this lets acorn26 link again.

branches: 1.52.2; 1.52.4; 1.52.8;
Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

Make want_resched a member of cpu_info.

branches: 1.50.2;
ARM cpu_switchto() has been partially broken since yamt-idlelwp was merged
as its cache/tlb management smarts relied too heavily on pre-merge context-
switch behaviour. See PR kern/36548 for one manifestation of the breakage.

To address this:
- Ditch the shadow pmap variables in the PCB (pagedir, l1vec, dacr, cstate)
as it was too easy for them to get out of sync with the pmap.
- Re-write (and fix) the convoluted cpuswitch.S cache/tlb ASM code in C.
It's only slightly less efficient, but is much more readable/maintainable.
- Document cpufuncs.cf_context_switch() as being C-callable.
- pmap_activate() becomes a no-op if the lwp's vmspace is already active.
(Good performance win, since pmap_activate() is now invoked on every
context-switch, even though ARM's cpu_switchto() already does all the
grunt work)

XXX: Some CPU-specific armXX_context_switch() implementations (arm67,
arm7tdmi, arm8) always flush the I+D caches. This should not be necessary.
Someone with access to hardware (acorn32?) needs to deal with this.

branches: 1.49.6; 1.49.8; 1.49.10; 1.49.12;
merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

branches: 1.48.2; 1.48.4; 1.48.10;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

TRUE -> true, FALSE -> false

branches: 1.46.26;
merge ktrace-lwp.

branches: 1.45.2;
Move the MI printing of `copyright' to the MD cpu_startup() code
where the printing of `version' is already performed.
This has the benefit of allowing the copyright to be available
via dmesg(8) on platforms which need the `msgbuf' to be setup
in cpu_startup() before printed output is remembered.

branches: 1.44.8;
Tango on sysctl_createv() and flags. The flags have all been renamed,
and sysctl_createv() now uses more arguments.

Uppercase CPU, plural is CPUs.

Replace the traditional buffer memory management -- based on fixed per buffer
virtual memory reservation and a private pool of memory pages -- by a scheme
based on memory pools.

This allows better utilization of memory because buffers can now be allocated
with a granularity finer than the system's native page size (useful for
filesystems with e.g. 1k or 2k fragment sizes). It also avoids fragmentation
of virtual to physical memory mappings (due to the former fixed virtual
address reservation) resulting in better utilization of MMU resources on some
platforms. Finally, the scheme is more flexible by allowing run-time decisions
on the amount of memory to be used for buffers.

On the other hand, the effectiveness of the LRU queue for buffer recycling
may be somewhat reduced compared to the traditional method since, due to the
nature of the pool based memory allocation, the actual least recently used
buffer may release its memory to a pool different from the one needed by a
newly allocated buffer. However, this effect will kick in only if the
system is under memory pressure.

The machdep.debug sysctl variable uses code CPU_DEBUG
(not CPU_CONSDEV).

The machdep.debug node is an int, not a struct

Dynamic sysctl.

Gone are the old kern_sysctl(), cpu_sysctl(), hw_sysctl(),
vfs_sysctl(), etc, routines, along with sysctl_int() et al. Now all
nodes are registered with the tree, and nodes can be added (or
removed) easily, and I/O to and from the tree is handled generically.

Since the nodes are registered with the tree, the mapping from name to
number (and back again) can now be discovered, instead of having to be
hard coded. Adding new nodes to the tree is likewise much simpler --
the new infrastructure handles almost all the work for simple types,
and just about anything else can be done with a small helper function.

All existing nodes are where they were before (numerically speaking),
so all existing consumers of sysctl information should notice no
difference.

PS - I'm sorry, but there's a distinct lack of documentation at the
moment. I'm working on sysctl(3/8/9) right now, and I promise to
watch out for buses.

Change some type-punning detected by gcc 3.3.1 to (void *).

__KERNEL_RCSID()

branches: 1.36.2;
Back out the lwp/ktrace changes. They contained a lot of colateral damage,
and need to be examined and discussed more.

struct proc * -> struct lwp *

ixp425_com:
add some status flags

Remove prototype for strtoul() that was in the wrong place.

Remove #ifdefs supporting the old pmap, switching fully to the new.

Add a comment indicating that the current method of enabling high vectors
requires that the CPU control vector be properly readable. I believe that
all CPUs that have high vector support have a readable CPU control register,
but if we ever encounter one that does not, then we'll have to adjust this
code.

Add the generic arm32 bits of the new pmap, contributed by Wasabi Systems.

Some features of the new pmap are:

- It allows L1 descriptor tables to be shared efficiently between
multiple processes. A typical "maxusers 32" kernel, where NPROC is set
to 532, requires 35 L1s. A "maxusers 2" kernel runs quite happily
with just 4 L1s. This completely solves the problem of running out
of contiguous physical memory for allocating new L1s at runtime on a
busy system.

- Much improved cache/TLB management "smarts". This change ripples
out to encompass the low-level context switch code, which is also
much smarter about when to flush the cache/TLB, and when not to.

- Faster allocation of L2 page tables and associated metadata thanks,
in part, to the pool_cache enhancements recently contributed to
NetBSD by Wasabi Systems.

- Faster VM space teardown due to accurate referenced tracking of L2
page tables.

- Better/faster cache-alias tracking.

The new pmap is enabled by adding options ARM32_PMAP_NEW to the kernel
config file, and making the necessary changes to the port-specific
initarm() function. Several ports have already been converted and will
be committed shortly.

In arm32_vector_init(), if the vector page is ARM_VECTORS_HIGH, make
sure the CPU_CONTROL_VECRELOC bit is set in the cpu control register
before returning.

Use PAGE_SIZE rather than NBPG.

Change pcb32_pagedir to a paddr_t (after all, it's used as a paddr_t
everywhere in the code).

Merge the nathanw_sa branch.

Make nbuf, nswbuf, and bufpages unsigned. Make all operations on these
variables unsigned, and update places where their values are printed.

* Add a new machdep.powersave sysctl, which controls the use of
the CPU's "sleep" function in the idle loop.
* Default all CPUs to not use powersave, except for the PDA processors
(SA11x0 and PXA2x0).

This significantly reduces inteterrupt latency in high-performance
applications (and was good to squeeze another ~10% out of an XScale
IOP on a Gig-E benchmark).

branches: 1.24.2;
Update to md(4) changes: memory_disk_size is now md_root_size, and
type is size_t

Remove the Control register handling from arm32_vector_init(). Apparently,
the ARM6 and ARM7 do completely the wrong thing if you read this register,
so we have to handle this a different way.

Clean up handling of the vector page on 32-bit ARM systems:
* Don't refer to VA 0, instead refer to a new variable: vector_page
* Delete the old zero_page_*() functions, replacing them with a new
one: vector_page_setprot().
* When manipulating vector page mappings in user pmaps, only do so if
the vector page is below KERNEL_BASE (if it's above KERNEL_BASE, the
vector page is mapped by the kernel pmap).
* Add a new function, arm32_vector_init(), which takes the virtual
address of the vector page (which MUST be valid when the function
is called) and a bitmask of vectors the kernel is going to take
over, and performs all vector page initialization, including setting
the V bit in the CPU Control register ("relocate vectors to high
address"), if necessary.

Rename MEMORY_DISK_SIZE (formerly MINIROOTSIZE) to MEMORY_DISK_ROOT_SIZE,
which was suggested by Izumi Tsutsui <tsutsui@ceres.dti.ne.jp> as
being more consistent with what it's controlling...

* arm_byte_to_page() -> arm_btop()
* arm_page_to_byte() -> arm_ptob()

Garbage-collect the "pagehook" stuff.

* Rename PROCESS_PAGE_TBLS_BASE -> PTE_BASE
* Rename ALT_PAGE_TBLS_BASE -> APTE_BASE
* Garbage-collect PAGE_TABLE_SPACE_START

* rename MINIROOTSIZE to MEMORY_DISK_SIZE, so that all md(4) options
are now consistently named
* fold opt_mdsize.h into opt_md.h

map_chunk() -> pmap_map_chunk(), and move it to pmap.c

map_pagetable() -> pmap_link_l2pt(), and move it to pmap.c

Collapse map_entry{,ro,nc}() into a single pmap_map_entry() that
takes a prot and a "cacheable" indicator.

Rename map_section() to pmap_map_section(), move it to pmap.c, and give it
an extra argument (prot - specifies protection of the mapping).

Add some extra comments for the `booted_kernel' variable.

Some prototype cleanup.

Make GENERIC cats kernel boot again. By allocating a 2nd second level page table for the kernel and stack space we can now have to 8MB of kernel and stacks (if the kernel ever gets really bloated might need to add a 3rd!)
Also update the funcs in arm32_machdep.c that create the entries so that on cats they expect the 2 pagetables to be contiguous, note this means that for now cats is special cased in lots of funcs. I'll tidy this up to something a bit more sane soon, to avoid the multitude of #ifndef cats that I had to sprinkle in.

Make some of the arm32 files build with LOOSE_PROTOTYPES not set in the makefile. Turned up a few mismatched functions. Note that this isn't all of the arm32 files. Aim will be to get arm32 kernels built with LOOSE_PROTOTYPES not set.

No need to pull in <machine/pte.h> directly.

Kill <machine/katelib.h>. Any place that still uses it should just
reference <arm/arm32/katelib.h> until such time as all use of this
file has been purged from the face of the earth.

branches: 1.6.2;
When creating section maps, use pte_cache_mode for setting the
page attributes of cacheable pages.

branches: 1.5.2;
Update pmap_update to now take the updated pmap as an argument.
This will allow improvements to the pmaps so that they can more easily defer expensive operations, eg tlb/cache flush, til the last possible moment.

Currently this is a no-op on most platforms, so they should see no difference.

Reviewed by Jason.

Don't define pcb_* register macros.
pcb_sp macro conflicts with sys/netinet6/ipsec.c.

branches: 1.3.2;
Make use of pmap_kenter instead of pmap_enter for kernel buffers.

branches: 1.2.2;
A couple of tidy ups to pmap:
pmap_t -> struct pmap * in pmap.c and pmap.h
kernel_pmap -> pmap_kernel() everywhere.

Compiled and booted on riscpc and cats.

Move the generic arm32 files into arm/arm32 from arm32/arm32, tested kernel builds on cats and riscpc.

Remove the advertising clause from Microsoft's licenses.

Thanks to Scott Hanselman at Microsoft for turning the wheels to get this
approved!

KNF #includes

Remove some unnecessary ones while I'm here.

Trailing whitespace

docpureset() doesn't return anything, so mark it void.
(probably could also be __dead.)

branches: 1.10.16;
fix RB_POWERDOWN test

add support for optional RB_POWERDOWN handler

Mark end of cpu_reboot as unreachable.

- print a warning about powerdown not supported like other ports do
- merge duplicated code
- if halt is requested and there is no console, keep looping instead of
rebooting.

branches: 1.6.2; 1.6.6; 1.6.8;
Move parts of cpu.h that are not needed by MI code in <arm/locore.h>
Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h>
Use <arm/asm.h> instead of <machine/arm.h>

branches: 1.5.2;
Move pmf_system_shutdown earlier and ensure interrupts are enabled.

Sprinkle cnpollc for correct (usb) keyboard handling.

Avoid warning from cngetc byt doing the proper cnpollc dance

branches: 1.2.2; 1.2.4; 1.2.6;
Call pmf_system_shutdown in cpu_reboot. OK matt

Make cpu_reset, most of initarm and the kvm init code common.
Add MP hooks for cpu_need_resced
Add idlestck which is allocated in arm32_kvminit

Pass the pmap in tlb_set_asid for the benefit of aarch64.

Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.

Collapse all CPU_CORTEXA<n> options into CPU_CORTEX and do runtime
detection instead of ifdefs where required.

Sprinkle #include "opt_cputypes.h"

branches: 1.11.2; 1.11.4;
Do runtime detection of MP extensions to allow using a MULTIPROCESSOR
kernel on CPUs without the MP extensions feature (like Cortex-A8).

Adapt to common pmap changes.

don't use armreg_tlbiasidis_write() and armreg_icialluis_write()
on single processor platforms.

fix CPU_CORTEXA5 && !MULTIPROCESSOR build

branches: 1.7.2;
Part of break-before-make is to dsb after the TLB invalidation. Do it in
tlb_invalidate_addr

s/0/KERNEL_PID/

isb after setting TTBCR_S_PD0 as per Example B3-5 Disable non-global
mappings when changing ASID in the ARM ARM.

Sprinkle #include "opt_multiprocessor.h"

armreg_tlbiasid_write -> armreg_tlbiasidis_write

Use tlb is variants for MULTIPROCESSOR

branches: 1.2.2; 1.2.4; 1.2.6; 1.2.8;
Deal with ASID tagged VIVT icaches (not that we have any cpus with them but...)

branches: 1.1.2;
Add tlb routines for pmap_tlb.c

move from sys/arch/arm/arm32/armv7_generic_dma.c to sys/arch/arm/arm/arm_generic_dma.c,
and change variable name from armv7_generic_dma_tag to arm_generic_dma_tag

no functional change. (preliminary changes for merging aarch64)

branches: 1.1.6; 1.1.10; 1.1.12;
Add a generic armv7 bus dma tag.

Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.

KNF #includes

Remove some unnecessary ones while I'm here.

Fix the armv[67] memory attributes for uncached memory. Previously it was
mapped as strongly-ordered which meant that unaligned accesses would fault.

armv7_generic_bs_map now maps pages with PMAP_DEV which is treated as SO

bus_dma continues to use PMAP_NOCACHE as appropriate, but this now get
mapped to the correct memory attribute bits for armv[67]

DEVMAP_ENTRY usees a new flag PTE_DEV.

The workaround for the unaligned access faults is now removed.

XXX Other armv[67] boards bus_space implementations should be checked.
XXX There is scope to reduce the difference to aarch64

branches: 1.10.4; 1.10.6;
On second thought, get rid of "bs_base" from struct bus_space and use a
custom bs_map for acpipchb instead.

Add a "bs_base" field to struct bus_space. If present, use it to translate
mappings by appending the value to the pa passed to bus_space_map.

branches: 1.8.2;
Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

use designated initializer to make adaptability and flexibility for changing struct bus_space.
no functional change.

branches: 1.6.2;
Pass PMAP_WRITE_COMBINE as appropriate in armv7_generic_bs_map, i.e.
same fix as bcm283x_bs_map just got.

Trailing whitespace

branches: 1.4.2;
KNF

Add pointer to bus_space_set_region_4 implemenation in armv7_generic_bs_tag.

branches: 1.2.2;
mark a4x read region / write region as not implemented

branches: 1.1.2;
Shared armv7 bus space implementation.

Merge ast() and userret() between arm32 and arm26. The implementation used
is the arm32 one.

Remove some overly-paranoid debug code that grovels too much
platform-specific internals.

Don't include <machine/psl.h> directly.

Use <arm/cpufunc.h>, not <machine/cpufunc.h>.

branches: 1.1.2; 1.1.4; 1.1.6; 1.1.12;
Move arm32/arm32/ast.c to arm/arm32/ast.c

Nuke atomic.S since we have MI defined atomic ops

branches: 1.5.8; 1.5.18; 1.5.22;
implement ucas_* for arm.

branches: 1.4.6; 1.4.8;
Use IF32_bits instead of I32_bit

branches: 1.3.6; 1.3.8; 1.3.14;
Merge kernel changes in matt-armv6 to HEAD.

branches: 1.2.6; 1.2.8; 1.2.10;
When manipulating the interrupt status for atomic ops use cpsr_c rather
than cpsr_all, this avoids updating unnecessary fields in the cpsr.

As a side effect, the inline versions no longer clobber the condition
codes.

branches: 1.1.2; 1.1.4; 1.1.26; 1.1.74; 1.1.84; 1.1.88; 1.1.90; 1.1.96; 1.1.104;
non-inline version of atomic_{set,clear}_bit(), defined when
ATOMIC_SET_BIT_NONINLINE_REQUIRED is defined.
(extracted from arm/arm32/locore.S)

Write out register pairs for strd.

Move parts of cpu.h that are not needed by MI code in <arm/locore.h>
Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h>
Use <arm/asm.h> instead of <machine/arm.h>

branches: 1.8.98; 1.8.114; 1.8.124; 1.8.130;
merge ktrace-lwp.

Xscale-optimised b{copy,zero}_page().

Contributed by Wasabi Systems.

branches: 1.6.2;
Use PAGE_SIZE rather than NBPG.

More local label fixups.

* Use local label names (.Lfoo vs. (Lfoo or foo))
* When moving from cpsr, use "cpsr" instead of "cpsr_all" (which is
provided, but doesn't make sense since mrs doesn't support fields
like msr does).

Speed up bcopy_page() on the XScale slightly by using the "pld"
insn (prefetch) to look-ahead to the next chunk while we copy the
current chunk.

This could probably use a bit more tuning.

branches: 1.2.6; 1.2.14;
Patch in Richard E's changes to bcopy page, the loop doesn't need unrolling as much as it currently is due to the overhead of the load/stores taking most of the time. (profiling shows minimal time difference)

branches: 1.1.4; 1.1.6;
Move compat_13_machdep.c, strstr.c, copystr.S, bcopyinout.S, and
bcopy_page.S to arm/arm32 and remove port-local copies.

New, improved version of copyin(), copyout(), and kcopy() by Allen Briggs.
This version works on both 26-bit and 32-bit machines. For large copies,
it's up to three times as fast as the old arm32 version and five times as
fast as the old arm26 version. For small copies it seems to be even faster
(getrusage() is apparently over ten times faster on an ARM610).

Hooray for Allen!

branches: 1.5.2; 1.5.4;
* Rename PROCESS_PAGE_TBLS_BASE -> PTE_BASE
* Rename ALT_PAGE_TBLS_BASE -> APTE_BASE
* Garbage-collect PAGE_TABLE_SPACE_START

Implement pmap_growkernel for arm32 based ports.
Note that this has been compiled on some systems, cats, IQ80310, IPAQ, netwinder and shark (note that shark's build is currently broken due to other reasons), but only actually run on cats.
Shark doesn't make use of the functionality as I believe there has to be a correlation between OFW and the kernel tables so that calls into OFW work.

Correct comment to avoid confusion, it really means 32 bits not 32 bites.

branches: 1.2.4;
Note the alignment state of the stack. This is part of the work to get the stack 8byte aligned for ELF

branches: 1.1.2; 1.1.4; 1.1.6;
Move compat_13_machdep.c, strstr.c, copystr.S, bcopyinout.S, and
bcopy_page.S to arm/arm32 and remove port-local copies.

Fix few typos in comments:
s/aready/already/
s/aleady/already/
s/imcoming/incoming/

arm: Adjust barriers issued in bus_dmamap_sync for the coherent case.

PR/59654

This change adjusts the memory barriers issued by bus_dmamap_sync for
the coherent case. In the non-coherent case the CPU cache operations
are expected to provide any, and all required barriers.

These barriers are emitted after bouncing for PREWRITE and before
bouncing for POSTREAD.

A new indrection is introduced to deal with the differencs in barrier
(dsb) options between Arm V8 and V7, the lack of options in Arm V6,
and the need to use cpu_drain_writebuf for all other earlier versions.

The Arm V8 Net change is:

op old new

branches: 1.149.2;
arm: Support BUS_DMA_NOCACHE

arm/bus_dma: Sprinkle error check with __predict_{true,false}.

Sprinkle error check in bus_dmamap_load*() and bus_dmamap_sync() with
__predict_{true,false} to improve performance.

Revert previous - I misread the code.

G/C an unused event counter.

Sync with the RISC-V version. Mostly

Use PRI{u,x}{BUSSIZE,VADDR,PADDR}

branches: 1.144.6;
arm/bus_dma: Fix misleading comment:

- * For a virtually-indexed write-back cache, we need
- * to do the following things:
+ * For a write-back cache, we need to do the following things:

This comment was written long ago when we supported only virtually-
indexed caches for arm. But subsequent comments are valid also for
physically-indexed cache.

Use PRI{u,x}{BUSSIZE,VADDR,PADDR} etc

More KNF

Some KNF

spaces -> TAB

Don't refer to physical_{start,end} here and just pass minimum (0UL)
address and maximum (~0UL) physical address. The values are passed
through to uvm_pglistalloc which knows about the RAM ranges.

branches: 1.138.2;
fix typos in log messages s/bus_dmamem_create/bus_dmamap_create/ and
s/bus_dmamem_load/bus_dmamap_load/.
Inspired by recent similar fixes in OpenBSD.

s/functin/function/ in copy pasted comment.

s/entrace/entrance/ in copy pasted comment.

if we have to bounce a buffer, clear our anything already setup in
the map before trying again.

riastradh@ noticed that a map had two types of mbuf types, and this
seems to avoid it as seen on eqos(4) on quartz64.

add a couple more event counts for bus dma events.

ok @skrll @raistradh @jmcneill


XXX: pullup-8 and pullup-9 probably.

_bus_dmatag_subregion is always EOPNOTSUPP for !_ARM32_NEED_BUS_DMA_BOUNCE
No need to check {min,max}_addr. Compiler did the right thing, but...

Add storage for an iommu cookie in bus_dmamap_t and store untranslated CPU
address in bus_dma_segment_t.

Check for programming errors in _bus_dmamap_load_buffer

pretty print

Consistently use %#x, etc

Count bus_dmamap_sync events for coherent ranges and non-coherent ranges

style fix

No need to allocate bounce buffers if we have a single range that covers
all of physical memory.

Use __func__ in panic calls (and misc style changes)

Update stats in the coherent case. Reported by jmcneill.

branches: 1.124.2;
Fix the logic around "parent is a subset and can be re-used" in
bus_dmatag_subregion. Thanks to mrg@ for spotting the problem.

A few bus_dmatag_subregion fixes

- return EOPNOTSUPP if min_addr isn't less than max_addr
- fix the subset check to ensure that all the ranges in the parent tag are
within the {min,max}_addr range. If so we can just continue to use the
parent tag.
- when building the new ranges read the parent tag range rather than un-
initialised memory.
- remove the max_addr != 0xffffffff check - the overflow should be handled
by the unsigned arithmetic for arm32.
- add a KASSERT
- add comments

KNF #includes

Remove some unnecessary ones while I'm here.

- Hide the details of SPCF_SHOULDYIELD and related behind a couple of small
functions: preempt_point() and preempt_needed().

- preempt(): if the LWP has exceeded its timeslice in kernel, strip it of
any priority boost gained earlier from blocking.

Fix previous for _ARM32_NEED_BUS_DMA_BOUNCE

Make sure to convey a failure to the calling function

Likely fix for PR kern/54999, but that was a one-off panic.

branches: 1.118.2;
Do not try to use direct map for prefetchable mappings

bus_dmamem_map: honour BUS_DMA_PREFETCHABLE hint

bus_dmamap_load_raw: support coherent mappings
bus_dmamap_sync: support syncing "raw" buffer types

branches: 1.115.2;
Simplify the _ARM32_NEED_BUS_DMA_BOUNCE #ifdefs and rely on compiler
optimisation of the bouncing = false case.

Drain the write buf (aka DSB) in more cases

Catch all CPUs that support speculation. (thunderx isn't CPU_CORTEX)

Fix comment

Fix BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE for aarch64.

The readonly mbuf optimisation is for the old arm pmap.

Rename min/max -> uimin/uimax for better honesty.

These functions are defined on unsigned int. The generic name
min/max should not silently truncate to 32 bits on 64-bit systems.
This is purely a name change -- no functional change intended.

HOWEVER! Some subsystems have

#define min(a, b) ((a) < (b) ? (a) : (b))
#define max(a, b) ((a) > (b) ? (a) : (b))

even though our standard name for that is MIN/MAX. Although these
may invite multiple evaluation bugs, these do _not_ cause integer
truncation.

To avoid `fixing' these cases, I first changed the name in libkern,
and then compile-tested every file where min/max occurred in order to
confirm that it failed -- and thus confirm that nothing shadowed
min/max -- before changing it.

I have left a handful of bootloaders that are too annoying to
compile-test, and some dead code:

cobalt ews4800mips hp300 hppa ia64 luna68k vax
acorn32/if_ie.c (not included in any kernels)
macppc/if_gm.c (superseded by gem(4))

It should be easy to fix the fallout once identified -- this way of
doing things fails safe, and the goal here, after all, is to _avoid_
silent integer truncations, not introduce them.

Maybe one day we can reintroduce min/max as type-generic things that
never silently truncate. But we should avoid doing that for a while,
so that existing code has a chance to be detected by the compiler for
conversion to uimin/uimax without changing the semantics until we can
properly audit it all. (Who knows, maybe in some cases integer
truncation is actually intended!)

use unintmax_t instead of u_quad_t.

Revert previous and cast to u_quad_t instead (t is for ptrdiff_t and off_t
does not match that on all arm)

fix incorrect printf format (off_t needs t)

branches: 1.108.2;
M_CLUSTER -> M_EXT_CLUSTER

Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

branches: 1.106.2;
Less ifdefs -> more readable.

NFC intended

Style

Rely on the cache operations to perform the necessary barriers.

Wrap some long lines

Remove unnecessary includes

More KNF

KNF
cvS: ----------------------------------------------------------------------

Fix a comment

branches: 1.98.8;
Update the dmamp argument only when the allocation succeeded.

"Make NetBSD great again!"

Introduce uvm_hotplug(9) to the kernel.

Many thanks, in no particular order to:

TNF, for funding the project.

Chuck Silvers - for multiple API reviews and feedback.
Nick Hudson - for testing on multiple architectures and bugfix patches.
Everyone who helped with boot testing.

KeK (http://www.kek.org.in) for hosting the primary developers.

Also return early from _bus_dmamap_sync if we're not bouncing and there
are no {pre,post} ops

Now the KASSERT doesn't fire on cats

branches: 1.95.2;
Trailing whitespace.

implement _bus_dmamap_load_raw, ok skrll@

Fix mbuf dmasyncing for extended MMU kernels.

Assert we aren't trying to sync a read-only mbuf as PREREAD.

Improve inline asm around dsb/dmb/isb:
- always use volatile and mark them as memory barrier
- use the common version from locore.h in all places not included from
userland

Kill redundant semicolons.

branches: 1.89.2;
Post a dmb before invalidating the cache in the post-{read,write}
operations to ensure that any/all cachelines brought in via speculation
are really flushed.

src is too big these days to tolerate superfluous apostrophes. It's
"its", people!

With PMAP_NEED_ALLOC_POOLPAGE, before using pmap_map_poolpage make sure
the page comes from the same freelist that pmap_map_poolpage uses.

branches: 1.86.2;
Deal with non-4KB pages properly.

Remove a comment that became largely redundant with the PMAP_NOCACHE
change.

branches: 1.84.2;
Deal with bus_dmamem_unmap of direct mapped KVA.

use cpu_{g,s}etmodel

Fix off by one in _bus_dma_{paddr_inrange,_to_paddr} when checking the
dma range.

Use kmem instead of malloc.
Fix various corner cases with bounce buffers.
Use PMAP_NOCACHE instead of manipulating PTEs directly.

branches: 1.80.2;
Disable when using extended MMU support.

Use KASSERT* in preference to #ifdef DIAGNOSTIC / panic

Actually use the calculated uboundary.

Make sync counters only count when caches ops are performed.

Rework counters.
Get rid of a badly done goto.
Properly deal with boundary in bus_dmamem_alloc_range.

fix writebuf draining fix.

bounce buffer fixes + convert some kassert -> kassertmsg

support BUS_DMA_PREFETCHABLE in bus_dmamem_mmap()

Move and tweak an #if 0 printf

Get rid of _BUS_DMAMAP_MEM_XLATE

Add a _BUS_DMAMAP_NOALLOC which tells bus_dmamem_alloc to skip that
dmarange when allocating memory.
Add a second dmarange to bcm23xx obio to allow it to map coherently mapped
memory.

Make _BUS_DMAMAP_MEM_XLATE supplied by the caller.

Add a flag to make bus_dmamem_map use the bus/sys transation table when
mapping bus addresses. Make bcm2835 obio use it.

On Cortex, speculative loads can cache lines to be populated after then they've
been invalidated for a DMA read. So after the DMA read we have to reinvalidate
them again. We have to both invalidates since the former prevents dirty lines
overwriting just DMAed data.

Correct inverted boolean logic for the coherent flag introduced in r1.61

Fixes slow nfs seen by msaitoh@

Only call cpu_{,s}dcache_inv_range if len > 0

Use right flag name for bus_dmamem_map (fixes usb on BCM53xx).

Make IS_BOUNCING a map flag and use it to simplify code and to avoid calling
the sync routines if (COHERENT|IS_BOUNCING) == COHERENT. (this eeks out a
little bit more performance).

Make bus_dmamem_map aware of coherent dma regions. Also, take advantage
of the use/existance of PMAP_MAP_POOLPAGE to avoid redundant mappings.

Add per-segment and per-ragne flag (to store _BUS_DMAMAP_COHERENT).
Use the per-range flag to set the per-segment flag.
This allows bus_dma to skip flushing for known coherent memory regions.

Fix a cut&paste error with supersections.

Add busaddr to paddr routine and use it.
cleanup the PREREAD sync case.

Add bounce buffer support for ARM bus_dma(9). Add macros to help initialize
bus_dma_tag structures.

branches: 1.57.2;
Rework dmasync routines so that secondary caches can be flushed as well
as the primary caches.

Supersections are on armv6 too.

Make bus_dma understand supersections.

branches: 1.54.2; 1.54.10;
#include <sys/bus.h> instead of <machine/bus.h>.

Machine dependent code is considered as part of UVM. Include
internal API header.

branches: 1.52.16; 1.52.18; 1.52.20;
vm_page: put TAILQ_ENTRY into a union with LIST_ENTRY, so we can use both.

branches: 1.51.2;
Remove clause 3 and 4 from TNF licenses

branches: 1.50.42; 1.50.44; 1.50.46;
Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

branches: 1.49.14;
Unwrap a not-too-long-line.

branches: 1.48.2; 1.48.4; 1.48.6;
merge yamt-uio_vmspace branch.

- use vmspace rather than proc or lwp where appropriate.
the latter is more natural to specify an address space.
(and less likely to be abused for random purposes.)
- fix a swdmover race.

branches: 1.47.2; 1.47.4; 1.47.6;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

bus_dmamem_map: honour BUS_DMA_NOWAIT. noted by Manuel Bouyer.
bus_space_map: always do NOWAIT allocation as it used to be before yamt-km.

we have too many copies!

branches: 1.44.2; 1.44.8;
merge yamt-km branch.
- don't use managed mappings/backing objects for wired memory allocations.
save some resources like pv_entry. also fix (most of) PR/27030.
- simplify kernel memory management API.
- simplify pmap bootstrap of some ports.
- some related cleanups.

Add a dm_maxsegsz public member to bus_dmamap_t. This allows a user of the API
to select the maximum segment size for each bus_dmamap_load (up to the maxsegsz
supplied to bus_dmamap_create). dm_maxsegsz is reset to the value supplied to
bus_dmamap_create when the dmamap is unloaded.

branches: 1.42.2; 1.42.4;
Remove direct references to TAILQ internal structures.

No functional change, just tidying up code.

Sync with i386 bus_dma.

Apply patch provided by Hiroki Nakano in PR kern/27159 to fix
compilation with DEBUG_DMA defined.

Merge x86/bus_dma.c 1.11 by yamt:

Simplify bus_dma internal "load" functions by eliminating the "first"
variable, using seg == -1 instead.

In bus_dmamap_sync(), we can no longer rely on the data cache being
flushed on every context switch as an indicator that a mapping is
not resident in the cache.

Instead, used the per-pmap flag maintained by the cpu_switch/pmap code.

If something goes wrong, we want to return ENOMEM, not 0!

Fix up some unitialised variables.

Make sure _ARM32_BUS_DMA_PRIVATE is defined before we pull in any
include files to avoid problems with the rats nest of dependencies.

Clear ARM32_DMAMAP_COHERENT in _bus_dmamap_load_buffer for userspace mappings.

__KERNEL_RCSID()

branches: 1.32.2;
Back out the lwp/ktrace changes. They contained a lot of colateral damage,
and need to be examined and discussed more.

Pass lwp pointers throughtout the kernel, as required, so that the lwpid can
be inserted into ktrace records. The general change has been to replace
"struct proc *" with "struct lwp *" in various function prototypes, pass
the lwp through and use l_proc to get the process pointer when needed.

Bump the kernel rev up to 1.6V

Remove #ifdefs supporting the old pmap, switching fully to the new.

Add the generic arm32 bits of the new pmap, contributed by Wasabi Systems.

Some features of the new pmap are:

- It allows L1 descriptor tables to be shared efficiently between
multiple processes. A typical "maxusers 32" kernel, where NPROC is set
to 532, requires 35 L1s. A "maxusers 2" kernel runs quite happily
with just 4 L1s. This completely solves the problem of running out
of contiguous physical memory for allocating new L1s at runtime on a
busy system.

- Much improved cache/TLB management "smarts". This change ripples
out to encompass the low-level context switch code, which is also
much smarter about when to flush the cache/TLB, and when not to.

- Faster allocation of L2 page tables and associated metadata thanks,
in part, to the pool_cache enhancements recently contributed to
NetBSD by Wasabi Systems.

- Faster VM space teardown due to accurate referenced tracking of L2
page tables.

- Better/faster cache-alias tracking.

The new pmap is enabled by adding options ARM32_PMAP_NEW to the kernel
config file, and making the necessary changes to the port-specific
initarm() function. Several ports have already been converted and will
be committed shortly.

Use cached physical addresses for mbufs and clusters to save having
to extract the physical address from the virtual.

On the ARM, also use the "read-only at MMU" indication to avoid a
redundant cache clean operation.

Other platforms should use these two as examples of how to use these
new pool/mbuf features to improve network performance. Note this requires
a platform to provide a working POOL_VTOPHYS().

Part 3 in a series of simple patches contributed by Wasabi Systems
to improve network performance.

Use PAGE_SIZE rather than NBPG.

Remove references to variables that aren't used here.

bus dma memory is allocated as M_DMAMAP so free it as M_DMAMAP, not DEVBUF.

guarantee, not guarentee. Idea from miod@openbsd.

Merge the nathanw_sa branch.

Don't include <sys/map.h>.

* Add PTE_SYNC() and PTE_SYNC_RANGE() macros. These don't actually do
anything yet.
* Use PTE_SYNC() and PTE_SYNC_RANGE() in some obvious places, i.e.
where vtopte() is used.

Do not trim 'offset' from 'len' in _bus_dmamap_sync_linear().

Inline bus_dma_inrange() and bus_dmamap_sync_*().

When doing PREREAD sync operations, if the start and end addresses
of the range are aligned to a cacheline boundary, when do a dcache-inv
operation, rather than a dcache-wbinv operation.

XXX It could be a little smarter (align using wbinv, inv, then finish
up using wbinv), but even this simple change is good for a nearly 40%
improvement in my test case on XScale.

* Add an ARM32_DMAMAP_COHERENT flag to indicate that a loaded DMA
map contains "coherent" (non-cached in ARM-land) mappings.
* Set ARM32_DMAMAP_COHERENT in the map at the start of a load operation,
and clear it in _bus_dmamap_load_buffer() if we encounter any cacheable
mappings.
* In _bus_dmamap_sync(), if the map is marked COHERENT, skip any cache
flushing.

Whe making a mapping "coherent", clear *ALL* the cache bits, not
just L2_B and L2_C.

Overhaul how DMA ranges work in the ARM bus_dma implementation.

A new "arm32_dma_range" structure now describes a DMA window, with
a system address base, bus address base, and length. In addition to
providing info about which memory regions are legal for DMA, the new
structure provides address translation support, as well.

As before, if a tag does not list any ranges, then all addresses are
considered valid, and no DMA address translation is performed.

This allows us to remove a large chunk of code which was duplicated and
tweaked slightly (to do the address translation) from the stock ARM
bus_dma in the XScale IOP and ARM Integrator ports.

Test compiled on all ARM platforms, test booted on Intel IQ80321 and Shark.

Change the way that DMA map syncs are done. Instead of remembering
the virtual address for each DMA segment, just cache a pointer to the
original buffer/buftype used to load the DMA map, and use that. This
lets us shrink the bus_dma_segment_t down from 12 bytes to 8, and the
cache flushing is also more efficient.

Tested on an i80321 -- changes to others are mechanical.

Remove complaint: bus_dmamap_destroy() called for map with valid
mappings bus_dma(9) states: "In the event that the DMA handle contains
a valid mapping, the mapping will be unloaded via the same mechanism
used by bus_dmamap_unload()." And some drivers do mean to skip the
unload step.

move initialization of the "struct pglist" returned by uvm_pglistalloc()
from the calling code into uvm_pglistalloc() itself for consistency
and easier error handling

branches: 1.11.2; 1.11.4;
vm_offset_t -> vaddr_t,paddr_t

* Rewrite the 32-bit ARM pte.h based on the ARM architecture manual.
Significant cleanup, here, including better PTE bit names.
* Add XScale PTE extensions (ECC enable, write-allocate cache mode).
* Mechanical changes everywhere else to update for new pte.h. While
doing this, two bugs (as a result of typos) were fixed in

arm/arm32/bus_dma.c
evbarm/integrator/int_bus_dma.c

* arm_byte_to_page() -> arm_btop()
* arm_page_to_byte() -> arm_ptob()

Overhaul bus_dmamap_sync for the ARM:
* Track which process (XXX really, vmspace) owns the mapping. When
we sync the map, if the mapping doesn't belong to the kernel or to
the current process (XXX really, vmspace), then no cache fobbing
is necessary, since the cache is Wb-Inv'd on context switch (XXX need
to revisit this when we support FCSE).
* Be smarter about which cache operation we do when sync'ing the map:
- PREREAD -- Invalidate D$ (XXX right now, we actually do Wb-Inv)
- PREWRITE -- Write-back D$ (note, we do NOT invalidate here)
- PREREAD|PREWRITE -- Wb-Inv D$

More work is needed here. In particular, a version for CPUs
with write-through caches should be provided, to eliminate
the write-back steps (which are noops on such CPUs, but skipping
two branches would be nice).

ANSI'ify function decls.

Overhaul of the ARM cache code. This is mostly a simplification
pass. Rather than providing a whole slew of cache operations that
aren't ever used, distill them down to some useful primitives:

icache_sync_all Synchronize I-cache
icache_sync_range Synchronize I-cache range

dcache_wbinv_all Write-back and Invalidate D-cache
dcache_wbinv_range Write-back and Invalidate D-cache range
dcache_inv_range Invalidate D-cache range
dcache_wb_range Write-back D-cache range

idcache_wbinv_all Write-back and Invalidate D-cache,
Invalidate I-cache
idcache_wbinv_range Write-back and Invalidate D-cache,
Invalidate I-cache range

Note: This does not yet include an overhaul of the actual asm files
that implement the primitives. Instead, we've provided a safe default
for each CPU type, and the individual CPU types can now be optimized
one at a time.

Don't include <machine/psl.h> directly.

Use <arm/cpufunc.h>, not <machine/cpufunc.h>.

branches: 1.3.4;
Fix warning errors for printing size_t types when compiling with
DEBUG_DMA (uses casts due to a.out and ELF having different base
types for size_t).

Update pmap_update to now take the updated pmap as an argument.
This will allow improvements to the pmaps so that they can more easily defer expensive operations, eg tlb/cache flush, til the last possible moment.

Currently this is a no-op on most platforms, so they should see no difference.

Reviewed by Jason.

branches: 1.1.2; 1.1.4;
Move the generic arm32 files into arm/arm32 from arm32/arm32, tested kernel builds on cats and riscpc.

Make compat_13_sys_sigreturn() work on arm26, and move it from
arch/arm/arm32/compat_13_machdep.c to arch/arm/arm/compat_13_machdep.c.

Move compat_13_machdep.c, strstr.c, copystr.S, bcopyinout.S, and
bcopy_page.S to arm/arm32 and remove port-local copies.

now that mem_no is emitted by config(8), there is no reason to keep
copy of more or less identical iskmemdev() for every arch; move the function
to spec_vnop.c, and g/c machine-dependant copies

Merge the gehenna-devsw branch into the trunk.

This merge changes the device switch tables from static array to
dynamically generated by config(8).

- All device switches is defined as a constant structure in device drivers.

- The new grammer ``device-major'' is introduced to ``files''.

device-major <prefix> char <num> [block <num>] [<rules>]

- All device major numbers must be listed up in port dependent majors.<arch>
by using this grammer.

- Added the new naming convention.
The name of the device switch must be <prefix>_[bc]devsw for auto-generation
of device switch tables.

- The backward compatibility of loading block/character device
switch by LKM framework is broken. This is necessary to convert
from block/character device major to device name in runtime and vice versa.

- The restriction to assign device major by LKM is completely removed.
We don't need to reserve LKM entries for dynamic loading of device switch.

- In compile time, device major numbers list is packed into the kernel and
the LKM framework will refer it to assign device major number dynamically.

Add dmoverio.

Add sysmon at cdev 101.

cdev_tty_init(NIXPCOM,ixpcom) move to end of cdevsw array

Add an "#ifndef NIXPCOM" check so that this builds on non-evbarm.

Rename cdev_systrace_init() to cdev_clonemisc_init(), so it can
be properly used by any misc. cloning device. While here, correct
a comment to indicate that "open" is the only entry point and that
everything else is handled with fileops.

add ixpcom to cdevsw

Add kttcp device.

MD systrace gluons.

branches: 1.10.2;
Complete renaming of opms to opms (was partly named pms, externally and
internally). Move arm/iomd/pms* to arm/iomd/opms*. Mechanical change,
tested by cross-compiling a kernel from i386.

Approved by christos.

XXX: What are arm/arm32/conf.c and arm/include/conf.h good for?

Fix typo: ISDNCTL -> NISDNCTL.

Rename ISDN devices, per discussion on tech-kern. The network devices
become ippp (ISDN ppp) and irip (ISDN raw IP). The character device now
are called: /dev/isdn (isdnd <-> kernel communication), /dev/isdnctl (dialing
and other control), /dev/isdntrc* (tracing), /dev/isdnbchan* (raw B channel
access, i.e. for user land PPP) and /dev/isdntel* (telephone devices, i.e.
for answering machines).

Update with radio, cir and irframe. also add block device for ld. Update other tables in file as appropriate.

Add clockctl device.
Note that someone needs to tidy this up, we've got 92 block devices, which just ain't true. Also appears we're actually missing some, eg the ld block device.

branches: 1.5.2;
Add the IFPGA console device.

branches: 1.4.2;
Add missing devices (IOP,MLX,MLY,LD), PCI, stub AGP, ...

branches: 1.3.2;
Readd sacom to cdevsw.

branches: 1.2.2;
Fix typos (CONS instead of CONF, and specifc instead of specific).

Switch netwinder to use a common conf.c for the arm ports.

Move the arm32 copystr.S from arch/arm/arm32 to arch/arm/arm and add support
for 26-bit modes (basically saving R14 when we might get a page fault).
Use it on all ARM architectures now.

Reduce stalls on StrongARM and XScale by waiting one insn before using
the result of a load.

Use ldrbt/strbt. Some other random cleanup.

branches: 1.3.6; 1.3.8;
Implement pmap_growkernel for arm32 based ports.
Note that this has been compiled on some systems, cats, IQ80310, IPAQ, netwinder and shark (note that shark's build is currently broken due to other reasons), but only actually run on cats.
Shark doesn't make use of the functionality as I believe there has to be a correlation between OFW and the kernel tables so that calls into OFW work.

branches: 1.2.4;
Note the alignment state of the stack. This is part of the work to get the stack 8byte aligned for ELF

branches: 1.1.2; 1.1.4; 1.1.6;
Move compat_13_machdep.c, strstr.c, copystr.S, bcopyinout.S, and
bcopy_page.S to arm/arm32 and remove port-local copies.

Remove the advertising clause from Microsoft's licenses.

Thanks to Scott Hanselman at Microsoft for turning the wheels to get this
approved!

KNF #includes

Remove some unnecessary ones while I'm here.

Merge the [pgoyette-compat] branch

Remove the kernel PMC code. Sent yesterday on tech-kern@.

This change:

* Removes "options PERFCTRS", the associated includes, and the associated
ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is
good.

* Removes the PMC code of ARM XSCALE.

* Removes all the pmc.h files. They were all empty, except for ARM XSCALE.

* Reorders the x86 PMC code not to rely on the legacy pmc.h file. The
definitions are put in sysarch.h.

* Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control
and sys_pmc_get_info syscalls. They are marked as OBSOL in kern,
netbsd32 and rump.

* Removes the pmc_evid_t and pmc_ctr_t types.

* Removes all the associated man pages. The sets are marked as obsolete.

branches: 1.5.2; 1.5.4;
KNF

fix: Cortex delay() shorten rarely.

RCSid police

branches: 1.2.2; 1.2.12; 1.2.16; 1.2.18;
Since the PMC cycle counter is started in cpufunc no reason to do so here.
Use curcpu()->ci_data.cpu_cc_freq and new armreg* inlines.

branches: 1.1.2; 1.1.4; 1.1.6; 1.1.14; 1.1.22;
Cleanup the armv7 changes. Add ARM_ARCH_7. Use CPU_CORTEX instead of
CPU_CORTEXA8 everywhere since there more types of Cortex than just the A8.
CPU_CORTEXA8 still exists but causes CPU_CORTEX to be defined.
Add CPU_CORTEXA9 as well. Use .arch armv7a to get us the isb/dsb
instructions.

Test booted to root device prompt on a Beagleboard.
All ARM kernels successfully test built.

This was renamed to cortex_pmc.c

PR port-arm/43299: Support added for igepv2/cortexa8/omap3530

Apply patch from PR, with build fixes. ok skrll, matt

Add the beginnings of a GENERIC_V5 kernel that targets armv5 boards and
uses FDT.

In this first iteration some support is added for OLinuXino boards.

Thanks to Yuri Honegger for doing the vast majority of the work.

kern/58195: arm: Support drvctl -d and -r for cpufeaturebus

This is required for detaching and re-attaching the vmt(4) driver on aarch64.

arm: Use device_set_private for cpuN.

For cpu at fdt, nix the fdt softc -- this was leaked and never used
for anything. The device's private storage is the cpu_info.

Rework Arm (32bit and 64bit) AP startup so that cpu_hatch doesn't sleep.

The AP initialisation code in cpu_init_secondary_processor will read and
initialise the required system registers and state for the BP to attach
and report.

Rework the interrupt handler code for this new sequence. Thankfully,
this removes a bunch of code for bcm2836mp.

The VFP detection handler on <= armv7 relies on the global undefined
handler being in place until the BP attaches vfp. That is, after the
APs have been spun up.

gicv3_its.c has a serialisation issue which is protected against in
the gicv3_its_cpu_init, which is called from cpu_hatch, with a spin
lock. The serialisation issue needs addressing more completely.

Tested on RPI3, Apple M1, QEMU, and lx2k

Fixes PR port-arm/56264:
diagnostic assertion "l->l_stat == LSONPROC" failed on RPI3

For some classic CPUs, info->[id]cache_sets are not initialized.
Calculate and print numbers of sets in this case.

pN steppings are used for ARM926EJ-S, although only r0 seems to be available.

Print the cache information in similar formats and arm and aarch64, e.g.

arm before
[ 1.0000000] cpu0: 32KB/64B 2-way L1 PIPT Instruction cache
[ 1.0000000] cpu0: 32KB/64B 2-way write-back-locking-C L1 PIPT Data cache
[ 1.0000000] cpu0: 2304KB/64B 16-way write-through L2 PIPT Unified cache

arm after
[ 1.0000000] cpu0: L1 32KB/64B 2-way (256 set) PIPT Instruction cache
[ 1.0000000] cpu0: L1 32KB/64B 2-way (256 set) write-back-locking-C PIPT Data cache
[ 1.0000000] cpu0: L2 2304KB/64B 16-way (2304 set) write-through PIPT Unified cache

aarch64 before
[ 1.0000030] cpu1: L1 48KB/64B*256L*3W PIPT Instruction cache
[ 1.0000030] cpu1: L1 32KB/64B*256L*2W PIPT Data cache
[ 1.0000030] cpu1: L2 2048KB/64B*2048L*16W PIPT Unified cache

aarch64 after
[ 1.0000030] cpu1: L1 48KB/64B 3-way (256 set) PIPT Instruction cache
[ 1.0000030] cpu1: L1 32KB/64B 2-way (256 set) PIPT Data cache
[ 1.0000030] cpu1: L2 2048KB/64B 16-way (2048 set) PIPT Unified cache

Assume all ARM11[37]6 r0 variants are missing ISAR and friends. This is
certainly the case for r0 variants I could find TRMs for.

PR/50596 CPU_ID_ARM1136JS r0p4 does not support feature registers

branches: 1.147.6;
Initialize ci_kfpu_spl earlier for secondary CPUs. From riastradh

Implement fpu_kern_enter/leave for arm32.

KNF #includes

Remove some unnecessary ones while I'm here.

Various updates and improvements to cpu start up on arm/aarch64

- start sharing more code around the AP startup messaging.
- call arm_cpu_topology_set early so that ci_core_id is available for
drivers, e.g. bcm2835_intr.c
- both arm and aarch64 now have
- a static cpu_info_store array
- the same arm_cpu_{hatched,mbox}

#ifdef whack-a-mole for the pmap_maxproc_set functionality

s/_ARM_ARCH_6/ARM_MMU_EXTENDED/ in the #ifdef for the recent 4k pages
change

Use 4K pages on ARM_MMU_EXTENDED platforms (all armv[67] except RPI) by
creating a new pool l1ttpl for the userland L1 translation table which
needs to be 8KB and 8KB aligned.

Limit the pool to maxproc and add hooks to allow the sysctl changing of
maxproc to adjust the pool.

This comes at a 5% performance penalty for build.sh -j8 kernel on a
Tegra TK1.

port the arm64 cpu topology setup for big.little to arm.

rename arm64 cpu_do_topology() to arm_cpu_do_topology() and
call it from both arm cpu_attach().

replace both aarch64_set_topology() inline code in arm
cpu_attach() with new arm_cpu_do_topology(), which is called
by the arm64 locore as well (possibly not needed, which would
allow it to become static.)

not yet tested on a real big.little armv7 system. tested
on rockpro64 and pinebook pro.

- Many small tweaks to the SMT awareness in the scheduler. It does a much
better job now at keeping all physical CPUs busy, while using the extra
threads to help out. In particular, during preempt() if we're using SMT,
try to find a better CPU to run on and teleport curlwp there.

- Change the CPU topology stuff so it can work on asymmetric systems. This
mainly entails rearranging one of the CPU lists so it makes sense in all
configurations.

- Add a parameter to cpu_topology_set() to note that a CPU is "slow", for
where there are fast CPUs and slow CPUs, like with the Rockwell RK3399.
Extend the SMT awareness to try and handle that situation too (keep fast
CPUs busy, use slow CPUs as helpers).

When attaching the first fdtbus, use the root "comptabile" (or failing that:
"model") property to set the cpu model (in userland aka sysctl hw.model).
When attaching the first cpu, do not overwrite a cpu model if it already
had been set.

cpu_hatch is too late to report AP topology, do it at attach time instead

branches: 1.136.2;
Some more CPU topology stuff:

- Use cegger@'s ACPI SRAT parsing code to figure out NUMA node ID for each
CPU as it is attached.

- For scheduler experiments with SMT, flag CPUs with the lowest numbered SMT
IDs as "primaries", link back to the primaries from secondaries, and build
a circular list of CPUs in each package with identical SMT IDs.

- No need for package/core/smt/numa IDs to be anything other than a u_int.

Take the basic CPU topology information we already collect, and use it
to make circular lists of CPU siblings in the same core, and in the
same package. Nothing fancy, just enough to have a bit of fun in the
scheduler trying out different tactics.

cpu_hatched_p only for MULTIPROCESSOR

Increase aarch64 MAXCPUS to 256.

aprint_debug_dev output alignment

report A12 as A17 to the user. A12 is retcon'ed by ARM.