Cross Reference: /src/sys/arch/arm/arm32

History log of /src/sys/arch/arm/arm32
Revision	Date	Author	Comments
1.1	10-Nov-2007	matt	branches: 1.1.2; file arm1136_pmc.c was initially added on branch matt-nb4-arm.
1.1.2.1	10-Nov-2007	matt	Add AT91 support from Sami Kantoluoto Add TI OMAP2430 support from Marty Fouts @ Danger Inc
1.8	20-Jun-2020	skrll	KNF #includes Remove some unnecessary ones while I'm here.
1.7	20-Jun-2020	skrll	Trailing whitespace
1.6	27-Jan-2019	pgoyette	Merge the [pgoyette-compat] branch
1.5	12-Jul-2018	maxv	Remove the kernel PMC code. Sent yesterday on tech-kern@. This change: * Removes "options PERFCTRS", the associated includes, and the associated ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is good. * Removes the PMC code of ARM XSCALE. * Removes all the pmc.h files. They were all empty, except for ARM XSCALE. * Reorders the x86 PMC code not to rely on the legacy pmc.h file. The definitions are put in sysarch.h. * Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control and sys_pmc_get_info syscalls. They are marked as OBSOL in kern, netbsd32 and rump. * Removes the pmc_evid_t and pmc_ctr_t types. * Removes all the associated man pages. The sets are marked as obsolete.
1.4	01-Dec-2013	joerg	branches: 1.4.28; 1.4.30; Mark unused inline functions as such.
1.3	03-Jul-2008	matt	branches: 1.3.14; 1.3.30; 1.3.40; 1.3.46; Fix a typo in the delay loop time delta calculation. From Irme Desk <imre.deak@teleca.com>.
1.2	27-Apr-2008	matt	branches: 1.2.2; 1.2.4; Merge kernel changes in matt-armv6 to HEAD.
1.1	25-Sep-2007	matt	branches: 1.1.2; 1.1.18; 1.1.20; 1.1.22; file arm11_pmc.c was initially added on branch matt-armv6.
1.1.22.2	04-May-2009	yamt	sync with head.
1.1.22.1	16-May-2008	yamt	sync with head.
1.1.20.1	18-May-2008	yamt	sync with head.
1.1.18.2	28-Sep-2008	mjf	Sync with HEAD.
1.1.18.1	02-Jun-2008	mjf	Sync with HEAD.
1.1.2.2	29-Oct-2007	matt	Fix typo.
1.1.2.1	25-Sep-2007	matt	Add PMC counter (really cycle counter) support for ARM11.
1.2.4.1	03-Jul-2008	simonb	Sync with head.
1.2.2.1	18-Sep-2008	wrstuden	Sync with wrstuden-revivesa-base-2.
1.3.46.1	18-May-2014	rmind	sync with head
1.3.40.1	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.3.30.1	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.3.14.1	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.4.30.1	10-Jun-2019	christos	Sync with HEAD
1.4.28.1	28-Jul-2018	pgoyette	Sync with HEAD
1.45	22-Dec-2022	ryo	Explicitly disable overflow interrupts before enabling the cycle counter.
1.44	31-Oct-2021	skrll	branches: 1.44.4; Rework Arm (32bit and 64bit) AP startup so that cpu_hatch doesn't sleep. The AP initialisation code in cpu_init_secondary_processor will read and initialise the required system registers and state for the BP to attach and report. Rework the interrupt handler code for this new sequence. Thankfully, this removes a bunch of code for bcm2836mp. The VFP detection handler on <= armv7 relies on the global undefined handler being in place until the BP attaches vfp. That is, after the APs have been spun up. gicv3_its.c has a serialisation issue which is protected against in the gicv3_its_cpu_init, which is called from cpu_hatch, with a spin lock. The serialisation issue needs addressing more completely. Tested on RPI3, Apple M1, QEMU, and lx2k Fixes PR port-arm/56264: diagnostic assertion "l->l_stat == LSONPROC" failed on RPI3
1.43	03-Jun-2021	skrll	Mirror changes to passing pages to UVM into aarch64_machdep.c Two fixes for loading free pages into UVM - Only consider a boot_physmem (inner loop) range that has its end (bp_end) after the bootconfig.dram (outer loop) range start (start). This was harmless as a later condition correctly checks there is only something to do if start < bp_end. - Stop processing boot_physmem ranges if all the bootconfig.dram range has been passed to UVM. This fixes a boot problem for simon@ Copy a comment over and do the VPRINTF before the uvm_page_physload in the same way as aarch64_machdep.c as well.
1.42	01-Jun-2021	skrll	branches: 1.42.2; G/C
1.41	01-Dec-2020	rin	branches: 1.41.4; Switch earmv6{,hf}eb to BE8 in kernel side. My strategy here is to define _ARM_ARCH_BE8 macro in arm/cdefs.h, if __ARMEB__ && _ARM_ARCH_6. Use this macro to determine whether system is compiled for and running on BE8 mode or not. Note that, for __ARMEB__, some conditions become compile-time constants determined by _ARM_ARCH_BE8 macro, e.g., whether BE8 or BE32 are accepted as a userland binary, or unaligned memory access is possible or not.
1.40	11-Sep-2020	skrll	branches: 1.40.2; Wrap a long comment
1.39	10-Jul-2020	skrll	Add support for KASAN on ARMv[67] Thanks to maxv for many pointers and reviews.
1.38	06-Jun-2020	skrll	KNF
1.37	15-Feb-2020	skrll	Various updates and improvements to cpu start up on arm/aarch64 - start sharing more code around the AP startup messaging. - call arm_cpu_topology_set early so that ci_core_id is available for drivers, e.g. bcm2835_intr.c - both arm and aarch64 now have - a static cpu_info_store array - the same arm_cpu_{hatched,mbox}
1.36	08-Jan-2020	jmcneill	cpu_hatch is too late to report AP topology, do it at attach time instead
1.35	20-Dec-2019	ad	branches: 1.35.2; Some more CPU topology stuff: - Use cegger@'s ACPI SRAT parsing code to figure out NUMA node ID for each CPU as it is attached. - For scheduler experiments with SMT, flag CPUs with the lowest numbered SMT IDs as "primaries", link back to the primaries from secondaries, and build a circular list of CPUs in each package with identical SMT IDs. - No need for package/core/smt/numa IDs to be anything other than a u_int.
1.34	02-Dec-2019	ad	Take the basic CPU topology information we already collect, and use it to make circular lists of CPU siblings in the same core, and in the same package. Nothing fancy, just enough to have a bit of fun in the scheduler trying out different tactics.
1.33	16-Mar-2019	skrll	branches: 1.33.4; Flush the BP cache just before starting APs so that cache coherency starts with a correct view.
1.32	27-Jan-2019	pgoyette	Merge the [pgoyette-compat] branch
1.31	25-Jan-2019	skrll	Make sure ci_{smt,core,package}_id are all filled in appropriately. Previously the BP was missed and __SHIFTOUT wasn't used.
1.30	03-Jan-2019	skrll	Simplify
1.29	03-Jan-2019	jmcneill	Read mpidr and cpuid from the secondary processor itself instead of the boot processor. While here, add Cortex-A15 r4p0 to supported list.
1.28	03-Jan-2019	skrll	Start CPUs more like aarch64 by using a cpu_mpidr array (if populated) to map MPIDRs to an index for each CPU. Towards big.LITTLE support.
1.27	31-Oct-2018	skrll	Tidyup VERBOSE_INIT_ARM output
1.26	28-Oct-2018	skrll	Fix a commit
1.25	18-Oct-2018	skrll	Fix VPRINTF
1.24	18-Oct-2018	skrll	Provide generic start code that assumes the MMU is off and caches are disabled as per the linux booting protocol for ARMv6 and ARMv7 boards. u-boot image type should be changed to 'linux' for correct behaviour. The new start code builds a minimal "bootstrap" L1PT with cached access disabled and uses the same table for all processors. AP startup is performed in less steps and more code is written in C. The bootstrap tables and stack are placed into an (orphaned) section "_init_memory" which is given to uvm when it is no longer used. Various kernels have been converted to use this code and tested. Some boards were provided by TNF. Thanks! The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS kernels. The GENERIC kernel will also work on RPI2 using u-boot. Thanks to martin@ and aymeric@ for testing on parallella and nanosoc respectively
1.23	14-Oct-2018	skrll	Use __nothing
1.22	16-Sep-2018	skrll	G/C
1.21	15-Aug-2018	skrll	Sprinkle #include "opt_cputypes.h"
1.20	31-Jul-2018	skrll	Define and use VPRINTF
1.19	02-Jul-2017	skrll	branches: 1.19.4; 1.19.6; Consistency around the user trapframe for all LWPs and there's no need to keep assigning it in kernel entry points.
1.18	22-Dec-2016	cherry	switch all ports to use uvm_init.c:uvm_md_init() uvm_setpagesize() is now subsumed within this funciton.
1.17	08-Mar-2016	skrll	branches: 1.17.2; #if 0 a KASSERT for now as it doesn't apply to Raspberry Pi 3
1.16	17-May-2015	matt	KASSERT in cpu_hatch that AUXCTL.SMP is set for Cortex CPUs.
1.15	04-May-2015	matt	Deal with 4GB overflow in arm32_kvminit.c
1.14	04-May-2015	matt	Fix 4GB wraparound math.
1.13	04-May-2015	matt	If not using LPAE, if memory ends at 4GB ignore the last page so physical_end doesn't wrap to 0.
1.12	12-Jan-2015	jakllsch	use IPL_NONE for CPU attach message serialization mutex
1.11	13-Dec-2014	jmcneill	serialize printing of secondary cpu info
1.10	04-Nov-2014	matt	branches: 1.10.2; Fix the stacks used by the other CPU to not overlap with the boot cpu's stacks.
1.9	29-Oct-2014	skrll	Sprinkle #include "opt_multiprocessor.h"
1.8	14-Sep-2014	ryo	add memory access barrier
1.7	28-Mar-2014	matt	branches: 1.7.4; Various MP changes.
1.6	03-Mar-2014	matt	Further cpu_info inits in cpu_hatch
1.5	18-Aug-2013	matt	branches: 1.5.2; Move parts of cpu.h that are not needed by MI code in <arm/locore.h> Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h> Use <arm/asm.h> instead of <machine/arm.h>
1.4	12-Jun-2013	matt	branches: 1.4.2; Add printfs around initializing the vector_page.
1.3	11-May-2013	skrll	Include opt_{ddb,kgdb} and fix KGDB build
1.2	17-Oct-2012	matt	branches: 1.2.2; 1.2.4; Change the semantics of the boot_physmem array to select a freelist to use with uvm_page_physload. Reduces duplication of work.
1.1	31-Aug-2012	matt	branches: 1.1.2; Make cpu_reset, most of initarm and the kvm init code common. Add MP hooks for cpu_need_resced Add idlestck which is allocated in arm32_kvminit
1.1.2.4	03-Dec-2017	jdolecek	update from HEAD
1.1.2.3	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.1.2.2	23-Jun-2013	tls	resync from head
1.1.2.1	20-Nov-2012	tls	Resync to 2012-11-19 00:00:00 UTC
1.2.4.2	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.2.4.1	17-Oct-2012	matt	file arm32_boot.c was added on branch matt-nb6-plus on 2012-11-28 22:40:16 +0000
1.2.2.3	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.2.2.2	30-Oct-2012	yamt	sync with head
1.2.2.1	17-Oct-2012	yamt	file arm32_boot.c was added on branch yamt-pagecache on 2012-10-30 17:18:56 +0000
1.4.2.2	18-May-2014	rmind	sync with head
1.4.2.1	28-Aug-2013	rmind	sync with head
1.5.2.3	24-Mar-2014	matt	Need to deal with proc0paddr.
1.5.2.2	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.5.2.1	18-Aug-2013	matt	file arm32_boot.c was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
1.7.4.3	12-Jan-2015	snj	Pull up following revision(s) (requested by jmcneill in ticket #412): sys/arch/arm/arm32/arm32_boot.c: revision 1.12 use IPL_NONE for CPU attach message serialization mutex
1.7.4.2	13-Dec-2014	martin	Pull up following revision(s) (requested by jmcneill in ticket #319): sys/arch/arm/arm32/arm32_boot.c: revision 1.11 serialize printing of secondary cpu info
1.7.4.1	09-Nov-2014	martin	Pull up following revision(s) (requested by skrll in ticket #188): sys/arch/arm/include/arm32/pmap.h: revision 1.136 sys/arch/arm/include/armreg.h: revision 1.100 sys/arch/arm/cortex/gic.c: revision 1.11 sys/arch/arm/arm32/db_interface.c: revision 1.54 sys/arch/arm/include/armreg.h: revision 1.101 sys/arch/arm/cortex/gic.c: revision 1.12 sys/arch/arm/arm32/arm32_machdep.c: revision 1.107 sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.19 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.20 sys/arch/evbarm/conf/BPI: revision 1.5 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.21 sys/arch/arm/arm32/pmap.c: revision 1.306 sys/arch/arm/arm32/db_machdep.c: revision 1.22 sys/arch/arm/arm32/arm32_tlb.c: revision 1.3 sys/arch/arm/arm/undefined.c: revision 1.55 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.22 sys/arch/arm/arm32/pmap.c: revision 1.307 sys/arch/arm/arm32/arm32_tlb.c: revision 1.4 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.23 sys/arch/arm/arm32/arm32_tlb.c: revision 1.5 sys/arch/evbarm/conf/BPI: revision 1.8 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.24 sys/arch/arm/arm32/arm32_tlb.c: revision 1.6 sys/arch/arm/arm32/arm32_tlb.c: revision 1.7 sys/arch/evbarm/conf/CUBIETRUCK: revision 1.5 sys/arch/arm/pic/pic.c: revision 1.23 sys/arch/arm/pic/pic.c: revision 1.24 sys/arch/arm/pic/picvar.h: revision 1.11 sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.20 sys/arch/arm/mainbus/cpu_mainbus.c: revision 1.16 sys/arch/arm/arm32/pmap.c: revision 1.298 sys/arch/arm/arm/cpufunc_asm_arm11.S: revision 1.17 sys/arch/arm/arm/cpufunc_asm_pj4b.S: revision 1.5 sys/arch/arm/arm32/pmap.c: revision 1.310 sys/arch/arm/arm32/pmap.c: revision 1.311 sys/arch/arm/arm32/arm32_kvminit.c: revision 1.32 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.19 sys/arch/arm/arm32/arm32_boot.c: revision 1.10 sys/arch/arm/arm/ast.c: revision 1.25 sys/arch/arm/include/armreg.h: revision 1.98 sys/uvm/pmap/pmap_tlb.c: revision 1.10 sys/arch/arm/arm32/arm32_boot.c: revision 1.8 sys/arch/arm/arm32/arm32_boot.c: revision 1.9 sys/arch/arm/arm/arm_machdep.c: revision 1.43 Various ARM MP fixes.
1.10.2.5	28-Aug-2017	skrll	Sync with HEAD
1.10.2.4	05-Feb-2017	skrll	Sync with HEAD
1.10.2.3	19-Mar-2016	skrll	Sync with HEAD
1.10.2.2	06-Jun-2015	skrll	Sync with HEAD
1.10.2.1	06-Apr-2015	skrll	Sync with HEAD
1.17.2.1	07-Jan-2017	pgoyette	Sync with HEAD. (Note that most of these changes are simply $NetBSD$ tag issues.)
1.19.6.2	08-Apr-2020	martin	Merge changes from current as of 20200406
1.19.6.1	10-Jun-2019	christos	Sync with HEAD
1.19.4.6	26-Jan-2019	pgoyette	Sync with HEAD
1.19.4.5	18-Jan-2019	pgoyette	Synch with HEAD
1.19.4.4	26-Nov-2018	pgoyette	Sync with HEAD, resolve a couple of conflicts
1.19.4.3	20-Oct-2018	pgoyette	Sync with head
1.19.4.2	30-Sep-2018	pgoyette	Ssync with HEAD
1.19.4.1	06-Sep-2018	pgoyette	Sync with HEAD Resolve a couple of conflicts (result of the uimin/uimax changes)
1.33.4.1	05-Jun-2021	martin	Pull up following revision(s) (requested by skrll in ticket #1279): sys/arch/arm/arm32/arm32_boot.c: revision 1.42 sys/arch/arm/arm32/arm32_boot.c: revision 1.43 G/C - Mirror the changes around passing pages to UVM in aarch64_machdep.c: Two fixes for loading free pages into UVM - Only consider a boot_physmem (inner loop) range that has its end (bp_end) after the bootconfig.dram (outer loop) range start (start). This was harmless as a later condition correctly checks there is only something to do if start < bp_end. - Stop processing boot_physmem ranges if all the bootconfig.dram range has been passed to UVM. This fixes a boot problem for simon@ Copy a comment over and do the VPRINTF before the uvm_page_physload in the same way as aarch64_machdep.c as well.
1.35.2.2	29-Feb-2020	ad	Sync with head.
1.35.2.1	17-Jan-2020	ad	Sync with head.
1.40.2.1	14-Dec-2020	thorpej	Sync w/ HEAD.
1.41.4.1	17-Jun-2021	thorpej	Sync w/ HEAD.
1.42.2.1	06-Jun-2021	cjep	sync with head
1.44.4.1	23-Dec-2022	martin	Pull up following revision(s) (requested by ryo in ticket #20): sys/arch/arm/arm/cpufunc.c: revision 1.185 sys/dev/tprof/tprof.c: revision 1.22 sys/arch/arm/arm32/arm32_boot.c: revision 1.45 sys/dev/tprof/tprof_armv8.c: revision 1.19 sys/dev/tprof/tprof_armv7.c: revision 1.12 sys/arch/aarch64/aarch64/cpu.c: revision 1.71 sys/arch/aarch64/aarch64/cpu.c: revision 1.72 tprof_lock is not a spin mutex. use mutex_{enter,exit}(). oops Explicitly disable overflow interrupts before enabling the cycle counter. PMCR_EL0.LC should be set. ARM deprecates use of PMCR_EL0.LC=0 Even if an overflow interrupt is occured for a counter outside tprof management, the bit of onverflow status register must be cleared to prevent an interrupt storm.
1.69	02-Apr-2022	skrll	Update to support EFI runtime outside the kernel virtual address space by creating an EFI RT pmap that can be activated / deactivated when required. Adds support for EFI RT to ARM_MMU_EXTENDED (ASID) 32-bit Arm machines. On Arm64 the usage of pmapboot_enter is reduced and the mappings are created much later in the boot process -- now in cpu_startup_hook. Backward compatiblity for KVA mapped RT from old bootaa64.efi is maintained. Adding support to other platforms should be easier as a result.
1.68	21-Mar-2021	skrll	-DKERNEL_BASE_VOFFSET= has annoyed me for the last time... Introduce KERNEL_VOFFSET_RUNTIME which prevents the addition of -DKERNEL_BASE_VOFFSET= to the command line and use it on the __HAVE_GENERIC_START kernels which do runtime calculation of the offset.
1.67	12-Dec-2020	skrll	branches: 1.67.2; Move evbarm/fdt/fdt_memory.[ch] to sys/dev/fdt and simplify the api and some operations. This allows other architectures to use it.
1.66	30-Oct-2020	skrll	branches: 1.66.2; Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.
1.65	28-Aug-2020	skrll	Some KASAN fixes and tweaks - don't access BSS variables when __md_early - centralise the INIT_ARM_STACK_{SHIFT,SIZE} defines and create a new INIT_ARM_TOTAL_STACK - Only create L1PT entries in kasan_md_shadow_map_page if arm32_kernel_vm_init hasn't created the L2PTs (and their L1PT entries) - Add some comments to explain what's going on
1.64	10-Jul-2020	skrll	Add support for KASAN on ARMv[67] Thanks to maxv for many pointers and reviews.
1.63	03-Jul-2020	skrll	Style and share a debug string
1.62	03-Jul-2020	skrll	Use howmany()
1.61	03-Jul-2020	skrll	Whitespace
1.60	26-Jun-2020	skrll	Avoid unbounded stack usage warning
1.59	20-Jun-2020	skrll	KNF #includes Remove some unnecessary ones while I'm here.
1.58	04-Feb-2020	skrll	KNF
1.57	04-Feb-2020	skrll	grammar in a comment
1.56	02-Feb-2020	skrll	G/C L1_TABLE_SIZE_REAL
1.55	08-May-2019	skrll	branches: 1.55.4; Really go back to pre-whitespace change (1.52) arm32_kernel_vm_init
1.54	23-Apr-2019	skrll	Revert the part of the previous Whitespace commit which clearly was functional. This will probably come back with other changes and a proper commit message.
1.53	17-Mar-2019	skrll	Whitespace
1.52	06-Feb-2019	skrll	Make sure the start stacks are covered by the new translation tables. They might get placed after ARM_BOOTSTRAP_LxPT by the linker. AP startup uses VA sp in cpu_init_secondary_processor
1.51	06-Feb-2019	skrll	Misc style
1.50	06-Feb-2019	skrll	Slight update to comment and KNF it while I'm here
1.49	04-Feb-2019	skrll	Fix typo in VPRINTF
1.48	13-Nov-2018	skrll	On second/third thoughts we can use the pages before the kernel everywhere.
1.47	20-Oct-2018	skrll	Clean up around cpu_ttb and fix a bunch of builds
1.46	18-Oct-2018	skrll	Provide generic start code that assumes the MMU is off and caches are disabled as per the linux booting protocol for ARMv6 and ARMv7 boards. u-boot image type should be changed to 'linux' for correct behaviour. The new start code builds a minimal "bootstrap" L1PT with cached access disabled and uses the same table for all processors. AP startup is performed in less steps and more code is written in C. The bootstrap tables and stack are placed into an (orphaned) section "_init_memory" which is given to uvm when it is no longer used. Various kernels have been converted to use this code and tested. Some boards were provided by TNF. Thanks! The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS kernels. The GENERIC kernel will also work on RPI2 using u-boot. Thanks to martin@ and aymeric@ for testing on parallella and nanosoc respectively
1.45	14-Oct-2018	skrll	Use __nothing
1.44	03-Aug-2018	skrll	Provide and use kern_vtopdiff in KERN_{VTOPHYS,PHYSTOV}. A step towards generic arm.
1.43	31-Jul-2018	martin	#ifdef VERBOSE_INIT_ARM some format strings only used in that case.
1.42	31-Jul-2018	skrll	Define and use VPRINTF
1.41	10-Dec-2017	skrll	branches: 1.41.2; 1.41.4; FDTise RapberryPI support. Thanks for jmcneill for a lot of help with this. The kernel image that the RPI firmware boots is now netbsd.img in the kernel build directory. XXX fdtbus_get_reg needs reworking
1.40	06-Jul-2017	skrll	Now that we can... mark kernel text as non-writable on MMUs that support it.
1.39	01-Jul-2017	skrll	Report an error if compiled with MULTIPROCESSOR support but without __HAVE_CPU_UAREA_ALLOC_IDLELWP
1.38	24-Dec-2016	skrll	Fix VERBOSE_INIT_ARM build
1.37	25-Nov-2015	skrll	branches: 1.37.2; In the ARM_MMU_EXTENDED case make sure the kernel mappings are marked with XN (eXecute Never) appropriately. The XN logic is inconsistent and could do with changing to XN always set and cleared for VM_PROT_EXECUTE (or the inverse) everywhere.
1.36	25-Nov-2015	skrll	Trailing whitespace.
1.35	01-Jun-2015	matt	pmap_directbase is a failed experiment, nuke it.
1.34	30-May-2015	matt	Support directmapped systems with >1GB that start memory at 0x80000000.
1.33	04-May-2015	matt	Deal with 2GB of ram or memory ending at or above 4GB.
1.32	29-Oct-2014	skrll	branches: 1.32.2; Sprinkle #include "opt_multiprocessor.h"
1.31	24-Oct-2014	skrll	Remove unnecessary #include
1.30	23-May-2014	kiyohara	branches: 1.30.2; Fix build failed with GUMSTIX(pxa2x0). build test only now.
1.29	13-Apr-2014	matt	When figuring out the physical size for direct-mapped systems, round up to L1_SS_SIZE.
1.28	11-Apr-2014	matt	Add a kernel for the CUBIETRUCK (CUBIEBOARD3). Allow direct mapping of all memory (but for now allow the memory mapped above KERNEL_BASE to used for poolpages).
1.27	05-Apr-2014	matt	If using arm32_kvminit, don't bother mapping msgbuf since it's already mapped.
1.26	01-Apr-2014	skrll	branches: 1.26.2; Remove unnecessary { } around code block. No functional change.
1.25	28-Mar-2014	matt	ARM_MMU_EXTENDED support.
1.24	05-Mar-2014	matt	rearrange some printfs. when using the extended mmu, make sure to disable ttbr0 until there is an activated pmap.
1.23	03-Mar-2014	matt	If we are going to map all of physical memory, we don't need to allocate l2 page tables for the kernel.
1.22	29-Aug-2013	riz	branches: 1.22.2; Fix typo: VERBOSE_INIT_ARM, not VERBOSE_ARM_INIT. From Dennis Ferguson in PR#48163.
1.21	22-Jun-2013	matt	branches: 1.21.2; Fix inverted logic for mapping exception vector.
1.20	12-Jun-2013	matt	Add a ARM_HAS_VBAR option which forces the use of the VBAR register. This allows much code to deal with vector_page mappings to be eliminated. On a BEAGLEBONE kernel, this saves 8KB of text and instructions that never have to be executed. (The PJ4B has VBAR but doesn't implement the security extensions it is part of so a method was needed to allow it use VBAR with relying on the default test for the security extensions.)
1.19	12-Jun-2013	matt	Add support for the VBAR (vector base address register) to remap the vectors into the kernel text segment. This register is available on arm1176 and all cortex processors since they all have the arm security (trustzone) extension. We avoid having to specially map either vector page (0x00000000 or 0xffff0000) and use VBAR to both to page0rel in the text segment. These vector group differs from the normal page0, that since it's in the kernel, it can branch directly to the exception routine, instead of loading the address into the PC. This should result in a tiny improvement in speed since we eliminate a TLB mapping the vector page and a load on every exception. XXX Add __HAVE_ARM_TRUSTZONE cpp define and use that to eliminate all code have to do with manipulating the vector page.
1.18	27-Feb-2013	matt	Actually use zero_p now that we pass it in.
1.17	27-Feb-2013	matt	Add a zero flag to valloc_pages so that we can not zero the msgbuf so it will be preserved across boots.
1.16	31-Dec-2012	matt	Correct one of the kernel_size calculations.
1.15	10-Dec-2012	matt	if __HAVE_MM_MD_DIRECT_MAPPED_PHYS is defined, make sure mapallmem_p is true.
1.14	24-Oct-2012	skrll	branches: 1.14.2; 1.14.4; Compare pointer against NULL not 0.
1.13	21-Oct-2012	matt	Make sure when mapping all the kernel, start at KERNEL_BASE, not kernel_base.
1.12	19-Oct-2012	skrll	Make sure that start.S and machdep.c don't disagree wrt L1 page table location during bootstrap.
1.11	19-Oct-2012	skrll	slop wasn't sloppy enough in the kernel_size calculation. Add in the L2 page tables required as well. Should fix the dockstar boot problem reported by Andy Ruhl on port-arm. http://mail-index.netbsd.org/port-arm/2012/09/20/msg001471.html
1.10	19-Oct-2012	skrll	Comments.
1.9	19-Oct-2012	skrll	Print the message buffer VAs and number of pages. Other minor cosmetics.
1.8	17-Oct-2012	skrll	Fix two off-by-one loops. Saves a whole two pages.
1.7	15-Oct-2012	skrll	More VERBOSE_INIT_ARM output tweaks.
1.6	15-Oct-2012	skrll	Typo in comment.
1.5	15-Oct-2012	skrll	Print the system vectors in order so I don't get confused.
1.4	22-Sep-2012	matt	Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead but add a second argument to it to indicate whether the TLB/caches need to be flushed. Default cortex to pmap_needs_fixup = 1. But check the MMFR3 field to see if the fixed can be skipped. Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1) or enabeld (bit = 0). With these changes, the A9 MMU can use traverse caches to do MMU tablewalks Also, make sure all memory has the shareable bit for the A9.
1.3	06-Sep-2012	matt	branches: 1.3.2; Before setting the new TTB wbinv the caches.
1.2	05-Sep-2012	matt	Print TTBR/TTBR1/TTBCR registers
1.1	31-Aug-2012	matt	Make cpu_reset, most of initarm and the kvm init code common. Add MP hooks for cpu_need_resced Add idlestck which is allocated in arm32_kvminit
1.3.2.5	03-Dec-2017	jdolecek	update from HEAD
1.3.2.4	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.3.2.3	23-Jun-2013	tls	resync from head
1.3.2.2	25-Feb-2013	tls	resync with head
1.3.2.1	20-Nov-2012	tls	Resync to 2012-11-19 00:00:00 UTC
1.14.4.2	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.14.4.1	24-Oct-2012	matt	file arm32_kvminit.c was added on branch matt-nb6-plus on 2012-11-28 22:40:16 +0000
1.14.2.5	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.14.2.4	23-Jan-2013	yamt	sync with head
1.14.2.3	16-Jan-2013	yamt	sync with (a bit old) head
1.14.2.2	30-Oct-2012	yamt	sync with head
1.14.2.1	24-Oct-2012	yamt	file arm32_kvminit.c was added on branch yamt-pagecache on 2012-10-30 17:18:56 +0000
1.21.2.1	18-May-2014	rmind	sync with head
1.22.2.4	13-Aug-2015	matt	Make sure the amount of direct mapped memory doesn't cross over into the mappable KVA range.
1.22.2.3	24-Mar-2014	matt	Make sure kernel starts on a page boundary.
1.22.2.2	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.22.2.1	29-Aug-2013	matt	file arm32_kvminit.c was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
1.26.2.1	10-Aug-2014	tls	Rebase.
1.30.2.1	09-Nov-2014	martin	Pull up following revision(s) (requested by skrll in ticket #188): sys/arch/arm/include/arm32/pmap.h: revision 1.136 sys/arch/arm/include/armreg.h: revision 1.100 sys/arch/arm/cortex/gic.c: revision 1.11 sys/arch/arm/arm32/db_interface.c: revision 1.54 sys/arch/arm/include/armreg.h: revision 1.101 sys/arch/arm/cortex/gic.c: revision 1.12 sys/arch/arm/arm32/arm32_machdep.c: revision 1.107 sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.19 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.20 sys/arch/evbarm/conf/BPI: revision 1.5 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.21 sys/arch/arm/arm32/pmap.c: revision 1.306 sys/arch/arm/arm32/db_machdep.c: revision 1.22 sys/arch/arm/arm32/arm32_tlb.c: revision 1.3 sys/arch/arm/arm/undefined.c: revision 1.55 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.22 sys/arch/arm/arm32/pmap.c: revision 1.307 sys/arch/arm/arm32/arm32_tlb.c: revision 1.4 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.23 sys/arch/arm/arm32/arm32_tlb.c: revision 1.5 sys/arch/evbarm/conf/BPI: revision 1.8 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.24 sys/arch/arm/arm32/arm32_tlb.c: revision 1.6 sys/arch/arm/arm32/arm32_tlb.c: revision 1.7 sys/arch/evbarm/conf/CUBIETRUCK: revision 1.5 sys/arch/arm/pic/pic.c: revision 1.23 sys/arch/arm/pic/pic.c: revision 1.24 sys/arch/arm/pic/picvar.h: revision 1.11 sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.20 sys/arch/arm/mainbus/cpu_mainbus.c: revision 1.16 sys/arch/arm/arm32/pmap.c: revision 1.298 sys/arch/arm/arm/cpufunc_asm_arm11.S: revision 1.17 sys/arch/arm/arm/cpufunc_asm_pj4b.S: revision 1.5 sys/arch/arm/arm32/pmap.c: revision 1.310 sys/arch/arm/arm32/pmap.c: revision 1.311 sys/arch/arm/arm32/arm32_kvminit.c: revision 1.32 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.19 sys/arch/arm/arm32/arm32_boot.c: revision 1.10 sys/arch/arm/arm/ast.c: revision 1.25 sys/arch/arm/include/armreg.h: revision 1.98 sys/uvm/pmap/pmap_tlb.c: revision 1.10 sys/arch/arm/arm32/arm32_boot.c: revision 1.8 sys/arch/arm/arm32/arm32_boot.c: revision 1.9 sys/arch/arm/arm/arm_machdep.c: revision 1.43 Various ARM MP fixes.
1.32.2.4	28-Aug-2017	skrll	Sync with HEAD
1.32.2.3	05-Feb-2017	skrll	Sync with HEAD
1.32.2.2	27-Dec-2015	skrll	Sync with HEAD (as of 26th Dec)
1.32.2.1	06-Jun-2015	skrll	Sync with HEAD
1.37.2.1	07-Jan-2017	pgoyette	Sync with HEAD. (Note that most of these changes are simply $NetBSD$ tag issues.)
1.41.4.2	08-Apr-2020	martin	Merge changes from current as of 20200406
1.41.4.1	10-Jun-2019	christos	Sync with HEAD
1.41.2.3	26-Nov-2018	pgoyette	Sync with HEAD, resolve a couple of conflicts
1.41.2.2	20-Oct-2018	pgoyette	Sync with head
1.41.2.1	06-Sep-2018	pgoyette	Sync with HEAD Resolve a couple of conflicts (result of the uimin/uimax changes)
1.55.4.1	29-Feb-2020	ad	Sync with head.
1.66.2.2	03-Apr-2021	thorpej	Sync with HEAD.
1.66.2.1	14-Dec-2020	thorpej	Sync w/ HEAD.
1.67.2.1	03-Apr-2021	thorpej	Sync with HEAD.
1.148	06-Sep-2025	thorpej	Refactor the "platform" defitions into fdt_platform.h
1.147	05-Mar-2024	thorpej	Move the at-shutdown call to resettodr() from cpu_reboot() to kern_reboot(). It's a small step, but it's a step.
1.146	07-Apr-2023	skrll	Rename ARM_PLATFORM to FDT_PLATFORM and make it available outside arm.
1.145	19-Jan-2023	mlelstv	Support remaining common boot options.
1.144	28-Jul-2022	riastradh	arm32: Refactor splhigh and restore in dosoftints. No functional change intended. splhigh always returns ci->ci_cpl, which should not be changing at this point. Makes the bracketing by splhigh/splx clearer.
1.143	12-Mar-2022	skrll	No need to call arm_fdt_platform twice.
1.142	13-Nov-2021	jmcneill	Support 'boot -1' on arm
1.141	31-Oct-2021	skrll	Rework Arm (32bit and 64bit) AP startup so that cpu_hatch doesn't sleep. The AP initialisation code in cpu_init_secondary_processor will read and initialise the required system registers and state for the BP to attach and report. Rework the interrupt handler code for this new sequence. Thankfully, this removes a bunch of code for bcm2836mp. The VFP detection handler on <= armv7 relies on the global undefined handler being in place until the BP attaches vfp. That is, after the APs have been spun up. gicv3_its.c has a serialisation issue which is protected against in the gicv3_its_cpu_init, which is called from cpu_hatch, with a spin lock. The serialisation issue needs addressing more completely. Tested on RPI3, Apple M1, QEMU, and lx2k Fixes PR port-arm/56264: diagnostic assertion "l->l_stat == LSONPROC" failed on RPI3
1.140	21-Oct-2021	skrll	Whitespace in a comment
1.139	01-Dec-2020	rin	Switch earmv6{,hf}eb to BE8 in kernel side. My strategy here is to define _ARM_ARCH_BE8 macro in arm/cdefs.h, if __ARMEB__ && _ARM_ARCH_6. Use this macro to determine whether system is compiled for and running on BE8 mode or not. Note that, for __ARMEB__, some conditions become compile-time constants determined by _ARM_ARCH_BE8 macro, e.g., whether BE8 or BE32 are accepted as a userland binary, or unaligned memory access is possible or not.
1.138	30-Oct-2020	skrll	branches: 1.138.2; Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.
1.137	28-Aug-2020	skrll	Use C rather than assembly
1.136	10-Jul-2020	skrll	Add support for KASAN on ARMv[67] Thanks to maxv for many pointers and reviews.
1.135	21-Jun-2020	jmcneill	Add support for installing modules that were loaded by the bootloader.
1.134	20-Jun-2020	skrll	KNF
1.133	18-Apr-2020	skrll	PMAP_DEBUG has been deleted on arm
1.132	15-Feb-2020	skrll	branches: 1.132.4; Various updates and improvements to cpu start up on arm/aarch64 - start sharing more code around the AP startup messaging. - call arm_cpu_topology_set early so that ci_core_id is available for drivers, e.g. bcm2835_intr.c - both arm and aarch64 now have - a static cpu_info_store array - the same arm_cpu_{hatched,mbox}
1.131	02-Feb-2020	skrll	KNF. One #include <sys/atomic.h> is enough
1.130	27-Dec-2019	msaitoh	branches: 1.130.2; s/sucess/success/ in comment.
1.129	18-Dec-2019	riastradh	New function cpu_startup_hook on arm. Called at end of cpu_startup. Can be defined in, e.g., evbarm to do additional stuff after cpu_startup. Defined as a weak alias to a function that does nothing, so optional. ok jmcneill
1.128	10-May-2019	skrll	branches: 1.128.2; Fix a printf
1.127	04-Feb-2019	skrll	Report hatched value after the atomic_or so the VERBOSE_INIT_ARM output doesn't get mangled. We start a cpu and wait for it before progressing now.
1.126	21-Jan-2019	skrll	Wrong long lined comment
1.125	03-Jan-2019	skrll	Start CPUs more like aarch64 by using a cpu_mpidr array (if populated) to map MPIDRs to an index for each CPU. Towards big.LITTLE support.
1.124	19-Oct-2018	skrll	Fix build for non-generic start kernels
1.123	18-Oct-2018	skrll	Provide generic start code that assumes the MMU is off and caches are disabled as per the linux booting protocol for ARMv6 and ARMv7 boards. u-boot image type should be changed to 'linux' for correct behaviour. The new start code builds a minimal "bootstrap" L1PT with cached access disabled and uses the same table for all processors. AP startup is performed in less steps and more code is written in C. The bootstrap tables and stack are placed into an (orphaned) section "_init_memory" which is given to uvm when it is no longer used. Various kernels have been converted to use this code and tested. Some boards were provided by TNF. Thanks! The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS kernels. The GENERIC kernel will also work on RPI2 using u-boot. Thanks to martin@ and aymeric@ for testing on parallella and nanosoc respectively
1.122	14-Oct-2018	skrll	Use __nothing
1.121	12-Oct-2018	jmcneill	Add optional ap_startup callback to struct arm_platform. This allows for late (post-UVM init) initialization of platform specific stuff.
1.120	22-Aug-2018	skrll	Use banner
1.119	15-Aug-2018	skrll	G/C
1.118	05-Aug-2018	skrll	Add prefixes to struct arm_platform{,_info} members. No functional change.
1.117	05-Aug-2018	skrll	Refactor code to split aarch{32,64} kernel page tables and VM setup. This will help re-build the kernel page tables on aarch64 with correct section mappings.
1.116	31-Jul-2018	skrll	Define and use VPRINTF
1.115	31-Oct-2017	martin	branches: 1.115.2; 1.115.4; Allow architectures to define a macro PROC_MACHINE_ARCH(P) and PROC_MACHINE_ARCH32(P) to override the value for sysctl hw.machine_arch (native and netbsd32 commpat resp.). Use these for arm and mips instead of the (not working, noisy, in case of arm) sysctl override and #ifdef __mips__ in architecture neutral code.
1.114	02-Jul-2017	skrll	Consistency around the user trapframe for all LWPs and there's no need to keep assigning it in kernel entry points.
1.113	02-Jul-2017	skrll	Trailing whitespace
1.112	16-Jul-2016	mrg	apply some #if (ARM_MMU_V6 + ARM_MMU_V7) != 0. now this builds on pre v6-only.
1.111	15-Jul-2016	skrll	Provide a mm_md_page_color and fix some kernel builds
1.110	30-Apr-2016	ryo	branches: 1.110.2; * fix checking physical address range. on some arm devices, physical memory doesn't start from 0x00000000. * allow /dev/mem to read/write memory mapped I/O area depending on kauth.
1.109	11-Apr-2015	bouyer	Handle boot option -x (alias 'debug') and set AB_DEBUG in boothowto.
1.108	19-Nov-2014	martin	branches: 1.108.2; Add a machdep.unaligned_sigbus sysctl (just like alpha does), but on arm it is readonly (depends on architecture version).
1.107	29-Oct-2014	skrll	Sprinkle #include "opt_multiprocessor.h"
1.106	25-Oct-2014	skrll	Remove katelib.h and references to it. {Read,Write}{Word,Byte} macros are provided in the files that still use them. Someone(tm) should convert them to bus_space(9)
1.105	19-May-2014	rmind	branches: 1.105.2; Implement MI IPI interface with cross-call support.
1.104	11-Apr-2014	matt	Add a kernel for the CUBIETRUCK (CUBIEBOARD3). Allow direct mapping of all memory (but for now allow the memory mapped above KERNEL_BASE to used for poolpages).
1.103	05-Apr-2014	matt	If using arm32_kvminit, don't bother mapping msgbuf since it's already mapped.
1.102	28-Mar-2014	matt	branches: 1.102.2; Various MP changes.
1.101	03-Mar-2014	matt	Add most of the cpu_* variables to <arm/locore.h> Add and initialize cpu_synchprim_present
1.100	25-Feb-2014	pooka	Ensure that the top level sysctl nodes (kern, vfs, net, ...) exist before the sysctl link sets are processed, and remove redundancy. Shaves >13kB off of an amd64 GENERIC, not to mention >1k duplicate lines of code.
1.99	11-Jan-2014	matt	Add hw.printfataltraps sysctl. Always print fatal traps for init. For all other processes, only do so if cpu_printfataltraps is true.
1.98	10-Sep-2013	matt	Support an optional MARCH ELF tag. Store the MACHINE_ARCH of the executable in mdproc and override sysctl so that value returned.
1.97	07-Sep-2013	matt	Add a machdep.hwdiv_present sysctl (cortex A7 and A15 have hwdiv instructions)
1.96	18-Aug-2013	matt	Move parts of cpu.h that are not needed by MI code in <arm/locore.h> Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h> Use <arm/asm.h> instead of <machine/arm.h>
1.95	15-Aug-2013	matt	Fix tpyo.
1.94	12-Jun-2013	matt	branches: 1.94.2; Add a ARM_HAS_VBAR option which forces the use of the VBAR register. This allows much code to deal with vector_page mappings to be eliminated. On a BEAGLEBONE kernel, this saves 8KB of text and instructions that never have to be executed. (The PJ4B has VBAR but doesn't implement the security extensions it is part of so a method was needed to allow it use VBAR with relying on the default test for the security extensions.)
1.93	12-Jun-2013	matt	Add support for the VBAR (vector base address register) to remap the vectors into the kernel text segment. This register is available on arm1176 and all cortex processors since they all have the arm security (trustzone) extension. We avoid having to specially map either vector page (0x00000000 or 0xffff0000) and use VBAR to both to page0rel in the text segment. These vector group differs from the normal page0, that since it's in the kernel, it can branch directly to the exception routine, instead of loading the address into the PC. This should result in a tiny improvement in speed since we eliminate a TLB mapping the vector page and a load on every exception. XXX Add __HAVE_ARM_TRUSTZONE cpp define and use that to eliminate all code have to do with manipulating the vector page.
1.92	03-Feb-2013	matt	Add a machdep.cpu_arch sysctl
1.91	31-Jan-2013	matt	Add simple sysctls for cpu_id, fpu_id, neon_present, simd_present, simdex_present. Add struct sysctls to return the isar, mmfr, pfr, and mvfr sets.
1.90	28-Jan-2013	matt	Add a machdep.fpu_present sysctl for ld.elf_so to use in ld.so.conf to load libc_vfp.so.
1.89	19-Jan-2013	skrll	Add -d as a synonym for getting into DDB to match other ports.
1.88	31-Dec-2012	jmcneill	reset todr clock on shutdown
1.87	10-Dec-2012	matt	add mm_md_direct_mapped_phys
1.86	10-Dec-2012	matt	Rename pcb_sp/PCB_SP to pcb_ksp/PCB_KSP so that ipsec.c will compile.
1.85	27-Oct-2012	chs	split device_t/softc for all remaining drivers. replace "struct device *" with "device_t". use device_xname(), device_unit(), etc.
1.84	16-Sep-2012	rmind	Rename kcpuset_copybits() to kcpuset_export_u32() and thus be more specific about the interface.
1.83	31-Aug-2012	matt	branches: 1.83.2; Make cpu_reset, most of initarm and the kvm init code common. Add MP hooks for cpu_need_resced Add idlestck which is allocated in arm32_kvminit
1.82	16-Aug-2012	matt	Move the standard definitions of the {UND,IRQ,FIQ,ABT}_STACK_SIZE to <arm32/machdep.h> Move the extern for cpu_reset_address to the same file. Add cpu_reset_address_paddr. Kill cpu_reset_v4_MMU_disable. if cpu_reset_address is NULL, then the MMU will be disabled.
1.81	16-Aug-2012	matt	small rototill. pcb_flags is dead. PCB_NOALIGNFLT is now in stored l_md.md_flags as MDLWP_NOALIGNFLT. This avoids a few loads of the PCB in exception handling. pcb_tf has been moved to l_md.md_tf. Again this avoids a lot of pcb references just to access or set this. It also means that pcb doesn't need to accessed by MI code. Move pcb_onfault to after the pcb union. Add pcb_sp macro to make code prettier. Add lwp_settrapframe(l, tf) to set the l_md.md_tf field. Use lwp_trapframe to access it (was process_frame but that name was changed in a previous commit). Kill off curpcb in acorn26. Kill the checks for curlwp being NULL. Move TRAP_USERMODE from arm32/fault.c to frame.h and a __PROG26 version. Replace tests for usermode with that macro.
1.80	14-Aug-2012	matt	Kill curpcb/ci_curpcb. Use device_t in cpu_info. Add ci_softc (where ci_curpcb was so cpu_info doesn't change).
1.79	29-Jul-2012	matt	Fix more -fno-common fallout. Move more variables to common locations.
1.78	16-Jul-2012	skrll	Make the result from SOFTIPLMASK match the comment. "Wouldn't hurt" from matt@
1.77	16-Jul-2012	skrll	Fix racy softint dispatch that lead to KASSERT(si->si_active) in softint_execute Discussed with matt@. "Looks good to me"
1.76	30-Jun-2011	wiz	branches: 1.76.2; 1.76.8; dependant -> dependent
1.75	12-Jun-2011	rmind	Welcome to 5.99.53! Merge rmind-uvmplock branch: - Reorganize locking in UVM and provide extra serialisation for pmap(9). New lock order: [vmpage-owner-lock] -> pmap-lock. - Simplify locking in some pmap(9) modules by removing P->V locking. - Use lock object on vmobjlock (and thus vnode_t::v_interlock) to share the locks amongst UVM objects where necessary (tmpfs, layerfs, unionfs). - Rewrite and optimise x86 TLB shootdown code, make it simpler and cleaner. Add TLBSTATS option for x86 to collect statistics about TLB shootdowns. - Unify /dev/mem et al in MI code and provide required locking (removes kernel-lock on some ports). Also, avoid cache-aliasing issues. Thanks to Andrew Doran and Joerg Sonnenberger, as their initial patches formed the core changes of this branch.
1.74	28-Nov-2010	hannken	branches: 1.74.6; As md(4) no longer has "needs-count" there is no "md.h" anymore. Remove the inclusion of this file. Acorn32 now always builds load_memory_disc_from_floppy(). This should not be a problem as all configs have md(4). Observed by: Masao Uebayashi <uebayasi@netbsd.org>
1.73	08-Feb-2010	joerg	branches: 1.73.2; Remove separate mb_map. The nmbclusters is computed at boot time based on the amount of physical memory and limited by NMBCLUSTERS if present. Architectures without direct mapping also limit it based on the kmem_map size, which is used as backing store. On i386 and ARM, the maximum KVA used for mbuf clusters is limited to 64MB by default. The old default limits and limits based on GATEWAY have been removed. key_registered_sb_max is hard-wired to a value derived from 2048 clusters.
1.72	18-Jan-2010	jmmv	branches: 1.72.2; Define an empty module_init_md function so that kernels with 'options MODULAR' can be built (at least in shark). Still not working due to some relocations resolving to too far away symbols though.
1.71	29-Nov-2009	rmind	Replace l_addr with uvm_lwp_getuarea() in various MD code, mostly cpu_lwp_fork().
1.70	27-Nov-2009	rmind	- Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr. - Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb(). - Amend assembly in ports where it accesses PCB via struct user. - Rename L_ADDR to L_PCB in few places. Reduce sys/user.h inclusions.
1.69	26-Nov-2009	matt	Kill proc0paddr. Use lwp0.l_addr instead.
1.68	21-Nov-2009	rmind	Use lwp_getpcb() on ARM (and acorn26/32), clean from struct user usage.
1.67	07-Nov-2009	cegger	Add a flags argument to pmap_kenter_pa(9). Patch showed on tech-kern@ http://mail-index.netbsd.org/tech-kern/2009/11/04/msg006434.html No objections.
1.66	11-Aug-2009	matt	Remove all declarations of physmem from sys/arch. Add an include of <sys/systm.h> to the one file that did not already contain it. This now means that physmem can be changed by updating systm.h and uvm_page.c (excluding fixing printfs)
1.65	15-Mar-2009	cegger	ansify function definitions
1.64	14-Mar-2009	dsl	Change about 4500 of the K&R function definitions to ANSI ones. There are still about 1600 left, but they have ',' or /* ... */ in the actual variable definitions - which my awk script doesn't handle. There are also many that need () -> (void). (The script does handle misordered arguments.)
1.63	14-Mar-2009	dsl	Remove all the __P() from sys (excluding sys/dist) Diff checked with grep and MK1 eyeball. i386 and amd64 GENERIC and sys still build.
1.62	17-Jan-2009	bjh21	branches: 1.62.2; Remove the implementation of cpu_intr_p() from here now that it's in arm/arm_machdep.h. Should fix builds on arm32 platforms. Thanks to Matt Fleming for reporting the problem.
1.61	16-Jan-2009	bjh21	cpu_info_store, machine, and machine_arch can all be shared by acorn26 and arm32, so share them.
1.60	16-Jan-2009	bjh21	acorn26 and arm32 have identical versions of cpu_need_resched(). Unify them. Similarly, with a small tweak acorn26 can use the same cpu_intr_p() as arm32, so those can be unified too.
1.59	19-Nov-2008	matt	Fix __HAVE_FAST_SOFTINTS (boolean dyslexia strikes again). Add some KASSERTS to make sure assumptions are valid.
1.58	07-Aug-2008	matt	branches: 1.58.2; 1.58.8; Commit missing part of __HAVE_FAST_SOFTINTS support.
1.57	02-Jul-2008	ad	branches: 1.57.2; Replce exec_map with a pool. Proposed on tech-kern@, reviewed by chs@.
1.56	27-Apr-2008	matt	branches: 1.56.2; 1.56.4; Merge kernel changes in matt-armv6 to HEAD.
1.55	19-Jan-2008	chris	branches: 1.55.6; 1.55.8; 1.55.10; With the removal of IPKDB on arm, the undefined stack is only used to bounce into SVC32 mode, there is no per-process data stored on it. We can therefore use the undefined stack setup by the platform machdep.c as a system wide undefined stack. This removes the need for a per-process undefined stack, and the processor mode switching overhead it causes in cpu_switchto. The space freed in the USPACE is used to increase the per process kernel stack size.
1.54	19-Jan-2008	chris	Remove arm support for IPKDB. It hasn't worked since arm was broken out from arm32 in Jan 2001, and no-one has noticed or cared to fix it.
1.53	16-Dec-2007	mrg	move the arm32 cpu_intr_p() function into arm32_machdep.c from arm_machdep.c. this lets acorn26 link again.
1.52	17-Oct-2007	garbled	branches: 1.52.2; 1.52.4; 1.52.8; Merge the ppcoea-renovation branch to HEAD. This branch was a major cleanup and rototill of many of the various OEA cpu based PPC ports that focused on sharing as much code as possible between the various ports to eliminate near-identical copies of files in every tree. Additionally there is a new PIC system that unifies the interface to interrupt code for all different OEA ppc arches. The work for this branch was done by a variety of people, too long to list here. TODO: bebox still needs work to complete the transition to -renovation. ofppc still needs a bunch of work, which I will be looking at. ev64260 still needs to be renovated amigappc was not attempted. NOTES: pmppc was removed as an arch, and moved to a evbppc target.
1.51	02-Oct-2007	ad	Make want_resched a member of cpu_info.
1.50	15-Sep-2007	scw	branches: 1.50.2; ARM cpu_switchto() has been partially broken since yamt-idlelwp was merged as its cache/tlb management smarts relied too heavily on pre-merge context- switch behaviour. See PR kern/36548 for one manifestation of the breakage. To address this: - Ditch the shadow pmap variables in the PCB (pagedir, l1vec, dacr, cstate) as it was too easy for them to get out of sync with the pmap. - Re-write (and fix) the convoluted cpuswitch.S cache/tlb ASM code in C. It's only slightly less efficient, but is much more readable/maintainable. - Document cpufuncs.cf_context_switch() as being C-callable. - pmap_activate() becomes a no-op if the lwp's vmspace is already active. (Good performance win, since pmap_activate() is now invoked on every context-switch, even though ARM's cpu_switchto() already does all the grunt work) XXX: Some CPU-specific armXX_context_switch() implementations (arm67, arm7tdmi, arm8) always flush the I+D caches. This should not be necessary. Someone with access to hardware (acorn32?) needs to deal with this.
1.49	17-May-2007	yamt	branches: 1.49.6; 1.49.8; 1.49.10; 1.49.12; merge yamt-idlelwp branch. asked by core@. some ports still needs work. from doc/BRANCHES: idle lwp, and some changes depending on it. 1. separate context switching and thread scheduling. (cf. gmcgarry_ctxsw) 2. implement idle lwp. 3. clean up related MD/MI interfaces. 4. make scheduler(s) modular.
1.48	04-Mar-2007	christos	branches: 1.48.2; 1.48.4; 1.48.10; Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.
1.47	22-Feb-2007	thorpej	TRUE -> true, FALSE -> false
1.46	11-Dec-2005	christos	branches: 1.46.26; merge ktrace-lwp.
1.45	25-Apr-2005	lukem	branches: 1.45.2; Move the MI printing of `copyright' to the MD cpu_startup() code where the printing of `version' is already performed. This has the benefit of allowing the copyright to be available via dmesg(8) on platforms which need the `msgbuf' to be setup in cpu_startup() before printed output is remembered.
1.44	24-Mar-2004	atatat	branches: 1.44.8; Tango on sysctl_createv() and flags. The flags have all been renamed, and sysctl_createv() now uses more arguments.
1.43	13-Feb-2004	wiz	Uppercase CPU, plural is CPUs.
1.42	30-Dec-2003	pk	Replace the traditional buffer memory management -- based on fixed per buffer virtual memory reservation and a private pool of memory pages -- by a scheme based on memory pools. This allows better utilization of memory because buffers can now be allocated with a granularity finer than the system's native page size (useful for filesystems with e.g. 1k or 2k fragment sizes). It also avoids fragmentation of virtual to physical memory mappings (due to the former fixed virtual address reservation) resulting in better utilization of MMU resources on some platforms. Finally, the scheme is more flexible by allowing run-time decisions on the amount of memory to be used for buffers. On the other hand, the effectiveness of the LRU queue for buffer recycling may be somewhat reduced compared to the traditional method since, due to the nature of the pool based memory allocation, the actual least recently used buffer may release its memory to a pool different from the one needed by a newly allocated buffer. However, this effect will kick in only if the system is under memory pressure.
1.41	13-Dec-2003	rearnsha	The machdep.debug sysctl variable uses code CPU_DEBUG (not CPU_CONSDEV).
1.40	12-Dec-2003	atatat	The machdep.debug node is an int, not a struct
1.39	04-Dec-2003	atatat	Dynamic sysctl. Gone are the old kern_sysctl(), cpu_sysctl(), hw_sysctl(), vfs_sysctl(), etc, routines, along with sysctl_int() et al. Now all nodes are registered with the tree, and nodes can be added (or removed) easily, and I/O to and from the tree is handled generically. Since the nodes are registered with the tree, the mapping from name to number (and back again) can now be discovered, instead of having to be hard coded. Adding new nodes to the tree is likewise much simpler -- the new infrastructure handles almost all the work for simple types, and just about anything else can be done with a small helper function. All existing nodes are where they were before (numerically speaking), so all existing consumers of sysctl information should notice no difference. PS - I'm sorry, but there's a distinct lack of documentation at the moment. I'm working on sysctl(3/8/9) right now, and I promise to watch out for buses.
1.38	21-Sep-2003	matt	Change some type-punning detected by gcc 3.3.1 to (void *).
1.37	15-Jul-2003	lukem	__KERNEL_RCSID()
1.36	29-Jun-2003	fvdl	branches: 1.36.2; Back out the lwp/ktrace changes. They contained a lot of colateral damage, and need to be examined and discussed more.
1.35	29-Jun-2003	ichiro	struct proc * -> struct lwp * ixp425_com: add some status flags
1.34	04-Jun-2003	simonb	Remove prototype for strtoul() that was in the wrong place.
1.33	21-May-2003	thorpej	Remove #ifdefs supporting the old pmap, switching fully to the new.
1.32	18-Apr-2003	thorpej	Add a comment indicating that the current method of enabling high vectors requires that the CPU control vector be properly readable. I believe that all CPUs that have high vector support have a readable CPU control register, but if we ever encounter one that does not, then we'll have to adjust this code.
1.31	18-Apr-2003	scw	Add the generic arm32 bits of the new pmap, contributed by Wasabi Systems. Some features of the new pmap are: - It allows L1 descriptor tables to be shared efficiently between multiple processes. A typical "maxusers 32" kernel, where NPROC is set to 532, requires 35 L1s. A "maxusers 2" kernel runs quite happily with just 4 L1s. This completely solves the problem of running out of contiguous physical memory for allocating new L1s at runtime on a busy system. - Much improved cache/TLB management "smarts". This change ripples out to encompass the low-level context switch code, which is also much smarter about when to flush the cache/TLB, and when not to. - Faster allocation of L2 page tables and associated metadata thanks, in part, to the pool_cache enhancements recently contributed to NetBSD by Wasabi Systems. - Faster VM space teardown due to accurate referenced tracking of L2 page tables. - Better/faster cache-alias tracking. The new pmap is enabled by adding options ARM32_PMAP_NEW to the kernel config file, and making the necessary changes to the port-specific initarm() function. Several ports have already been converted and will be committed shortly.
1.30	18-Apr-2003	scw	In arm32_vector_init(), if the vector page is ARM_VECTORS_HIGH, make sure the CPU_CONTROL_VECRELOC bit is set in the cpu control register before returning.
1.29	01-Apr-2003	thorpej	Use PAGE_SIZE rather than NBPG.
1.28	23-Feb-2003	thorpej	Change pcb32_pagedir to a paddr_t (after all, it's used as a paddr_t everywhere in the code).
1.27	17-Jan-2003	thorpej	Merge the nathanw_sa branch.
1.26	25-Aug-2002	thorpej	Make nbuf, nswbuf, and bufpages unsigned. Make all operations on these variables unsigned, and update places where their values are printed.
1.25	16-Aug-2002	thorpej	* Add a new machdep.powersave sysctl, which controls the use of the CPU's "sleep" function in the idle loop. * Default all CPUs to not use powersave, except for the PDA processors (SA11x0 and PXA2x0). This significantly reduces inteterrupt latency in high-performance applications (and was good to squeeze another ~10% out of an XScale IOP on a Gig-E benchmark).
1.24	05-May-2002	jdolecek	branches: 1.24.2; Update to md(4) changes: memory_disk_size is now md_root_size, and type is size_t
1.23	10-Apr-2002	thorpej	Remove the Control register handling from arm32_vector_init(). Apparently, the ARM6 and ARM7 do completely the wrong thing if you read this register, so we have to handle this a different way.
1.22	03-Apr-2002	thorpej	Clean up handling of the vector page on 32-bit ARM systems: * Don't refer to VA 0, instead refer to a new variable: vector_page * Delete the old zero_page_() functions, replacing them with a new one: vector_page_setprot(). When manipulating vector page mappings in user pmaps, only do so if the vector page is below KERNEL_BASE (if it's above KERNEL_BASE, the vector page is mapped by the kernel pmap). * Add a new function, arm32_vector_init(), which takes the virtual address of the vector page (which MUST be valid when the function is called) and a bitmask of vectors the kernel is going to take over, and performs all vector page initialization, including setting the V bit in the CPU Control register ("relocate vectors to high address"), if necessary.
1.21	02-Apr-2002	lukem	Rename MEMORY_DISK_SIZE (formerly MINIROOTSIZE) to MEMORY_DISK_ROOT_SIZE, which was suggested by Izumi Tsutsui <tsutsui@ceres.dti.ne.jp> as being more consistent with what it's controlling...
1.20	24-Mar-2002	thorpej	* arm_byte_to_page() -> arm_btop() * arm_page_to_byte() -> arm_ptob()
1.19	23-Mar-2002	thorpej	Garbage-collect the "pagehook" stuff.
1.18	23-Mar-2002	thorpej	* Rename PROCESS_PAGE_TBLS_BASE -> PTE_BASE * Rename ALT_PAGE_TBLS_BASE -> APTE_BASE * Garbage-collect PAGE_TABLE_SPACE_START
1.17	10-Mar-2002	lukem	* rename MINIROOTSIZE to MEMORY_DISK_SIZE, so that all md(4) options are now consistently named * fold opt_mdsize.h into opt_md.h
1.16	21-Feb-2002	thorpej	map_chunk() -> pmap_map_chunk(), and move it to pmap.c
1.15	20-Feb-2002	thorpej	map_pagetable() -> pmap_link_l2pt(), and move it to pmap.c
1.14	20-Feb-2002	thorpej	Collapse map_entry{,ro,nc}() into a single pmap_map_entry() that takes a prot and a "cacheable" indicator.
1.13	20-Feb-2002	thorpej	Rename map_section() to pmap_map_section(), move it to pmap.c, and give it an extra argument (prot - specifies protection of the mapping).
1.12	10-Feb-2002	reinoud	Add some extra comments for the `booted_kernel' variable.
1.11	20-Jan-2002	thorpej	Some prototype cleanup.
1.10	12-Jan-2002	chris	Make GENERIC cats kernel boot again. By allocating a 2nd second level page table for the kernel and stack space we can now have to 8MB of kernel and stacks (if the kernel ever gets really bloated might need to add a 3rd!) Also update the funcs in arm32_machdep.c that create the entries so that on cats they expect the 2 pagetables to be contiguous, note this means that for now cats is special cased in lots of funcs. I'll tidy this up to something a bit more sane soon, to avoid the multitude of #ifndef cats that I had to sprinkle in.
1.9	05-Jan-2002	chris	Make some of the arm32 files build with LOOSE_PROTOTYPES not set in the makefile. Turned up a few mismatched functions. Note that this isn't all of the arm32 files. Aim will be to get arm32 kernels built with LOOSE_PROTOTYPES not set.
1.8	23-Nov-2001	thorpej	No need to pull in <machine/pte.h> directly.
1.7	22-Nov-2001	thorpej	Kill <machine/katelib.h>. Any place that still uses it should just reference <arm/arm32/katelib.h> until such time as all use of this file has been purged from the face of the earth.
1.6	27-Oct-2001	rearnsha	branches: 1.6.2; When creating section maps, use pte_cache_mode for setting the page attributes of cacheable pages.
1.5	10-Sep-2001	chris	branches: 1.5.2; Update pmap_update to now take the updated pmap as an argument. This will allow improvements to the pmaps so that they can more easily defer expensive operations, eg tlb/cache flush, til the last possible moment. Currently this is a no-op on most platforms, so they should see no difference. Reviewed by Jason.
1.4	09-Sep-2001	toshii	Don't define pcb_* register macros. pcb_sp macro conflicts with sys/netinet6/ipsec.c.
1.3	11-Aug-2001	chris	branches: 1.3.2; Make use of pmap_kenter instead of pmap_enter for kernel buffers.
1.2	28-Jul-2001	chris	branches: 1.2.2; A couple of tidy ups to pmap: pmap_t -> struct pmap * in pmap.c and pmap.h kernel_pmap -> pmap_kernel() everywhere. Compiled and booted on riscpc and cats.
1.1	28-Jul-2001	chris	Move the generic arm32 files into arm/arm32 from arm32/arm32, tested kernel builds on cats and riscpc.
1.2.2.9	06-Sep-2002	jdolecek	sync kqueue branch with HEAD
1.2.2.8	23-Jun-2002	jdolecek	catch up with -current on kqueue branch
1.2.2.7	16-Mar-2002	jdolecek	Catch up with -current.
1.2.2.6	11-Feb-2002	jdolecek	Sync w/ -current.
1.2.2.5	10-Jan-2002	thorpej	Sync kqueue branch with -current.
1.2.2.4	13-Sep-2001	thorpej	Update the kqueue branch to HEAD.
1.2.2.3	25-Aug-2001	thorpej	Merge Aug 24 -current into the kqueue branch.
1.2.2.2	03-Aug-2001	lukem	update to -current
1.2.2.1	28-Jul-2001	lukem	file arm32_machdep.c was added on branch kqueue on 2001-08-03 04:10:57 +0000
1.3.2.1	01-Oct-2001	fvdl	Catch up with -current.
1.5.2.1	12-Nov-2001	thorpej	Sync the thorpej-mips-cache branch with -current.
1.6.2.10	27-Aug-2002	thorpej	Sync with -current.
1.6.2.9	19-Aug-2002	thorpej	Partial (ARM only) sync with trunk -- significant performance improvements for XScale-based systems.
1.6.2.8	20-Jun-2002	nathanw	Catch up to -current.
1.6.2.7	17-Apr-2002	nathanw	Catch up to -current.
1.6.2.6	01-Apr-2002	nathanw	Catch up to -current. (CVS: It's not just a program. It's an adventure!)
1.6.2.5	28-Feb-2002	nathanw	Catch up to -current.
1.6.2.4	11-Jan-2002	nathanw	More catchup.
1.6.2.3	08-Jan-2002	nathanw	Catch up to -current.
1.6.2.2	15-Nov-2001	thorpej	Machine-dependent kernel mods for scheduler activations on 32-bit ARM processors. Kernel boots multi-user on an XScale, but upcalls not yet tested.
1.6.2.1	27-Oct-2001	thorpej	file arm32_machdep.c was added on branch nathanw_sa on 2001-11-15 06:39:21 +0000
1.24.2.1	30-Aug-2002	gehenna	catch up with -current.
1.36.2.5	10-Nov-2005	skrll	Sync with HEAD. Here we go again...
1.36.2.4	21-Sep-2004	skrll	Fix the sync with head I botched.
1.36.2.3	18-Sep-2004	skrll	Sync with HEAD.
1.36.2.2	03-Aug-2004	skrll	Sync with HEAD
1.36.2.1	02-Jul-2003	wrstuden	Check in lwp-ification changes needed to get the evbarm/IQ80321 kernel to compile. only question I have is over the: l->l_proc->p_stats->p_ru.ru_msgsnd++; command at line 245 of dev/kttcp.c. Should we be doing per-lwp or per-proc accounting?
1.44.8.1	29-Apr-2005	kent	sync with -current
1.45.2.4	21-Jan-2008	yamt	sync with head
1.45.2.3	27-Oct-2007	yamt	sync with head.
1.45.2.2	03-Sep-2007	yamt	sync with head.
1.45.2.1	26-Feb-2007	yamt	sync with head.
1.46.26.3	29-Mar-2007	skrll	Adapt arm32. Thanks to scw for helping out. Tested on my cats (SA1) XXX hydra should die. i've made some changes, but no guarantees.
1.46.26.2	12-Mar-2007	rmind	Sync with HEAD.
1.46.26.1	27-Feb-2007	yamt	- sync with head. - move sched_changepri back to kern_synch.c as it doesn't know PPQ anymore.
1.48.10.2	03-Oct-2007	garbled	Sync with HEAD
1.48.10.1	22-May-2007	matt	Update to HEAD.
1.48.4.1	11-Jul-2007	mjf	Sync with head.
1.48.2.2	09-Oct-2007	ad	Sync with head.
1.48.2.1	27-May-2007	ad	Sync with head.
1.49.12.7	23-Mar-2008	matt	Restore $NetBSD$
1.49.12.6	23-Mar-2008	matt	fix typo.
1.49.12.5	23-Mar-2008	matt	sync with HEAD
1.49.12.4	09-Jan-2008	matt	sync with HEAD
1.49.12.3	06-Nov-2007	matt	sync with HEAD
1.49.12.2	29-Aug-2007	matt	Initial cpu_info_store.ci_lwp to &lwp0
1.49.12.1	28-Aug-2007	matt	Deal with want_resched move to cpu_info
1.49.10.2	20-Jan-2008	chris	Sync to HEAD.
1.49.10.1	01-Jan-2008	chris	Sync with HEAD.
1.49.8.1	02-Oct-2007	joerg	Sync with HEAD.
1.49.6.4	28-Feb-2008	rjs	Sync with HEAD.
1.49.6.3	26-Dec-2007	rjs	Sync with HEAD.
1.49.6.2	01-Nov-2007	rjs	Sync with HEAD.
1.49.6.1	06-Oct-2007	rjs	Sync with HEAD.
1.50.2.1	06-Oct-2007	yamt	sync with head.
1.52.8.2	20-Jan-2008	bouyer	Sync with HEAD
1.52.8.1	02-Jan-2008	bouyer	Sync with HEAD
1.52.4.1	26-Dec-2007	ad	Sync with head.
1.52.2.1	18-Feb-2008	mjf	Sync with HEAD.
1.55.10.4	11-Mar-2010	yamt	sync with head
1.55.10.3	19-Aug-2009	yamt	sync with head.
1.55.10.2	04-May-2009	yamt	sync with head.
1.55.10.1	16-May-2008	yamt	sync with head.
1.55.8.1	18-May-2008	yamt	sync with head.
1.55.6.4	17-Jan-2009	mjf	Sync with HEAD.
1.55.6.3	28-Sep-2008	mjf	Sync with HEAD.
1.55.6.2	02-Jul-2008	mjf	Sync with HEAD.
1.55.6.1	02-Jun-2008	mjf	Sync with HEAD.
1.56.4.1	03-Jul-2008	simonb	Sync with head.
1.56.2.1	18-Sep-2008	wrstuden	Sync with wrstuden-revivesa-base-2.
1.57.2.2	13-Dec-2008	haad	Update haad-dm branch to haad-dm-base2.
1.57.2.1	19-Oct-2008	haad	Sync with HEAD.
1.58.8.1	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.58.2.2	28-Apr-2009	skrll	Sync with HEAD.
1.58.2.1	19-Jan-2009	skrll	Sync with HEAD.
1.62.2.1	13-May-2009	jym	Sync with HEAD. Commit is split, to avoid a "too many arguments" protocol error.
1.72.2.1	30-Apr-2010	uebayasi	Sync with HEAD.
1.73.2.3	05-Mar-2011	rmind	sync with head
1.73.2.2	25-Apr-2010	rmind	A round of compile and other fixes to previous.
1.73.2.1	18-Mar-2010	rmind	Unify /dev/{mem,kmem,zero,null} implementations in MI code. Based on patch from Joerg Sonnenberger, proposed on tech-kern@, in February 2008. Work and depression still in progress.
1.74.6.1	23-Jun-2011	cherry	Catchup with rmind-uvmplock merge.
1.76.8.1	09-Aug-2012	jdc	branches: 1.76.8.1.2; Pull up revisions: src/sys/arch/evbarm/dev/plcomreg.h revisions 1.2,1.3,1.4 src/sys/arch/evbarm/conf/INTEGRATOR revision 1.65 src/sys/arch/evbarm/dev/plcom.c revisions 1.34,1.35,1.36,1.37,1.38,1.39,1.40 src/sys/arch/evbarm/ifpga/plcom_ifpga.c revisions 1.12,1.13,1.14 src/sys/arch/evbarm/dev/plcomvar.h revisions 1.9,1.10,1.11 src/sys/arch/evbarm/ifpga/plcom_ifpgavar.h revision 1.2 src/sys/arch/arm/arm/cpufunc.c revisions 1.105,1.108 src/sys/arch/arm/arm32/cpu.c revision 1.79 src/sys/arch/arm/include/armreg.h revisions 1.49,1.54 src/sys/arch/arm/arm32/pmap.c revision 1.229 src/sys/arch/arm/arm32/arm32_machdep.c revision 1.77 src/sys/arch/arm/include/cpu.h revision 1.64 src/sys/arch/arm/arm/cpufunc_asm_arm1136.S revision 1.3 src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S revision 1.1 src/sys/arch/arm/conf/files.arm revision 1.106 src/sys/arch/arm/include/cpufunc.h revision 1.57 src/sys/dev/sdmmc/sdhc.c revisions 1.14,1.24 src/sys/dev/sdmmc/sdhcvar.h revisions 1.7,1.8 src/sys/arch/evbarm/ifpga/ifpgareg.h revision 1.4 src/sys/arch/evbarm/integrator/integrator_machdep.c revision 1.69 src/sys/arch/arm/broadcom/bcm2835_dma.c revision 1.1 src/sys/arch/arm/broadcom/bcm2835_emmc.c revision 1.1 src/sys/arch/arm/broadcom/bcm2835_intr.c revision 1.1 src/sys/arch/arm/broadcom/bcm2835_intr.h revision 1.1 src/sys/arch/arm/broadcom/bcm2835_obio.c revision 1.1 src/sys/arch/arm/broadcom/bcm2835_plcom.c revision 1.1 src/sys/arch/arm/broadcom/bcm2835_pm.c revision 1.1 src/sys/arch/arm/broadcom/bcm2835_pmvar.h revision 1.1 src/sys/arch/arm/broadcom/bcm2835_space.c revision 1.1 src/sys/arch/arm/broadcom/bcm2835_tmr.c revision 1.1 src/sys/arch/arm/broadcom/bcm2835reg.h revision 1.1 src/sys/arch/arm/broadcom/bcm2835var.h revision 1.1 src/sys/arch/arm/broadcom/bcm_amba.h revision 1.1 src/sys/arch/arm/broadcom/files.bcm2835 revision 1.1 src/sys/arch/evbarm/Makefile revision 1.9 src/sys/arch/evbarm/conf/RPI revision 1.1 src/sys/arch/evbarm/conf/files.rpi revision 1.1 src/sys/arch/evbarm/conf/mk.rpi revision 1.1 src/sys/arch/evbarm/conf/std.rpi revision 1.1 src/sys/arch/evbarm/rpi/genassym.cf revision 1.1 src/sys/arch/evbarm/rpi/rpi.h revision 1.1 src/sys/arch/evbarm/rpi/rpi_machdep.c revision 1.1 src/sys/arch/evbarm/rpi/rpi_start.S revision 1.1,1.2 src/etc/etc.evbarm/Makefile.inc revision 1.28 (requested by skrll in ticket #454). don't mix #define<TAB> and #define<SPACE> in a file. avoid warning with options PLCOM_DEBUG for INTEGRATOR. Rename register values. No functional change - same code before and after. Existing names are prefixed with PL01X_ where they're common between the PL010 and the PL011. The PL010_/PL011_ prefixes are added where they're found only on the respective chips. Replace the simple_lock with a kmutex_t. Update the locking to match com(4) in the few places it didn't already. DOH. Replace a line that got accidently deleted in the last commit. device_t/softc split struct device * -> device_t struct cfdata * -> cfdata_t Add the 'Z' to the 1176 cpu product name. ok matt@ Fix locking botch introduced in 1.36. Fix a KASSERT. From/OK'ed by matt@ Fix racy softint dispatch that lead to KASSERT(si->si_active) in softint_execute Discussed with matt@. "Looks good to me" Add the documented ARM11[37]6 Auxiliary control register defines. Add support for the ARM1176JZS Add a flag for the lack of LED_ON in HOST_CTL (ti omap3 doesn't do that). Provide a method for attachments to specify capabilites. Add support for the PL011 to plcom. Pull across a bunch of fixes from com(4) while I'm here and do some other tidyup. Tested on a RaspberryPi. PL010 not tested. Initial commit of support for the RaspberryPI (www.raspberrypi.org) This is enough for serial console via the gpio header pins and to get to multiuser. A huge thank you to Matt Thomas for all his help. Add RPI to KERNEL_SETS Remove #if 0 code.
1.76.8.1.2.1	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.76.2.4	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.76.2.3	23-Jan-2013	yamt	sync with head
1.76.2.2	16-Jan-2013	yamt	sync with (a bit old) head
1.76.2.1	30-Oct-2012	yamt	sync with head
1.83.2.5	03-Dec-2017	jdolecek	update from HEAD
1.83.2.4	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.83.2.3	23-Jun-2013	tls	resync from head
1.83.2.2	25-Feb-2013	tls	resync with head
1.83.2.1	20-Nov-2012	tls	Resync to 2012-11-19 00:00:00 UTC
1.94.2.2	18-May-2014	rmind	sync with head
1.94.2.1	28-Aug-2013	rmind	sync with head
1.102.2.1	10-Aug-2014	tls	Rebase.
1.105.2.1	09-Nov-2014	martin	Pull up following revision(s) (requested by skrll in ticket #188): sys/arch/arm/include/arm32/pmap.h: revision 1.136 sys/arch/arm/include/armreg.h: revision 1.100 sys/arch/arm/cortex/gic.c: revision 1.11 sys/arch/arm/arm32/db_interface.c: revision 1.54 sys/arch/arm/include/armreg.h: revision 1.101 sys/arch/arm/cortex/gic.c: revision 1.12 sys/arch/arm/arm32/arm32_machdep.c: revision 1.107 sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.19 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.20 sys/arch/evbarm/conf/BPI: revision 1.5 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.21 sys/arch/arm/arm32/pmap.c: revision 1.306 sys/arch/arm/arm32/db_machdep.c: revision 1.22 sys/arch/arm/arm32/arm32_tlb.c: revision 1.3 sys/arch/arm/arm/undefined.c: revision 1.55 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.22 sys/arch/arm/arm32/pmap.c: revision 1.307 sys/arch/arm/arm32/arm32_tlb.c: revision 1.4 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.23 sys/arch/arm/arm32/arm32_tlb.c: revision 1.5 sys/arch/evbarm/conf/BPI: revision 1.8 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.24 sys/arch/arm/arm32/arm32_tlb.c: revision 1.6 sys/arch/arm/arm32/arm32_tlb.c: revision 1.7 sys/arch/evbarm/conf/CUBIETRUCK: revision 1.5 sys/arch/arm/pic/pic.c: revision 1.23 sys/arch/arm/pic/pic.c: revision 1.24 sys/arch/arm/pic/picvar.h: revision 1.11 sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.20 sys/arch/arm/mainbus/cpu_mainbus.c: revision 1.16 sys/arch/arm/arm32/pmap.c: revision 1.298 sys/arch/arm/arm/cpufunc_asm_arm11.S: revision 1.17 sys/arch/arm/arm/cpufunc_asm_pj4b.S: revision 1.5 sys/arch/arm/arm32/pmap.c: revision 1.310 sys/arch/arm/arm32/pmap.c: revision 1.311 sys/arch/arm/arm32/arm32_kvminit.c: revision 1.32 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.19 sys/arch/arm/arm32/arm32_boot.c: revision 1.10 sys/arch/arm/arm/ast.c: revision 1.25 sys/arch/arm/include/armreg.h: revision 1.98 sys/uvm/pmap/pmap_tlb.c: revision 1.10 sys/arch/arm/arm32/arm32_boot.c: revision 1.8 sys/arch/arm/arm32/arm32_boot.c: revision 1.9 sys/arch/arm/arm/arm_machdep.c: revision 1.43 Various ARM MP fixes.
1.108.2.4	28-Aug-2017	skrll	Sync with HEAD
1.108.2.3	05-Oct-2016	skrll	Sync with HEAD
1.108.2.2	29-May-2016	skrll	Sync with HEAD
1.108.2.1	06-Jun-2015	skrll	Sync with HEAD
1.110.2.1	26-Jul-2016	pgoyette	Sync with HEAD
1.115.4.3	21-Apr-2020	martin	Sync with HEAD
1.115.4.2	08-Apr-2020	martin	Merge changes from current as of 20200406
1.115.4.1	10-Jun-2019	christos	Sync with HEAD
1.115.2.4	26-Jan-2019	pgoyette	Sync with HEAD
1.115.2.3	18-Jan-2019	pgoyette	Synch with HEAD
1.115.2.2	20-Oct-2018	pgoyette	Sync with head
1.115.2.1	06-Sep-2018	pgoyette	Sync with HEAD Resolve a couple of conflicts (result of the uimin/uimax changes)
1.128.2.2	19-Oct-2025	martin	Pull up following revision(s) (requested by riastradh in ticket #60): sys/arch/sparc/sparc/locore.s: revision 1.287 share/man/man9/Makefile: revision 1.475 sys/arch/mips/mips/cpu_subr.c: revision 1.65 sys/arch/mips/mips/cpu_subr.c: revision 1.66 sys/arch/amd64/amd64/cpufunc.S: revision 1.70 sys/arch/hppa/hppa/support.S: revision 1.9 sys/arch/alpha/alpha/locore.s: revision 1.145 share/man/man9/paravirt_membar_sync.9: revision 1.1 sys/arch/sparc64/sparc64/locore.s: revision 1.436 distrib/sets/lists/comp/mi: revision 1.2499 sys/arch/i386/i386/cpufunc.S: revision 1.54 sys/sys/paravirt_membar.h: revision 1.1 sys/arch/arm/arm/cpu_subr.c: revision 1.6 (all via patch) paravirt_membar_sync(9): New memory barrier. For use in paravirtualized drivers which require store-before-load ordering -- irrespective of whether the kernel is built for a single processor, or whether the (virtual) machine is booted with a single processor. This is even required on architectures that don't even have a store-before-load ordering barrier, like m68k; adding, e.g., a virtio bus is _as if_ the architecture has been extended with relaxed memory ordering when talking with that new bus. Such architectures need some way to request the hypervisor enforce that ordering -- on m68k, that's done by issuing a CASL instruction, which qemu maps to an atomic r/m/w with sequential consistency ordering in the host. PR kern/59618: occasional virtio block device lock ups/hangs mips: Fix asm arch options in new paravirt_membar_sync. Need to explicitly enable mips2 (MIPS-II) instructions in order to use sync. Fixes: /tmp/ccxgOmXc.s: Assembler messages: /tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync' --- cpu_subr.o --- *** Failed target: cpu_subr.o PR kern/59618: occasional virtio block device lock ups/hangs
1.128.2.1	12-Feb-2020	martin	Pull up following revision(s) (requested by riastradh in ticket #705): sys/arch/aarch64/aarch64/aarch64_machdep.c: revision 1.35 sys/stand/efiboot/efifdt.c: revision 1.20 sys/stand/efiboot/efifdt.h: revision 1.7 sys/arch/aarch64/include/machdep.h: revision 1.9 sys/stand/efiboot/efiboot.h: revision 1.11 sys/arch/arm/arm32/arm32_machdep.c: revision 1.129 sys/arch/arm/include/arm32/machdep.h: revision 1.30 sys/stand/efiboot/exec.c: revision 1.12 sys/arch/evbarm/fdt/fdt_machdep.c: revision 1.65 sys/stand/efiboot/version: revision 1.14 sys/stand/efiboot/boot.c: revision 1.19 New function cpu_startup_hook on arm. Called at end of cpu_startup. Can be defined in, e.g., evbarm to do additional stuff after cpu_startup. Defined as a weak alias to a function that does nothing, so optional. ok jmcneill Implement rndseed support in efiboot and fdt arm. The EFI environment variable `rndseed' specifies the path to the random seed. It is loaded only for fdt platforms at the moment. Since the rndseed (an rndsave_t object as defined in <sys/rndio.h>) is 536 bytes long (for hysterical raisins), and to avoid having to erase parts of the fdt tree, we load it into a physical page whose address is passed in the fdt tree, rather than passing the content of the file as an fdt node directly; the kernel then reserves the page from uvm, and maps it into kva to call rnd_seed. For now, the only kernel that does use efiboot with fdt is evbarm, which knows to handle the rndseed. Any new kernels that use efiboot with fdt must do the same; otherwise uvm may hand out the page with the secret key on it for a normal page allocation in the kernel -- which should be OK if there are no kernel memory disclosure bugs, but would lead to worse consequences than simply loading the seed late in userland with /etc/rc.d/random_seed otherwise. ok jmcneill
1.130.2.1	29-Feb-2020	ad	Sync with head.
1.132.4.1	20-Apr-2020	bouyer	Sync with HEAD
1.138.2.1	14-Dec-2020	thorpej	Sync w/ HEAD.
1.13	20-Jun-2020	skrll	KNF #includes Remove some unnecessary ones while I'm here.
1.12	20-Jun-2020	skrll	Trailing whitespace
1.11	31-May-2018	mrg	docpureset() doesn't return anything, so mark it void. (probably could also be __dead.)
1.10	11-Nov-2015	jmcneill	branches: 1.10.16; fix RB_POWERDOWN test
1.9	11-Nov-2015	jmcneill	add support for optional RB_POWERDOWN handler
1.8	05-Jan-2015	joerg	Mark end of cpu_reboot as unreachable.
1.7	02-Jan-2015	christos	- print a warning about powerdown not supported like other ports do - merge duplicated code - if halt is requested and there is no console, keep looping instead of rebooting.
1.6	18-Aug-2013	matt	branches: 1.6.2; 1.6.6; 1.6.8; Move parts of cpu.h that are not needed by MI code in <arm/locore.h> Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h> Use <arm/asm.h> instead of <machine/arm.h>
1.5	11-May-2013	skrll	branches: 1.5.2; Move pmf_system_shutdown earlier and ensure interrupts are enabled.
1.4	05-May-2013	skrll	Sprinkle cnpollc for correct (usb) keyboard handling.
1.3	19-Jan-2013	skrll	Avoid warning from cngetc byt doing the proper cnpollc dance
1.2	05-Sep-2012	skrll	branches: 1.2.2; 1.2.4; 1.2.6; Call pmf_system_shutdown in cpu_reboot. OK matt
1.1	31-Aug-2012	matt	Make cpu_reset, most of initarm and the kvm init code common. Add MP hooks for cpu_need_resced Add idlestck which is allocated in arm32_kvminit
1.2.6.2	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.2.6.1	05-Sep-2012	matt	file arm32_reboot.c was added on branch matt-nb6-plus on 2012-11-28 22:40:17 +0000
1.2.4.4	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.2.4.3	23-Jan-2013	yamt	sync with head
1.2.4.2	30-Oct-2012	yamt	sync with head
1.2.4.1	05-Sep-2012	yamt	file arm32_reboot.c was added on branch yamt-pagecache on 2012-10-30 17:18:56 +0000
1.2.2.4	03-Dec-2017	jdolecek	update from HEAD
1.2.2.3	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.2.2.2	23-Jun-2013	tls	resync from head
1.2.2.1	25-Feb-2013	tls	resync with head
1.5.2.1	28-Aug-2013	rmind	sync with head
1.6.8.2	27-Dec-2015	skrll	Sync with HEAD (as of 26th Dec)
1.6.8.1	06-Apr-2015	skrll	Sync with HEAD
1.6.6.1	17-Jul-2015	snj	Pull up following revision(s) (requested by christos in ticket #876): sys/arch/arm/arm32/arm32_reboot.c: revisions 1.7, 1.8 - print a warning about powerdown not supported like other ports do - merge duplicated code - if halt is requested and there is no console, keep looping instead of rebooting. -- Mark end of cpu_reboot as unreachable.
1.6.2.2	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.6.2.1	18-Aug-2013	matt	file arm32_reboot.c was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
1.10.16.1	25-Jun-2018	pgoyette	Sync with HEAD
1.15	02-Oct-2021	skrll	Pass the pmap in tlb_set_asid for the benefit of aarch64.
1.14	30-Oct-2020	skrll	Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.
1.13	29-Sep-2020	jmcneill	Collapse all CPU_CORTEXA<n> options into CPU_CORTEX and do runtime detection instead of ifdefs where required.
1.12	15-Aug-2018	skrll	Sprinkle #include "opt_cputypes.h"
1.11	24-Aug-2017	jmcneill	branches: 1.11.2; 1.11.4; Do runtime detection of MP extensions to allow using a MULTIPROCESSOR kernel on CPUs without the MP extensions feature (like Cortex-A8).
1.10	11-Jul-2016	matt	Adapt to common pmap changes.
1.9	26-Mar-2015	hsuenaga	don't use armreg_tlbiasidis_write() and armreg_icialluis_write() on single processor platforms.
1.8	07-Feb-2015	jmcneill	fix CPU_CORTEXA5 && !MULTIPROCESSOR build
1.7	30-Oct-2014	skrll	branches: 1.7.2; Part of break-before-make is to dsb after the TLB invalidation. Do it in tlb_invalidate_addr
1.6	30-Oct-2014	skrll	s/0/KERNEL_PID/ isb after setting TTBCR_S_PD0 as per Example B3-5 Disable non-global mappings when changing ASID in the ARM ARM.
1.5	29-Oct-2014	skrll	Sprinkle #include "opt_multiprocessor.h"
1.4	14-Oct-2014	matt	armreg_tlbiasid_write -> armreg_tlbiasidis_write
1.3	14-Oct-2014	matt	Use tlb is variants for MULTIPROCESSOR
1.2	11-Apr-2014	matt	branches: 1.2.2; 1.2.4; 1.2.6; 1.2.8; Deal with ASID tagged VIVT icaches (not that we have any cpus with them but...)
1.1	28-Mar-2014	matt	branches: 1.1.2; Add tlb routines for pmap_tlb.c
1.1.2.1	10-Aug-2014	tls	Rebase.
1.2.8.3	03-Dec-2017	jdolecek	update from HEAD
1.2.8.2	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.2.8.1	11-Apr-2014	tls	file arm32_tlb.c was added on branch tls-maxphys on 2014-08-20 00:02:45 +0000
1.2.6.2	10-Nov-2014	martin	Revision 1.7 got somehow lost in the merge from -current
1.2.6.1	09-Nov-2014	martin	Pull up following revision(s) (requested by skrll in ticket #188): sys/arch/arm/include/arm32/pmap.h: revision 1.136 sys/arch/arm/include/armreg.h: revision 1.100 sys/arch/arm/cortex/gic.c: revision 1.11 sys/arch/arm/arm32/db_interface.c: revision 1.54 sys/arch/arm/include/armreg.h: revision 1.101 sys/arch/arm/cortex/gic.c: revision 1.12 sys/arch/arm/arm32/arm32_machdep.c: revision 1.107 sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.19 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.20 sys/arch/evbarm/conf/BPI: revision 1.5 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.21 sys/arch/arm/arm32/pmap.c: revision 1.306 sys/arch/arm/arm32/db_machdep.c: revision 1.22 sys/arch/arm/arm32/arm32_tlb.c: revision 1.3 sys/arch/arm/arm/undefined.c: revision 1.55 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.22 sys/arch/arm/arm32/pmap.c: revision 1.307 sys/arch/arm/arm32/arm32_tlb.c: revision 1.4 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.23 sys/arch/arm/arm32/arm32_tlb.c: revision 1.5 sys/arch/evbarm/conf/BPI: revision 1.8 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.24 sys/arch/arm/arm32/arm32_tlb.c: revision 1.6 sys/arch/arm/arm32/arm32_tlb.c: revision 1.7 sys/arch/evbarm/conf/CUBIETRUCK: revision 1.5 sys/arch/arm/pic/pic.c: revision 1.23 sys/arch/arm/pic/pic.c: revision 1.24 sys/arch/arm/pic/picvar.h: revision 1.11 sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.20 sys/arch/arm/mainbus/cpu_mainbus.c: revision 1.16 sys/arch/arm/arm32/pmap.c: revision 1.298 sys/arch/arm/arm/cpufunc_asm_arm11.S: revision 1.17 sys/arch/arm/arm/cpufunc_asm_pj4b.S: revision 1.5 sys/arch/arm/arm32/pmap.c: revision 1.310 sys/arch/arm/arm32/pmap.c: revision 1.311 sys/arch/arm/arm32/arm32_kvminit.c: revision 1.32 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.19 sys/arch/arm/arm32/arm32_boot.c: revision 1.10 sys/arch/arm/arm/ast.c: revision 1.25 sys/arch/arm/include/armreg.h: revision 1.98 sys/uvm/pmap/pmap_tlb.c: revision 1.10 sys/arch/arm/arm32/arm32_boot.c: revision 1.8 sys/arch/arm/arm32/arm32_boot.c: revision 1.9 sys/arch/arm/arm/arm_machdep.c: revision 1.43 Various ARM MP fixes.
1.2.4.2	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.2.4.1	11-Apr-2014	yamt	file arm32_tlb.c was added on branch yamt-pagecache on 2014-05-22 11:39:31 +0000
1.2.2.2	18-May-2014	rmind	sync with head
1.2.2.1	11-Apr-2014	rmind	file arm32_tlb.c was added on branch rmind-smpnet on 2014-05-18 17:44:56 +0000
1.7.2.3	28-Aug-2017	skrll	Sync with HEAD
1.7.2.2	05-Oct-2016	skrll	Sync with HEAD
1.7.2.1	06-Apr-2015	skrll	Sync with HEAD
1.11.4.1	10-Jun-2019	christos	Sync with HEAD
1.11.2.1	06-Sep-2018	pgoyette	Sync with HEAD Resolve a couple of conflicts (result of the uimin/uimax changes)
1.2	17-Mar-2018	ryo	move from sys/arch/arm/arm32/armv7_generic_dma.c to sys/arch/arm/arm/arm_generic_dma.c, and change variable name from armv7_generic_dma_tag to arm_generic_dma_tag no functional change. (preliminary changes for merging aarch64)
1.1	28-May-2017	jmcneill	branches: 1.1.6; 1.1.10; 1.1.12; Add a generic armv7 bus dma tag.
1.1.12.1	22-Mar-2018	pgoyette	Synch with HEAD, resolve conflicts
1.1.10.2	03-Dec-2017	jdolecek	update from HEAD
1.1.10.1	28-May-2017	jdolecek	file armv7_generic_dma.c was added on branch tls-maxphys on 2017-12-03 11:35:51 +0000
1.1.6.2	28-Aug-2017	skrll	Sync with HEAD
1.1.6.1	28-May-2017	skrll	file armv7_generic_dma.c was added on branch nick-nhusb on 2017-08-28 17:51:29 +0000
1.13	30-Oct-2020	skrll	Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.
1.12	20-Jun-2020	skrll	KNF #includes Remove some unnecessary ones while I'm here.
1.11	05-Feb-2020	skrll	Fix the armv[67] memory attributes for uncached memory. Previously it was mapped as strongly-ordered which meant that unaligned accesses would fault. armv7_generic_bs_map now maps pages with PMAP_DEV which is treated as SO bus_dma continues to use PMAP_NOCACHE as appropriate, but this now get mapped to the correct memory attribute bits for armv[67] DEVMAP_ENTRY usees a new flag PTE_DEV. The workaround for the unaligned access faults is now removed. XXX Other armv[67] boards bus_space implementations should be checked. XXX There is scope to reduce the difference to aarch64
1.10	19-Nov-2018	jmcneill	branches: 1.10.4; 1.10.6; On second thought, get rid of "bs_base" from struct bus_space and use a custom bs_map for acpipchb instead.
1.9	18-Nov-2018	jmcneill	Add a "bs_base" field to struct bus_space. If present, use it to translate mappings by appending the value to the pa passed to bus_space_map.
1.8	01-Apr-2018	ryo	branches: 1.8.2; Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@) - sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@) - add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)
1.7	16-Mar-2018	ryo	use designated initializer to make adaptability and flexibility for changing struct bus_space. no functional change.
1.6	22-Jan-2018	skrll	branches: 1.6.2; Pass PMAP_WRITE_COMBINE as appropriate in armv7_generic_bs_map, i.e. same fix as bcm283x_bs_map just got.
1.5	22-Jan-2018	skrll	Trailing whitespace
1.4	27-Nov-2017	skrll	branches: 1.4.2; KNF
1.3	01-Aug-2016	jakllsch	Add pointer to bus_space_set_region_4 implemenation in armv7_generic_bs_tag.
1.2	18-Oct-2015	jmcneill	branches: 1.2.2; mark a4x read region / write region as not implemented
1.1	29-Mar-2015	jmcneill	branches: 1.1.2; Shared armv7 bus space implementation.
1.1.2.4	05-Oct-2016	skrll	Sync with HEAD
1.1.2.3	27-Dec-2015	skrll	Sync with HEAD (as of 26th Dec)
1.1.2.2	06-Apr-2015	skrll	Sync with HEAD
1.1.2.1	29-Mar-2015	skrll	file armv7_generic_space.c was added on branch nick-nhusb on 2015-04-06 15:17:52 +0000
1.2.2.1	06-Aug-2016	pgoyette	Sync with HEAD
1.4.2.2	03-Dec-2017	jdolecek	update from HEAD
1.4.2.1	27-Nov-2017	jdolecek	file armv7_generic_space.c was added on branch tls-maxphys on 2017-12-03 11:35:51 +0000
1.6.2.3	26-Nov-2018	pgoyette	Sync with HEAD, resolve a couple of conflicts
1.6.2.2	07-Apr-2018	pgoyette	Sync with HEAD. 77 conflicts resolved - all of them $NetBSD$
1.6.2.1	22-Mar-2018	pgoyette	Synch with HEAD, resolve conflicts
1.8.2.2	08-Apr-2020	martin	Merge changes from current as of 20200406
1.8.2.1	10-Jun-2019	christos	Sync with HEAD
1.10.6.1	29-Feb-2020	ad	Sync with head.
1.10.4.1	27-Feb-2020	martin	Pull up following revision(s) (requested by skrll in ticket #742): sys/arch/arm/arm32/pmap.c: revision 1.388 sys/arch/arm/arm32/armv7_generic_space.c: revision 1.11 sys/arch/arm/arm/cpufunc.c: revision 1.176 sys/arch/arm/conf/Makefile.arm: revision 1.54 (via patch) sys/arch/arm/include/arm32/pmap.h: revision 1.161 Fix the armv[67] memory attributes for uncached memory. Previously it was mapped as strongly-ordered which meant that unaligned accesses would fault. armv7_generic_bs_map now maps pages with PMAP_DEV which is treated as SO bus_dma continues to use PMAP_NOCACHE as appropriate, but this now get mapped to the correct memory attribute bits for armv[67] DEVMAP_ENTRY usees a new flag PTE_DEV. The workaround for the unaligned access faults is now removed. XXX Other armv[67] boards bus_space implementations should be checked. XXX There is scope to reduce the difference to aarch64
1.5	21-Dec-2001	bjh21	Merge ast() and userret() between arm32 and arm26. The implementation used is the arm32 one.
1.4	29-Nov-2001	thorpej	Remove some overly-paranoid debug code that grovels too much platform-specific internals.
1.3	26-Nov-2001	thorpej	Don't include <machine/psl.h> directly.
1.2	23-Nov-2001	thorpej	Use <arm/cpufunc.h>, not <machine/cpufunc.h>.
1.1	06-Mar-2001	matt	branches: 1.1.2; 1.1.4; 1.1.6; 1.1.12; Move arm32/arm32/ast.c to arm/arm32/ast.c
1.1.12.5	28-Feb-2002	nathanw	Catch up to -current.
1.1.12.4	17-Dec-2001	nathanw	cpu_upcall() -> sa_upcall_userret().
1.1.12.3	17-Nov-2001	thorpej	Adapt to latest MI changes. Update copyright in arm_machdep.c
1.1.12.2	15-Nov-2001	thorpej	Machine-dependent kernel mods for scheduler activations on 32-bit ARM processors. Kernel boots multi-user on an XScale, but upcalls not yet tested.
1.1.12.1	06-Mar-2001	thorpej	file ast.c was added on branch nathanw_sa on 2001-11-15 06:39:21 +0000
1.1.6.1	10-Jan-2002	thorpej	Sync kqueue branch with -current.
1.1.4.1	09-Apr-2001	nathanw	Catch up with -current.
1.1.2.2	12-Mar-2001	bouyer	Sync with HEAD.
1.1.2.1	06-Mar-2001	bouyer	file ast.c was added on branch thorpej_scsipi on 2001-03-12 13:27:19 +0000
1.6	17-Aug-2013	matt	Nuke atomic.S since we have MI defined atomic ops
1.5	07-Jul-2010	chs	branches: 1.5.8; 1.5.18; 1.5.22; implement ucas_* for arm.
1.4	19-Nov-2008	matt	branches: 1.4.6; 1.4.8; Use IF32_bits instead of I32_bit
1.3	27-Apr-2008	matt	branches: 1.3.6; 1.3.8; 1.3.14; Merge kernel changes in matt-armv6 to HEAD.
1.2	13-Jan-2008	chris	branches: 1.2.6; 1.2.8; 1.2.10; When manipulating the interrupt status for atomic ops use cpsr_c rather than cpsr_all, this avoids updating unnecessary fields in the cpsr. As a side effect, the inline versions no longer clobber the condition codes.
1.1	19-Oct-2002	bsh	branches: 1.1.2; 1.1.4; 1.1.26; 1.1.74; 1.1.84; 1.1.88; 1.1.90; 1.1.96; 1.1.104; non-inline version of atomic_{set,clear}_bit(), defined when ATOMIC_SET_BIT_NONINLINE_REQUIRED is defined. (extracted from arm/arm32/locore.S)
1.1.104.1	19-Jan-2008	bouyer	Sync with HEAD
1.1.96.1	18-Feb-2008	mjf	Sync with HEAD.
1.1.90.3	23-Mar-2008	matt	sync with HEAD
1.1.90.2	28-Jan-2008	matt	Comment out armv6 atomic stubs for now.
1.1.90.1	11-Sep-2007	matt	Add atomic__32 stubs for now (until thorpej-atomic gets merged).
1.1.88.1	20-Jan-2008	chris	Sync to HEAD.
1.1.84.1	28-Feb-2008	rjs	Sync with HEAD.
1.1.74.1	19-Apr-2007	thorpej	Convert to the new atomic ops API.
1.1.26.1	21-Jan-2008	yamt	sync with head
1.1.4.2	11-Nov-2002	nathanw	Catch up to -current
1.1.4.1	19-Oct-2002	nathanw	file atomic.S was added on branch nathanw_sa on 2002-11-11 21:56:32 +0000
1.1.2.2	24-Oct-2002	bjh21	Sync with trunk.
1.1.2.1	19-Oct-2002	bjh21	file atomic.S was added on branch bjh21-hydra on 2002-10-24 22:33:45 +0000
1.2.10.3	11-Aug-2010	yamt	sync with head.
1.2.10.2	04-May-2009	yamt	sync with head.
1.2.10.1	16-May-2008	yamt	sync with head.
1.2.8.1	18-May-2008	yamt	sync with head.
1.2.6.2	17-Jan-2009	mjf	Sync with HEAD.
1.2.6.1	02-Jun-2008	mjf	Sync with HEAD.
1.3.14.1	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.3.8.1	19-Jan-2009	skrll	Sync with HEAD.
1.3.6.1	13-Dec-2008	haad	Update haad-dm branch to haad-dm-base2.
1.4.8.1	05-Mar-2011	rmind	sync with head
1.4.6.1	17-Aug-2010	uebayasi	Sync with HEAD.
1.5.22.1	28-Aug-2013	rmind	sync with head
1.5.18.1	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.5.8.1	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.10	17-Dec-2013	joerg	Write out register pairs for strd.
1.9	18-Aug-2013	matt	Move parts of cpu.h that are not needed by MI code in <arm/locore.h> Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h> Use <arm/asm.h> instead of <machine/arm.h>
1.8	11-Dec-2005	christos	branches: 1.8.98; 1.8.114; 1.8.124; 1.8.130; merge ktrace-lwp.
1.7	13-Oct-2003	scw	Xscale-optimised b{copy,zero}_page(). Contributed by Wasabi Systems.
1.6	08-Apr-2003	thorpej	branches: 1.6.2; Use PAGE_SIZE rather than NBPG.
1.5	17-Aug-2002	thorpej	More local label fixups.
1.4	15-Aug-2002	briggs	* Use local label names (.Lfoo vs. (Lfoo or foo)) * When moving from cpsr, use "cpsr" instead of "cpsr_all" (which is provided, but doesn't make sense since mrs doesn't support fields like msr does).
1.3	07-Aug-2002	thorpej	Speed up bcopy_page() on the XScale slightly by using the "pld" insn (prefetch) to look-ahead to the next chunk while we copy the current chunk. This could probably use a bit more tuning.
1.2	11-Aug-2001	chris	branches: 1.2.6; 1.2.14; Patch in Richard E's changes to bcopy page, the loop doesn't need unrolling as much as it currently is due to the overhead of the load/stores taking most of the time. (profiling shows minimal time difference)
1.1	04-Mar-2001	matt	branches: 1.1.4; 1.1.6; Move compat_13_machdep.c, strstr.c, copystr.S, bcopyinout.S, and bcopy_page.S to arm/arm32 and remove port-local copies.
1.1.6.2	06-Sep-2002	jdolecek	sync kqueue branch with HEAD
1.1.6.1	25-Aug-2001	thorpej	Merge Aug 24 -current into the kqueue branch.
1.1.4.2	12-Mar-2001	bouyer	Sync with HEAD.
1.1.4.1	04-Mar-2001	bouyer	file bcopy_page.S was added on branch thorpej_scsipi on 2001-03-12 13:27:19 +0000
1.2.14.1	30-Aug-2002	gehenna	catch up with -current.
1.2.6.3	19-Aug-2002	thorpej	Partial (ARM only) sync with trunk -- significant performance improvements for XScale-based systems.
1.2.6.2	13-Aug-2002	nathanw	Catch up to -current.
1.2.6.1	11-Aug-2001	nathanw	file bcopy_page.S was added on branch nathanw_sa on 2002-08-13 02:17:49 +0000
1.6.2.3	21-Sep-2004	skrll	Fix the sync with head I botched.
1.6.2.2	18-Sep-2004	skrll	Sync with HEAD.
1.6.2.1	03-Aug-2004	skrll	Sync with HEAD
1.8.130.2	18-May-2014	rmind	sync with head
1.8.130.1	28-Aug-2013	rmind	sync with head
1.8.124.1	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.8.114.1	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.8.98.1	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.6	11-Aug-2002	bjh21	New, improved version of copyin(), copyout(), and kcopy() by Allen Briggs. This version works on both 26-bit and 32-bit machines. For large copies, it's up to three times as fast as the old arm32 version and five times as fast as the old arm26 version. For small copies it seems to be even faster (getrusage() is apparently over ten times faster on an ARM610). Hooray for Allen!
1.5	23-Mar-2002	thorpej	branches: 1.5.2; 1.5.4; * Rename PROCESS_PAGE_TBLS_BASE -> PTE_BASE * Rename ALT_PAGE_TBLS_BASE -> APTE_BASE * Garbage-collect PAGE_TABLE_SPACE_START
1.4	03-Mar-2002	chris	Implement pmap_growkernel for arm32 based ports. Note that this has been compiled on some systems, cats, IQ80310, IPAQ, netwinder and shark (note that shark's build is currently broken due to other reasons), but only actually run on cats. Shark doesn't make use of the functionality as I believe there has to be a correlation between OFW and the kernel tables so that calls into OFW work.
1.3	20-Nov-2001	chris	Correct comment to avoid confusion, it really means 32 bits not 32 bites.
1.2	28-Sep-2001	chris	branches: 1.2.4; Note the alignment state of the stack. This is part of the work to get the stack 8byte aligned for ELF
1.1	04-Mar-2001	matt	branches: 1.1.2; 1.1.4; 1.1.6; Move compat_13_machdep.c, strstr.c, copystr.S, bcopyinout.S, and bcopy_page.S to arm/arm32 and remove port-local copies.
1.1.6.4	06-Sep-2002	jdolecek	sync kqueue branch with HEAD
1.1.6.3	23-Jun-2002	jdolecek	catch up with -current on kqueue branch
1.1.6.2	16-Mar-2002	jdolecek	Catch up with -current.
1.1.6.1	10-Jan-2002	thorpej	Sync kqueue branch with -current.
1.1.4.2	12-Mar-2001	bouyer	Sync with HEAD.
1.1.4.1	04-Mar-2001	bouyer	file bcopyinout.S was added on branch thorpej_scsipi on 2001-03-12 13:27:19 +0000
1.1.2.1	01-Oct-2001	fvdl	Catch up with -current.
1.2.4.4	13-Aug-2002	nathanw	Catch up to -current.
1.2.4.3	01-Apr-2002	nathanw	Catch up to -current. (CVS: It's not just a program. It's an adventure!)
1.2.4.2	08-Jan-2002	nathanw	Catch up to -current.
1.2.4.1	28-Sep-2001	nathanw	file bcopyinout.S was added on branch nathanw_sa on 2002-01-08 00:23:07 +0000
1.5.4.1	18-Nov-2002	he	Pull up file removal (requested by bjh21 in ticket #689): New and much improved version of copyin(), copyout(), and kcopy() which works on both 26-bit and 32-bit machines.
1.5.2.1	30-Aug-2002	gehenna	catch up with -current.
1.150	26-Sep-2025	skrll	arm: Adjust barriers issued in bus_dmamap_sync for the coherent case. PR/59654 This change adjusts the memory barriers issued by bus_dmamap_sync for the coherent case. In the non-coherent case the CPU cache operations are expected to provide any, and all required barriers. These barriers are emitted after bouncing for PREWRITE and before bouncing for POSTREAD. A new indrection is introduced to deal with the differencs in barrier (dsb) options between Arm V8 and V7, the lack of options in Arm V6, and the need to use cpu_drain_writebuf for all other earlier versions. The Arm V8 Net change is: op old new
1.149	08-Mar-2025	jmcneill	branches: 1.149.2; arm: Support BUS_DMA_NOCACHE
1.148	10-Dec-2024	msaitoh	arm/bus_dma: Sprinkle error check with __predict_{true,false}. Sprinkle error check in bus_dmamap_load*() and bus_dmamap_sync() with __predict_{true,false} to improve performance.
1.147	20-Oct-2024	skrll	Revert previous - I misread the code.
1.146	20-Oct-2024	skrll	G/C an unused event counter.
1.145	20-Oct-2024	skrll	Sync with the RISC-V version. Mostly Use PRI{u,x}{BUSSIZE,VADDR,PADDR}
1.144	28-Jul-2023	rin	branches: 1.144.6; arm/bus_dma: Fix misleading comment: - * For a virtually-indexed write-back cache, we need - * to do the following things: + * For a write-back cache, we need to do the following things: This comment was written long ago when we supported only virtually- indexed caches for arm. But subsequent comments are valid also for physically-indexed cache.
1.143	03-Apr-2023	skrll	Use PRI{u,x}{BUSSIZE,VADDR,PADDR} etc
1.142	03-Apr-2023	skrll	More KNF
1.141	03-Apr-2023	skrll	Some KNF
1.140	03-Apr-2023	skrll	spaces -> TAB
1.139	25-Feb-2023	skrll	Don't refer to physical_{start,end} here and just pass minimum (0UL) address and maximum (~0UL) physical address. The values are passed through to uvm_pglistalloc which knows about the RAM ranges.
1.138	11-Oct-2022	andvar	branches: 1.138.2; fix typos in log messages s/bus_dmamem_create/bus_dmamap_create/ and s/bus_dmamem_load/bus_dmamap_load/. Inspired by recent similar fixes in OpenBSD.
1.137	26-Jul-2022	andvar	s/functin/function/ in copy pasted comment.
1.136	24-May-2022	andvar	s/entrace/entrance/ in copy pasted comment.
1.135	06-Feb-2022	mrg	if we have to bounce a buffer, clear our anything already setup in the map before trying again. riastradh@ noticed that a map had two types of mbuf types, and this seems to avoid it as seen on eqos(4) on quartz64. add a couple more event counts for bus dma events. ok @skrll @raistradh @jmcneill XXX: pullup-8 and pullup-9 probably.
1.134	20-Dec-2021	skrll	_bus_dmatag_subregion is always EOPNOTSUPP for !_ARM32_NEED_BUS_DMA_BOUNCE No need to check {min,max}_addr. Compiler did the right thing, but...
1.133	30-Aug-2021	jmcneill	Add storage for an iommu cookie in bus_dmamap_t and store untranslated CPU address in bus_dma_segment_t.
1.132	07-Feb-2021	skrll	Check for programming errors in _bus_dmamap_load_buffer
1.131	07-Feb-2021	skrll	pretty print
1.130	07-Feb-2021	skrll	Consistently use %#x, etc
1.129	22-Dec-2020	skrll	Count bus_dmamap_sync events for coherent ranges and non-coherent ranges
1.128	20-Dec-2020	jmcneill	style fix
1.127	19-Dec-2020	jmcneill	No need to allocate bounce buffers if we have a single range that covers all of physical memory.
1.126	04-Dec-2020	skrll	Use __func__ in panic calls (and misc style changes)
1.125	04-Dec-2020	skrll	Update stats in the coherent case. Reported by jmcneill.
1.124	24-Oct-2020	skrll	branches: 1.124.2; Fix the logic around "parent is a subset and can be re-used" in bus_dmatag_subregion. Thanks to mrg@ for spotting the problem.
1.123	08-Sep-2020	skrll	A few bus_dmatag_subregion fixes - return EOPNOTSUPP if min_addr isn't less than max_addr - fix the subset check to ensure that all the ranges in the parent tag are within the {min,max}_addr range. If so we can just continue to use the parent tag. - when building the new ranges read the parent tag range rather than un- initialised memory. - remove the max_addr != 0xffffffff check - the overflow should be handled by the unsigned arithmetic for arm32. - add a KASSERT - add comments
1.122	20-Jun-2020	skrll	KNF #includes Remove some unnecessary ones while I'm here.
1.121	14-Mar-2020	ad	- Hide the details of SPCF_SHOULDYIELD and related behind a couple of small functions: preempt_point() and preempt_needed(). - preempt(): if the LWP has exceeded its timeslice in kernel, strip it of any priority boost gained earlier from blocking.
1.120	22-Feb-2020	skrll	Fix previous for _ARM32_NEED_BUS_DMA_BOUNCE
1.119	21-Feb-2020	maya	Make sure to convey a failure to the calling function Likely fix for PR kern/54999, but that was a one-off panic.
1.118	05-Nov-2019	jmcneill	branches: 1.118.2; Do not try to use direct map for prefetchable mappings
1.117	05-Nov-2019	jmcneill	bus_dmamem_map: honour BUS_DMA_PREFETCHABLE hint
1.116	24-Aug-2019	jmcneill	bus_dmamap_load_raw: support coherent mappings bus_dmamap_sync: support syncing "raw" buffer types
1.115	14-Jun-2019	skrll	branches: 1.115.2; Simplify the _ARM32_NEED_BUS_DMA_BOUNCE #ifdefs and rely on compiler optimisation of the bouncing = false case. Drain the write buf (aka DSB) in more cases Catch all CPUs that support speculation. (thunderx isn't CPU_CORTEX)
1.114	08-Jun-2019	skrll	Fix comment
1.113	14-Sep-2018	skrll	Fix BUS_DMASYNC_PREREAD\|BUS_DMASYNC_PREWRITE for aarch64. The readonly mbuf optimisation is for the old arm pmap.
1.112	03-Sep-2018	riastradh	Rename min/max -> uimin/uimax for better honesty. These functions are defined on unsigned int. The generic name min/max should not silently truncate to 32 bits on 64-bit systems. This is purely a name change -- no functional change intended. HOWEVER! Some subsystems have #define min(a, b) ((a) < (b) ? (a) : (b)) #define max(a, b) ((a) > (b) ? (a) : (b)) even though our standard name for that is MIN/MAX. Although these may invite multiple evaluation bugs, these do _not_ cause integer truncation. To avoid `fixing' these cases, I first changed the name in libkern, and then compile-tested every file where min/max occurred in order to confirm that it failed -- and thus confirm that nothing shadowed min/max -- before changing it. I have left a handful of bootloaders that are too annoying to compile-test, and some dead code: cobalt ews4800mips hp300 hppa ia64 luna68k vax acorn32/if_ie.c (not included in any kernels) macppc/if_gm.c (superseded by gem(4)) It should be easy to fix the fallout once identified -- this way of doing things fails safe, and the goal here, after all, is to _avoid_ silent integer truncations, not introduce them. Maybe one day we can reintroduce min/max as type-generic things that never silently truncate. But we should avoid doing that for a while, so that existing code has a chance to be detected by the compiler for conversion to uimin/uimax without changing the semantics until we can properly audit it all. (Who knows, maybe in some cases integer truncation is actually intended!)
1.111	17-Jul-2018	christos	use unintmax_t instead of u_quad_t.
1.110	17-Jul-2018	martin	Revert previous and cast to u_quad_t instead (t is for ptrdiff_t and off_t does not match that on all arm)
1.109	16-Jul-2018	christos	fix incorrect printf format (off_t needs t)
1.108	27-Apr-2018	maxv	branches: 1.108.2; M_CLUSTER -> M_EXT_CLUSTER
1.107	01-Apr-2018	ryo	Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@) - sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@) - add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)
1.106	04-Mar-2018	skrll	branches: 1.106.2; Less ifdefs -> more readable. NFC intended
1.105	03-Mar-2018	skrll	Style
1.104	03-Mar-2018	skrll	Rely on the cache operations to perform the necessary barriers.
1.103	03-Mar-2018	skrll	Wrap some long lines
1.102	03-Mar-2018	skrll	Remove unnecessary includes
1.101	29-Dec-2017	skrll	More KNF
1.100	29-Dec-2017	skrll	KNF cvS: ----------------------------------------------------------------------
1.99	03-Nov-2017	skrll	Fix a comment
1.98	05-Jan-2017	msaitoh	branches: 1.98.8; Update the dmamp argument only when the allocation succeeded.
1.97	23-Dec-2016	cherry	"Make NetBSD great again!" Introduce uvm_hotplug(9) to the kernel. Many thanks, in no particular order to: TNF, for funding the project. Chuck Silvers - for multiple API reviews and feedback. Nick Hudson - for testing on multiple architectures and bugfix patches. Everyone who helped with boot testing. KeK (http://www.kek.org.in) for hosting the primary developers.
1.96	05-Nov-2016	skrll	Also return early from _bus_dmamap_sync if we're not bouncing and there are no {pre,post} ops Now the KASSERT doesn't fire on cats
1.95	18-Jun-2016	skrll	branches: 1.95.2; Trailing whitespace.
1.94	18-Oct-2015	jmcneill	implement _bus_dmamap_load_raw, ok skrll@
1.93	24-Aug-2015	matt	Fix mbuf dmasyncing for extended MMU kernels.
1.92	21-Aug-2015	matt	Assert we aren't trying to sync a read-only mbuf as PREREAD.
1.91	25-Feb-2015	joerg	Improve inline asm around dsb/dmb/isb: - always use volatile and mark them as memory barrier - use the common version from locore.h in all places not included from userland
1.90	12-Feb-2015	joerg	Kill redundant semicolons.
1.89	09-Nov-2014	skrll	branches: 1.89.2; Post a dmb before invalidating the cache in the post-{read,write} operations to ensure that any/all cachelines brought in via speculation are really flushed.
1.88	18-Oct-2014	snj	src is too big these days to tolerate superfluous apostrophes. It's "its", people!
1.87	08-Sep-2014	matt	With PMAP_NEED_ALLOC_POOLPAGE, before using pmap_map_poolpage make sure the page comes from the same freelist that pmap_map_poolpage uses.
1.86	10-Apr-2014	matt	branches: 1.86.2; Deal with non-4KB pages properly.
1.85	06-Apr-2014	skrll	Remove a comment that became largely redundant with the PMAP_NOCACHE change.
1.84	02-Apr-2014	matt	branches: 1.84.2; Deal with bus_dmamem_unmap of direct mapped KVA.
1.83	24-Mar-2014	christos	use cpu_{g,s}etmodel
1.82	26-Feb-2014	skrll	Fix off by one in _bus_dma_{paddr_inrange,_to_paddr} when checking the dma range.
1.81	26-Feb-2014	matt	Use kmem instead of malloc. Fix various corner cases with bounce buffers. Use PMAP_NOCACHE instead of manipulating PTEs directly.
1.80	18-Feb-2013	matt	branches: 1.80.2; Disable when using extended MMU support.
1.79	16-Feb-2013	matt	Use KASSERT* in preference to #ifdef DIAGNOSTIC / panic
1.78	15-Feb-2013	matt	Actually use the calculated uboundary.
1.77	14-Feb-2013	matt	Make sync counters only count when caches ops are performed.
1.76	14-Feb-2013	matt	Rework counters. Get rid of a badly done goto. Properly deal with boundary in bus_dmamem_alloc_range.
1.75	14-Feb-2013	matt	fix writebuf draining fix.
1.74	13-Feb-2013	matt	bounce buffer fixes + convert some kassert -> kassertmsg
1.73	04-Feb-2013	macallan	support BUS_DMA_PREFETCHABLE in bus_dmamem_mmap()
1.72	28-Jan-2013	skrll	Move and tweak an #if 0 printf
1.71	27-Jan-2013	matt	Get rid of _BUS_DMAMAP_MEM_XLATE
1.70	27-Jan-2013	matt	Add a _BUS_DMAMAP_NOALLOC which tells bus_dmamem_alloc to skip that dmarange when allocating memory. Add a second dmarange to bcm23xx obio to allow it to map coherently mapped memory.
1.69	27-Jan-2013	matt	Make _BUS_DMAMAP_MEM_XLATE supplied by the caller.
1.68	27-Jan-2013	matt	Add a flag to make bus_dmamem_map use the bus/sys transation table when mapping bus addresses. Make bcm2835 obio use it.
1.67	16-Jan-2013	matt	On Cortex, speculative loads can cache lines to be populated after then they've been invalidated for a DMA read. So after the DMA read we have to reinvalidate them again. We have to both invalidates since the former prevents dirty lines overwriting just DMAed data.
1.66	23-Oct-2012	skrll	Correct inverted boolean logic for the coherent flag introduced in r1.61 Fixes slow nfs seen by msaitoh@
1.65	22-Oct-2012	matt	Only call cpu_{,s}dcache_inv_range if len > 0
1.64	21-Oct-2012	matt	Use right flag name for bus_dmamem_map (fixes usb on BCM53xx).
1.63	19-Oct-2012	matt	Make IS_BOUNCING a map flag and use it to simplify code and to avoid calling the sync routines if (COHERENT\|IS_BOUNCING) == COHERENT. (this eeks out a little bit more performance).
1.62	19-Oct-2012	matt	Make bus_dmamem_map aware of coherent dma regions. Also, take advantage of the use/existance of PMAP_MAP_POOLPAGE to avoid redundant mappings.
1.61	17-Oct-2012	matt	Add per-segment and per-ragne flag (to store _BUS_DMAMAP_COHERENT). Use the per-range flag to set the per-segment flag. This allows bus_dma to skip flushing for known coherent memory regions.
1.60	06-Oct-2012	matt	Fix a cut&paste error with supersections.
1.59	22-Sep-2012	matt	Add busaddr to paddr routine and use it. cleanup the PREREAD sync case.
1.58	18-Sep-2012	matt	Add bounce buffer support for ARM bus_dma(9). Add macros to help initialize bus_dma_tag structures.
1.57	11-Sep-2012	matt	branches: 1.57.2; Rework dmasync routines so that secondary caches can be flushed as well as the primary caches.
1.56	02-Sep-2012	matt	Supersections are on armv6 too.
1.55	02-Sep-2012	matt	Make bus_dma understand supersections.
1.54	01-Jul-2011	dyoung	branches: 1.54.2; 1.54.10; #include <sys/bus.h> instead of <machine/bus.h>.
1.53	06-Nov-2010	uebayasi	Machine dependent code is considered as part of UVM. Include internal API header.
1.52	04-Jun-2008	ad	branches: 1.52.16; 1.52.18; 1.52.20; vm_page: put TAILQ_ENTRY into a union with LIST_ENTRY, so we can use both.
1.51	28-Apr-2008	martin	branches: 1.51.2; Remove clause 3 and 4 from TNF licenses
1.50	04-Mar-2007	christos	branches: 1.50.42; 1.50.44; 1.50.46; Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.
1.49	10-Apr-2006	simonb	branches: 1.49.14; Unwrap a not-too-long-line.
1.48	01-Mar-2006	yamt	branches: 1.48.2; 1.48.4; 1.48.6; merge yamt-uio_vmspace branch. - use vmspace rather than proc or lwp where appropriate. the latter is more natural to specify an address space. (and less likely to be abused for random purposes.) - fix a swdmover race.
1.47	24-Dec-2005	perry	branches: 1.47.2; 1.47.4; 1.47.6; Remove leading __ from __(const\|inline\|signed\|volatile) -- it is obsolete.
1.46	11-Dec-2005	christos	merge ktrace-lwp.
1.45	24-Nov-2005	yamt	bus_dmamem_map: honour BUS_DMA_NOWAIT. noted by Manuel Bouyer. bus_space_map: always do NOWAIT allocation as it used to be before yamt-km. we have too many copies!
1.44	01-Apr-2005	yamt	branches: 1.44.2; 1.44.8; merge yamt-km branch. - don't use managed mappings/backing objects for wired memory allocations. save some resources like pv_entry. also fix (most of) PR/27030. - simplify kernel memory management API. - simplify pmap bootstrap of some ports. - some related cleanups.
1.43	09-Mar-2005	matt	Add a dm_maxsegsz public member to bus_dmamap_t. This allows a user of the API to select the maximum segment size for each bus_dmamap_load (up to the maxsegsz supplied to bus_dmamap_create). dm_maxsegsz is reset to the value supplied to bus_dmamap_create when the dmamap is unloaded.
1.42	02-Jan-2005	chris	branches: 1.42.2; 1.42.4; Remove direct references to TAILQ internal structures. No functional change, just tidying up code.
1.41	28-Nov-2004	thorpej	Sync with i386 bus_dma.
1.40	06-Oct-2004	scw	Apply patch provided by Hiroki Nakano in PR kern/27159 to fix compilation with DEBUG_DMA defined.
1.39	19-Jun-2004	thorpej	Merge x86/bus_dma.c 1.11 by yamt: Simplify bus_dma internal "load" functions by eliminating the "first" variable, using seg == -1 instead.
1.38	30-Oct-2003	scw	In bus_dmamap_sync(), we can no longer rely on the data cache being flushed on every context switch as an indicator that a mapping is not resident in the cache. Instead, used the per-pmap flag maintained by the cpu_switch/pmap code.
1.37	29-Oct-2003	mycroft	If something goes wrong, we want to return ENOMEM, not 0!
1.36	26-Oct-2003	chris	Fix up some unitialised variables.
1.35	06-Sep-2003	rearnsha	Make sure _ARM32_BUS_DMA_PRIVATE is defined before we pull in any include files to avoid problems with the rats nest of dependencies.
1.34	24-Jul-2003	briggs	Clear ARM32_DMAMAP_COHERENT in _bus_dmamap_load_buffer for userspace mappings.
1.33	15-Jul-2003	lukem	__KERNEL_RCSID()
1.32	29-Jun-2003	fvdl	branches: 1.32.2; Back out the lwp/ktrace changes. They contained a lot of colateral damage, and need to be examined and discussed more.
1.31	28-Jun-2003	darrenr	Pass lwp pointers throughtout the kernel, as required, so that the lwpid can be inserted into ktrace records. The general change has been to replace "struct proc " with "struct lwp " in various function prototypes, pass the lwp through and use l_proc to get the process pointer when needed. Bump the kernel rev up to 1.6V
1.30	21-May-2003	thorpej	Remove #ifdefs supporting the old pmap, switching fully to the new.
1.29	18-Apr-2003	scw	Add the generic arm32 bits of the new pmap, contributed by Wasabi Systems. Some features of the new pmap are: - It allows L1 descriptor tables to be shared efficiently between multiple processes. A typical "maxusers 32" kernel, where NPROC is set to 532, requires 35 L1s. A "maxusers 2" kernel runs quite happily with just 4 L1s. This completely solves the problem of running out of contiguous physical memory for allocating new L1s at runtime on a busy system. - Much improved cache/TLB management "smarts". This change ripples out to encompass the low-level context switch code, which is also much smarter about when to flush the cache/TLB, and when not to. - Faster allocation of L2 page tables and associated metadata thanks, in part, to the pool_cache enhancements recently contributed to NetBSD by Wasabi Systems. - Faster VM space teardown due to accurate referenced tracking of L2 page tables. - Better/faster cache-alias tracking. The new pmap is enabled by adding options ARM32_PMAP_NEW to the kernel config file, and making the necessary changes to the port-specific initarm() function. Several ports have already been converted and will be committed shortly.
1.28	09-Apr-2003	thorpej	Use cached physical addresses for mbufs and clusters to save having to extract the physical address from the virtual. On the ARM, also use the "read-only at MMU" indication to avoid a redundant cache clean operation. Other platforms should use these two as examples of how to use these new pool/mbuf features to improve network performance. Note this requires a platform to provide a working POOL_VTOPHYS(). Part 3 in a series of simple patches contributed by Wasabi Systems to improve network performance.
1.27	01-Apr-2003	thorpej	Use PAGE_SIZE rather than NBPG.
1.26	27-Mar-2003	mycroft	Remove references to variables that aren't used here.
1.25	03-Feb-2003	chris	bus dma memory is allocated as M_DMAMAP so free it as M_DMAMAP, not DEVBUF.
1.24	02-Feb-2003	wiz	guarantee, not guarentee. Idea from miod@openbsd.
1.23	17-Jan-2003	thorpej	Merge the nathanw_sa branch.
1.22	25-Sep-2002	thorpej	Don't include <sys/map.h>.
1.21	22-Aug-2002	thorpej	* Add PTE_SYNC() and PTE_SYNC_RANGE() macros. These don't actually do anything yet. * Use PTE_SYNC() and PTE_SYNC_RANGE() in some obvious places, i.e. where vtopte() is used.
1.20	17-Aug-2002	briggs	Do not trim 'offset' from 'len' in _bus_dmamap_sync_linear().
1.19	17-Aug-2002	briggs	Inline bus_dma_inrange() and bus_dmamap_sync_*().
1.18	14-Aug-2002	thorpej	When doing PREREAD sync operations, if the start and end addresses of the range are aligned to a cacheline boundary, when do a dcache-inv operation, rather than a dcache-wbinv operation. XXX It could be a little smarter (align using wbinv, inv, then finish up using wbinv), but even this simple change is good for a nearly 40% improvement in my test case on XScale.
1.17	14-Aug-2002	thorpej	* Add an ARM32_DMAMAP_COHERENT flag to indicate that a loaded DMA map contains "coherent" (non-cached in ARM-land) mappings. * Set ARM32_DMAMAP_COHERENT in the map at the start of a load operation, and clear it in _bus_dmamap_load_buffer() if we encounter any cacheable mappings. * In _bus_dmamap_sync(), if the map is marked COHERENT, skip any cache flushing.
1.16	14-Aug-2002	thorpej	Whe making a mapping "coherent", clear ALL the cache bits, not just L2_B and L2_C.
1.15	31-Jul-2002	thorpej	Overhaul how DMA ranges work in the ARM bus_dma implementation. A new "arm32_dma_range" structure now describes a DMA window, with a system address base, bus address base, and length. In addition to providing info about which memory regions are legal for DMA, the new structure provides address translation support, as well. As before, if a tag does not list any ranges, then all addresses are considered valid, and no DMA address translation is performed. This allows us to remove a large chunk of code which was duplicated and tweaked slightly (to do the address translation) from the stock ARM bus_dma in the XScale IOP and ARM Integrator ports. Test compiled on all ARM platforms, test booted on Intel IQ80321 and Shark.
1.14	28-Jul-2002	thorpej	Change the way that DMA map syncs are done. Instead of remembering the virtual address for each DMA segment, just cache a pointer to the original buffer/buftype used to load the DMA map, and use that. This lets us shrink the bus_dma_segment_t down from 12 bytes to 8, and the cache flushing is also more efficient. Tested on an i80321 -- changes to others are mechanical.
1.13	28-Jun-2002	briggs	Remove complaint: bus_dmamap_destroy() called for map with valid mappings bus_dma(9) states: "In the event that the DMA handle contains a valid mapping, the mapping will be unloaded via the same mechanism used by bus_dmamap_unload()." And some drivers do mean to skip the unload step.
1.12	02-Jun-2002	drochner	move initialization of the "struct pglist" returned by uvm_pglistalloc() from the calling code into uvm_pglistalloc() itself for consistency and easier error handling
1.11	10-Apr-2002	thorpej	branches: 1.11.2; 1.11.4; vm_offset_t -> vaddr_t,paddr_t
1.10	05-Apr-2002	thorpej	* Rewrite the 32-bit ARM pte.h based on the ARM architecture manual. Significant cleanup, here, including better PTE bit names. * Add XScale PTE extensions (ECC enable, write-allocate cache mode). * Mechanical changes everywhere else to update for new pte.h. While doing this, two bugs (as a result of typos) were fixed in arm/arm32/bus_dma.c evbarm/integrator/int_bus_dma.c
1.9	24-Mar-2002	thorpej	* arm_byte_to_page() -> arm_btop() * arm_page_to_byte() -> arm_ptob()
1.8	25-Jan-2002	thorpej	Overhaul bus_dmamap_sync for the ARM: * Track which process (XXX really, vmspace) owns the mapping. When we sync the map, if the mapping doesn't belong to the kernel or to the current process (XXX really, vmspace), then no cache fobbing is necessary, since the cache is Wb-Inv'd on context switch (XXX need to revisit this when we support FCSE). * Be smarter about which cache operation we do when sync'ing the map: - PREREAD -- Invalidate D$ (XXX right now, we actually do Wb-Inv) - PREWRITE -- Write-back D$ (note, we do NOT invalidate here) - PREREAD\|PREWRITE -- Wb-Inv D$ More work is needed here. In particular, a version for CPUs with write-through caches should be provided, to eliminate the write-back steps (which are noops on such CPUs, but skipping two branches would be nice).
1.7	25-Jan-2002	thorpej	ANSI'ify function decls.
1.6	25-Jan-2002	thorpej	Overhaul of the ARM cache code. This is mostly a simplification pass. Rather than providing a whole slew of cache operations that aren't ever used, distill them down to some useful primitives: icache_sync_all Synchronize I-cache icache_sync_range Synchronize I-cache range dcache_wbinv_all Write-back and Invalidate D-cache dcache_wbinv_range Write-back and Invalidate D-cache range dcache_inv_range Invalidate D-cache range dcache_wb_range Write-back D-cache range idcache_wbinv_all Write-back and Invalidate D-cache, Invalidate I-cache idcache_wbinv_range Write-back and Invalidate D-cache, Invalidate I-cache range Note: This does not yet include an overhaul of the actual asm files that implement the primitives. Instead, we've provided a safe default for each CPU type, and the individual CPU types can now be optimized one at a time.
1.5	26-Nov-2001	thorpej	Don't include <machine/psl.h> directly.
1.4	23-Nov-2001	thorpej	Use <arm/cpufunc.h>, not <machine/cpufunc.h>.
1.3	12-Sep-2001	rearnsha	branches: 1.3.4; Fix warning errors for printing size_t types when compiling with DEBUG_DMA (uses casts due to a.out and ELF having different base types for size_t).
1.2	10-Sep-2001	chris	Update pmap_update to now take the updated pmap as an argument. This will allow improvements to the pmaps so that they can more easily defer expensive operations, eg tlb/cache flush, til the last possible moment. Currently this is a no-op on most platforms, so they should see no difference. Reviewed by Jason.
1.1	28-Jul-2001	chris	branches: 1.1.2; 1.1.4; Move the generic arm32 files into arm/arm32 from arm32/arm32, tested kernel builds on cats and riscpc.
1.1.4.1	01-Oct-2001	fvdl	Catch up with -current.
1.1.2.8	10-Oct-2002	jdolecek	sync kqueue with -current; this includes merge of gehenna-devsw branch, merge of i386 MP branch, and part of autoconf rototil work
1.1.2.7	06-Sep-2002	jdolecek	sync kqueue branch with HEAD
1.1.2.6	23-Jun-2002	jdolecek	catch up with -current on kqueue branch
1.1.2.5	11-Feb-2002	jdolecek	Sync w/ -current.
1.1.2.4	10-Jan-2002	thorpej	Sync kqueue branch with -current.
1.1.2.3	13-Sep-2001	thorpej	Update the kqueue branch to HEAD.
1.1.2.2	03-Aug-2001	lukem	update to -current
1.1.2.1	28-Jul-2001	lukem	file bus_dma.c was added on branch kqueue on 2001-08-03 04:10:57 +0000
1.3.4.12	18-Oct-2002	nathanw	Catch up to -current.
1.3.4.11	27-Aug-2002	thorpej	Sync with -current.
1.3.4.10	19-Aug-2002	thorpej	Partial (ARM only) sync with trunk -- significant performance improvements for XScale-based systems.
1.3.4.9	01-Aug-2002	nathanw	Catch up to -current.
1.3.4.8	24-Jun-2002	nathanw	Curproc->curlwp renaming. Change uses of "curproc->l_proc" back to "curproc", which is more like the original use. Bare uses of "curproc" are now "curlwp". "curproc" is now #defined in proc.h as ((curlwp) ? (curlwp)->l_proc) : NULL) so that it is always safe to reference curproc (dereferencing curproc is another story, but that's always been true).
1.3.4.7	20-Jun-2002	nathanw	Catch up to -current.
1.3.4.6	17-Apr-2002	nathanw	Catch up to -current.
1.3.4.5	11-Apr-2002	thorpej	Make this compile again. XXX Need to re-think this.
1.3.4.4	01-Apr-2002	nathanw	Catch up to -current. (CVS: It's not just a program. It's an adventure!)
1.3.4.3	28-Feb-2002	nathanw	Catch up to -current.
1.3.4.2	08-Jan-2002	nathanw	Catch up to -current.
1.3.4.1	12-Sep-2001	nathanw	file bus_dma.c was added on branch nathanw_sa on 2002-01-08 00:23:07 +0000
1.11.4.2	07-Dec-2002	he	Pull up revision 1.16 (requested by thorpej in ticket #678): When making a mapping ``coherent'', clear all the cacche bits, not just L2_B and L2_C.
1.11.4.1	07-Dec-2002	he	Pull up revisions 1.13-1.14 (requested by thorpej in ticket #568): Remove warning from bus_dmamap_destroy(). Change the way DMA map syncs are done. Instead of remembering the virtual address for each DMA segment, just cache a pointer to the original buffer/buftype used to load the DMA map, and use that. Shrinks bus_dma_segment_t from 12 to 8 bytes, and the cache flushing is also more efficient.
1.11.2.3	30-Aug-2002	gehenna	catch up with -current.
1.11.2.2	16-Jul-2002	gehenna	catch up with -current.
1.11.2.1	14-Jul-2002	gehenna	catch up with -current.
1.32.2.10	11-Dec-2005	christos	Sync with head.
1.32.2.9	01-Apr-2005	skrll	Sync with HEAD.
1.32.2.8	19-Feb-2005	skrll	Don't deref a NULL struct lwp *. This shouldn't happen, but...
1.32.2.7	17-Jan-2005	skrll	Sync with HEAD.
1.32.2.6	18-Dec-2004	skrll	Sync with HEAD.
1.32.2.5	19-Oct-2004	skrll	Sync with HEAD
1.32.2.4	21-Sep-2004	skrll	Fix the sync with head I botched.
1.32.2.3	18-Sep-2004	skrll	Sync with HEAD.
1.32.2.2	03-Aug-2004	skrll	Sync with HEAD
1.32.2.1	02-Jul-2003	darrenr	Apply the aborted ktrace-lwp changes to a specific branch. This is just for others to review, I'm concerned that patch fuziness may have resulted in some errant code being generated but I'll look at that later by comparing the diff from the base to the branch with the file I attempt to apply to it. This will, at the very least, put the changes in a better context for others to review them and attempt to tinker with removing passing of 'struct lwp' through the kernel.
1.42.4.2	19-Mar-2005	yamt	sync with head. xen and whitespace. xen part is not finished.
1.42.4.1	28-Jan-2005	yamt	convert arch/arm to new apis.
1.42.2.1	29-Apr-2005	kent	sync with -current
1.44.8.1	29-Nov-2005	yamt	sync with head.
1.44.2.2	03-Sep-2007	yamt	sync with head.
1.44.2.1	21-Jun-2006	yamt	sync with head.
1.47.6.1	22-Apr-2006	simonb	Sync with head.
1.47.4.1	09-Sep-2006	rpaulo	sync with head
1.47.2.2	18-Feb-2006	yamt	keep vmspace rather than proc in bus_dmamap_t.
1.47.2.1	18-Feb-2006	yamt	adapt bus_dma implementations.
1.48.6.1	24-May-2006	tron	Merge 2006-05-24 NetBSD-current into the "peter-altq" branch.
1.48.4.1	19-Apr-2006	elad	sync with head - hopefully this will work
1.48.2.1	11-Apr-2006	yamt	sync with head
1.49.14.1	12-Mar-2007	rmind	Sync with HEAD.
1.50.46.2	04-May-2009	yamt	sync with head.
1.50.46.1	16-May-2008	yamt	sync with head.
1.50.44.2	17-Jun-2008	yamt	sync with head.
1.50.44.1	18-May-2008	yamt	sync with head.
1.50.42.2	05-Jun-2008	mjf	Sync with HEAD. Also fix build.
1.50.42.1	02-Jun-2008	mjf	Sync with HEAD.
1.51.2.1	23-Jun-2008	wrstuden	Sync w/ -current. 34 merge conflicts to follow.
1.52.20.1	05-Mar-2011	rmind	sync with head
1.52.18.1	08-Jul-2010	uebayasi	Fix build.
1.52.16.1	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.54.10.6	15-Feb-2013	matt	Actually use the calculated uboundary
1.54.10.5	14-Feb-2013	matt	Sync with HEAD.
1.54.10.4	14-Feb-2013	matt	Sync with HEAD
1.54.10.3	14-Feb-2013	matt	sync with HEAD
1.54.10.2	16-Jan-2013	matt	Pullup from HEAD: On Cortex, speculative loads can cache lines to be populated after then they've been invalidated for a DMA read. So after the DMA read we have to reinvalidate them again. We have to both invalidates since the former prevents dirty lines overwriting just DMAed data.
1.54.10.1	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.54.2.3	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.54.2.2	23-Jan-2013	yamt	sync with head
1.54.2.1	30-Oct-2012	yamt	sync with head
1.57.2.4	03-Dec-2017	jdolecek	update from HEAD
1.57.2.3	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.57.2.2	25-Feb-2013	tls	resync with head
1.57.2.1	20-Nov-2012	tls	Resync to 2012-11-19 00:00:00 UTC
1.80.2.1	18-May-2014	rmind	sync with head
1.84.2.1	10-Aug-2014	tls	Rebase.
1.86.2.3	27-May-2015	msaitoh	Pull up following revision(s) (requested by skrll in ticket #805): sys/arch/arm/include/arm32/pmap.h: revision 1.138 sys/arch/arm/arm/cpufunc.c: revision 1.151 sys/arch/arm/arm32/bus_dma.c: revision 1.90 sys/arch/arm/broadcom/bcm53xx_pax.c: revision 1.14 sys/arch/arm/arm32/bus_dma.c: revision 1.91 sys/arch/arm/samsung/exynos_space.c: revision 1.2 sys/arch/arm/arm32/db_machdep.c: revision 1.23 sys/arch/arm/allwinner/awin_space.c: revision 1.4 sys/arch/arm/include/rwlock.h: revision 1.9 sys/arch/arm/amlogic/amlogic_space.c: revision 1.2 sys/arch/arm/zynq/zynq_space.c: revision 1.2 sys/arch/arm/broadcom/bcm2835_space.c: revision 1.7 sys/arch/arm/arm32/pmap.c: revision 1.317 sys/arch/arm/include/locore.h: revision 1.19 sys/arch/arm/include/mutex.h: revision 1.20 sys/arch/arm/include/lock.h: revision 1.31 sys/arch/arm/include/lock.h: revision 1.32 sys/arch/arm/broadcom/bcmgen_space.c: revision 1.5 - Kill redundant semicolons. - Indentation. - Improve inline asm around dsb/dmb/isb: - always use volatile and mark them as memory barrier - use the common version from locore.h in all places not included from userland
1.86.2.2	14-Nov-2014	martin	Pull up the following revisions, requested by skrll in ticket #222: src/sys/arch/arm/arm32/locore.S 1.37 src/sys/arch/arm/arm32/bus_dma.c 1.87 Make the initial svcstack is doubleword aligned if EABI. With PMAP_NEED_ALLOC_POOLPAGE, before using pmap_map_poolpage make sure the page comes from the same freelist that pmap_map_poolpage uses.
1.86.2.1	10-Nov-2014	martin	Pull up following revision(s) (requested by skrll in ticket #209): sys/arch/arm/pic/pic.c: revision 1.25 sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.21 sys/arch/arm/arm32/pmap.c: revision 1.312 sys/arch/arm/arm32/bus_dma.c: revision 1.89 sys/arch/arm/arm32/pmap.c: revision 1.313 sys/arch/arm/arm32/pmap.c: revision 1.314 sys/arch/arm/arm32/pmap.c: revision 1.315 sys/arch/arm/arm32/pmap.c: revision 1.316 Include opt_multiprocessor.h When allocing a l1page, if a page isn't available, use uvm_wait to wait for one to become available. Should fix PR/49364. Post a dmb before invalidating the cache in the post-{read,write} operations to ensure that any/all cachelines brought in via speculation are really flushed. Ensure all memory operations are complete by before wfi. For example, the cpu could have just been in uvm_pageidlezero. In pmap_fault_fixup re-instate the TLB flush for the shared L1 case that occurs for non-ARM_MMU_EXTENDED kernels. This fixes rump/rumpkern/t_sp:stress_killer on rpi which is currently non-ARM_MMU_EXTENDED Remove an unnecessary flush that sneaked in as part of break-before-make change. Remove an XXXNH comment. Update PTE_SYNC_CURRENT to add a dsb for armv7 - part of the break-before-make fix.
1.89.2.5	05-Feb-2017	skrll	Sync with HEAD
1.89.2.4	05-Dec-2016	skrll	Sync with HEAD
1.89.2.3	27-Dec-2015	skrll	Sync with HEAD (as of 26th Dec)
1.89.2.2	22-Sep-2015	skrll	Sync with HEAD
1.89.2.1	06-Apr-2015	skrll	Sync with HEAD
1.95.2.1	07-Jan-2017	pgoyette	Sync with HEAD. (Note that most of these changes are simply $NetBSD$ tag issues.)
1.98.8.1	25-Feb-2020	martin	Pull up following revision(s) (requested by skrll in ticket #1510): sys/arch/arm/arm32/bus_dma.c: revision 1.119 sys/arch/arm/arm32/bus_dma.c: revision 1.120 Make sure to convey a failure to the calling function Likely fix for PR kern/54999, but that was a one-off panic. - Fix previous for non-_ARM32_NEED_BUS_DMA_BOUNCE builds
1.106.2.5	30-Sep-2018	pgoyette	Ssync with HEAD
1.106.2.4	06-Sep-2018	pgoyette	Sync with HEAD Resolve a couple of conflicts (result of the uimin/uimax changes)
1.106.2.3	28-Jul-2018	pgoyette	Sync with HEAD
1.106.2.2	02-May-2018	pgoyette	Synch with HEAD
1.106.2.1	07-Apr-2018	pgoyette	Sync with HEAD. 77 conflicts resolved - all of them $NetBSD$
1.108.2.3	13-Apr-2020	martin	Mostly merge changes from HEAD upto 20200411
1.108.2.2	08-Apr-2020	martin	Merge changes from current as of 20200406
1.108.2.1	10-Jun-2019	christos	Sync with HEAD
1.115.2.3	25-Feb-2020	martin	Pull up following revision(s) (requested by skrll in ticket #721): sys/arch/arm/arm32/bus_dma.c: revision 1.119 sys/arch/arm/arm32/bus_dma.c: revision 1.120 Make sure to convey a failure to the calling function Likely fix for PR kern/54999, but that was a one-off panic. - Fix previous for non-_ARM32_NEED_BUS_DMA_BOUNCE builds
1.115.2.2	06-Nov-2019	martin	Pull up following revision(s) (requested by jmcneill in ticket #399): sys/arch/arm/arm32/bus_dma.c: revision 1.117 sys/arch/arm/arm32/bus_dma.c: revision 1.118 sys/external/bsd/drm2/drm/drm_gem_cma_helper.c: revision 1.8 bus_dmamem_map: honour BUS_DMA_PREFETCHABLE hint Map buffer objects with BUS_DMA_PREFETCHABLE. Do not try to use direct map for prefetchable mappings
1.115.2.1	24-Sep-2019	martin	Pull up following revision(s) (requested by jmcneill in ticket #236): sys/arch/arm/arm32/bus_dma.c: revision 1.116 bus_dmamap_load_raw: support coherent mappings bus_dmamap_sync: support syncing "raw" buffer types
1.118.2.1	29-Feb-2020	ad	Sync with head.
1.124.2.3	03-Apr-2021	thorpej	Sync with HEAD.
1.124.2.2	03-Jan-2021	thorpej	Sync w/ HEAD.
1.124.2.1	14-Dec-2020	thorpej	Sync w/ HEAD.
1.138.2.1	01-Oct-2025	martin	Pull up following revision(s) (requested by skrll in ticket #1166): sys/arch/arm/arm32/bus_dma.c: revision 1.142 sys/arch/arm/include/cpufunc.h: revision 1.92 sys/arch/arm/arm32/bus_dma.c: revision 1.150 More KNF arm: Adjust barriers issued in bus_dmamap_sync for the coherent case. PR/59654 This change adjusts the memory barriers issued by bus_dmamap_sync for the coherent case. In the non-coherent case the CPU cache operations are expected to provide any, and all required barriers. These barriers are emitted after bouncing for PREWRITE and before bouncing for POSTREAD. A new indrection is introduced to deal with the differencs in barrier (dsb) options between Arm V8 and V7, the lack of options in Arm V6, and the need to use cpu_drain_writebuf for all other earlier versions. The Arm V8 Net change is: op old new
1.144.6.1	02-Aug-2025	perseant	Sync with HEAD
1.149.2.1	01-Oct-2025	martin	Pull up following revision(s) (requested by skrll in ticket #40): sys/arch/arm/include/cpufunc.h: revision 1.92 sys/arch/arm/arm32/bus_dma.c: revision 1.150 arm: Adjust barriers issued in bus_dmamap_sync for the coherent case. PR/59654 This change adjusts the memory barriers issued by bus_dmamap_sync for the coherent case. In the non-coherent case the CPU cache operations are expected to provide any, and all required barriers. These barriers are emitted after bouncing for PREWRITE and before bouncing for POSTREAD. A new indrection is introduced to deal with the differencs in barrier (dsb) options between Arm V8 and V7, the lack of options in Arm V6, and the need to use cpu_drain_writebuf for all other earlier versions. The Arm V8 Net change is: op old new
1.2	04-Mar-2001	bjh21	Make compat_13_sys_sigreturn() work on arm26, and move it from arch/arm/arm32/compat_13_machdep.c to arch/arm/arm/compat_13_machdep.c.
1.1	04-Mar-2001	matt	Move compat_13_machdep.c, strstr.c, copystr.S, bcopyinout.S, and bcopy_page.S to arm/arm32 and remove port-local copies.
1.20	26-Oct-2002	jdolecek	now that mem_no is emitted by config(8), there is no reason to keep copy of more or less identical iskmemdev() for every arch; move the function to spec_vnop.c, and g/c machine-dependant copies
1.19	06-Sep-2002	gehenna	Merge the gehenna-devsw branch into the trunk. This merge changes the device switch tables from static array to dynamically generated by config(8). - All device switches is defined as a constant structure in device drivers. - The new grammer ``device-major'' is introduced to ``files''. device-major <prefix> char <num> [block <num>] [<rules>] - All device major numbers must be listed up in port dependent majors.<arch> by using this grammer. - Added the new naming convention. The name of the device switch must be <prefix>_[bc]devsw for auto-generation of device switch tables. - The backward compatibility of loading block/character device switch by LKM framework is broken. This is necessary to convert from block/character device major to device name in runtime and vice versa. - The restriction to assign device major by LKM is completely removed. We don't need to reserve LKM entries for dynamic loading of device switch. - In compile time, device major numbers list is packed into the kernel and the LKM framework will refer it to assign device major number dynamically.
1.18	02-Aug-2002	thorpej	Add dmoverio.
1.17	29-Jul-2002	thorpej	Add sysmon at cdev 101.
1.16	22-Jul-2002	ichiro	cdev_tty_init(NIXPCOM,ixpcom) move to end of cdevsw array
1.15	20-Jul-2002	simonb	Add an "#ifndef NIXPCOM" check so that this builds on non-evbarm.
1.14	19-Jul-2002	thorpej	Rename cdev_systrace_init() to cdev_clonemisc_init(), so it can be properly used by any misc. cloning device. While here, correct a comment to indicate that "open" is the only entry point and that everything else is handled with fileops.
1.13	16-Jul-2002	ichiro	add ixpcom to cdevsw
1.12	30-Jun-2002	thorpej	Add kttcp device.
1.11	17-Jun-2002	christos	MD systrace gluons.
1.10	19-Apr-2002	wiz	branches: 1.10.2; Complete renaming of opms to opms (was partly named pms, externally and internally). Move arm/iomd/pms* to arm/iomd/opms*. Mechanical change, tested by cross-compiling a kernel from i386. Approved by christos. XXX: What are arm/arm32/conf.c and arm/include/conf.h good for?
1.9	18-Mar-2002	briggs	Fix typo: ISDNCTL -> NISDNCTL.
1.8	16-Mar-2002	martin	Rename ISDN devices, per discussion on tech-kern. The network devices become ippp (ISDN ppp) and irip (ISDN raw IP). The character device now are called: /dev/isdn (isdnd <-> kernel communication), /dev/isdnctl (dialing and other control), /dev/isdntrc* (tracing), /dev/isdnbchan* (raw B channel access, i.e. for user land PPP) and /dev/isdntel* (telephone devices, i.e. for answering machines).
1.7	05-Jan-2002	chris	Update with radio, cir and irframe. also add block device for ld. Update other tables in file as appropriate.
1.6	11-Dec-2001	chris	Add clockctl device. Note that someone needs to tidy this up, we've got 92 block devices, which just ain't true. Also appears we're actually missing some, eg the ld block device.
1.5	27-Oct-2001	rearnsha	branches: 1.5.2; Add the IFPGA console device.
1.4	16-Sep-2001	matt	branches: 1.4.2; Add missing devices (IOP,MLX,MLY,LD), PCI, stub AGP, ...
1.3	09-Sep-2001	toshii	branches: 1.3.2; Readd sacom to cdevsw.
1.2	04-Sep-2001	wiz	branches: 1.2.2; Fix typos (CONS instead of CONF, and specifc instead of specific).
1.1	03-Sep-2001	matt	Switch netwinder to use a common conf.c for the arm ports.
1.2.2.1	01-Oct-2001	fvdl	Catch up with -current.
1.3.2.6	10-Oct-2002	jdolecek	sync kqueue with -current; this includes merge of gehenna-devsw branch, merge of i386 MP branch, and part of autoconf rototil work
1.3.2.5	06-Sep-2002	jdolecek	sync kqueue branch with HEAD
1.3.2.4	23-Jun-2002	jdolecek	catch up with -current on kqueue branch
1.3.2.3	10-Jan-2002	thorpej	Sync kqueue branch with -current.
1.3.2.2	13-Sep-2001	thorpej	Update the kqueue branch to HEAD.
1.3.2.1	09-Sep-2001	thorpej	file conf.c was added on branch kqueue on 2001-09-13 01:13:06 +0000
1.4.2.1	12-Nov-2001	thorpej	Sync the thorpej-mips-cache branch with -current.
1.5.2.10	11-Nov-2002	nathanw	Catch up to -current
1.5.2.9	17-Sep-2002	nathanw	Catch up to -current.
1.5.2.8	13-Aug-2002	nathanw	Catch up to -current.
1.5.2.7	01-Aug-2002	nathanw	Catch up to -current.
1.5.2.6	20-Jun-2002	nathanw	Catch up to -current.
1.5.2.5	01-Apr-2002	nathanw	Catch up to -current. (CVS: It's not just a program. It's an adventure!)
1.5.2.4	28-Feb-2002	nathanw	Catch up to -current.
1.5.2.3	11-Jan-2002	nathanw	More catchup.
1.5.2.2	08-Jan-2002	nathanw	Catch up to -current.
1.5.2.1	27-Oct-2001	nathanw	file conf.c was added on branch nathanw_sa on 2002-01-08 00:23:07 +0000
1.10.2.5	30-Aug-2002	gehenna	catch up with -current.
1.10.2.4	21-Jul-2002	gehenna	catch up with -current.
1.10.2.3	16-Jul-2002	gehenna	catch up with -current.
1.10.2.2	14-Jul-2002	gehenna	catch up with -current.
1.10.2.1	16-May-2002	gehenna	Bye block/character device swicth tables.
1.6	11-Aug-2002	bjh21	Move the arm32 copystr.S from arch/arm/arm32 to arch/arm/arm and add support for 26-bit modes (basically saving R14 when we might get a page fault). Use it on all ARM architectures now.
1.5	09-Aug-2002	thorpej	Reduce stalls on StrongARM and XScale by waiting one insn before using the result of a load.
1.4	09-Aug-2002	thorpej	Use ldrbt/strbt. Some other random cleanup.
1.3	03-Mar-2002	chris	branches: 1.3.6; 1.3.8; Implement pmap_growkernel for arm32 based ports. Note that this has been compiled on some systems, cats, IQ80310, IPAQ, netwinder and shark (note that shark's build is currently broken due to other reasons), but only actually run on cats. Shark doesn't make use of the functionality as I believe there has to be a correlation between OFW and the kernel tables so that calls into OFW work.
1.2	28-Sep-2001	chris	branches: 1.2.4; Note the alignment state of the stack. This is part of the work to get the stack 8byte aligned for ELF
1.1	04-Mar-2001	matt	branches: 1.1.2; 1.1.4; 1.1.6; Move compat_13_machdep.c, strstr.c, copystr.S, bcopyinout.S, and bcopy_page.S to arm/arm32 and remove port-local copies.
1.1.6.3	06-Sep-2002	jdolecek	sync kqueue branch with HEAD
1.1.6.2	16-Mar-2002	jdolecek	Catch up with -current.
1.1.6.1	10-Jan-2002	thorpej	Sync kqueue branch with -current.
1.1.4.2	12-Mar-2001	bouyer	Sync with HEAD.
1.1.4.1	04-Mar-2001	bouyer	file copystr.S was added on branch thorpej_scsipi on 2001-03-12 13:27:19 +0000
1.1.2.1	01-Oct-2001	fvdl	Catch up with -current.
1.2.4.3	13-Aug-2002	nathanw	Catch up to -current.
1.2.4.2	01-Apr-2002	nathanw	Catch up to -current. (CVS: It's not just a program. It's an adventure!)
1.2.4.1	28-Sep-2001	nathanw	file copystr.S was added on branch nathanw_sa on 2002-04-01 07:39:07 +0000
1.3.8.1	16-Nov-2002	he	Pull up revision 1.4 (requested by thorpej in ticket #658): Use ldrbt/strbt, and some other cleanups.
1.3.6.1	30-Aug-2002	gehenna	catch up with -current.
1.8	20-Jun-2020	skrll	KNF #includes Remove some unnecessary ones while I'm here.
1.7	27-Jan-2019	pgoyette	Merge the [pgoyette-compat] branch
1.6	12-Jul-2018	maxv	Remove the kernel PMC code. Sent yesterday on tech-kern@. This change: * Removes "options PERFCTRS", the associated includes, and the associated ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is good. * Removes the PMC code of ARM XSCALE. * Removes all the pmc.h files. They were all empty, except for ARM XSCALE. * Reorders the x86 PMC code not to rely on the legacy pmc.h file. The definitions are put in sysarch.h. * Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control and sys_pmc_get_info syscalls. They are marked as OBSOL in kern, netbsd32 and rump. * Removes the pmc_evid_t and pmc_ctr_t types. * Removes all the associated man pages. The sets are marked as obsolete.
1.5	04-Dec-2017	skrll	branches: 1.5.2; 1.5.4; KNF
1.4	13-Aug-2015	knakahara	fix: Cortex delay() shorten rarely.
1.3	08-Feb-2015	skrll	RCSid police
1.2	29-Aug-2012	matt	branches: 1.2.2; 1.2.12; 1.2.16; 1.2.18; Since the PMC cycle counter is started in cpufunc no reason to do so here. Use curcpu()->ci_data.cpu_cc_freq and new armreg* inlines.
1.1	19-Jun-2010	matt	branches: 1.1.2; 1.1.4; 1.1.6; 1.1.14; 1.1.22; Cleanup the armv7 changes. Add ARM_ARCH_7. Use CPU_CORTEX instead of CPU_CORTEXA8 everywhere since there more types of Cortex than just the A8. CPU_CORTEXA8 still exists but causes CPU_CORTEX to be defined. Add CPU_CORTEXA9 as well. Use .arch armv7a to get us the isb/dsb instructions. Test booted to root device prompt on a Beagleboard. All ARM kernels successfully test built.
1.1.22.1	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.1.14.1	30-Oct-2012	yamt	sync with head
1.1.6.2	17-Aug-2010	uebayasi	Sync with HEAD.
1.1.6.1	19-Jun-2010	uebayasi	file cortex_pmc.c was added on branch uebayasi-xip on 2010-08-17 06:44:01 +0000
1.1.4.2	11-Aug-2010	yamt	sync with head.
1.1.4.1	19-Jun-2010	yamt	file cortex_pmc.c was added on branch yamt-nfs-mp on 2010-08-11 22:51:39 +0000
1.1.2.2	03-Jul-2010	rmind	sync with head
1.1.2.1	19-Jun-2010	rmind	file cortex_pmc.c was added on branch rmind-uvmplock on 2010-07-03 01:19:13 +0000
1.2.18.2	22-Sep-2015	skrll	Sync with HEAD
1.2.18.1	06-Apr-2015	skrll	Sync with HEAD
1.2.16.1	04-Sep-2015	martin	Pull up following revision(s) (requested by skrll in ticket #953): sys/arch/arm/arm32/cortex_pmc.c: revision 1.4 fix: Cortex delay() shorten rarely.
1.2.12.2	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.2.12.1	29-Aug-2012	matt	file cortex_pmc.c was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
1.2.2.1	03-Dec-2017	jdolecek	update from HEAD
1.5.4.1	10-Jun-2019	christos	Sync with HEAD
1.5.2.1	28-Jul-2018	pgoyette	Sync with HEAD
1.2	19-Jun-2010	matt	This was renamed to cortex_pmc.c
1.1	16-Jun-2010	jmcneill	PR port-arm/43299: Support added for igepv2/cortexa8/omap3530 Apply patch from PR, with build fixes. ok skrll, matt
1.155	09-Oct-2025	skrll	Add the beginnings of a GENERIC_V5 kernel that targets armv5 boards and uses FDT. In this first iteration some support is added for OLinuXino boards. Thanks to Yuri Honegger for doing the vast majority of the work.
1.154	09-May-2024	pho	kern/58195: arm: Support drvctl -d and -r for cpufeaturebus This is required for detaching and re-attaching the vmt(4) driver on aarch64.
1.153	03-Mar-2022	riastradh	arm: Use device_set_private for cpuN. For cpu at fdt, nix the fdt softc -- this was leaked and never used for anything. The device's private storage is the cpu_info.
1.152	31-Oct-2021	skrll	Rework Arm (32bit and 64bit) AP startup so that cpu_hatch doesn't sleep. The AP initialisation code in cpu_init_secondary_processor will read and initialise the required system registers and state for the BP to attach and report. Rework the interrupt handler code for this new sequence. Thankfully, this removes a bunch of code for bcm2836mp. The VFP detection handler on <= armv7 relies on the global undefined handler being in place until the BP attaches vfp. That is, after the APs have been spun up. gicv3_its.c has a serialisation issue which is protected against in the gicv3_its_cpu_init, which is called from cpu_hatch, with a spin lock. The serialisation issue needs addressing more completely. Tested on RPI3, Apple M1, QEMU, and lx2k Fixes PR port-arm/56264: diagnostic assertion "l->l_stat == LSONPROC" failed on RPI3
1.151	11-Oct-2021	rin	For some classic CPUs, info->[id]cache_sets are not initialized. Calculate and print numbers of sets in this case.
1.150	11-Oct-2021	rin	pN steppings are used for ARM926EJ-S, although only r0 seems to be available.
1.149	23-Sep-2021	skrll	Print the cache information in similar formats and arm and aarch64, e.g. arm before [ 1.0000000] cpu0: 32KB/64B 2-way L1 PIPT Instruction cache [ 1.0000000] cpu0: 32KB/64B 2-way write-back-locking-C L1 PIPT Data cache [ 1.0000000] cpu0: 2304KB/64B 16-way write-through L2 PIPT Unified cache arm after [ 1.0000000] cpu0: L1 32KB/64B 2-way (256 set) PIPT Instruction cache [ 1.0000000] cpu0: L1 32KB/64B 2-way (256 set) write-back-locking-C PIPT Data cache [ 1.0000000] cpu0: L2 2304KB/64B 16-way (2304 set) write-through PIPT Unified cache aarch64 before [ 1.0000030] cpu1: L1 48KB/64B256L3W PIPT Instruction cache [ 1.0000030] cpu1: L1 32KB/64B256L2W PIPT Data cache [ 1.0000030] cpu1: L2 2048KB/64B2048L16W PIPT Unified cache aarch64 after [ 1.0000030] cpu1: L1 48KB/64B 3-way (256 set) PIPT Instruction cache [ 1.0000030] cpu1: L1 32KB/64B 2-way (256 set) PIPT Data cache [ 1.0000030] cpu1: L2 2048KB/64B 16-way (2048 set) PIPT Unified cache
1.148	06-Jul-2021	skrll	Assume all ARM11[37]6 r0 variants are missing ISAR and friends. This is certainly the case for r0 variants I could find TRMs for. PR/50596 CPU_ID_ARM1136JS r0p4 does not support feature registers
1.147	02-Jul-2020	martin	branches: 1.147.6; Initialize ci_kfpu_spl earlier for secondary CPUs. From riastradh
1.146	29-Jun-2020	riastradh	Implement fpu_kern_enter/leave for arm32.
1.145	20-Jun-2020	skrll	KNF #includes Remove some unnecessary ones while I'm here.
1.144	15-Feb-2020	skrll	Various updates and improvements to cpu start up on arm/aarch64 - start sharing more code around the AP startup messaging. - call arm_cpu_topology_set early so that ci_core_id is available for drivers, e.g. bcm2835_intr.c - both arm and aarch64 now have - a static cpu_info_store array - the same arm_cpu_{hatched,mbox}
1.143	22-Jan-2020	skrll	#ifdef whack-a-mole for the pmap_maxproc_set functionality
1.142	20-Jan-2020	skrll	s/_ARM_ARCH_6/ARM_MMU_EXTENDED/ in the #ifdef for the recent 4k pages change
1.141	18-Jan-2020	skrll	Use 4K pages on ARM_MMU_EXTENDED platforms (all armv[67] except RPI) by creating a new pool l1ttpl for the userland L1 translation table which needs to be 8KB and 8KB aligned. Limit the pool to maxproc and add hooks to allow the sysctl changing of maxproc to adjust the pool. This comes at a 5% performance penalty for build.sh -j8 kernel on a Tegra TK1.
1.140	15-Jan-2020	mrg	port the arm64 cpu topology setup for big.little to arm. rename arm64 cpu_do_topology() to arm_cpu_do_topology() and call it from both arm cpu_attach(). replace both aarch64_set_topology() inline code in arm cpu_attach() with new arm_cpu_do_topology(), which is called by the arm64 locore as well (possibly not needed, which would allow it to become static.) not yet tested on a real big.little armv7 system. tested on rockpro64 and pinebook pro.
1.139	09-Jan-2020	ad	- Many small tweaks to the SMT awareness in the scheduler. It does a much better job now at keeping all physical CPUs busy, while using the extra threads to help out. In particular, during preempt() if we're using SMT, try to find a better CPU to run on and teleport curlwp there. - Change the CPU topology stuff so it can work on asymmetric systems. This mainly entails rearranging one of the CPU lists so it makes sense in all configurations. - Add a parameter to cpu_topology_set() to note that a CPU is "slow", for where there are fast CPUs and slow CPUs, like with the Rockwell RK3399. Extend the SMT awareness to try and handle that situation too (keep fast CPUs busy, use slow CPUs as helpers).
1.138	09-Jan-2020	martin	When attaching the first fdtbus, use the root "comptabile" (or failing that: "model") property to set the cpu model (in userland aka sysctl hw.model). When attaching the first cpu, do not overwrite a cpu model if it already had been set.
1.137	08-Jan-2020	jmcneill	cpu_hatch is too late to report AP topology, do it at attach time instead
1.136	20-Dec-2019	ad	branches: 1.136.2; Some more CPU topology stuff: - Use cegger@'s ACPI SRAT parsing code to figure out NUMA node ID for each CPU as it is attached. - For scheduler experiments with SMT, flag CPUs with the lowest numbered SMT IDs as "primaries", link back to the primaries from secondaries, and build a circular list of CPUs in each package with identical SMT IDs. - No need for package/core/smt/numa IDs to be anything other than a u_int.
1.135	02-Dec-2019	ad	Take the basic CPU topology information we already collect, and use it to make circular lists of CPU siblings in the same core, and in the same package. Nothing fancy, just enough to have a bit of fun in the scheduler trying out different tactics.
1.134	20-Oct-2019	jmcneill	cpu_hatched_p only for MULTIPROCESSOR
1.133	19-Oct-2019	jmcneill	Increase aarch64 MAXCPUS to 256.
1.132	29-Sep-2019	skrll	aprint_debug_dev output alignment
1.131	08-Sep-2019	tnn	report A12 as A17 to the user. A12 is retcon'ed by ARM.
1.130	07-Sep-2019	tnn	Cortex A12 is marketed as A17 but has a distinct part number observed on Rockchip RK3288
1.129	17-Mar-2019	skrll	branches: 1.129.4; Wrap arm_cpu_marker if #ifdef MPDEBUG. One day a9_mpsubr.S will die
1.128	27-Jan-2019	pgoyette	Merge the [pgoyette-compat] branch
1.127	25-Jan-2019	skrll	Make sure ci_{smt,core,package}_id are all filled in appropriately. Previously the BP was missed and __SHIFTOUT wasn't used.
1.126	03-Jan-2019	jmcneill	Read mpidr and cpuid from the secondary processor itself instead of the boot processor. While here, add Cortex-A15 r4p0 to supported list.
1.125	03-Jan-2019	skrll	Start CPUs more like aarch64 by using a cpu_mpidr array (if populated) to map MPIDRs to an index for each CPU. Towards big.LITTLE support.
1.124	02-Jan-2019	skrll	Don't overwrite the setting of cpu_core_id from mpidr
1.123	18-Oct-2018	skrll	Provide generic start code that assumes the MMU is off and caches are disabled as per the linux booting protocol for ARMv6 and ARMv7 boards. u-boot image type should be changed to 'linux' for correct behaviour. The new start code builds a minimal "bootstrap" L1PT with cached access disabled and uses the same table for all processors. AP startup is performed in less steps and more code is written in C. The bootstrap tables and stack are placed into an (orphaned) section "_init_memory" which is given to uvm when it is no longer used. Various kernels have been converted to use this code and tested. Some boards were provided by TNF. Thanks! The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS kernels. The GENERIC kernel will also work on RPI2 using u-boot. Thanks to martin@ and aymeric@ for testing on parallella and nanosoc respectively
1.122	08-Oct-2018	skrll	Trialing whitespace
1.121	06-Oct-2018	skrll	Use __BIT. NFC.
1.120	15-Aug-2018	skrll	KNF
1.119	15-Aug-2018	skrll	Fix includes (sys/cdefs.h then sys/param.h)
1.118	15-Aug-2018	skrll	Sprinkle #include "opt_cputypes.h"
1.117	10-Aug-2018	maxv	Retire CPU_ARM2, CPU_ARM250 and CPU_ARM3, they are all leftovers of acorn26. ok jmcneill@ skrll@
1.116	16-Sep-2017	matt	branches: 1.116.2; 1.116.4; Add Cortex-A35 CPU ID.
1.115	01-Jun-2017	chs	branches: 1.115.6; remove checks for failure after memory allocation calls that cannot fail: kmem_alloc() with KM_SLEEP kmem_zalloc() with KM_SLEEP percpu_alloc() pserialize_create() psref_class_create() all of these paths include an assertion that the allocation has not failed, so callers should not assert that again.
1.114	11-Jul-2016	kiyohara	Add Cortex-A9 r1.
1.113	03-Mar-2016	skrll	Get the RPI3 working (in aarch32 mode) by recognising Cortex A53 CPUs. While I'm here add some A57/A72 info as well. My RPI3 works with FB console - the uart needs some help with its clocks.
1.112	23-Jan-2016	christos	Rename the cpu_id() define to cpu_idnum() so that it does not conflict with dtrace and friends.
1.111	12-Nov-2015	jmcneill	change some register dumps from aprint_verbose to aprint_debug
1.110	08-Jul-2015	skrll	aprint_verbose [sa]ctlr
1.109	05-Jun-2015	skrll	Print the Revision ID regster (verbose)
1.108	17-May-2015	matt	Print out mpidr on MP systems (verbose print)
1.107	03-Mar-2015	jmcneill	cache type 12 is "write-back", from matt
1.106	27-Nov-2014	matt	branches: 1.106.2; Add entry for Cortex-A17 r1
1.105	01-Sep-2014	reinoud	Increase the `freqbuf' buffer that holds the result of humanize_number(). Now it prints 1600 Mhz instead of 1 Ghz. Pitty enough humanize_number(9) doesn't do 1.6 Ghz type output.
1.104	28-Mar-2014	matt	branches: 1.104.4; Various MP changes.
1.103	24-Mar-2014	christos	use cpu_{g,s}etmodel
1.102	20-Mar-2014	matt	Define cache type 13
1.101	03-Mar-2014	matt	Add most of the cpu_* variables to <arm/locore.h> Add and initialize cpu_synchprim_present
1.100	20-Feb-2014	matt	Keep track of what each cache is (VIVT/VIPT/PIPT). cpu0: 32KB/32B 2-way L1 VIPT Instruction cache cpu0: 32KB/64B 4-way write-back-locking-C L1 PIPT Data cache cpu0: 256KB/64B 8-way write-through L2 PIPT Unified cache
1.99	07-Sep-2013	matt	Add a machdep.hwdiv_present sysctl (cortex A7 and A15 have hwdiv instructions)
1.98	07-Sep-2013	matt	Add CPU_ID_CORTEXA7R0 entry
1.97	18-Aug-2013	matt	Move parts of cpu.h that are not needed by MI code in <arm/locore.h> Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h> Use <arm/asm.h> instead of <machine/arm.h>
1.96	12-Jun-2013	matt	branches: 1.96.2; Nuke cpu_pfr, just use the armreg_pfr?_read inlines
1.95	12-Jun-2013	matt	Use the armreg_pfr?_read inlines.
1.94	19-May-2013	rkujawa	Plug support for PJ4B into our ARM CPU infrastructure. Obtained from Marvell, Semihalf.
1.93	03-Feb-2013	matt	Add a machdep.cpu_arch sysctl
1.92	31-Jan-2013	matt	Add simple sysctls for cpu_id, fpu_id, neon_present, simd_present, simdex_present. Add struct sysctls to return the isar, mmfr, pfr, and mvfr sets.
1.91	05-Dec-2012	matt	ARMFPE hasn't compiled since NetBSD 4. Remove it. Complete support for FPU_VFP. fpregs now contains vfpreg. XXX vfpreg only has space for 16 64-bit FP registers though VFPv3 and later have 32 64-bit FP registers.
1.90	30-Nov-2012	msaitoh	Use snprintf() instead of sprintf().
1.89	30-Nov-2012	msaitoh	s/,/;/
1.88	12-Nov-2012	skrll	C99 types
1.87	22-Sep-2012	matt	Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead but add a second argument to it to indicate whether the TLB/caches need to be flushed. Default cortex to pmap_needs_fixup = 1. But check the MMFR3 field to see if the fixed can be skipped. Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1) or enabeld (bit = 0). With these changes, the A9 MMU can use traverse caches to do MMU tablewalks Also, make sure all memory has the shareable bit for the A9.
1.86	07-Sep-2012	matt	branches: 1.86.2; Switch cortex_a9 back to need_ptesync = 1 Add code to disable the L2 cache on cortex-a9 (for now). Add evcnt for all the fault types. Move cache info in a structure and have one for the pcache and one for scache. Probe L1/L2 caches properly for ARMv7
1.85	29-Aug-2012	matt	Use new armv7 CP15 register to print out cache types. If the cpu_cc_freq is set, report it. Add macros to make inlines for reading/writing co-processor registers.
1.84	14-Aug-2012	matt	Use device_t
1.83	12-Aug-2012	matt	Rework VFP support to use PCU. Add emulation of instruction which save/restore the VFP FPSCR. Add a sysarch hook to VFP FPSCR manipulation. [The emulation will be used by libc to store/fetch exception modes and rounding mode on a per-thread basis.]
1.82	14-Jul-2012	matt	Refresh cortex cpus
1.81	20-May-2012	skrll	Remove the ARM1156T2 bloat - it only has an MPU. Prompted by matt@
1.80	20-May-2012	skrll	Add the ARM1156T2-S
1.79	20-May-2012	skrll	Add the 'Z' to the 1176 cpu product name. ok matt@
1.78	10-Mar-2011	bsh	branches: 1.78.4; 1.78.8; 1.78.10; add MPCore to CPU-ID table add branch predict bit to arm11_options
1.77	02-Oct-2010	kiyohara	branches: 1.77.2; Add support Marvell Sheeva Core and SoC. (Orion/Kirkwood) Discovery Innovation not yet.
1.76	19-Jun-2010	matt	Fix cache probing on Cortex. Add missing CORTEX dependency in cpu.c
1.75	19-Jun-2010	matt	Fix c&p error.
1.74	19-Jun-2010	matt	Cleanup the armv7 changes. Add ARM_ARCH_7. Use CPU_CORTEX instead of CPU_CORTEXA8 everywhere since there more types of Cortex than just the A8. CPU_CORTEXA8 still exists but causes CPU_CORTEX to be defined. Add CPU_CORTEXA9 as well. Use .arch armv7a to get us the isb/dsb instructions. Test booted to root device prompt on a Beagleboard. All ARM kernels successfully test built.
1.73	16-Jun-2010	jmcneill	PR port-arm/43299: Support added for igepv2/cortexa8/omap3530 Apply patch from PR, with build fixes. ok skrll, matt
1.72	23-Jan-2010	mrg	branches: 1.72.2; 1.72.4; rename a local cpu_name structure member to avoid potential conflict with <sys/cpu.h>'s.
1.71	25-Oct-2008	matt	branches: 1.71.4; 1.71.12; Fix some missing things for CPU_ID_FA526.
1.70	24-Oct-2008	matt	Add entry for FA526.
1.69	21-Oct-2008	matt	Add Cortex cpus
1.68	27-Apr-2008	matt	branches: 1.68.6; Merge kernel changes in matt-armv6 to HEAD.
1.67	15-Mar-2008	rearnsha	branches: 1.67.2; 1.67.4; VFP support.
1.66	17-Oct-2007	garbled	branches: 1.66.12; 1.66.16; Merge the ppcoea-renovation branch to HEAD. This branch was a major cleanup and rototill of many of the various OEA cpu based PPC ports that focused on sharing as much code as possible between the various ports to eliminate near-identical copies of files in every tree. Additionally there is a new PIC system that unifies the interface to interrupt code for all different OEA ppc arches. The work for this branch was done by a variety of people, too long to list here. TODO: bebox still needs work to complete the transition to -renovation. ofppc still needs a bunch of work, which I will be looking at. ev64260 still needs to be renovated amigappc was not attempted. NOTES: pmppc was removed as an arch, and moved to a evbppc target.
1.65	17-May-2007	yamt	branches: 1.65.10; 1.65.12; merge yamt-idlelwp branch. asked by core@. some ports still needs work. from doc/BRANCHES: idle lwp, and some changes depending on it. 1. separate context switching and thread scheduling. (cf. gmcgarry_ctxsw) 2. implement idle lwp. 3. clean up related MD/MI interfaces. 4. make scheduler(s) modular.
1.64	06-Jan-2007	christos	branches: 1.64.2; 1.64.6; 1.64.8; 1.64.14; Scott Allan in http://mail-index.netbsd.org/port-arm/2006/07/31/0000.html Patch to add support for ARM9E
1.63	06-Jan-2007	christos	From Scott Alan in http://mail-index.netbsd.org/port-arm/2006/07/26/0000.html identify_arm_cpu() prints out a helpful message when it detects that you're trying to run on a CPU that you didn't configure for. Unfortunately, the check for class_option being NULL is backward, so it either won't print the class_option, or it will try to dereference a NULL. The patch just flips the != NULL to be == NULL.
1.62	15-Mar-2006	drochner	branches: 1.62.10; 1.62.14; use km_alloc to get wired kernel memory for kernel stacks of idle processes for secondary CPUs (affects the MULTIPROCESSOR case only - does this exist?) (untested)
1.61	11-Dec-2005	christos	branches: 1.61.4; 1.61.6; 1.61.8; 1.61.10; merge ktrace-lwp.
1.60	20-Jul-2005	nonaka	Added i80219.
1.59	04-Jul-2005	bsh	branches: 1.59.2; The first step to support Intel PXA270. kernel config option CPU_XSCALE_PXA2X0 is now obsoleted by CPU_XSCALE_PXA250 and CPU_XSCALE_PXA270. If both of them are defined, CPU is determined run-time.
1.58	03-Jun-2005	rearnsha	Very basic support for the ARM1136. This code takes no advantage of any 'new' features provided by architecture 6 devices (such as physically tagged caches or new MMU features), and basically runs the chip in a 'legacy v5' mode.
1.57	10-May-2005	rearnsha	Add support for arm1026ej-s.
1.56	14-Apr-2004	bsh	distinguish PXA255/26x from PXA2[15]0 in CPU attach message
1.55	13-Feb-2004	wiz	Uppercase CPU, plural is CPUs.
1.54	26-Oct-2003	chris	Fix up some unitialised variables.
1.53	06-Sep-2003	rearnsha	Support for ARM10E class devices.
1.52	03-Sep-2003	mycroft	Recognize some TI processors -- not that you'd want to use them.
1.51	23-Jun-2003	martin	branches: 1.51.2; Make sure to include opt_foo.h if a defflag option FOO is used.
1.50	23-May-2003	ichiro	support IXP425 Intel Network Processor running on BigEndian
1.49	29-Apr-2003	thorpej	Use aprint*().
1.48	14-Feb-2003	rjs	Add CPU IDs for PXA B2 and C0 steppings.
1.47	06-Jan-2003	wiz	specified, not specifed.
1.46	17-Nov-2002	chs	change uvm_uarea_alloc() to indicate whether the returned uarea is already backed by physical pages (ie. because it reused a previously-freed one), so that we can skip a bunch of useless work in that case. this fixes the underlying problem behind PR 18543, and also speeds up fork() quite a bit (eg. 7% on my pc, 1% on my ultra2) when we get a cache hit.
1.45	13-Oct-2002	chris	branches: 1.45.2; Fix arm kernel build breaks for non multiprocessor systems.
1.44	13-Oct-2002	bjh21	It appears that MI code requires ci_cpuid to be the CPU number of the CPU in question, whereas the ARM code was using it to hold the model identification. To fix this, rename: ci_cpuid -> ci_arm_cpuid ci_cputype -> ci_arm_cputype (for consistency) ci_cpurev -> ci_arm_cpurev (ditto) ci_cpunum -> ci_cpuid This makes top(1) give correct CPU numbers in its "STATE" column (all 0 for now).
1.43	12-Oct-2002	bjh21	Remember the location of each CPU's idle PCB in struct cpu_info. Move allocation of the idle PCB from hydra.c to cpu.c and add some extra initialisation from cpu_fork().
1.42	01-Oct-2002	bjh21	constify various string tables.
1.41	06-Sep-2002	gehenna	Merge the gehenna-devsw branch into the trunk. This merge changes the device switch tables from static array to dynamically generated by config(8). - All device switches is defined as a constant structure in device drivers. - The new grammer ``device-major'' is introduced to ``files''. device-major <prefix> char <num> [block <num>] [<rules>] - All device major numbers must be listed up in port dependent majors.<arch> by using this grammer. - Added the new naming convention. The name of the device switch must be <prefix>_[bc]devsw for auto-generation of device switch tables. - The backward compatibility of loading block/character device switch by LKM framework is broken. This is necessary to convert from block/character device major to device name in runtime and vice versa. - The restriction to assign device major by LKM is completely removed. We don't need to reserve LKM entries for dynamic loading of device switch. - In compile time, device major numbers list is packed into the kernel and the LKM framework will refer it to assign device major number dynamically.
1.40	22-Jul-2002	briggs	Handle i80200 step D0 and i80321 step B0
1.39	10-Jul-2002	ichiro	add cpu id for "PXA250/210 3rd version CPUcore". for using many PDA/xscale-core.
1.38	07-Jun-2002	thorpej	Add the CPU ID for the 600MHz i80321 part.
1.37	12-May-2002	ichiro	branches: 1.37.2; 1.37.4; change ICP12x0 steppings. define CPU_IXP12X0
1.36	10-May-2002	thorpej	Add IXP1200 steppings.
1.35	03-May-2002	thorpej	Add support for the Intel PXA210 and PXA250. From Hiroyuki Bessho, PR 16617.
1.34	02-May-2002	rjs	Enable CPU_CLASS_SA1 for SA1100 and SA1110.
1.33	12-Apr-2002	thorpej	Centralize ARM CPU configuration information by adding a new header file, <arm/cpuconf.h>, which pulls in "opt_cputypes.h" and then defines the following: * CPU_NTYPES -- now many CPU types are configured into the kernel. What you really want to know is "== 1" or "> 1". * Defines ARM_ARCH_2, ARM_ARCH_3, ARM_ARCH_4, ARM_ARCH_5, depending on which ARM architecture versions are configured (based on CPU_* options). Also defines ARM_NARCH to determins how many architecture versions are configured. * Defines ARM_MMU_MEMC, ARM_MMU_GENERIC, ARM_MMU_XSCALE depending on which classes of ARM MMUs are configured into the kernel, and ARM_NMMUS to determine how many MMU classes are configured. Remove the needless inclusion of "opt_cputypes.h" in several places. Convert remaining users to <arm/cpuconf.h>.
1.32	27-Mar-2002	thorpej	The 80321 manual lies; it does have a CPU ID distinct from the 80200. Add that CPU ID, and add a case for it.
1.31	26-Mar-2002	thorpej	Restructure a few things in order to support other XScale core I/O processors: * The i80200 and the i80321 have the same CPU ID, so split the CPU_XSCALE option into CPU_XSCALE_80200 and CPU_XSCALE_80321 options, and don't let them both be defined at the same time. XXX May want to revisit this in the future. * Split some registers common between the i80200 and i80321 into <arm/xscale/xscalereg.h>. * Rename a few existing functions.
1.30	24-Mar-2002	thorpej	Cache the cpu type and cpu revision in cpu_info.
1.29	16-Mar-2002	bjh21	Only put the CPU type into cpu_model, not the state of the control register. Instead, print the control register state on the next line at startup.
1.28	16-Mar-2002	bjh21	Add CPU ID for the ARM1022ES. Also add a CPU class for ARM10E processors in general.
1.27	11-Mar-2002	reinoud	When ARMFPE wasn't enabled the `usearmfpe' flag was statically initialised but not used resulting in a compiler error. By splitting the declaration and the initialisation this is solved. Better would be to not even declare the flag when ARMFPE isnt enabled but that would just add to the #ifdef jungle.
1.26	10-Mar-2002	bjh21	__RCSID -> __KERNEL_RCSID
1.25	10-Mar-2002	bjh21	Re-work the way that FPAs are handled. If ARMFPE isn't configured, don't even bother probing for an FPA. If ARMFPE is configured, always use it, even if there's an FPA (since it provides the FPA support code). Move all printfs about FPAs into armfpe_init.c. This means I can delete the last two elements from struct _cpu, so that the structure, and the whole of <arm/cpus.h> is redundant and can be deleted.
1.24	10-Mar-2002	bjh21	Remove fpu_model from struct _cpu. Instead, have initialise_arm_fpe() printf() the FPE version number itself.
1.23	10-Mar-2002	bjh21	Add a ci_dev element to struct cpu_info, pointing to the device that corresponds to the CPU.
1.22	10-Mar-2002	bjh21	Kill the fpu_flags element from struct _cpu. It was only ever set to 0 anyway.
1.21	10-Mar-2002	bjh21	Clean up inline assembler. Rather than saving R0, copying FPSR to R0, copying it to the output register and then restoring R0, just copy the FPSR straight to the output.
1.20	09-Mar-2002	bjh21	Remove the cpu_model member from struct _cpu, and just use the cpu_model variable directly. While we're at it, make cpu_model rather larger.
1.19	09-Mar-2002	bjh21	Remove the cpu_class element from struct _cpu, and make it a local variable in identify_arm_cpu(), since it's almost unused elsewhere. Change the detection of bugged StrongARMs to use the cpu ID rather than the class. This turns "almost" into "entirely".
1.18	09-Mar-2002	bjh21	Replace cpu_id and cpu_ctrl in struct _cpu with ci_cpuid and ci_ctrl in struct cpu_info. Also kill the cpuctrl global while we're here, and make identify_arm_cpu() take a struct cpu_info * as an argument alongside the CPU number.
1.17	09-Mar-2002	bjh21	Move arm700bugcount into stuct cpu_info, and attach it in identify_master_cpu().
1.16	17-Feb-2002	bjh21	Our assembler handles FPA instructions fine, so don't use .word for them.
1.15	17-Feb-2002	bjh21	ANSIfy, and othe KNF cleanup.
1.14	27-Jan-2002	bjh21	Add revision->stepping maps for the SA-110, SA-1100 and SA-1110. Those for the SA-1100 and SA-1110 are from Intel's documentation. The mapping for the SA-110 is from various sources on the net, since Intel don't seem to document it. Also, change the layout of the maps to have four steppings per line, so they aren't quite so unwieldy.
1.13	24-Jan-2002	thorpej	Use a table to look up stepping names. Add a generic stepping table ("rev 0", "rev 1", etc.) and an i80200 stepping table that has the stepping names that appear in the i80200 manuals/errata..
1.12	29-Nov-2001	thorpej	Fetch cache info from the Cache Type register on ARM7TDMI and "greater" processors. Report this when the processor is attached.
1.11	24-Nov-2001	thorpej	Move the ARM, Ltd. floating point emulator to arch/arm.
1.10	23-Nov-2001	thorpej	Use <arm/undefined.h> instead of <machine/undefined.h>.
1.9	06-Nov-2001	thorpej	branches: 1.9.2; Const poisoning of cpu/class names.
1.8	06-Nov-2001	thorpej	"i80200", not "80200".
1.7	06-Nov-2001	thorpej	"XScale", not "Xscale".
1.6	18-Oct-2001	rearnsha	branches: 1.6.2; Support for ARM9.
1.5	28-Sep-2001	chris	Add extra arg to fpa_test as it should have 4 args. Also add prototypes for fpa_test and fpa_handler.
1.4	05-Sep-2001	matt	branches: 1.4.2; Flesh XSCALE support.
1.3	03-Jun-2001	chris	branches: 1.3.2; 1.3.4; Add support for ARM7TDMI, as provided in a patch from John Fremlin to port-arm32. Shouldn't effect any currently in tree ports.
1.2	13-May-2001	bjh21	Use get_bootconf_option() to find boot options, rather than home-grown strstr()-based hacks.
1.1	20-Apr-2001	matt	branches: 1.1.2; Split cpu from mainbus so that cpu can attached to other buses (like ofbus).
1.1.2.2	23-Apr-2001	bouyer	Sync with HEAD.
1.1.2.1	20-Apr-2001	bouyer	file cpu.c was added on branch thorpej_scsipi on 2001-04-23 09:41:33 +0000
1.3.4.7	10-Oct-2002	jdolecek	sync kqueue with -current; this includes merge of gehenna-devsw branch, merge of i386 MP branch, and part of autoconf rototil work
1.3.4.6	06-Sep-2002	jdolecek	sync kqueue branch with HEAD
1.3.4.5	23-Jun-2002	jdolecek	catch up with -current on kqueue branch
1.3.4.4	16-Mar-2002	jdolecek	Catch up with -current.
1.3.4.3	11-Feb-2002	jdolecek	Sync w/ -current.
1.3.4.2	10-Jan-2002	thorpej	Sync kqueue branch with -current.
1.3.4.1	13-Sep-2001	thorpej	Update the kqueue branch to HEAD.
1.3.2.1	21-Jun-2001	nathanw	Catch up to -current.
1.4.2.1	01-Oct-2001	fvdl	Catch up with -current.
1.6.2.1	12-Nov-2001	thorpej	Sync the thorpej-mips-cache branch with -current.
1.9.2.11	07-Jan-2003	thorpej	Sync with HEAD.
1.9.2.10	11-Dec-2002	thorpej	Sync with HEAD.
1.9.2.9	18-Oct-2002	nathanw	Catch up to -current.
1.9.2.8	17-Sep-2002	nathanw	Catch up to -current.
1.9.2.7	01-Aug-2002	nathanw	Catch up to -current.
1.9.2.6	20-Jun-2002	nathanw	Catch up to -current.
1.9.2.5	17-Apr-2002	nathanw	Catch up to -current.
1.9.2.4	01-Apr-2002	nathanw	Catch up to -current. (CVS: It's not just a program. It's an adventure!)
1.9.2.3	28-Feb-2002	nathanw	Catch up to -current.
1.9.2.2	08-Jan-2002	nathanw	Catch up to -current.
1.9.2.1	06-Nov-2001	nathanw	file cpu.c was added on branch nathanw_sa on 2002-01-08 00:23:08 +0000
1.37.4.2	29-Jul-2002	lukem	Pull up revision 1.40 (requested by thorpej in ticket #549): Handle i80200 step D0 and i80321 step B0
1.37.4.1	07-Jun-2002	thorpej	pullup-1-6 ticket #208: syssrc/sys/arch/arm/arm/cpufunc.c 1.46 syssrc/sys/arch/arm/arm32/cpu.c 1.38 syssrc/sys/arch/arm/include/armreg.h 1.19 Original log message: Add the CPU ID for the 600MHz i80321 part.
1.37.2.4	30-Aug-2002	gehenna	catch up with -current.
1.37.2.3	16-Jul-2002	gehenna	catch up with -current.
1.37.2.2	14-Jul-2002	gehenna	catch up with -current.
1.37.2.1	19-May-2002	gehenna	Remove unnecessary #include
1.45.2.1	19-Oct-2002	bjh21	In cpu_attach(), allocate an idle PCB if the CPU doesn't already have one (which the boot CPU won't).
1.51.2.4	10-Nov-2005	skrll	Sync with HEAD. Here we go again...
1.51.2.3	21-Sep-2004	skrll	Fix the sync with head I botched.
1.51.2.2	18-Sep-2004	skrll	Sync with HEAD.
1.51.2.1	03-Aug-2004	skrll	Sync with HEAD
1.59.2.4	17-Mar-2008	yamt	sync with head.
1.59.2.3	03-Sep-2007	yamt	sync with head.
1.59.2.2	26-Feb-2007	yamt	sync with head.
1.59.2.1	21-Jun-2006	yamt	sync with head.
1.61.10.1	19-Apr-2006	elad	sync with head - hopefully this will work
1.61.8.1	01-Apr-2006	yamt	sync with head.
1.61.6.1	22-Apr-2006	simonb	Sync with head.
1.61.4.1	09-Sep-2006	rpaulo	sync with head
1.62.14.2	21-Feb-2007	snj	branches: 1.62.14.2.4; Pull up following revision(s) (requested by matt in ticket #457): sys/arch/arm/include/cpufunc.h: revision 1.38 sys/arch/arm/arm/cpufunc.c: revision 1.78 sys/arch/arm/arm/cpufunc_asm_arm10.S: revision 1.6 sys/arch/arm/include/armreg.h: revision 1.37 sys/arch/arm/arm32/cpu.c: revision 1.64 sys/arch/arm/arm/cpufunc_asm_armv5.S: revision 1.3 sys/arch/arm/include/cpuconf.h: revision 1.13 sys/arch/arm/conf/files.arm: revision 1.82 sys/arch/arm/arm/cpufunc_asm_armv5_ec.S: revision 1.1 Scott Allan in http://mail-index.netbsd.org/port-arm/2006/07/31/0000.html Patch to add support for ARM9E
1.62.14.1	21-Feb-2007	snj	Pull up following revision(s) (requested by matt in ticket #457): sys/arch/arm/arm32/cpu.c: revision 1.63 From Scott Allan in http://mail-index.netbsd.org/port-arm/2006/07/26/0000.html identify_arm_cpu() prints out a helpful message when it detects that you're trying to run on a CPU that you didn't configure for. Unfortunately, the check for class_option being NULL is backward, so it either won't print the class_option, or it will try to dereference a NULL. The patch just flips the != NULL to be == NULL.
1.62.14.2.4.1	10-Nov-2007	matt	Add AT91 support from Sami Kantoluoto Add TI OMAP2430 support from Marty Fouts @ Danger Inc
1.62.10.1	12-Jan-2007	ad	Sync with head.
1.64.14.1	22-May-2007	matt	Update to HEAD.
1.64.8.1	11-Jul-2007	mjf	Sync with head.
1.64.6.1	27-May-2007	ad	Sync with head.
1.64.2.1	29-Mar-2007	skrll	Adapt arm32. Thanks to scw for helping out. Tested on my cats (SA1) XXX hydra should die. i've made some changes, but no guarantees.
1.65.12.2	23-Mar-2008	matt	sync with HEAD
1.65.12.1	28-Aug-2007	matt	Add 1176 and print arm11 rev as rVpR (r0p6, r1p0).
1.65.10.2	21-Mar-2008	chris	Sync with head.
1.65.10.1	01-Jan-2008	chris	Sync with HEAD.
1.66.16.3	17-Jan-2009	mjf	Sync with HEAD.
1.66.16.2	02-Jun-2008	mjf	Sync with HEAD.
1.66.16.1	03-Apr-2008	mjf	Sync with HEAD.
1.66.12.1	24-Mar-2008	keiichi	sync with head.
1.67.4.5	09-Oct-2010	yamt	sync with head
1.67.4.4	11-Aug-2010	yamt	sync with head.
1.67.4.3	11-Mar-2010	yamt	sync with head
1.67.4.2	04-May-2009	yamt	sync with head.
1.67.4.1	16-May-2008	yamt	sync with head.
1.67.2.1	18-May-2008	yamt	sync with head.
1.68.6.1	13-Dec-2008	haad	Update haad-dm branch to haad-dm-base2.
1.71.12.1	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.71.4.1	20-Jan-2013	bouyer	Pull up following revision(s) (requested by msaitoh in ticket #1841): sys/arch/arm/arm32/cpu.c: revision 1.89 S/,/;/
1.72.4.3	21-Apr-2011	rmind	sync with head
1.72.4.2	05-Mar-2011	rmind	sync with head
1.72.4.1	03-Jul-2010	rmind	sync with head
1.72.2.2	22-Oct-2010	uebayasi	Sync with HEAD (-D20101022).
1.72.2.1	17-Aug-2010	uebayasi	Sync with HEAD.
1.77.2.1	06-Jun-2011	jruoho	Sync with HEAD.
1.78.10.2	08-Feb-2013	riz	Pull up following revision(s) (requested by msaitoh in ticket #788): sys/arch/arm/arm32/cpu.c: revision 1.89 S/,/;/
1.78.10.1	09-Aug-2012	jdc	branches: 1.78.10.1.2; Pull up revisions: src/sys/arch/evbarm/dev/plcomreg.h revisions 1.2,1.3,1.4 src/sys/arch/evbarm/conf/INTEGRATOR revision 1.65 src/sys/arch/evbarm/dev/plcom.c revisions 1.34,1.35,1.36,1.37,1.38,1.39,1.40 src/sys/arch/evbarm/ifpga/plcom_ifpga.c revisions 1.12,1.13,1.14 src/sys/arch/evbarm/dev/plcomvar.h revisions 1.9,1.10,1.11 src/sys/arch/evbarm/ifpga/plcom_ifpgavar.h revision 1.2 src/sys/arch/arm/arm/cpufunc.c revisions 1.105,1.108 src/sys/arch/arm/arm32/cpu.c revision 1.79 src/sys/arch/arm/include/armreg.h revisions 1.49,1.54 src/sys/arch/arm/arm32/pmap.c revision 1.229 src/sys/arch/arm/arm32/arm32_machdep.c revision 1.77 src/sys/arch/arm/include/cpu.h revision 1.64 src/sys/arch/arm/arm/cpufunc_asm_arm1136.S revision 1.3 src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S revision 1.1 src/sys/arch/arm/conf/files.arm revision 1.106 src/sys/arch/arm/include/cpufunc.h revision 1.57 src/sys/dev/sdmmc/sdhc.c revisions 1.14,1.24 src/sys/dev/sdmmc/sdhcvar.h revisions 1.7,1.8 src/sys/arch/evbarm/ifpga/ifpgareg.h revision 1.4 src/sys/arch/evbarm/integrator/integrator_machdep.c revision 1.69 src/sys/arch/arm/broadcom/bcm2835_dma.c revision 1.1 src/sys/arch/arm/broadcom/bcm2835_emmc.c revision 1.1 src/sys/arch/arm/broadcom/bcm2835_intr.c revision 1.1 src/sys/arch/arm/broadcom/bcm2835_intr.h revision 1.1 src/sys/arch/arm/broadcom/bcm2835_obio.c revision 1.1 src/sys/arch/arm/broadcom/bcm2835_plcom.c revision 1.1 src/sys/arch/arm/broadcom/bcm2835_pm.c revision 1.1 src/sys/arch/arm/broadcom/bcm2835_pmvar.h revision 1.1 src/sys/arch/arm/broadcom/bcm2835_space.c revision 1.1 src/sys/arch/arm/broadcom/bcm2835_tmr.c revision 1.1 src/sys/arch/arm/broadcom/bcm2835reg.h revision 1.1 src/sys/arch/arm/broadcom/bcm2835var.h revision 1.1 src/sys/arch/arm/broadcom/bcm_amba.h revision 1.1 src/sys/arch/arm/broadcom/files.bcm2835 revision 1.1 src/sys/arch/evbarm/Makefile revision 1.9 src/sys/arch/evbarm/conf/RPI revision 1.1 src/sys/arch/evbarm/conf/files.rpi revision 1.1 src/sys/arch/evbarm/conf/mk.rpi revision 1.1 src/sys/arch/evbarm/conf/std.rpi revision 1.1 src/sys/arch/evbarm/rpi/genassym.cf revision 1.1 src/sys/arch/evbarm/rpi/rpi.h revision 1.1 src/sys/arch/evbarm/rpi/rpi_machdep.c revision 1.1 src/sys/arch/evbarm/rpi/rpi_start.S revision 1.1,1.2 src/etc/etc.evbarm/Makefile.inc revision 1.28 (requested by skrll in ticket #454). don't mix #define<TAB> and #define<SPACE> in a file. avoid warning with options PLCOM_DEBUG for INTEGRATOR. Rename register values. No functional change - same code before and after. Existing names are prefixed with PL01X_ where they're common between the PL010 and the PL011. The PL010_/PL011_ prefixes are added where they're found only on the respective chips. Replace the simple_lock with a kmutex_t. Update the locking to match com(4) in the few places it didn't already. DOH. Replace a line that got accidently deleted in the last commit. device_t/softc split struct device * -> device_t struct cfdata * -> cfdata_t Add the 'Z' to the 1176 cpu product name. ok matt@ Fix locking botch introduced in 1.36. Fix a KASSERT. From/OK'ed by matt@ Fix racy softint dispatch that lead to KASSERT(si->si_active) in softint_execute Discussed with matt@. "Looks good to me" Add the documented ARM11[37]6 Auxiliary control register defines. Add support for the ARM1176JZS Add a flag for the lack of LED_ON in HOST_CTL (ti omap3 doesn't do that). Provide a method for attachments to specify capabilites. Add support for the PL011 to plcom. Pull across a bunch of fixes from com(4) while I'm here and do some other tidyup. Tested on a RaspberryPi. PL010 not tested. Initial commit of support for the RaspberryPI (www.raspberrypi.org) This is enough for serial console via the gpio header pins and to get to multiuser. A huge thank you to Matt Thomas for all his help. Add RPI to KERNEL_SETS Remove #if 0 code.
1.78.10.1.2.1	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.78.8.1	02-Jun-2012	mrg	sync to latest -current.
1.78.4.4	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.78.4.3	16-Jan-2013	yamt	sync with (a bit old) head
1.78.4.2	30-Oct-2012	yamt	sync with head
1.78.4.1	23-May-2012	yamt	sync with head.
1.86.2.5	03-Dec-2017	jdolecek	update from HEAD
1.86.2.4	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.86.2.3	23-Jun-2013	tls	resync from head
1.86.2.2	25-Feb-2013	tls	resync with head
1.86.2.1	20-Nov-2012	tls	Resync to 2012-11-19 00:00:00 UTC
1.96.2.2	18-May-2014	rmind	sync with head
1.96.2.1	28-Aug-2013	rmind	sync with head
1.104.4.2	26-Jul-2017	snj	Pull up following revision(s) (requested by jmcneill in ticket #1435): sys/arch/arm/arm32/cpu.c: 1.113 via patch sys/arch/arm/broadcom/bcm2835_bsc.c: 1.6 via patch sys/arch/arm/broadcom/bcm2835_plcom.c: 1.4 via patch sys/arch/arm/cortex/gtmr.c: 1.18 via patch sys/arch/arm/include/armreg.h: 1.110 via patch sys/arch/arm/include/vfpreg.h: 1.15 via patch sys/arch/arm/vfp/vfp_init.c: 1.50 via patch sys/arch/evbarm/rpi/rpi_machdep.c: 1.59, 1.70-1.72 via patch sys/arch/evbarm/rpi/vcprop.h: 1.16 Get the RPI3 working (in aarch32 mode) by recognising Cortex A53 CPUs. While I'm here add some A57/A72 info as well. My RPI3 works with FB console - the uart needs some help with its clocks. -- Do invalidate the cache as RPI2 build with Clang can't fetch the memory config otherwise. -- Use the VC property mailbox to request the UART clock rate and use it appropriately Newer firmwares use 48MHz -- Disable BSC0 on Raspberry Pi 3 and Zero W boards. -- Interrupts are enabled before the timer is configured. Ensure that the timer is disabled when attaching so it doesn't go crazy between the time interrupts are enabled and clocks are initialized. My RPI3 makes it multi-user now. -- Enable UART0 (PL011) on GPIO header for Raspberry Pi 3 / Zero W
1.104.4.1	06-Apr-2015	snj	Pull up following revision(s) (requested by jmcneill in ticket #663): sys/arch/arm/arm32/cpu.c: revision 1.105 Increase the `freqbuf' buffer that holds the result of humanize_number(). Now it prints 1600 Mhz instead of 1 Ghz. Pitty enough humanize_number(9) doesn't do 1.6 Ghz type output.
1.106.2.7	28-Aug-2017	skrll	Sync with HEAD
1.106.2.6	05-Oct-2016	skrll	Sync with HEAD
1.106.2.5	19-Mar-2016	skrll	Sync with HEAD
1.106.2.4	27-Dec-2015	skrll	Sync with HEAD (as of 26th Dec)
1.106.2.3	22-Sep-2015	skrll	Sync with HEAD
1.106.2.2	06-Jun-2015	skrll	Sync with HEAD
1.106.2.1	06-Apr-2015	skrll	Sync with HEAD
1.115.6.1	13-Dec-2017	matt	Add Cortex A35
1.116.4.3	13-Apr-2020	martin	Mostly merge changes from HEAD upto 20200411
1.116.4.2	08-Apr-2020	martin	Merge changes from current as of 20200406
1.116.4.1	10-Jun-2019	christos	Sync with HEAD
1.116.2.4	26-Jan-2019	pgoyette	Sync with HEAD
1.116.2.3	18-Jan-2019	pgoyette	Synch with HEAD
1.116.2.2	20-Oct-2018	pgoyette	Sync with head
1.116.2.1	06-Sep-2018	pgoyette	Sync with HEAD Resolve a couple of conflicts (result of the uimin/uimax changes)
1.129.4.2	09-Jan-2020	snj	Pull up following revision(s) (requested by martin in ticket #614): sys/arch/aarch64/aarch64/cpu.c: 1.32 sys/arch/arm/arm32/cpu.c: 1.138 sys/dev/fdt/fdtbus.c: 1.31 When attaching the first fdtbus, use the root "comptabile" (or failing that: "model") property to set the cpu model (in userland aka sysctl hw.model). When attaching the first cpu, do not overwrite a cpu model if it already had been set.
1.129.4.1	23-Oct-2019	martin	Pull up following revision(s) (requested by jmcneill in ticket #359): sys/arch/aarch64/aarch64/locore.S: revision 1.42 sys/arch/aarch64/aarch64/locore.S: revision 1.43 sys/arch/aarch64/aarch64/locore.S: revision 1.44 sys/arch/arm/fdt/cpu_fdt.c: revision 1.28 sys/arch/aarch64/include/cpu.h: revision 1.14 sys/arch/aarch64/include/param.h: revision 1.12 sys/arch/arm/arm32/cpu.c: revision 1.133 sys/arch/arm/arm32/cpu.c: revision 1.134 sys/arch/arm/include/cpu.h: revision 1.101 sys/arch/arm/acpi/cpu_acpi.c: revision 1.7 sys/arch/aarch64/aarch64/cpu.c: revision 1.23 sys/arch/aarch64/aarch64/cpu.c: revision 1.24 sys/arch/aarch64/aarch64/cpu.c: revision 1.25 Increase aarch64 MAXCPUS to 256. - Invalidate dcache before polling AP hatched status - Avoid overlap between BP and last AP stack. AP stacks are now in order of increasing address order. Spotted by and idea from mlelstv. - Use separate cacheline aligned arrays for mbox and hatched as before. - cpu_hatched_p only for MULTIPROCESSOR
1.136.2.3	29-Feb-2020	ad	Sync with head.
1.136.2.2	25-Jan-2020	ad	Sync with head.
1.136.2.1	17-Jan-2020	ad	Sync with head.
1.147.6.1	01-Aug-2021	thorpej	Sync with HEAD.
1.108	07-Oct-2025	skrll	Retire the locore.h assembly versions of IRQ{enable,disable} in favour of the "experimental" cpuswitch.S versions, but rename them IRQ_{DISABLE,ENABLE} and have them take a temporary register which is only used for < armv6.
1.107	01-Mar-2023	riastradh	arm32: Optimization: Omit needless membar when triggering softint. When we are triggering a softint, it can't already hold any mutexes. So any path to mutex_exit(mtx) must go via mutex_enter(mtx), which is always done with atomic r/m/w, and we need not issue any explicit barrier between ci->ci_curlwp = softlwp and a potential load of mtx->mtx_owner in mutex_exit. PR kern/57240 XXX pullup-8 XXX pullup-9 XXX pullup-10
1.106	23-Feb-2023	riastradh	arm32: Add missing barriers in cpu_switchto. Details in comments. PR kern/57240 XXX pullup-8 XXX pullup-9 XXX pullup-10
1.105	30-May-2021	dholland	branches: 1.105.12; typo in comment
1.104	21-Nov-2020	skrll	branches: 1.104.4; 1.104.6; Ensure that r5 contains curlwp before DO_AST_AND_RESTORE_ALIGNMENT_FAULTS in lwp_trampoline as required by the move to make ASTs operate per-LWP rather than per-CPU. Thanks to martin@ for bisecting the amap corruption he was seeing and testing this fix.
1.103	15-Aug-2020	skrll	branches: 1.103.2; #ifdef _ARM_ARCH_7 the dmbs
1.102	14-Aug-2020	skrll	Mirror the changes to aarch64 and - Switch to TPIDRPRW_IS_CURLWP, because curlwp is accessed much more often by MI code. It also makes curlwp preemption safe, - Make ASTs operate per-LWP rather than per-CPU, otherwise sometimes LWPs can see spurious ASTs (which doesn't cause a problem, it just means some time may be wasted). - Make sure ASTs are always set on the same CPU as the target LWP, and delivered via IPI if posted from a remote CPU so that they are resolved quickly. - Add some cache line padding to struct cpu_info. - Add a memory barrier in a couple of places where ci_curlwp is set. This is needed whenever an LWP that is resuming on the CPU could hold an adaptive mutex. The barrier needs to drain the CPU's store buffer, so that the update to ci_curlwp becomes globally visible before the LWP can resume and call mutex_exit().
1.101	10-Jul-2020	skrll	Add support for KASAN on ARMv[67] Thanks to maxv for many pointers and reviews.
1.100	06-Jul-2020	skrll	Whitespace
1.99	03-Jul-2020	skrll	KNF (sort #includes)
1.98	11-Feb-2020	skrll	G/C
1.97	08-Jan-2020	skrll	oldlwp is always non-NULL in cpu_switchto so remove the test for NULL.
1.96	08-Jan-2020	ad	Hopefully fix some problems seen with MP support on non-x86, in particular where curcpu() is defined as curlwp->l_cpu: - mi_switch(): undo the ~2007ish optimisation to unlock curlwp before calling cpu_switchto(). It's not safe to let other actors mess with the LWP (in particular l->l_cpu) while it's still context switching. This removes l->l_ctxswtch. - Move the LP_RUNNING flag into l->l_flag and rename to LW_RUNNING since it's now covered by the LWP's lock. - Ditch lwp_exit_switchaway() and just call mi_switch() instead. Everything is in cache anyway so it wasn't buying much by trying to avoid saving old state. This means cpu_switchto() will never be called with prevlwp == NULL. - Remove some KERNEL_LOCK handling which hasn't been needed for years.
1.95	29-Oct-2019	joerg	branches: 1.95.2; Explicitly annotate FPU requirements for LLVM MC. When using GCC, this annotations change the global state, but there is no push/pop functionality for .fpu to avoid this problem. The state is local to each inline assembler block with LLVM MC.
1.94	13-Sep-2019	skrll	Typo in comment
1.93	22-Nov-2018	skrll	branches: 1.93.4; Typo in comment
1.92	01-Jul-2017	skrll	branches: 1.92.4; 1.92.6; Whitespace (align comments)
1.91	01-Jul-2017	skrll	Trailing whitespace
1.90	08-Apr-2015	matt	branches: 1.90.10; Make TPIDRPRW_IS_CURLWP work for MULTIPROCESSOR. get curcpu() from new lwp. don't set lwp l_cpu (already done). Remove support for __HAVE_UNNESTED_INTRS don't set curlwp until after we are done saving the oldlwp. disable interrupts when setting curlwp/kernel stack pointer. Overall, these changes simplify cpu_switchto even more.
1.89	24-Mar-2015	skrll	There is no need to save/restore l_private in softint_switch now that cpu_switchto is fixed
1.88	24-Mar-2015	matt	Rework register usage in cpu_switchto so curcpu() is preserved across ras_lookup. Only set vfp & tpid registers and do ras lookups if new lwp is not LW_SYSTEM. (tested on RPI and atf tests on BPI by skrll).
1.87	22-Mar-2015	matt	Fix register usage in softint_switch. load / restore l_private across softint_dispatch
1.86	22-Mar-2015	matt	Make sure to save the user thread point in softint_switch in case it was set just before we got an interrupt. Otherwise if the softint blocks, the old value would be restored and change lost.
1.85	18-Oct-2014	snj	branches: 1.85.2; src is too big these days to tolerate superfluous apostrophes. It's "its", people!
1.84	15-Jun-2014	ozaki-r	branches: 1.84.2; Fix wrong instruction; mcr => mrc
1.83	28-Mar-2014	matt	branches: 1.83.2; ARM_MMU_EXTENDED support.
1.82	26-Feb-2014	matt	Move pmap_recent_user to ci->ci_pmap_lastuser and pmap_previous_active_lwp to ci->ci_lastlwp. Fix some comments.
1.81	26-Dec-2013	joerg	Replicate mcr with equivalent vms instruction.
1.80	01-Dec-2013	joerg	For load/store double, name the second register explicitly.
1.79	18-Aug-2013	matt	Move parts of cpu.h that are not needed by MI code in <arm/locore.h> Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h> Use <arm/asm.h> instead of <machine/arm.h>
1.78	18-Aug-2013	matt	Move parts of cpu.h that are not needed by MI code in <arm/locore.h> Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h> Use <arm/asm.h> instead of <machine/arm.h>
1.77	27-Feb-2013	matt	branches: 1.77.6; Don't include <machine/param.h> since we should be getting that stuff from "assym.h"
1.76	17-Dec-2012	matt	Make sure to load the FPEXC context on context switch (if there a VFP) so that the VFP state will be what the LWP expects. (This isn't needed on PPC or MIPS since their FPU/VEC state is reflected in the PSL/CPO_STATUS which is handled automatically.)
1.75	10-Dec-2012	matt	Rename pcb_sp/PCB_SP to pcb_ksp/PCB_KSP so that ipsec.c will compile.
1.74	05-Dec-2012	matt	ARMFPE hasn't compiled since NetBSD 4. Remove it. Complete support for FPU_VFP. fpregs now contains vfpreg. XXX vfpreg only has space for 16 64-bit FP registers though VFPv3 and later have 32 64-bit FP registers.
1.73	08-Nov-2012	skrll	Use ENTRY_NP for lwp_trampoline
1.72	05-Sep-2012	matt	branches: 1.72.2; After calling lwp_startup, set fp to 0 to terminate call stack.
1.71	01-Sep-2012	matt	Need to do a GET_CURCPU(r4) before invoking DO_AST_AND_RESTORE_ALIGNMENT_FAULTS
1.70	01-Sep-2012	matt	blx reg is V5, not V4T
1.69	31-Aug-2012	skrll	DO_AST_AND_RESTORE_ALIGNMENT_FAULTS needs AST_ALIGNMENT_FAULT_LOCALS
1.68	29-Aug-2012	matt	Fix typo.
1.67	29-Aug-2012	matt	Rename ARM options PROCESS_ID_IS_CUR{CPU,LWP} to TPIDRPRW_IS_CUR{CPU,LWP} since TPIDRPRW is the cp15 register name. Initialize it early in start along with CI_ARM_CPUID. Remove other initializations. We alays have ci_curlwp. Enable TIPRPRW_IS_CURCPU in std.beagle. [tested on a beaglboard (cortex-a8)]
1.66	16-Aug-2012	matt	small rototill. pcb_flags is dead. PCB_NOALIGNFLT is now in stored l_md.md_flags as MDLWP_NOALIGNFLT. This avoids a few loads of the PCB in exception handling. pcb_tf has been moved to l_md.md_tf. Again this avoids a lot of pcb references just to access or set this. It also means that pcb doesn't need to accessed by MI code. Move pcb_onfault to after the pcb union. Add pcb_sp macro to make code prettier. Add lwp_settrapframe(l, tf) to set the l_md.md_tf field. Use lwp_trapframe to access it (was process_frame but that name was changed in a previous commit). Kill off curpcb in acorn26. Kill the checks for curlwp being NULL. Move TRAP_USERMODE from arm32/fault.c to frame.h and a __PROG26 version. Replace tests for usermode with that macro.
1.65	14-Aug-2012	matt	Kill curpcb/ci_curpcb. Use device_t in cpu_info. Add ci_softc (where ci_curpcb was so cpu_info doesn't change).
1.64	12-Aug-2012	matt	Rework VFP support to use PCU. Add emulation of instruction which save/restore the VFP FPSCR. Add a sysarch hook to VFP FPSCR manipulation. [The emulation will be used by libc to store/fetch exception modes and rounding mode on a per-thread basis.]
1.63	07-Apr-2011	matt	branches: 1.63.4; 1.63.12; Fetch user read-only thread and process id from l->l_private, not the pcb. (need to g/c the pcb field formerly used for this).
1.62	01-Feb-2011	matt	include "assym.h" instead of pte.h
1.61	14-Jan-2011	rmind	branches: 1.61.2; 1.61.4; Retire struct user, remove sys/user.h inclusions. Note sys/user.h header as obsolete. Remove USER_TO_UAREA/UAREA_TO_USER macros. Various #include fixes and review by matt@.
1.60	10-Dec-2009	rmind	branches: 1.60.4; Rename L_ADDR to L_PCB and amend some comments accordingly.
1.59	19-Nov-2008	matt	Use IF32_bits instead of I32_bit. Only disable/irq is __HAVE_UNNESTED_IRQS is undefined.
1.58	27-Apr-2008	matt	branches: 1.58.6; 1.58.8; 1.58.14; Merge kernel changes in matt-armv6 to HEAD.
1.57	20-Apr-2008	scw	branches: 1.57.2; There's really no need to switch VM contexts within cpu_switchto() as MI code always calls pmap_deactivate/pmap_activate on context switch. Instead, just record the last active lwp (or NULL if it exited) and defer switching VM context to pmap_activate(). This saves an additional function call overhead in cpu_switchto(). While here, g/c unused cpuswitch.S local .Lblock_userspace_access.
1.56	15-Mar-2008	rearnsha	branches: 1.56.2; VFP support.
1.55	19-Jan-2008	chris	branches: 1.55.2; 1.55.6; Optimize cpu_switchto to store the new PCB address in r7, rather than loading it from memory in 3 places. Also adjust ordering of a few loads to try and avoid stalling.
1.54	19-Jan-2008	chris	With the removal of IPKDB on arm, the undefined stack is only used to bounce into SVC32 mode, there is no per-process data stored on it. We can therefore use the undefined stack setup by the platform machdep.c as a system wide undefined stack. This removes the need for a per-process undefined stack, and the processor mode switching overhead it causes in cpu_switchto. The space freed in the USPACE is used to increase the per process kernel stack size.
1.53	13-Jan-2008	chris	Take a micro-optimization from FreeBSD/arm. When switching from SVC32->UND32 to read/write R13_und we don't need to clear the mode bits as: PSR_SVC32_MODE \| PSR_UND32_MODE = PSR_UND32_MODE While reading the code I also noted that interrupts are enabled for most of the function as pmap_switch returns with interrupts in the state they are on entry. This appears to be different to what the code after pmap_switch expects, in that the behaviour suggests they should be disabled. Because of this I've made the writing of R13_und explicitly disable. interupts as part of the mode switch. This also means that the IRQenableALL call is now redundant as the interrupts are already enabled. XXX: it's not clear if arm_fpe_core_changecontext should be called with interrupts disabled. Remove unused items: IRQdisableALL, IRQenableALL & Lcpufuncs. Tested on cats. lmbench shows no performance change.
1.52	12-Jan-2008	skrll	Add and fix a couple of comments.
1.51	12-Jan-2008	skrll	Push a switchframe in dumpsys and cpu_switchto, but as dumpsys calls other funcs a switchframe needs to be a multiple of 8 bytes. Stash sp as well in the switchframe to bump it to 24bytes. Setup the switchframe appropriately in cpu_lwp_fork. Remove savectx - nothing uses it. All of this make gdb's life much easier when dealing with crash dumps and live kernels. Reviewd by chris.
1.50	17-Oct-2007	garbled	branches: 1.50.2; 1.50.8; Merge the ppcoea-renovation branch to HEAD. This branch was a major cleanup and rototill of many of the various OEA cpu based PPC ports that focused on sharing as much code as possible between the various ports to eliminate near-identical copies of files in every tree. Additionally there is a new PIC system that unifies the interface to interrupt code for all different OEA ppc arches. The work for this branch was done by a variety of people, too long to list here. TODO: bebox still needs work to complete the transition to -renovation. ofppc still needs a bunch of work, which I will be looking at. ev64260 still needs to be renovated amigappc was not attempted. NOTES: pmppc was removed as an arch, and moved to a evbppc target.
1.49	15-Sep-2007	scw	ARM cpu_switchto() has been partially broken since yamt-idlelwp was merged as its cache/tlb management smarts relied too heavily on pre-merge context- switch behaviour. See PR kern/36548 for one manifestation of the breakage. To address this: - Ditch the shadow pmap variables in the PCB (pagedir, l1vec, dacr, cstate) as it was too easy for them to get out of sync with the pmap. - Re-write (and fix) the convoluted cpuswitch.S cache/tlb ASM code in C. It's only slightly less efficient, but is much more readable/maintainable. - Document cpufuncs.cf_context_switch() as being C-callable. - pmap_activate() becomes a no-op if the lwp's vmspace is already active. (Good performance win, since pmap_activate() is now invoked on every context-switch, even though ARM's cpu_switchto() already does all the grunt work) XXX: Some CPU-specific armXX_context_switch() implementations (arm67, arm7tdmi, arm8) always flush the I+D caches. This should not be necessary. Someone with access to hardware (acorn32?) needs to deal with this.
1.48	25-May-2007	skrll	branches: 1.48.6; 1.48.8; 1.48.10; 1.48.12; No need to check if oldl == newl in cpu_switchto. All the callers ensure this is never the case. Fixup a few comments while I'm here.
1.47	17-May-2007	yamt	merge yamt-idlelwp branch. asked by core@. some ports still needs work. from doc/BRANCHES: idle lwp, and some changes depending on it. 1. separate context switching and thread scheduling. (cf. gmcgarry_ctxsw) 2. implement idle lwp. 3. clean up related MD/MI interfaces. 4. make scheduler(s) modular.
1.46	19-Feb-2007	briggs	branches: 1.46.4; 1.46.6; 1.46.12; Get DOMAIN_CLIENT directly from arm/arm32/pte.h instead of from genassym to avoid redefinition when both assymh and pte.h are included (as in INTEGRATOR's intmmu.S, which uses more macros from pte.h).
1.45	09-Feb-2007	ad	branches: 1.45.2; Merge newlock2 to head.
1.44	13-May-2006	skrll	branches: 1.44.8; 1.44.12; Fix some more comments.
1.43	10-May-2006	skrll	Fix some comments.
1.42	11-Dec-2005	christos	branches: 1.42.4; 1.42.6; 1.42.8; 1.42.10; 1.42.12; merge ktrace-lwp.
1.41	15-Nov-2003	scw	branches: 1.41.16; - Add LOCKDEBUG-protected calls to sched_lock_idle() to cpu_switchto and the idle loop. They seem to have gone AWOL sometime in the past. Fixes port-arm/23390. - While here, tidy up the idle loop. - Add a cheap DIAGNOSTIC check for run queue sanity.
1.40	04-Nov-2003	scw	Fix a braino introduced in r1.37. Thanks to Tom Spindler for spotting it.
1.39	04-Nov-2003	dsl	Remove p_nras from struct proc - use LIST_EMPTY(&p->p_raslist) instead. Remove p_raslock and rename p_lwplock p_lock (one lock is enough). Simplify window test when adding a ras and correct test on VM_MAXUSER_ADDRESS. Avoid unpredictable branch in i386 locore.S (pad fields left in struct proc to avoid kernel bump)
1.38	23-Oct-2003	scw	Don't drop to spl0 in cpu_switch/cpu_switchto. Do it in the idle loop instead. With this change, we no longer need to save the current interrupt level in the switchframe. This is no great loss since both cpu_switch and cpu_switchto are always called at splsched, so the process' spl is effectively saved somewhere in the callstack. This fixes an evbarm problem reported by Allen Briggs: lwp gets into sa_switch -> mi_switch with newl != NULL when it's the last element on the runqueue, so it hits the second bit of: if (newl == NULL) { retval = cpu_switch(l, NULL); } else { remrunqueue(newl); cpu_switchto(l, newl); retval = 0; } mi_switch calls remrunqueue() and cpu_switchto() cpu_switchto unlocks the sched lock cpu_switchto drops CPU priority softclock is received schedcpu is called from softclock schedcpu hits the first if () {} block here: if (l->l_priority >= PUSER) { if (l->l_stat == LSRUN && (l->l_flag & L_INMEM) && (l->l_priority / PPQ) != (l->l_usrpri / PPQ)) { remrunqueue(l); l->l_priority = l->l_usrpri; setrunqueue(l); } else l->l_priority = l->l_usrpri; } Since mi_switch has already run remrunqueue, the LWP has been removed, but it's not been put back on any queue, so the remrunqueue panics.
1.37	13-Oct-2003	scw	A couple of Xscale tweaks: - Use the "clz" instruction to pick a run-queue, instead of using the ffs-by-table-lookup method. - Use strd instead of stmia where possible. - Use multiple ldr instructions instead of ldmia where possible.
1.36	23-Jun-2003	martin	branches: 1.36.2; Make sure to include opt_foo.h if a defflag option FOO is used.
1.35	23-Jun-2003	chris	Fix for port-arm/21962. Rather than fixing the #ifndef spl0, I removed the test as spl0 is actually a macro for splx(0). The code now calls splx(0) (note building with the #ifdef fixed, caused the build to fail on a GENERIC acorn32 kernel.)
1.34	31-May-2003	kristerw	Fix LINTSTUB comments.
1.33	21-May-2003	thorpej	Remove #ifdefs supporting the old pmap, switching fully to the new.
1.32	26-Apr-2003	chris	Remove a strh. I don't think it's available on archv3 and it doesn't work on acorn32's with an SA110 in them as the bus doesn't support halfword transfers.
1.31	22-Apr-2003	thorpej	Some ARM32_PMAP_NEW-related cleanup: * Define a new "MMU type", ARM_MMU_SA1. While the SA-1's MMU is basically compatible with the generic, the SA-1 cache does not have a write-through mode, and it is useful to know have an indication of this. * Add a new PMAP_NEEDS_PTE_SYNC indicator, and try to evaluate it at compile time. We evaluate it like so: - If SA-1-style MMU is the only type configured -> 1 - If SA-1-style MMU is not configured -> 0 - Otherwise, defer to a run-time variable. If PMAP_NEEDS_PTE_SYNC might evaluate to true (SA-1 only or run-time check), then we also define PMAP_INCLUDE_PTE_SYNC so that e.g. assembly code can include the necessary run-time support. PMAP_INCLUDE_PTE_SYNC largely replaces the ARM32_PMAP_NEEDS_PTE_SYNC manual setting Steve included with the original new pmap. * In the new pmap, make pmap_pte_init_generic() check to see if the CPU has a write-back cache. If so, init the PT cache mode to C=1,B=0 to get write-through mode. Otherwise, init the PT cache mode to C=1,B=1. * Add a new pmap_pte_init_arm8(). Old pmap, same as generic. New pmap, sets page table cacheability to 0 (ARM8 has a write-back cache, but flushing it is quite expensive). * In the new pmap, make pmap_pte_init_arm9() reset the PT cache mode to C=1,B=0, since the write-back check in generic gets it wrong for ARM9, since we use write-through mode all the time on ARM9 right now. (What this really tells me is that the test for write-through cache is less than perfect, but we can fix that later.) * Add a new pmap_pte_init_sa1(). Old pmap, same as generic. New pmap, does generic initialization, then resets page table cache mode to C=1,B=1, since C=1,B=0 does not produce write-through on the SA-1.
1.30	18-Apr-2003	scw	Add the generic arm32 bits of the new pmap, contributed by Wasabi Systems. Some features of the new pmap are: - It allows L1 descriptor tables to be shared efficiently between multiple processes. A typical "maxusers 32" kernel, where NPROC is set to 532, requires 35 L1s. A "maxusers 2" kernel runs quite happily with just 4 L1s. This completely solves the problem of running out of contiguous physical memory for allocating new L1s at runtime on a busy system. - Much improved cache/TLB management "smarts". This change ripples out to encompass the low-level context switch code, which is also much smarter about when to flush the cache/TLB, and when not to. - Faster allocation of L2 page tables and associated metadata thanks, in part, to the pool_cache enhancements recently contributed to NetBSD by Wasabi Systems. - Faster VM space teardown due to accurate referenced tracking of L2 page tables. - Better/faster cache-alias tracking. The new pmap is enabled by adding options ARM32_PMAP_NEW to the kernel config file, and making the necessary changes to the port-specific initarm() function. Several ports have already been converted and will be committed shortly.
1.29	17-Jan-2003	thorpej	Merge the nathanw_sa branch.
1.28	19-Oct-2002	bjh21	branches: 1.28.2; Undo recent cpu_switch register usage changes in order to decrease nathanw_sa merge pain.
1.27	18-Oct-2002	bjh21	The grand cpu_switch register reshuffle! In particular, use r8 to hold the old process, and r7 for medium-term scratch, saving r0-r3 for things we don't need saved over function calls. This gets rid of five register-to-register MOVs.
1.26	18-Oct-2002	bjh21	In cpu_switch(), stack more registers at the start of the function, and hence save fewer into the PCB. This should give me enough free registers in cpu_switch to tidy things up and support MULTIPROCESSOR properly. While we're here, make the stacked registers into an APCS stack frame, so that DDB backtraces through cpu_switch() will work. This also affects cpu_fork(), which has to fabricate a switchframe and PCB for the new process.
1.25	15-Oct-2002	bjh21	Switch to using the MI C versions of setrunqueue() and remrunqueue(). GCC produces almost exactly the same instructions as the hand-assembled versions, albeit in a different order. It even found one place where it could shave one off. Its insistence on creating a stack frame might slow things down marginally, but not, I think, enough to matter.
1.24	14-Oct-2002	bjh21	Continue the " - . - 8" purge. Specifically: add rd, pc, #foo - . - 8 -> adr rd, foo ldr rd, [pc, #foo - . - 8] -> ldr rd, foo Also, when saving the return address for a function pointer call, use "mov lr, pc" just before the call unless the return address is somewhere other than just after the call site. Finally, a few obvious little micro-optimisations like using LDR directly rather than ADR followed by LDR, and loading directly into PC rather than bouncing via R0.
1.23	13-Oct-2002	bjh21	Instead of "add rd, pc, #foo - . - 8", use either "adr rd, foo" or (where appropriate) "mov lr, pc". This makes things slightly less confusing and ugly.
1.22	12-Oct-2002	bjh21	Move curpcb into struct cpu_info in MULTIPROCESSOR kernels.
1.21	09-Oct-2002	bjh21	Use ADR rather than an explicit ADD from PC.
1.20	08-Oct-2002	bjh21	Remove an outdated register assignment comment.
1.19	05-Oct-2002	bjh21	Minimal changes to allow a kernel with "options MULTIPROCESSOR" to compile and boot multi-user on a single-processor machine. Many of these changes are wildly inappropriate for actual multi-processor operation, and correcting this will be my next task.
1.18	31-Aug-2002	thorpej	Add machine-dependent bits of RAS for arm32.
1.17	17-Aug-2002	thorpej	More local label fixups.
1.16	17-Aug-2002	thorpej	Must ... micro ... optimize! * Save an instruction in the transition from idle to have-process-to- switch-to, and eliminate two instructions that cause datadep-stalls on StrongARM And XScale (one in each idle block). * Rearrange some other instructions to avoid datadep-stalls on StrongARM and XScale. * Since cpu_do_powersave == 0 is by far the common case, avoid a pipeline flush by reordering the two idle blocks.
1.15	16-Aug-2002	thorpej	* Add a new machdep.powersave sysctl, which controls the use of the CPU's "sleep" function in the idle loop. * Default all CPUs to not use powersave, except for the PDA processors (SA11x0 and PXA2x0). This significantly reduces inteterrupt latency in high-performance applications (and was good to squeeze another ~10% out of an XScale IOP on a Gig-E benchmark).
1.14	15-Aug-2002	briggs	* Use local label names (.Lfoo vs. (Lfoo or foo)) * When moving from cpsr, use "cpsr" instead of "cpsr_all" (which is provided, but doesn't make sense since mrs doesn't support fields like msr does).
1.13	14-Aug-2002	thorpej	We only need to modify the CPSR's control field, so use cpsr_c rather than cpsr_all.
1.12	14-Aug-2002	chris	Tweak asm to avoid a couple of stalls.
1.11	12-Aug-2002	thorpej	Rearrange the beginning of cpu_switch() slightly to reduce data-dep stalls on StrongARM and XScale.
1.10	12-Aug-2002	thorpej	Make a slight tweak to register usage to save an instruction.
1.9	06-Aug-2002	thorpej	Rearrange the exit path so that we don't do a idcache_wbinv_all twice when a process exits.
1.8	06-Aug-2002	thorpej	* Pass proc0 to switch_exit(), to make this a little more like the nathanw_sa branch. * In switch_exit(), set the outgoing-proc register to NULL (rather than proc0) so that we actually use the "exiting process" optimization in cpu_switch().
1.7	14-May-2002	chris	branches: 1.7.2; Implement scheduler lock protocol, this fixes PR arm/10863. Also add correct locking when freeing pages in pmap_destroy (fix from potr) This now means that arm32 kernels can be built with LOCKDEBUG enabled. (only tested on cats though)
1.6	25-Jan-2002	thorpej	Overhaul of the ARM cache code. This is mostly a simplification pass. Rather than providing a whole slew of cache operations that aren't ever used, distill them down to some useful primitives: icache_sync_all Synchronize I-cache icache_sync_range Synchronize I-cache range dcache_wbinv_all Write-back and Invalidate D-cache dcache_wbinv_range Write-back and Invalidate D-cache range dcache_inv_range Invalidate D-cache range dcache_wb_range Write-back D-cache range idcache_wbinv_all Write-back and Invalidate D-cache, Invalidate I-cache idcache_wbinv_range Write-back and Invalidate D-cache, Invalidate I-cache range Note: This does not yet include an overhaul of the actual asm files that implement the primitives. Instead, we've provided a safe default for each CPU type, and the individual CPU types can now be optimized one at a time.
1.5	29-Nov-2001	thorpej	Provide a way for platforms to move away from the old RiscPC-centric interrupt code. Garbage-collect some unused stuff.
1.4	19-Nov-2001	chris	Give the idle loop a non-profiled entry, means it appears in profile info correctly (rather than all it's time being under remrunqueue) switch_exit only needs to take 1 parameter, it loads the value of proc0 into R1 itself Fixup some comments to reflect the real state of things. Tweak a couple of bits of asm to avoid a load delay. remove excess code for setting curpcb and curproc.
1.3	11-Nov-2001	chris	branches: 1.3.2; Correct comments for ffs algoritm (it isn't using register r0)
1.2	16-Sep-2001	matt	branches: 1.2.2; Fix .type which uses wrong symbol name.
1.1	28-Jul-2001	chris	branches: 1.1.2; 1.1.4; Move the generic arm32 files into arm/arm32 from arm32/arm32, tested kernel builds on cats and riscpc.
1.1.4.1	01-Oct-2001	fvdl	Catch up with -current.
1.1.2.6	06-Sep-2002	jdolecek	sync kqueue branch with HEAD
1.1.2.5	23-Jun-2002	jdolecek	catch up with -current on kqueue branch
1.1.2.4	11-Feb-2002	jdolecek	Sync w/ -current.
1.1.2.3	10-Jan-2002	thorpej	Sync kqueue branch with -current.
1.1.2.2	03-Aug-2001	lukem	update to -current
1.1.2.1	28-Jul-2001	lukem	file cpuswitch.S was added on branch kqueue on 2001-08-03 04:10:58 +0000
1.2.2.1	12-Nov-2001	thorpej	Sync the thorpej-mips-cache branch with -current.
1.3.2.28	07-Jan-2003	thorpej	Shave a couple of cycles off the beginning of cpu_switch().
1.3.2.27	03-Jan-2003	thorpej	Merge switch_exit() and switch_lwp_exit(), and hand-schedule the resulting function to avoid stalls on StrongARM and XScale.
1.3.2.26	31-Dec-2002	thorpej	Rename cpu_preempt() to cpu_switchto(), and make the caller remove the new process from its run queue before calling cpu_switchto(). While here, make a few cpu_switch() and cpu_switchto() implementations get the outgoing LWP from the args, rather than looking at the curlwp variable.
1.3.2.25	18-Oct-2002	nathanw	Catch up to -current.
1.3.2.24	18-Sep-2002	thorpej	Fix cpu_switch() after RAS integration from trunk.
1.3.2.23	17-Sep-2002	nathanw	Rearrange slightly and pass p, not l, to ras_lookup().
1.3.2.22	17-Sep-2002	nathanw	Catch up to -current.
1.3.2.21	20-Aug-2002	thorpej	Check to see if the incoming LWP has the same L1 table as the outgoing LWP. If so, then we can skip the cache purge and TTB reload. This results in a ~40% reduction in cache purges called from cpu_switch() in my test using two threaded applications which communicate with each other.
1.3.2.20	19-Aug-2002	thorpej	Partial (ARM only) sync with trunk -- significant performance improvements for XScale-based systems.
1.3.2.19	12-Aug-2002	thorpej	Rearrange the beginning of cpu_switch() slightly to reduce data-dep stalls on StrongARM and XScale.
1.3.2.18	12-Aug-2002	thorpej	Add the requisite calls to sched_lock_idle() and sched_unlock_idle() if LOCKDEBUG is defined, as is done on the trunk.
1.3.2.17	12-Aug-2002	thorpej	More register usage tweaks to reduce differences with trunk.
1.3.2.16	12-Aug-2002	thorpej	Tweak register usage in cpu_switch() slightly to reduce differences with the trunk.
1.3.2.15	12-Aug-2002	thorpej	Tweak register usage in cpu_preempt() slightly.
1.3.2.14	12-Aug-2002	thorpej	Reduce some differences with the trunk.
1.3.2.13	06-Aug-2002	thorpej	Rearrange the exit path so that we don't do a idcache_wbinv_all twice when a process or lwp exits.
1.3.2.12	06-Aug-2002	thorpej	* In switch_exit()/switch_lwp_exit(), set the outgoing-lwp register to NULL (rather than lwp0) so that we actually use the "exiting process" optimization in cpu_switch(). * Correct some comments.
1.3.2.11	05-Aug-2002	thorpej	Fix cpu_preempt() for the __NEWINTR case.
1.3.2.10	05-Aug-2002	thorpej	Back out the changes that implement the scheduler locking protocol. The register usage in this file is very different than on the trunk, and so the changes made to the trunk don't really apply here. Fix up some comments while here.
1.3.2.9	24-Jun-2002	nathanw	Curproc->curlwp renaming. Change uses of "curproc->l_proc" back to "curproc", which is more like the original use. Bare uses of "curproc" are now "curlwp". "curproc" is now #defined in proc.h as ((curlwp) ? (curlwp)->l_proc) : NULL) so that it is always safe to reference curproc (dereferencing curproc is another story, but that's always been true).
1.3.2.8	21-Jun-2002	nathanw	switch_search -> Lswitch_search in switch_exit().
1.3.2.7	20-Jun-2002	nathanw	Catch up to -current.
1.3.2.6	11-Apr-2002	thorpej	Make this compile again.
1.3.2.5	28-Feb-2002	nathanw	Catch up to -current.
1.3.2.4	08-Jan-2002	nathanw	Catch up to -current.
1.3.2.3	29-Nov-2001	thorpej	l_stat is an int now instead of a u_char. Pointed out by pk in a commit message.
1.3.2.2	15-Nov-2001	thorpej	Machine-dependent kernel mods for scheduler activations on 32-bit ARM processors. Kernel boots multi-user on an XScale, but upcalls not yet tested.
1.3.2.1	11-Nov-2001	thorpej	file cpuswitch.S was added on branch nathanw_sa on 2001-11-15 06:39:21 +0000
1.7.2.2	31-Aug-2002	gehenna	catch up with -current.
1.7.2.1	30-Aug-2002	gehenna	catch up with -current.
1.28.2.7	24-Oct-2002	bjh21	Flush the cache before reading sched_whichqs. This is entirely the wrong way to do this, but it should work (very slowly) until I work out the right way.
1.28.2.6	19-Oct-2002	bjh21	Switch to the idle PCB in the idle loop.
1.28.2.5	19-Oct-2002	bjh21	In cpu_switch and cpu_exit, use curcpu to find curproc and curpcb, rather than assuming CPU 0. Also fix a register-shuffling botch in cpu_exit.
1.28.2.4	19-Oct-2002	bjh21	Reshuffle register usage in cpu_exit along the lines of cpu_switch to reduce saving and restoring of registers.
1.28.2.3	19-Oct-2002	bjh21	Redo the following revision: syssrc/sys/arch/arm/arm32/cpuswitch.S 1.27 Original log message: The grand cpu_switch register reshuffle! In particular, use r8 to hold the old process, and r7 for medium-term scratch, saving r0-r3 for things we don't need saved over function calls. This gets rid of five register-to-register MOVs.
1.28.2.2	19-Oct-2002	bjh21	Re-do the following revisions, this time on a branch where they won't interfere with the nathanw_sa merge: syssrc/sys/arch/arm/arm32/cpuswitch.S 1.26 syssrc/sys/arch/arm/arm32/genassym.cf 1.18 syssrc/sys/arch/arm/arm32/vm_machdep.c 1.21 syssrc/sys/arch/arm/include/pcb.h 1.5 Original commit message: In cpu_switch(), stack more registers at the start of the function, and hence save fewer into the PCB. This should give me enough free registers in cpu_switch to tidy things up and support MULTIPROCESSOR properly. While we're here, make the stacked registers into an APCS stack frame, so that DDB backtraces through cpu_switch() will work. This also affects cpu_fork(), which has to fabricate a switchframe and PCB for the new process.
1.28.2.1	19-Oct-2002	bjh21	file cpuswitch.S was added on branch bjh21-hydra on 2002-10-19 11:59:36 +0000
1.36.2.3	21-Sep-2004	skrll	Fix the sync with head I botched.
1.36.2.2	18-Sep-2004	skrll	Sync with HEAD.
1.36.2.1	03-Aug-2004	skrll	Sync with HEAD
1.41.16.6	17-Mar-2008	yamt	sync with head.
1.41.16.5	21-Jan-2008	yamt	sync with head
1.41.16.4	27-Oct-2007	yamt	sync with head.
1.41.16.3	03-Sep-2007	yamt	sync with head.
1.41.16.2	26-Feb-2007	yamt	sync with head.
1.41.16.1	21-Jun-2006	yamt	sync with head.
1.42.12.1	24-May-2006	tron	Merge 2006-05-24 NetBSD-current into the "peter-altq" branch.
1.42.10.1	11-May-2006	elad	sync with head
1.42.8.1	24-May-2006	yamt	sync with head.
1.42.6.1	01-Jun-2006	kardel	Sync with head.
1.42.4.1	09-Sep-2006	rpaulo	sync with head
1.44.12.1	04-Mar-2007	bouyer	branches: 1.44.12.1.4; Pull up following revision(s) (requested by matt in ticket #470): sys/arch/evbarm/iq80310/iq80310_timer.c: revision 1.20 sys/arch/evbarm/ifpga/pl030_rtc.c: revision 1.8 sys/arch/evbarm/include/types.h: revision 1.7 sys/arch/arm/arm32/genassym.cf: revision 1.30 sys/arch/arm/arm32/cpuswitch.S: revision 1.46 Get DOMAIN_CLIENT directly from arm/arm32/pte.h instead of from genassym to avoid redefinition when both assymh and pte.h are included (as in INTEGRATOR's intmmu.S, which uses more macros from pte.h). Convert evbarm to __HAVE_GENERIC_TODR.
1.44.12.1.4.1	10-Nov-2007	matt	Add AT91 support from Sami Kantoluoto Add TI OMAP2430 support from Marty Fouts @ Danger Inc
1.44.8.1	30-Jan-2007	ad	For now always call sched_unlock_idle/sched_lock_idle. They will be removed by yamt's cpu_switchto() changes.
1.45.2.3	08-Apr-2007	skrll	Set curlwp in cpu_switchto and provide a cpu_did_resched. Who is copying who now?
1.45.2.2	29-Mar-2007	skrll	Adapt arm32. Thanks to scw for helping out. Tested on my cats (SA1) XXX hydra should die. i've made some changes, but no guarantees.
1.45.2.1	27-Feb-2007	yamt	- sync with head. - move sched_changepri back to kern_synch.c as it doesn't know PPQ anymore.
1.46.12.3	03-Oct-2007	garbled	Sync with HEAD
1.46.12.2	26-Jun-2007	garbled	Sync with HEAD.
1.46.12.1	22-May-2007	matt	Update to HEAD.
1.46.6.1	11-Jul-2007	mjf	Sync with head.
1.46.4.2	09-Oct-2007	ad	Sync with head.
1.46.4.1	27-May-2007	ad	Sync with head.
1.48.12.6	23-Mar-2008	matt	sync with HEAD
1.48.12.5	28-Jan-2008	matt	Add fast softint switch support.
1.48.12.4	07-Nov-2007	matt	Make sure instructions are aligned after .asciz
1.48.12.3	06-Nov-2007	matt	sync with HEAD
1.48.12.2	11-Sep-2007	matt	Add a diagnostic check for cpu_switchto(x, NULL);
1.48.12.1	29-Aug-2007	matt	Reworked cpuswitch for armv6 and new world order
1.48.10.3	21-Mar-2008	chris	Sync with head.
1.48.10.2	20-Jan-2008	chris	Sync to HEAD.
1.48.10.1	01-Jan-2008	chris	Sync with HEAD.
1.48.8.1	02-Oct-2007	joerg	Sync with HEAD.
1.48.6.2	28-Feb-2008	rjs	Sync with HEAD.
1.48.6.1	01-Nov-2007	rjs	Sync with HEAD.
1.50.8.2	20-Jan-2008	bouyer	Sync with HEAD
1.50.8.1	19-Jan-2008	bouyer	Sync with HEAD
1.50.2.1	18-Feb-2008	mjf	Sync with HEAD.
1.55.6.3	17-Jan-2009	mjf	Sync with HEAD.
1.55.6.2	02-Jun-2008	mjf	Sync with HEAD.
1.55.6.1	03-Apr-2008	mjf	Sync with HEAD.
1.55.2.1	24-Mar-2008	keiichi	sync with head.
1.56.2.1	18-May-2008	yamt	sync with head.
1.57.2.3	11-Mar-2010	yamt	sync with head
1.57.2.2	04-May-2009	yamt	sync with head.
1.57.2.1	16-May-2008	yamt	sync with head.
1.58.14.1	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.58.8.1	19-Jan-2009	skrll	Sync with HEAD.
1.58.6.1	13-Dec-2008	haad	Update haad-dm branch to haad-dm-base2.
1.60.4.2	21-Apr-2011	rmind	sync with head
1.60.4.1	05-Mar-2011	rmind	sync with head
1.61.4.1	08-Feb-2011	bouyer	Sync with HEAD
1.61.2.1	06-Jun-2011	jruoho	Sync with HEAD.
1.63.12.1	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.63.4.4	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.63.4.3	23-Jan-2013	yamt	sync with head
1.63.4.2	16-Jan-2013	yamt	sync with (a bit old) head
1.63.4.1	30-Oct-2012	yamt	sync with head
1.72.2.5	03-Dec-2017	jdolecek	update from HEAD
1.72.2.4	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.72.2.3	23-Jun-2013	tls	resync from head
1.72.2.2	25-Feb-2013	tls	resync with head
1.72.2.1	20-Nov-2012	tls	Resync to 2012-11-19 00:00:00 UTC
1.77.6.2	18-May-2014	rmind	sync with head
1.77.6.1	28-Aug-2013	rmind	sync with head
1.83.2.1	10-Aug-2014	tls	Rebase.
1.84.2.1	27-Mar-2015	martin	Pull up following revision(s) (requested by skrll in ticket #646): sys/arch/arm/arm32/genassym.cf: revision 1.70 sys/arch/arm/arm32/cpuswitch.S: revision 1.86-1.89 Only set vfp & tpid registers and do ras lookups if new lwp is not LW_SYSTEM.
1.85.2.3	28-Aug-2017	skrll	Sync with HEAD
1.85.2.2	06-Jun-2015	skrll	Sync with HEAD
1.85.2.1	06-Apr-2015	skrll	Sync with HEAD
1.90.10.1	31-Jul-2023	martin	Pull up following revision(s) (requested by riastradh in ticket #1859): sys/arch/ia64/ia64/vm_machdep.c: revision 1.18 sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67 sys/arch/aarch64/aarch64/locore.S: revision 1.91 sys/arch/mips/include/asm.h: revision 1.74 sys/arch/hppa/include/cpu.h: revision 1.13 sys/arch/arm/arm/armv6_start.S: revision 1.38 (applied also to sys/arch/arm/cortex/a9_mpsubr.S, sys/arch/arm/cortex/a9_mpsubr.S, sys/arch/arm/cortex/cortex_init.S) sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2 sys/arch/mips/mips/locore.S: revision 1.229 sys/arch/alpha/include/asm.h: revision 1.45 (applied to sys/arch/alpha/alpha/multiproc.s) sys/arch/sparc64/sparc64/locore.s: revision 1.432 sys/arch/vax/vax/subr.S: revision 1.42 sys/arch/mips/mips/locore_mips3.S: revision 1.116 sys/arch/ia64/ia64/machdep.c: revision 1.44 sys/arch/arm/arm32/cpuswitch.S: revision 1.106 sys/arch/sparc/sparc/locore.s: revision 1.284 (all via patch) aarch64: Add missing barriers in cpu_switchto. Details in comments. Note: This is a conservative change that inserts a barrier where there was a comment saying none is needed, which is probably correct. The goal of this change is to systematically add barriers to be confident in correctness; subsequent changes may remove some bariers, as an optimization, with an explanation of why each barrier is not needed. PR kern/57240 alpha: Add missing barriers in cpu_switchto. Details in comments. arm32: Add missing barriers in cpu_switchto. Details in comments. hppa: Add missing barriers in cpu_switchto. Not sure hppa has ever had working MULTIPROCESSOR, so maybe no pullups needed? ia64: Add missing barriers in cpu_switchto. (ia64 has never really worked, so no pullups needed, right?) mips: Add missing barriers in cpu_switchto. Details in comments. powerpc: Add missing barriers in cpu_switchto. Details in comments. sparc: Add missing barriers in cpu_switchto. sparc64: Add missing barriers in cpu_switchto. Details in comments. vax: Note where cpu_switchto needs barriers. Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not even sure how to spell store-before-load barriers on VAX, so no functional change for now.
1.92.6.3	13-Apr-2020	martin	Mostly merge changes from HEAD upto 20200411
1.92.6.2	08-Apr-2020	martin	Merge changes from current as of 20200406
1.92.6.1	10-Jun-2019	christos	Sync with HEAD
1.92.4.1	26-Nov-2018	pgoyette	Sync with HEAD, resolve a couple of conflicts
1.93.4.1	31-Jul-2023	martin	Pull up following revision(s) (requested by riastradh in ticket #1676): sys/arch/ia64/ia64/vm_machdep.c: revision 1.18 sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67 sys/arch/aarch64/aarch64/locore.S: revision 1.91 sys/arch/mips/include/asm.h: revision 1.74 sys/arch/hppa/include/cpu.h: revision 1.13 sys/arch/arm/arm/armv6_start.S: revision 1.38 sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2 sys/arch/mips/mips/locore.S: revision 1.229 sys/arch/aarch64/aarch64/cpuswitch.S: revision 1.40 sys/arch/alpha/include/asm.h: revision 1.45 sys/arch/sparc64/sparc64/locore.s: revision 1.432 sys/arch/vax/vax/subr.S: revision 1.42 sys/arch/mips/mips/locore_mips3.S: revision 1.116 sys/arch/ia64/ia64/machdep.c: revision 1.44 sys/arch/arm/arm32/cpuswitch.S: revision 1.106 sys/arch/sparc/sparc/locore.s: revision 1.284 (all via patch) aarch64: Add missing barriers in cpu_switchto. Details in comments. Note: This is a conservative change that inserts a barrier where there was a comment saying none is needed, which is probably correct. The goal of this change is to systematically add barriers to be confident in correctness; subsequent changes may remove some bariers, as an optimization, with an explanation of why each barrier is not needed. PR kern/57240 alpha: Add missing barriers in cpu_switchto. Details in comments. arm32: Add missing barriers in cpu_switchto. Details in comments. hppa: Add missing barriers in cpu_switchto. Not sure hppa has ever had working MULTIPROCESSOR, so maybe no pullups needed? ia64: Add missing barriers in cpu_switchto. (ia64 has never really worked, so no pullups needed, right?) mips: Add missing barriers in cpu_switchto. Details in comments. powerpc: Add missing barriers in cpu_switchto. Details in comments. sparc: Add missing barriers in cpu_switchto. sparc64: Add missing barriers in cpu_switchto. Details in comments. vax: Note where cpu_switchto needs barriers. Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not even sure how to spell store-before-load barriers on VAX, so no functional change for now.
1.95.2.2	29-Feb-2020	ad	Sync with head.
1.95.2.1	17-Jan-2020	ad	Sync with head.
1.103.2.1	14-Dec-2020	thorpej	Sync w/ HEAD.
1.104.6.1	31-May-2021	cjep	sync with head
1.104.4.1	17-Jun-2021	thorpej	Sync w/ HEAD.
1.105.12.1	31-Jul-2023	martin	Pull up following revision(s) (requested by riastradh in ticket #264): sys/arch/ia64/ia64/vm_machdep.c: revision 1.18 sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67 sys/arch/aarch64/aarch64/locore.S: revision 1.91 sys/arch/mips/include/asm.h: revision 1.74 sys/arch/hppa/include/cpu.h: revision 1.13 sys/arch/arm/arm/armv6_start.S: revision 1.38 sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2 sys/arch/mips/mips/locore.S: revision 1.229 sys/arch/aarch64/aarch64/cpuswitch.S: revision 1.40 sys/arch/alpha/include/asm.h: revision 1.45 sys/arch/sparc64/sparc64/locore.s: revision 1.432 sys/arch/vax/vax/subr.S: revision 1.42 sys/arch/mips/mips/locore_mips3.S: revision 1.116 sys/arch/riscv/riscv/cpu_switch.S: revision 1.3 sys/arch/ia64/ia64/machdep.c: revision 1.44 sys/arch/arm/arm32/cpuswitch.S: revision 1.106 sys/arch/sparc/sparc/locore.s: revision 1.284 aarch64: Add missing barriers in cpu_switchto. Details in comments. Note: This is a conservative change that inserts a barrier where there was a comment saying none is needed, which is probably correct. The goal of this change is to systematically add barriers to be confident in correctness; subsequent changes may remove some bariers, as an optimization, with an explanation of why each barrier is not needed. PR kern/57240 alpha: Add missing barriers in cpu_switchto. Details in comments. arm32: Add missing barriers in cpu_switchto. Details in comments. hppa: Add missing barriers in cpu_switchto. Not sure hppa has ever had working MULTIPROCESSOR, so maybe no pullups needed? ia64: Add missing barriers in cpu_switchto. (ia64 has never really worked, so no pullups needed, right?) mips: Add missing barriers in cpu_switchto. Details in comments. powerpc: Add missing barriers in cpu_switchto. Details in comments. riscv: Add missing barriers in cpu_switchto. Details in comments. sparc: Add missing barriers in cpu_switchto. sparc64: Add missing barriers in cpu_switchto. Details in comments. vax: Note where cpu_switchto needs barriers. Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not even sure how to spell store-before-load barriers on VAX, so no functional change for now.
1.66	20-Sep-2025	mrg	make sure ddb_regp doesn't point to some stack variable when kdb_trap() returns found by GCC 14.
1.65	02-Aug-2023	skrll	KNF
1.64	26-Oct-2022	riastradh	ddb/db_active.h: New home for extern db_active. This can be included unconditionally, and db_active can then be queried unconditionally; if DDB is not in the kernel, then db_active is a constant zero. Reduces need for #include opt_ddb.h, #ifdef DDB.
1.63	03-Dec-2020	skrll	Provide and use a sev() macro for the sev instruction. While here use the correct barrier to ensure completion of memory accesses before a couple of the sev() calls.
1.62	01-Dec-2020	rin	Fix confusions related to encoding of instructions. For __ARMEB__ in BE8 mode, instructions are encoded in little-endian. Therefore, we need to swap bytes against these in native byte order. In other cases, i.e., __ARMEL__ and __ARMEB__ in BE32 mode, instructions are in native byte order, and we don't need to swap them.
1.61	20-Jun-2020	skrll	branches: 1.61.2; KNF
1.60	20-Jun-2020	skrll	KNF #includes Remove some unnecessary ones while I'm here.
1.59	21-Jul-2019	rin	Fix hand-crafted trap instruction in cpu_Debugger() for big endian.
1.58	28-May-2018	chs	branches: 1.58.2; merge a new version of the CDDL dtrace and ZFS code. this changes the upstream vendor from OpenSolaris to FreeBSD, and this version is based on FreeBSD svn r315983. in addition to the 10 years of improvements from upstream, this version also has these NetBSD-specific enhancements: - dtrace FBT probes can now be placed in kernel modules. - ZFS now supports mmap().
1.57	17-Jan-2018	skrll	branches: 1.57.2; G/C ARM32_NEW_VM_LAYOUT
1.56	30-Jun-2017	skrll	KNF. Same code before and after.
1.55	30-Jun-2017	skrll	typo in comment
1.54	29-Oct-2014	skrll	branches: 1.54.2; Sprinkle #include "opt_multiprocessor.h"
1.53	25-Oct-2014	skrll	Remove katelib.h and references to it. {Read,Write}{Word,Byte} macros are provided in the files that still use them. Someone(tm) should convert them to bus_space(9)
1.52	30-Mar-2014	skrll	branches: 1.52.4; Provide a DDB_REGS in the same way to others. Makes crash buildable.
1.51	28-Mar-2014	matt	Make ddb_registers per-cpu. All switching of CPUs (xxx doesn't work yet).
1.50	15-Dec-2013	skrll	Trailing whitespace.
1.49	16-Feb-2012	christos	branches: 1.49.2; 1.49.4; move stuff between the two files, so db_interface contains the functions it needs for userland programs to link.
1.48	16-Jun-2010	jmcneill	branches: 1.48.8; 1.48.12; 1.48.16; PR port-arm/43299: Support added for igepv2/cortexa8/omap3530 Apply patch from PR, with build fixes. ok skrll, matt
1.47	14-Mar-2009	dsl	branches: 1.47.2; 1.47.4; Change about 4500 of the K&R function definitions to ANSI ones. There are still about 1600 left, but they have ',' or /* ... */ in the actual variable definitions - which my awk script doesn't handle. There are also many that need () -> (void). (The script does handle misordered arguments.)
1.46	14-Mar-2009	dsl	Remove all the __P() from sys (excluding sys/dist) Diff checked with grep and MK1 eyeball. i386 and amd64 GENERIC and sys still build.
1.45	26-Mar-2008	chris	branches: 1.45.4; 1.45.12; 1.45.18; 1.45.22; Add help text to arm machine specific ddb commands. Part of fix for port-arm/38311.
1.44	17-Oct-2007	garbled	branches: 1.44.16; Merge the ppcoea-renovation branch to HEAD. This branch was a major cleanup and rototill of many of the various OEA cpu based PPC ports that focused on sharing as much code as possible between the various ports to eliminate near-identical copies of files in every tree. Additionally there is a new PIC system that unifies the interface to interrupt code for all different OEA ppc arches. The work for this branch was done by a variety of people, too long to list here. TODO: bebox still needs work to complete the transition to -renovation. ofppc still needs a bunch of work, which I will be looking at. ev64260 still needs to be renovated amigappc was not attempted. NOTES: pmppc was removed as an arch, and moved to a evbppc target.
1.43	22-Sep-2007	martin	Add a new option DDB_VERBOSE_HELP that adds online help to ddb. From Adam Hamsik. Minor modifications by me, all bugs are probably mine.
1.42	22-Feb-2007	thorpej	branches: 1.42.4; 1.42.12; 1.42.18; 1.42.20; 1.42.22; 1.42.24; TRUE -> true, FALSE -> false
1.41	06-Jan-2007	christos	branches: 1.41.2; Fix branch handling in ddb. From Bucky Katz.
1.40	05-Apr-2006	uwe	branches: 1.40.8; Define ddb_regs in db_interface.c. Change its definion in db_machdep.h into a declaration.
1.39	24-Dec-2005	perry	branches: 1.39.4; 1.39.6; 1.39.8; 1.39.10; 1.39.12; bare asm -> __asm
1.38	11-Dec-2005	christos	merge ktrace-lwp.
1.37	02-Jun-2005	uwe	branches: 1.37.2; Catch up with constification.
1.36	02-Jun-2005	he	Adapt to shadowing and qualifier-cast warnings.
1.35	07-Aug-2004	rearnsha	Don't overload the unknown instruction handling for the core onto CP0. Instead, add a seventeenth 'co-processor' specifically for the core. Add support for ARMv5 unknown instructions in the 'NV' space.
1.34	26-Oct-2003	chris	Fix up some unitialised variables.
1.33	25-Aug-2003	mrg	make it "static long nil;" as it's used as &nil in an array wanting long *'s. makes GCC3 happy.
1.32	15-Jul-2003	lukem	__KERNEL_RCSID()
1.31	09-Jul-2003	thorpej	Make faulting in DDB continue back in the top-level command loop properly.
1.30	06-Jun-2003	scw	branches: 1.30.2; Modify db_{read,write}_bytes() to do a single 16- or 32-bit read/write if 'size' is 2 or 4 respectively. This makes reading/writing hardware registers work as expected in all cases.
1.29	21-May-2003	thorpej	Remove #ifdefs supporting the old pmap, switching fully to the new.
1.28	21-May-2003	bsh	fix warning when KGDB is defined and DDB is not defined.
1.27	03-May-2003	thorpej	In db_write_bytes(), use kernel_text rather than KERNEL_TEXT_BASE.
1.26	03-May-2003	thorpej	Remove the non-ELF case in db_machine_init().
1.25	29-Apr-2003	scw	KERNEL_TEXT_BASE is not defined for ARM32_NEW_VM_LAYOUT.
1.24	28-Apr-2003	briggs	Add arm32 machine-specific remote kgdb support. Largely from PR port-arm/15530 by bsh@, but with some updates from me, including a fresh arm32/kgdb_machdep.c--ported from pc532.
1.23	18-Apr-2003	scw	Add the generic arm32 bits of the new pmap, contributed by Wasabi Systems. Some features of the new pmap are: - It allows L1 descriptor tables to be shared efficiently between multiple processes. A typical "maxusers 32" kernel, where NPROC is set to 532, requires 35 L1s. A "maxusers 2" kernel runs quite happily with just 4 L1s. This completely solves the problem of running out of contiguous physical memory for allocating new L1s at runtime on a busy system. - Much improved cache/TLB management "smarts". This change ripples out to encompass the low-level context switch code, which is also much smarter about when to flush the cache/TLB, and when not to. - Faster allocation of L2 page tables and associated metadata thanks, in part, to the pool_cache enhancements recently contributed to NetBSD by Wasabi Systems. - Faster VM space teardown due to accurate referenced tracking of L2 page tables. - Better/faster cache-alias tracking. The new pmap is enabled by adding options ARM32_PMAP_NEW to the kernel config file, and making the necessary changes to the port-specific initarm() function. Several ports have already been converted and will be committed shortly.
1.22	22-Aug-2002	thorpej	* Add PTE_SYNC() and PTE_SYNC_RANGE() macros. These don't actually do anything yet. * Use PTE_SYNC() and PTE_SYNC_RANGE() in some obvious places, i.e. where vtopte() is used.
1.21	13-May-2002	matt	branches: 1.21.2; Nuke local extern label_t *db_recover; it's now in <ddb/db_extern.h>
1.20	10-Apr-2002	thorpej	vm_offset_t -> vaddr_t,paddr_t
1.19	09-Apr-2002	thorpej	Use abstract names for the protection and PTE type bits in L1 and L2 descriptors. This will allow us to support different PTE layouts that enable the use of extensions on different processor models.
1.18	05-Apr-2002	thorpej	* Rewrite the 32-bit ARM pte.h based on the ARM architecture manual. Significant cleanup, here, including better PTE bit names. * Add XScale PTE extensions (ECC enable, write-allocate cache mode). * Mechanical changes everywhere else to update for new pte.h. While doing this, two bugs (as a result of typos) were fixed in arm/arm32/bus_dma.c evbarm/integrator/int_bus_dma.c
1.17	25-Jan-2002	thorpej	Overhaul of the ARM cache code. This is mostly a simplification pass. Rather than providing a whole slew of cache operations that aren't ever used, distill them down to some useful primitives: icache_sync_all Synchronize I-cache icache_sync_range Synchronize I-cache range dcache_wbinv_all Write-back and Invalidate D-cache dcache_wbinv_range Write-back and Invalidate D-cache range dcache_inv_range Invalidate D-cache range dcache_wb_range Write-back D-cache range idcache_wbinv_all Write-back and Invalidate D-cache, Invalidate I-cache idcache_wbinv_range Write-back and Invalidate D-cache, Invalidate I-cache range Note: This does not yet include an overhaul of the actual asm files that implement the primitives. Instead, we've provided a safe default for each CPU type, and the individual CPU types can now be optimized one at a time.
1.16	17-Jan-2002	thorpej	Add cpwait's after TLB operations.
1.15	17-Jan-2002	thorpej	Cleanup a little, and teach db_write_text() about section mappings.
1.14	17-Jan-2002	thorpej	* db_validate_address(): Use pmap_extract(). * db_read_bytes()/db_write_bytes(): Do comparisons against the (unsigned) size_t correctly.
1.13	05-Jan-2002	chris	Make some of the arm32 files build with LOOSE_PROTOTYPES not set in the makefile. Turned up a few mismatched functions. Note that this isn't all of the arm32 files. Aim will be to get arm32 kernels built with LOOSE_PROTOTYPES not set.
1.12	28-Nov-2001	thorpej	Don't grovel interrupt-related info here; if a platform wants to do that, let it do that in a way it can control.
1.11	23-Nov-2001	thorpej	Use <arm/undefined.h> instead of <machine/undefined.h>.
1.10	23-Nov-2001	thorpej	No need to pull in <machine/pte.h> directly.
1.9	22-Nov-2001	thorpej	Kill <machine/katelib.h>. Any place that still uses it should just reference <arm/arm32/katelib.h> until such time as all use of this file has been purged from the face of the earth.
1.8	09-Nov-2001	thorpej	branches: 1.8.2; Add some rudimentary support for ELF symbols in DDB on the ARM ports. On platforms which load the kernel sans symbols directly from firmware (possibly in e.g. S-Record format), call ddb_init() with empty arguments, so that it will search any compiled in SYMTAB_SPACE. On all other platforms, if __ELF__, also call ddb_init() with empty arguments until ELF bootloaders which pass symbol information are ready.
1.7	28-Jul-2001	chris	branches: 1.7.4; A couple of tidy ups to pmap: pmap_t -> struct pmap * in pmap.c and pmap.h kernel_pmap -> pmap_kernel() everywhere. Compiled and booted on riscpc and cats.
1.6	24-Jun-2001	chs	branches: 1.6.2; remove "machine vmstat" command, since "show uvmexp" does the same thing.
1.5	02-May-2001	bjh21	In an ELF kernel, don't try to find an a.out symbol table.
1.4	13-Mar-2001	bjh21	Change the value of tf_pc in undefined-instruction handlers on arm32. It now always points to the undefined instruction in question. It's up to the handler to advance it to the next instruction if it wants execution to continue there. This is how things have always worked on arm26.
1.3	11-Mar-2001	bjh21	branches: 1.3.2; Change undefined instruction handler to use a linked list for each co-processor. This is necessary so we can have several handlers for CP0 (used as a catch-all for non-CP instructions). Handlers are now removed using remove_coproc_handler(), rather than by calling install_coproc_handler() with a NULL handler. Because install_coproc_handler() can now allocate memory, there's a version for use at boot time that doesn't.
1.2	04-Mar-2001	matt	branches: 1.2.2; Remove OFW hooks. Allow ports to add there own hooks via ARM_EXTRA_DB_COMMANDS.
1.1	04-Mar-2001	matt	Move these from arm32/arm32
1.2.2.2	21-Jun-2001	nathanw	Catch up to -current.
1.2.2.1	09-Apr-2001	nathanw	Catch up with -current.
1.3.2.3	27-Mar-2001	bouyer	Sync with HEAD.
1.3.2.2	12-Mar-2001	bouyer	Sync with HEAD.
1.3.2.1	11-Mar-2001	bouyer	file db_interface.c was added on branch thorpej_scsipi on 2001-03-12 13:27:19 +0000
1.6.2.5	06-Sep-2002	jdolecek	sync kqueue branch with HEAD
1.6.2.4	23-Jun-2002	jdolecek	catch up with -current on kqueue branch
1.6.2.3	11-Feb-2002	jdolecek	Sync w/ -current.
1.6.2.2	10-Jan-2002	thorpej	Sync kqueue branch with -current.
1.6.2.1	03-Aug-2001	lukem	update to -current
1.7.4.1	12-Nov-2001	thorpej	Sync the thorpej-mips-cache branch with -current.
1.8.2.9	27-Aug-2002	thorpej	Sync with -current.
1.8.2.8	24-Jun-2002	nathanw	Curproc->curlwp renaming. Change uses of "curproc->l_proc" back to "curproc", which is more like the original use. Bare uses of "curproc" are now "curlwp". "curproc" is now #defined in proc.h as ((curlwp) ? (curlwp)->l_proc) : NULL) so that it is always safe to reference curproc (dereferencing curproc is another story, but that's always been true).
1.8.2.7	20-Jun-2002	nathanw	Catch up to -current.
1.8.2.6	17-Apr-2002	nathanw	Catch up to -current.
1.8.2.5	28-Feb-2002	nathanw	Catch up to -current.
1.8.2.4	11-Jan-2002	nathanw	More catchup.
1.8.2.3	08-Jan-2002	nathanw	Catch up to -current.
1.8.2.2	15-Nov-2001	thorpej	Machine-dependent kernel mods for scheduler activations on 32-bit ARM processors. Kernel boots multi-user on an XScale, but upcalls not yet tested.
1.8.2.1	09-Nov-2001	thorpej	file db_interface.c was added on branch nathanw_sa on 2001-11-15 06:39:21 +0000
1.21.2.1	30-Aug-2002	gehenna	catch up with -current.
1.30.2.5	10-Nov-2005	skrll	Sync with HEAD. Here we go again...
1.30.2.4	21-Sep-2004	skrll	Fix the sync with head I botched.
1.30.2.3	18-Sep-2004	skrll	Sync with HEAD.
1.30.2.2	12-Aug-2004	skrll	Sync with HEAD.
1.30.2.1	03-Aug-2004	skrll	Sync with HEAD
1.37.2.3	27-Oct-2007	yamt	sync with head.
1.37.2.2	26-Feb-2007	yamt	sync with head.
1.37.2.1	21-Jun-2006	yamt	sync with head.
1.39.12.1	24-May-2006	tron	Merge 2006-05-24 NetBSD-current into the "peter-altq" branch.
1.39.10.1	19-Apr-2006	elad	sync with head - hopefully this will work
1.39.8.1	11-Apr-2006	yamt	sync with head
1.39.6.1	22-Apr-2006	simonb	Sync with head.
1.39.4.1	09-Sep-2006	rpaulo	sync with head
1.40.8.1	12-Jan-2007	ad	Sync with head.
1.41.2.1	27-Feb-2007	yamt	- sync with head. - move sched_changepri back to kern_synch.c as it doesn't know PPQ anymore.
1.42.24.1	06-Nov-2007	matt	sync with HEAD
1.42.22.1	01-Jan-2008	chris	Sync with HEAD.
1.42.20.1	02-Oct-2007	joerg	Sync with HEAD.
1.42.18.1	06-Oct-2007	rjs	Sync with HEAD.
1.42.12.1	03-Oct-2007	garbled	Sync with HEAD
1.42.4.1	09-Oct-2007	ad	Sync with head.
1.44.16.1	03-Apr-2008	mjf	Sync with HEAD.
1.45.22.1	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.45.18.1	13-May-2009	jym	Sync with HEAD. Commit is split, to avoid a "too many arguments" protocol error.
1.45.12.1	28-Apr-2009	skrll	Sync with HEAD.
1.45.4.2	11-Aug-2010	yamt	sync with head.
1.45.4.1	04-May-2009	yamt	sync with head.
1.47.4.1	03-Jul-2010	rmind	sync with head
1.47.2.1	17-Aug-2010	uebayasi	Sync with HEAD.
1.48.16.1	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.48.12.1	18-Feb-2012	mrg	merge to -current.
1.48.8.2	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.48.8.1	17-Apr-2012	yamt	sync with head
1.49.4.1	18-May-2014	rmind	sync with head
1.49.2.2	03-Dec-2017	jdolecek	update from HEAD
1.49.2.1	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.52.4.1	09-Nov-2014	martin	Pull up following revision(s) (requested by skrll in ticket #188): sys/arch/arm/include/arm32/pmap.h: revision 1.136 sys/arch/arm/include/armreg.h: revision 1.100 sys/arch/arm/cortex/gic.c: revision 1.11 sys/arch/arm/arm32/db_interface.c: revision 1.54 sys/arch/arm/include/armreg.h: revision 1.101 sys/arch/arm/cortex/gic.c: revision 1.12 sys/arch/arm/arm32/arm32_machdep.c: revision 1.107 sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.19 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.20 sys/arch/evbarm/conf/BPI: revision 1.5 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.21 sys/arch/arm/arm32/pmap.c: revision 1.306 sys/arch/arm/arm32/db_machdep.c: revision 1.22 sys/arch/arm/arm32/arm32_tlb.c: revision 1.3 sys/arch/arm/arm/undefined.c: revision 1.55 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.22 sys/arch/arm/arm32/pmap.c: revision 1.307 sys/arch/arm/arm32/arm32_tlb.c: revision 1.4 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.23 sys/arch/arm/arm32/arm32_tlb.c: revision 1.5 sys/arch/evbarm/conf/BPI: revision 1.8 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.24 sys/arch/arm/arm32/arm32_tlb.c: revision 1.6 sys/arch/arm/arm32/arm32_tlb.c: revision 1.7 sys/arch/evbarm/conf/CUBIETRUCK: revision 1.5 sys/arch/arm/pic/pic.c: revision 1.23 sys/arch/arm/pic/pic.c: revision 1.24 sys/arch/arm/pic/picvar.h: revision 1.11 sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.20 sys/arch/arm/mainbus/cpu_mainbus.c: revision 1.16 sys/arch/arm/arm32/pmap.c: revision 1.298 sys/arch/arm/arm/cpufunc_asm_arm11.S: revision 1.17 sys/arch/arm/arm/cpufunc_asm_pj4b.S: revision 1.5 sys/arch/arm/arm32/pmap.c: revision 1.310 sys/arch/arm/arm32/pmap.c: revision 1.311 sys/arch/arm/arm32/arm32_kvminit.c: revision 1.32 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.19 sys/arch/arm/arm32/arm32_boot.c: revision 1.10 sys/arch/arm/arm/ast.c: revision 1.25 sys/arch/arm/include/armreg.h: revision 1.98 sys/uvm/pmap/pmap_tlb.c: revision 1.10 sys/arch/arm/arm32/arm32_boot.c: revision 1.8 sys/arch/arm/arm32/arm32_boot.c: revision 1.9 sys/arch/arm/arm/arm_machdep.c: revision 1.43 Various ARM MP fixes.
1.54.2.1	28-Aug-2017	skrll	Sync with HEAD
1.57.2.1	25-Jun-2018	pgoyette	Sync with HEAD
1.58.2.1	13-Apr-2020	martin	Mostly merge changes from HEAD upto 20200411
1.61.2.1	14-Dec-2020	thorpej	Sync w/ HEAD.
1.39	23-Feb-2021	mrg	introduce DDB_END_CMD and replace more than 20 copies of the same list of NULLs and 0. idea from rillig@. all touched ports built, several booted.
1.38	03-Dec-2020	rin	tlb_print_*() are used only if _ARM_ARCH_7; caught by clang -Wunused-function.
1.37	30-Oct-2020	skrll	branches: 1.37.2; Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.
1.36	29-Sep-2020	jmcneill	Collapse all CPU_CORTEXA<n> options into CPU_CORTEX and do runtime detection instead of ifdefs where required.
1.35	14-Aug-2020	skrll	Mirror the changes to aarch64 and - Switch to TPIDRPRW_IS_CURLWP, because curlwp is accessed much more often by MI code. It also makes curlwp preemption safe, - Make ASTs operate per-LWP rather than per-CPU, otherwise sometimes LWPs can see spurious ASTs (which doesn't cause a problem, it just means some time may be wasted). - Make sure ASTs are always set on the same CPU as the target LWP, and delivered via IPI if posted from a remote CPU so that they are resolved quickly. - Add some cache line padding to struct cpu_info. - Add a memory barrier in a couple of places where ci_curlwp is set. This is needed whenever an LWP that is resuming on the CPU could hold an adaptive mutex. The barrier needs to drain the CPU's store buffer, so that the update to ci_curlwp becomes globally visible before the LWP can resume and call mutex_exit().
1.34	03-Jul-2020	jmcneill	Move db_reset_cmd prototype to db_machdep.h (forgot to commit this file)
1.33	03-Jul-2020	skrll	Provide a db_reset_cmd prototype
1.32	02-Jul-2020	jmcneill	Add ddb "mach reset" command for Arm ports.
1.31	20-Jun-2020	skrll	KNF #includes Remove some unnecessary ones while I'm here.
1.30	14-Apr-2020	skrll	Provide a "mach cpuinfo" which displays some struct cpuinfo fields for a/all CPUs.
1.29	14-Apr-2020	skrll	Remove unused ARM32_DB_COMMANDS
1.28	14-Apr-2020	skrll	Sort db_commands.
1.27	25-Mar-2020	skrll	branches: 1.27.2; Simplify #ifdefs
1.26	25-Mar-2020	skrll	Trailing whitespace
1.25	15-Aug-2018	skrll	Sprinkle #include "opt_cputypes.h"
1.24	25-Apr-2017	skrll	branches: 1.24.10; 1.24.12; Dump more of the trapframe
1.23	25-Feb-2015	joerg	branches: 1.23.2; Improve inline asm around dsb/dmb/isb: - always use volatile and mark them as memory barrier - use the common version from locore.h in all places not included from userland
1.22	12-Oct-2014	skrll	branches: 1.22.2; Typo. s/NC/NS/
1.21	30-Mar-2014	skrll	branches: 1.21.4; Provide a DDB_REGS in the same way to others. Makes crash buildable.
1.20	29-Mar-2014	skrll	Sprinkle #ifdef _KERNEL{,_OPT}
1.19	28-Mar-2014	matt	Make ddb_registers per-cpu. All switching of CPUs (xxx doesn't work yet).
1.18	01-Mar-2014	matt	Add support for printing the tlb on cortex a5 and a7.
1.17	15-Dec-2013	skrll	Trailing whitespace
1.16	05-Jan-2013	christos	branches: 1.16.2; remove show panic cmd
1.15	21-Sep-2012	matt	Add a 'mach fault' command to print DFAR/DFSR/IFAR/IFSR/TTBR
1.14	31-Aug-2012	skrll	branches: 1.14.2; Don't advertise the abt/und/irq stack pointers as accessible to crash(8) when they're not
1.13	16-Feb-2012	christos	move stuff between the two files, so db_interface contains the functions it needs for userland programs to link.
1.12	14-Mar-2009	dsl	branches: 1.12.12; 1.12.16; 1.12.20; Change about 4500 of the K&R function definitions to ANSI ones. There are still about 1600 left, but they have ',' or /* ... */ in the actual variable definitions - which my awk script doesn't handle. There are also many that need () -> (void). (The script does handle misordered arguments.)
1.11	22-Feb-2007	matt	branches: 1.11.48; 1.11.56; 1.11.62; 1.11.66; Fix lossage from boolean_t -> bool and updated x86 bus_dma.
1.10	11-Dec-2005	christos	branches: 1.10.26; merge ktrace-lwp.
1.9	02-Jun-2005	uwe	branches: 1.9.2; Catch up with constification.
1.8	15-Jul-2003	lukem	__KERNEL_RCSID()
1.7	05-Jan-2002	chris	branches: 1.7.18; Make some of the arm32 files build with LOOSE_PROTOTYPES not set in the makefile. Turned up a few mismatched functions. Note that this isn't all of the arm32 files. Aim will be to get arm32 kernels built with LOOSE_PROTOTYPES not set.
1.6	28-Nov-2001	thorpej	Don't grovel interrupt-related info here; if a platform wants to do that, let it do that in a way it can control.
1.5	05-Sep-2001	matt	branches: 1.5.6; Don't compile SPL/INTR stuff if NEWINTR is defined.
1.4	05-Sep-2001	matt	Change <machine/irqhandler.h> to <machine/intr.h> since the latter always includes the former and is a standard include file.
1.3	24-Jun-2001	chs	branches: 1.3.2; remove "machine vmstat" command, since "show uvmexp" does the same thing.
1.2	04-Mar-2001	matt	branches: 1.2.4; Remove OFW hooks. Allow ports to add there own hooks via ARM_EXTRA_DB_COMMANDS.
1.1	04-Mar-2001	matt	Move these from arm32/arm32
1.2.4.2	12-Mar-2001	bouyer	Sync with HEAD.
1.2.4.1	04-Mar-2001	bouyer	file db_machdep.c was added on branch thorpej_scsipi on 2001-03-12 13:27:20 +0000
1.3.2.2	10-Jan-2002	thorpej	Sync kqueue branch with -current.
1.3.2.1	13-Sep-2001	thorpej	Update the kqueue branch to HEAD.
1.5.6.4	28-Feb-2002	nathanw	Catch up to -current.
1.5.6.3	11-Jan-2002	nathanw	More catchup.
1.5.6.2	08-Jan-2002	nathanw	Catch up to -current.
1.5.6.1	05-Sep-2001	nathanw	file db_machdep.c was added on branch nathanw_sa on 2002-01-08 00:23:08 +0000
1.7.18.4	10-Nov-2005	skrll	Sync with HEAD. Here we go again...
1.7.18.3	21-Sep-2004	skrll	Fix the sync with head I botched.
1.7.18.2	18-Sep-2004	skrll	Sync with HEAD.
1.7.18.1	03-Aug-2004	skrll	Sync with HEAD
1.9.2.1	26-Feb-2007	yamt	sync with head.
1.10.26.1	27-Feb-2007	yamt	- sync with head. - move sched_changepri back to kern_synch.c as it doesn't know PPQ anymore.
1.11.66.1	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.11.62.1	13-May-2009	jym	Sync with HEAD. Commit is split, to avoid a "too many arguments" protocol error.
1.11.56.1	28-Apr-2009	skrll	Sync with HEAD.
1.11.48.1	04-May-2009	yamt	sync with head.
1.12.20.1	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.12.16.1	18-Feb-2012	mrg	merge to -current.
1.12.12.4	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.12.12.3	23-Jan-2013	yamt	sync with head
1.12.12.2	30-Oct-2012	yamt	sync with head
1.12.12.1	17-Apr-2012	yamt	sync with head
1.14.2.4	03-Dec-2017	jdolecek	update from HEAD
1.14.2.3	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.14.2.2	25-Feb-2013	tls	resync with head
1.14.2.1	20-Nov-2012	tls	Resync to 2012-11-19 00:00:00 UTC
1.16.2.1	18-May-2014	rmind	sync with head
1.21.4.2	27-May-2015	msaitoh	Pull up following revision(s) (requested by skrll in ticket #805): sys/arch/arm/include/arm32/pmap.h: revision 1.138 sys/arch/arm/arm/cpufunc.c: revision 1.151 sys/arch/arm/arm32/bus_dma.c: revision 1.90 sys/arch/arm/broadcom/bcm53xx_pax.c: revision 1.14 sys/arch/arm/arm32/bus_dma.c: revision 1.91 sys/arch/arm/samsung/exynos_space.c: revision 1.2 sys/arch/arm/arm32/db_machdep.c: revision 1.23 sys/arch/arm/allwinner/awin_space.c: revision 1.4 sys/arch/arm/include/rwlock.h: revision 1.9 sys/arch/arm/amlogic/amlogic_space.c: revision 1.2 sys/arch/arm/zynq/zynq_space.c: revision 1.2 sys/arch/arm/broadcom/bcm2835_space.c: revision 1.7 sys/arch/arm/arm32/pmap.c: revision 1.317 sys/arch/arm/include/locore.h: revision 1.19 sys/arch/arm/include/mutex.h: revision 1.20 sys/arch/arm/include/lock.h: revision 1.31 sys/arch/arm/include/lock.h: revision 1.32 sys/arch/arm/broadcom/bcmgen_space.c: revision 1.5 - Kill redundant semicolons. - Indentation. - Improve inline asm around dsb/dmb/isb: - always use volatile and mark them as memory barrier - use the common version from locore.h in all places not included from userland
1.21.4.1	09-Nov-2014	martin	Pull up following revision(s) (requested by skrll in ticket #188): sys/arch/arm/include/arm32/pmap.h: revision 1.136 sys/arch/arm/include/armreg.h: revision 1.100 sys/arch/arm/cortex/gic.c: revision 1.11 sys/arch/arm/arm32/db_interface.c: revision 1.54 sys/arch/arm/include/armreg.h: revision 1.101 sys/arch/arm/cortex/gic.c: revision 1.12 sys/arch/arm/arm32/arm32_machdep.c: revision 1.107 sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.19 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.20 sys/arch/evbarm/conf/BPI: revision 1.5 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.21 sys/arch/arm/arm32/pmap.c: revision 1.306 sys/arch/arm/arm32/db_machdep.c: revision 1.22 sys/arch/arm/arm32/arm32_tlb.c: revision 1.3 sys/arch/arm/arm/undefined.c: revision 1.55 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.22 sys/arch/arm/arm32/pmap.c: revision 1.307 sys/arch/arm/arm32/arm32_tlb.c: revision 1.4 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.23 sys/arch/arm/arm32/arm32_tlb.c: revision 1.5 sys/arch/evbarm/conf/BPI: revision 1.8 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.24 sys/arch/arm/arm32/arm32_tlb.c: revision 1.6 sys/arch/arm/arm32/arm32_tlb.c: revision 1.7 sys/arch/evbarm/conf/CUBIETRUCK: revision 1.5 sys/arch/arm/pic/pic.c: revision 1.23 sys/arch/arm/pic/pic.c: revision 1.24 sys/arch/arm/pic/picvar.h: revision 1.11 sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.20 sys/arch/arm/mainbus/cpu_mainbus.c: revision 1.16 sys/arch/arm/arm32/pmap.c: revision 1.298 sys/arch/arm/arm/cpufunc_asm_arm11.S: revision 1.17 sys/arch/arm/arm/cpufunc_asm_pj4b.S: revision 1.5 sys/arch/arm/arm32/pmap.c: revision 1.310 sys/arch/arm/arm32/pmap.c: revision 1.311 sys/arch/arm/arm32/arm32_kvminit.c: revision 1.32 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.19 sys/arch/arm/arm32/arm32_boot.c: revision 1.10 sys/arch/arm/arm/ast.c: revision 1.25 sys/arch/arm/include/armreg.h: revision 1.98 sys/uvm/pmap/pmap_tlb.c: revision 1.10 sys/arch/arm/arm32/arm32_boot.c: revision 1.8 sys/arch/arm/arm32/arm32_boot.c: revision 1.9 sys/arch/arm/arm/arm_machdep.c: revision 1.43 Various ARM MP fixes.
1.22.2.2	28-Aug-2017	skrll	Sync with HEAD
1.22.2.1	06-Apr-2015	skrll	Sync with HEAD
1.23.2.1	26-Apr-2017	pgoyette	Sync with HEAD
1.24.12.3	21-Apr-2020	martin	Sync with HEAD
1.24.12.2	08-Apr-2020	martin	Merge changes from current as of 20200406
1.24.12.1	10-Jun-2019	christos	Sync with HEAD
1.24.10.1	06-Sep-2018	pgoyette	Sync with HEAD Resolve a couple of conflicts (result of the uimin/uimax changes)
1.27.2.1	20-Apr-2020	bouyer	Sync with HEAD
1.37.2.2	03-Apr-2021	thorpej	Sync with HEAD.
1.37.2.1	14-Dec-2020	thorpej	Sync w/ HEAD.
1.4	11-Aug-2002	bjh21	Remove a file which was accidentally resurrected.
1.3	09-Sep-2001	toshii	branches: 1.3.4; 1.3.12; Don't define pcb_* register macros. pcb_sp macro conflicts with sys/netinet6/ipsec.c.
1.2	05-Jun-2001	bjh21	branches: 1.2.2; Replace arm/arm32/db_trace.c and arm26/arm26/db_trace.c with a unified version in arm/arm. This version is based on the arm26 version, and includes dumping the contents of stack frames, with automatic determination of the save code pointer offset.
1.1	04-Mar-2001	matt	branches: 1.1.4; Move these from arm32/arm32
1.1.4.2	12-Mar-2001	bouyer	Sync with HEAD.
1.1.4.1	04-Mar-2001	bouyer	file db_trace.c was added on branch thorpej_scsipi on 2001-03-12 13:27:20 +0000
1.2.2.2	11-Feb-2002	jdolecek	Sync w/ -current.
1.2.2.1	13-Sep-2001	thorpej	Update the kqueue branch to HEAD.
1.3.12.1	30-Aug-2002	gehenna	catch up with -current.
1.3.4.3	08-Jan-2002	nathanw	Catch up to -current.
1.3.4.2	15-Nov-2001	thorpej	Machine-dependent kernel mods for scheduler activations on 32-bit ARM processors. Kernel boots multi-user on an XScale, but upcalls not yet tested.
1.3.4.1	09-Sep-2001	thorpej	file db_trace.c was added on branch nathanw_sa on 2001-11-15 06:39:21 +0000
1.26	21-Nov-2020	skrll	Sprinkle some comments about ENABLE_ALIGNMENT_FAULTS leaving curcpu in r4 and curlwp in r5
1.25	11-Aug-2019	skrll	branches: 1.25.8; Trailing whitespace
1.24	07-Jul-2017	chs	branches: 1.24.6; split PUSHFRAMEINSVC into two pieces so that we can insert some additional instructions in the middle in undefinedinstruction_bounce, namely to add some additional space on the stack before the trapframe for undefineds from SVC mode. this extra space allows dtrace to emulate a "push" instruction. the initial version was from me and some improvements were from nick.
1.23	21-Jun-2015	matt	Remove duplicate ASEND(undefined_entry)
1.22	13-Mar-2014	matt	branches: 1.22.6; Add clrex when we get an abort. Simplify undefined_entry to use the undefined stack to do transfer to the undefined handler.
1.21	05-Mar-2014	matt	push/pop unsaved registers before using printf.
1.20	02-Dec-2013	joerg	Don't use cpsr_all/spsr_all with mrs, it doesn't take a mask.
1.19	18-Aug-2013	matt	Move parts of cpu.h that are not needed by MI code in <arm/locore.h> Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h> Use <arm/asm.h> instead of <machine/arm.h>
1.18	12-Sep-2012	matt	branches: 1.18.2; Make sure the handler addresses are 32-bit aligned.
1.17	29-Aug-2012	matt	branches: 1.17.2; Don't use locations in .data to store exception temporaries, use decidicated space in cpu_info instead. This also moves undefined_handler_address into cpu_info as well. Use the new armreg* inlines for getting TPIDRPRW register. Add MULTIPROCESSOR version of CPU_INFO_FOREACH
1.16	27-Apr-2008	matt	branches: 1.16.18; 1.16.34; 1.16.42; Merge kernel changes in matt-armv6 to HEAD.
1.15	19-Jan-2008	chris	branches: 1.15.6; 1.15.8; 1.15.10; Remove arm support for IPKDB. It hasn't worked since arm was broken out from arm32 in Jan 2001, and no-one has noticed or cared to fix it.
1.14	11-Dec-2005	christos	branches: 1.14.46; 1.14.50; 1.14.52; 1.14.58; 1.14.66; merge ktrace-lwp.
1.13	31-Oct-2003	scw	branches: 1.13.16; Overhaul arm32's abort handlers: - Assume a permission fault is always the result of an attempted write, so no need to disassemble the opcode. (as discussed with Richard Earnshaw/Jason Thorpe a week or two ago) - Split out non-MMU data aborts into separate functions, and deal correctly with XScale imprecise aborts. Specifically, the old code made no attempt to handle the double abort faults which can occur as a result of two consecutive external (imprecise) aborts. This was easy to provoke by read(2)ing from a /dev/mem offset which caused an external abort. With the old code, this would bring the system down instantly, with little clue as to why. (hint: tf_spsr held PSR_ABT32_MODE...) - Re-write badaddr_read() to use pcb_onfault instead of adding extra overhead to data_abort_handler(). A side effect of this is that it now benefits from the XScale double abort recovery. - Invoke the cpu-specific prefetch/data abort fixup routines only if the host cpu actually needs it. On other cpus, the code is optimised away. - Sprinkle __predict_{false,true} in all the right places. - G/C some excess debugging baggage.
1.12	30-Oct-2003	scw	Move the alignment fault enable/disable code into macroes to avoid needless duplication. Additionally, merge AST handling into the same code. exception.S and the generic irq_dispatch.S routines have been updated to use the macroes. XXX: I have patches for the non-generic IRQ dispatch routines, but they need testing by someone with hardware.
1.11	26-Oct-2003	scw	Assume that if curpcb is NULL, we're already running with alignment faults enabled.
1.10	25-Oct-2003	scw	Skip the alignment fault enabling code if we came from SVC mode. It's already enabled in this case.
1.9	25-Oct-2003	scw	Enable alignment faults on arm32 for both kernel and userland. If COMPAT_15 and EXEC_AOUT are defined, support per-process alignment checking where AFLTs are always enabled when running kernel code and userland ELF binaries, and dynamically disabled/ enabled when switching to/from a.out binaries. This is necessary in order to execute older a.out binaries, where gcc made deliberate use of misaligned loads under certain circumstances.
1.8	06-Jan-2003	wiz	branches: 1.8.2; interrupt with two rs.
1.7	13-Oct-2002	bjh21	Instead of "add rd, pc, #foo - . - 8", use either "adr rd, foo" or (where appropriate) "mov lr, pc". This makes things slightly less confusing and ugly.
1.6	15-Aug-2002	briggs	* Use local label names (.Lfoo vs. (Lfoo or foo)) * When moving from cpsr, use "cpsr" instead of "cpsr_all" (which is provided, but doesn't make sense since mrs doesn't support fields like msr does).
1.5	17-Jan-2002	bjh21	branches: 1.5.8; Separate out syscall() out into three parts: swi_handler() does stuff that all SWIs will need, then calls curproc->p_emul->e_syscall. syscall() handles native NetBSD system calls. linux_syscall() handles Linux system calls.
1.4	14-Jan-2002	bjh21	Simplify SWI entry: syscall() now extracts the SWI comment field itself.
1.3	20-Dec-2001	thorpej	* Share a common vector page between arm26 and arm32. * Use a common set of exception handlers for all arm32 platforms. * New FIQ framework based on discussions with Ben Harris, shared between arm26 and arm32.
1.2	28-Nov-2001	thorpej	- Garbage-collect some unused cruft. - When processing ASTs, restore interrupts after clearing astpending.
1.1	28-Jul-2001	chris	branches: 1.1.2; 1.1.8; Move the generic arm32 files into arm/arm32 from arm32/arm32, tested kernel builds on cats and riscpc.
1.1.8.6	07-Jan-2003	thorpej	Sync with HEAD.
1.1.8.5	18-Oct-2002	nathanw	Catch up to -current.
1.1.8.4	19-Aug-2002	thorpej	Partial (ARM only) sync with trunk -- significant performance improvements for XScale-based systems.
1.1.8.3	28-Feb-2002	nathanw	Catch up to -current.
1.1.8.2	08-Jan-2002	nathanw	Catch up to -current.
1.1.8.1	28-Jul-2001	nathanw	file exception.S was added on branch nathanw_sa on 2002-01-08 00:23:08 +0000
1.1.2.5	06-Sep-2002	jdolecek	sync kqueue branch with HEAD
1.1.2.4	11-Feb-2002	jdolecek	Sync w/ -current.
1.1.2.3	10-Jan-2002	thorpej	Sync kqueue branch with -current.
1.1.2.2	03-Aug-2001	lukem	update to -current
1.1.2.1	28-Jul-2001	lukem	file exception.S was added on branch kqueue on 2001-08-03 04:10:58 +0000
1.5.8.1	30-Aug-2002	gehenna	catch up with -current.
1.8.2.3	21-Sep-2004	skrll	Fix the sync with head I botched.
1.8.2.2	18-Sep-2004	skrll	Sync with HEAD.
1.8.2.1	03-Aug-2004	skrll	Sync with HEAD
1.13.16.1	21-Jan-2008	yamt	sync with head
1.14.66.1	20-Jan-2008	bouyer	Sync with HEAD
1.14.58.1	18-Feb-2008	mjf	Sync with HEAD.
1.14.52.2	23-Mar-2008	matt	sync with HEAD
1.14.52.1	28-Aug-2007	matt	#include "assym.h" first!
1.14.50.1	20-Jan-2008	chris	Sync to HEAD.
1.14.46.1	28-Feb-2008	rjs	Sync with HEAD.
1.15.10.1	16-May-2008	yamt	sync with head.
1.15.8.1	18-May-2008	yamt	sync with head.
1.15.6.1	02-Jun-2008	mjf	Sync with HEAD.
1.16.42.1	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.16.34.2	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.16.34.1	30-Oct-2012	yamt	sync with head
1.16.18.2	24-Mar-2014	matt	Use the improved undefined method from HEAD
1.16.18.1	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.17.2.3	03-Dec-2017	jdolecek	update from HEAD
1.17.2.2	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.17.2.1	20-Nov-2012	tls	Resync to 2012-11-19 00:00:00 UTC
1.18.2.2	18-May-2014	rmind	sync with head
1.18.2.1	28-Aug-2013	rmind	sync with head
1.22.6.2	28-Aug-2017	skrll	Sync with HEAD
1.22.6.1	22-Sep-2015	skrll	Sync with HEAD
1.24.6.1	13-Apr-2020	martin	Mostly merge changes from HEAD upto 20200411
1.25.8.1	14-Dec-2020	thorpej	Sync w/ HEAD.
1.119	02-Feb-2024	andvar	fix various typos in comments.
1.118	06-Oct-2023	martin	Fix previous and restore setting of "user" flag from trapframe.
1.117	05-Oct-2023	ad	Arrange to update cached LWP credentials in userret() rather than during syscall/trap entry, eliminating a test+branch on every syscall/trap. This wasn't possible in the 3.99.x timeframe when l->l_cred came about because there wasn't a reliable/timely way to force an ONPROC LWP running on a remote CPU into the kernel (which is just about the only new thing in this scheme).
1.116	01-Feb-2021	skrll	G/C some old code that was for acorn26
1.115	29-Jan-2021	skrll	the last_fault_code DEBUG variable is not MP safe, so don't compile it in.
1.114	29-Jan-2021	skrll	Typo in comment
1.113	20-Jun-2020	skrll	branches: 1.113.2; KNF
1.112	20-Jun-2020	skrll	KNF #includes Remove some unnecessary ones while I'm here.
1.111	29-Mar-2020	skrll	Support PMAP_FAULTINFO on arm
1.110	24-Feb-2020	rin	0x%#x --> %#x for non-external codes. Also, stop mixing up 0x%x and %#x in single files as far as possible.
1.109	29-Nov-2019	ryo	branches: 1.109.2; if Thumb-32 bit instruction located on a page boundariy, also need to consider the pc + 2 address. Fix PR/54720. more detail and PoC are descrived in the PR.
1.108	06-Apr-2019	thorpej	branches: 1.108.4; Overhaul the API used to fetch and store individual memory cells in userspace. The old fetch(9) and store(9) APIs (fubyte(), fuword(), subyte(), suword(), etc.) are retired and replaced with new ufetch(9) and ustore(9) APIs that can return proper error codes, etc. and are implemented consistently across all platforms. The interrupt-safe variants are no longer supported (and several of the existing attempts at fuswintr(), etc. were buggy and not actually interrupt-safe). Also augmement the ucas(9) API, making it consistently available on all plaforms, supporting uniprocessor and multiprocessor systems, even those that do not have CAS or LL/SC primitives. Welcome to NetBSD 8.99.37.
1.107	10-Aug-2018	maxv	Retire CPU_ARM2, CPU_ARM250 and CPU_ARM3, they are all leftovers of acorn26. ok jmcneill@ skrll@
1.106	15-Jul-2018	maxv	Retire ipkdb entirely. The option was removed from the config files yesterday. ok kamil christos
1.105	28-Oct-2017	pgoyette	branches: 1.105.2; 1.105.4; Update the kernhist(9) kernel history code to address issues identified in PR kern/52639, as well as some general cleaning-up... (As proposed on tech-kern@ with additional changes and enhancements.) Details of changes: * All history arguments are now stored as uintmax_t values[1], both in the kernel and in the structures used for exporting the history data to userland via sysctl(9). This avoids problems on some architectures where passing a 64-bit (or larger) value to printf(3) can cause it to process the value as multiple arguments. (This can be particularly problematic when printf()'s format string is not a literal, since in that case the compiler cannot know how large each argument should be.) * Update the data structures used for exporting kernel history data to include a version number as well as the length of history arguments. * All [2] existing users of kernhist(9) have had their format strings updated. Each format specifier now includes an explicit length modifier 'j' to refer to numeric values of the size of uintmax_t. * All [2] existing users of kernhist(9) have had their format strings updated to replace uses of "%p" with "%#jx", and the pointer arguments are now cast to (uintptr_t) before being subsequently cast to (uintmax_t). This is needed to avoid compiler warnings about casting "pointer to integer of a different size." * All [2] existing users of kernhist(9) have had instances of "%s" or "%c" format strings replaced with numeric formats; several instances of mis-match between format string and argument list have been fixed. * vmstat(1) has been modified to handle the new size of arguments in the history data as exported by sysctl(9). * vmstat(1) now provides a warning message if the history requested with the -u option does not exist (previously, this condition was silently ignored, with only a single blank line being printed). * vmstat(1) now checks the version and argument length included in the data exported via sysctl(9) and exits if they do not match the values with which vmstat was built. * The kernhist(9) man-page has been updated to note the additional requirements imposed on the format strings, along with several other minor changes and enhancements. [1] It would have been possible to use an explicit length (for example, uint64_t) for the history arguments. But that would require another "rototill" of all the users in the future when we add support for an architecture that supports a larger size. Also, the printf(3) format specifiers for explicitly-sized values, such as "%"PRIu64, are much more verbose (and less aesthetically appealing, IMHO) than simply using "%ju". [2] I've tried very hard to find "all [the] existing users of kernhist(9)" but it is possible that I've missed some of them. I would be glad to update any stragglers that anyone identifies.
1.104	02-Jul-2017	skrll	Consistency around the user trapframe for all LWPs and there's no need to keep assigning it in kernel entry points.
1.103	02-Mar-2015	martin	branches: 1.103.10; Handle EINVAL in the fault path and send SIGBUS for mmap acces past EOF.
1.102	25-Oct-2014	skrll	branches: 1.102.2; Remove katelib.h and references to it. {Read,Write}{Word,Byte} macros are provided in the files that still use them. Someone(tm) should convert them to bus_space(9)
1.101	13-Aug-2014	matt	Add __NO_FIQ to prevent testing of the PSR FIQ bit Use VALID_R15_PSR(pc, spsr) instead of testing explicitly
1.100	12-Apr-2014	skrll	Trailing whitespace
1.99	01-Apr-2014	matt	branches: 1.99.2; In prefetch_abort, call uvm_fault with VM_PROT_EXEC
1.98	05-Mar-2014	matt	Now that maphist is statically initialized, remove initialize tests
1.97	05-Mar-2014	matt	Only do UVMHIST_LOG is maphist have its entry buffer initialized
1.96	26-Feb-2014	skrll	Re-enable FSR_WRITE for armv6.
1.95	25-Feb-2014	matt	Only use FSR_WRITE on armv7 for now.
1.94	25-Feb-2014	matt	ARMv6+ supplied a write bit in the FSR so use instead of reading the instruction.
1.93	29-Jan-2014	matt	Add read_insn and read_thumb_insn inlines to hide the endianness of instructions and use them as appropriate.
1.92	11-Jan-2014	matt	Add hw.printfataltraps sysctl. Always print fatal traps for init. For all other processes, only do so if cpu_printfataltraps is true.
1.91	06-Nov-2013	christos	sprinkle diagused
1.90	18-Aug-2013	matt	Move parts of cpu.h that are not needed by MI code in <arm/locore.h> Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h> Use <arm/asm.h> instead of <machine/arm.h>
1.89	02-Jul-2013	matt	Use __func__ in UVMHIST_FUNC
1.88	18-Feb-2013	matt	branches: 1.88.2; Supply VM_PROT_EXECUTE to pmap_fault_fixup when trying to fixup prefetch aborts.
1.87	10-Dec-2012	matt	Rename pcb_sp/PCB_SP to pcb_ksp/PCB_KSP so that ipsec.c will compile.
1.86	12-Nov-2012	skrll	C99 types
1.85	07-Sep-2012	matt	branches: 1.85.2; Switch cortex_a9 back to need_ptesync = 1 Add code to disable the L2 cache on cortex-a9 (for now). Add evcnt for all the fault types. Move cache info in a structure and have one for the pcache and one for scache. Probe L1/L2 caches properly for ARMv7
1.84	29-Aug-2012	matt	Use curcpu() instead of l->l_cpu
1.83	16-Aug-2012	matt	small rototill. pcb_flags is dead. PCB_NOALIGNFLT is now in stored l_md.md_flags as MDLWP_NOALIGNFLT. This avoids a few loads of the PCB in exception handling. pcb_tf has been moved to l_md.md_tf. Again this avoids a lot of pcb references just to access or set this. It also means that pcb doesn't need to accessed by MI code. Move pcb_onfault to after the pcb union. Add pcb_sp macro to make code prettier. Add lwp_settrapframe(l, tf) to set the l_md.md_tf field. Use lwp_trapframe to access it (was process_frame but that name was changed in a previous commit). Kill off curpcb in acorn26. Kill the checks for curlwp being NULL. Move TRAP_USERMODE from arm32/fault.c to frame.h and a __PROG26 version. Replace tests for usermode with that macro.
1.82	14-Aug-2012	matt	Kill curpcb/ci_curpcb. Use device_t in cpu_info. Add ci_softc (where ci_curpcb was so cpu_info doesn't change).
1.81	30-Jul-2012	matt	Recognize STREX* as store instructions
1.80	19-Feb-2012	rmind	Remove COMPAT_SA / KERN_SA. Welcome to 6.99.3! Approved by core@.
1.79	09-Feb-2012	christos	branches: 1.79.4; Cosmetic: - add %s: __func__, function names change [most of them were wrong] - add a DIAGNOSTIC printf to help debug alignment fixups
1.78	20-Dec-2010	matt	branches: 1.78.8; 1.78.12; Move counting of faults, traps, intrs, soft[intr]s, syscalls, and nswtch from uvmexp to per-cpu cpu_data and move them to 64bits. Remove unneeded includes of <uvm/uvm_extern.h> and/or <uvm/uvm.h>.
1.77	07-Jul-2010	chs	implement ucas_* for arm.
1.76	21-Mar-2010	chs	assert that pcb_onfault is NULL in places where it should be.
1.75	03-Feb-2010	wiz	branches: 1.75.2; 1.75.4; Add missing parentheses. Found by cppcheck, reported by Henning Petersen in PR 42728.
1.74	05-Jan-2010	mbalmer	One semicolon is enough.
1.73	21-Nov-2009	rmind	Use lwp_getpcb() on ARM (and acorn26/32), clean from struct user usage.
1.72	19-Nov-2008	matt	Conditionalize the KERN_SA bits.
1.71	17-Oct-2008	cegger	branches: 1.71.2; 1.71.8; build fix: <sys/savar.h> is needed to make dereferencing sadata_vp compile. A fwd declaration is enough for defining a pointer, but you need the definition to access the structure
1.70	15-Oct-2008	wrstuden	Merge wrstuden-revivesa into HEAD.
1.69	14-Aug-2008	is	Fixed typo in message text noticed by Ilya Dogolazky. No functional change.
1.68	21-May-2008	ad	branches: 1.68.4; Remove unneeded playing about with kernel_lock.
1.67	27-Apr-2008	matt	branches: 1.67.2; Merge kernel changes in matt-armv6 to HEAD.
1.66	29-Mar-2008	chris	branches: 1.66.2; 1.66.4; Add missing bracing for some THUMB_CODE.
1.65	06-Jan-2008	matt	branches: 1.65.6; current_intr_depth is dead. Make sure we don't use it anymore.
1.64	18-Feb-2007	matt	branches: 1.64.18; 1.64.22; 1.64.24; 1.64.30; 1.64.36; Changes for newlock2.
1.63	09-Feb-2007	ad	branches: 1.63.2; Merge newlock2 to head.
1.62	23-Jul-2006	ad	branches: 1.62.4; Use the LWP cached credentials where sane.
1.61	19-Jul-2006	ad	- Hold a reference to the process credentials in each struct lwp. - Update the reference on syscall and user trap if p_cred has changed. - Collect accounting flags in the LWP, and collate on LWP exit.
1.60	15-May-2006	yamt	include kauth.h for kauth_cred_geteuid.
1.59	14-May-2006	elad	integrate kauth.
1.58	16-Mar-2006	drochner	branches: 1.58.2; adjust a diagnostic printf
1.57	16-Mar-2006	he	Transform to new signature for uvm_fault() by dropping the third arg. Discussed with drochner.
1.56	24-Dec-2005	perry	branches: 1.56.4; 1.56.6; 1.56.8; 1.56.10; Remove leading __ from __(const\|inline\|signed\|volatile) -- it is obsolete.
1.55	11-Dec-2005	christos	merge ktrace-lwp.
1.54	07-Jan-2005	skrll	branches: 1.54.10; KNF
1.53	02-Jan-2005	joff	set L_SA_PAGEFAULT for prefetch aborts, too. Fixes kern/28828
1.52	24-Oct-2004	skrll	Fix the argument to KERNEL_PROC_LOCK/KERNEL_PROC_UNLOCK.
1.51	21-Aug-2004	rearnsha	Add support for prefetch and data aborts in Thumb code.
1.50	08-Aug-2004	rearnsha	Add UVMHIST tracking for data and prefetch aborts.
1.49	14-Mar-2004	cl	add kernel part of concurrency support for SA on MP systems - move per VP data into struct sadata_vp referenced from l->l_savp * VP id * lock on VP data * LWP on VP * recently blocked LWP on VP * queue of LWPs woken which ran on this VP before sleep * faultaddr * LWP cache for upcalls * upcall queue - add current concurrency and requested concurrency variables - make process exit run LWP on all VPs - make signal delivery consider all VPs - make timer events consider all VPs - add sa_newsavp to allocate new sadata_vp structure - add sa_increaseconcurrency to prepare new VP - make sys_sa_setconcurrency request new VP or wakeup idle VP - make sa_yield lower current concurrency - set sa_cpu = VP id in upcalls - maintain cached LWPs per VP
1.48	13-Feb-2004	wiz	Uppercase CPU, plural is CPUs.
1.47	26-Jan-2004	scw	Make it possible to call badaddr_read() from interrupt context, even if curpcb is NULL, by borrowing lwp0's pcb if necessary (needed to be able to set pcb_onfault). Problem reported by Allen Briggs.
1.46	21-Jan-2004	skrll	Leave errno as zero when we SIGSEGV. This means my CATS now passes regress/lib/libc/siginfo/sigsegv OK'd by christos.
1.45	20-Nov-2003	scw	In data_abort_handler(), honour pcb_onfault even in the case where current_intr_depth > 0.
1.44	18-Nov-2003	scw	On a fatal fault, dump the trapframe's contents to the console. This is useful when DDB is not available, or practical.
1.43	15-Nov-2003	scw	Re-instate the behaviour of sending SIGKILL to a process if uvm_fault() returns ENOMEM. SIGSEGV just doesn't cut it. The original code looks to have been lost in revision 1.34.
1.42	14-Nov-2003	briggs	Make sure that L_SA_PAGEFAULT gets cleared from l_flag if pmap_fault_fixup returns non-zero and we want to shortcut out. This avoids a bogus pagefault condition being detected in sa_switch(). Many thanks to Christian Limpach for finding this, obviating my band-aid patch to kern_sa.c (posted on tech-kern).
1.41	14-Nov-2003	scw	- In data_abort_handler(), move the fault pc alignment check to before the call to data_abort_fixup() as the fixup routines also try to de-reference the fault pc. - If a fault came from kernel mode, and the fault address looks to be in the kernel's address space, and pcb_onfault is set, check the instruction which caused the fault. If it's LDR{B,}T or STR{B,}T then one of the copy in/out routines is trying to read/write a kernel address with the wrong privilege. If that address is actually mapped, we could end up in an infinite loop because we failed to notice that it's really a 'user mode' access. Yay for "crashme". I suspect this also fixes PR port-arm/23052. Note: This could be fixed by adding sanity checks to copyin et al, but that would add extra overhead to the non-error path... - Fix a couple of __predict_false cases.
1.40	14-Nov-2003	scw	Since data_abort_handler() may have to decode the instruction at tf->tf_pc to determine if a fault is read or write, make sure tf->tf_pc is 32-bit aligned before dereferencing it. Otherwise, deliver an illegal instruction signal to the process. We don't support execution of Thumb code at this time.
1.39	31-Oct-2003	scw	Overhaul arm32's abort handlers: - Assume a permission fault is always the result of an attempted write, so no need to disassemble the opcode. (as discussed with Richard Earnshaw/Jason Thorpe a week or two ago) - Split out non-MMU data aborts into separate functions, and deal correctly with XScale imprecise aborts. Specifically, the old code made no attempt to handle the double abort faults which can occur as a result of two consecutive external (imprecise) aborts. This was easy to provoke by read(2)ing from a /dev/mem offset which caused an external abort. With the old code, this would bring the system down instantly, with little clue as to why. (hint: tf_spsr held PSR_ABT32_MODE...) - Re-write badaddr_read() to use pcb_onfault instead of adding extra overhead to data_abort_handler(). A side effect of this is that it now benefits from the XScale double abort recovery. - Invoke the cpu-specific prefetch/data abort fixup routines only if the host cpu actually needs it. On other cpus, the code is optimised away. - Sprinkle __predict_{false,true} in all the right places. - G/C some excess debugging baggage.
1.38	25-Oct-2003	scw	Enable alignment faults on arm32 for both kernel and userland. If COMPAT_15 and EXEC_AOUT are defined, support per-process alignment checking where AFLTs are always enabled when running kernel code and userland ELF binaries, and dynamically disabled/ enabled when switching to/from a.out binaries. This is necessary in order to execute older a.out binaries, where gcc made deliberate use of misaligned loads under certain circumstances.
1.37	15-Oct-2003	scw	Remove the #ifdef __XSCALE__ around the strd test as the instruction is available on any v5E processor. Pointed out by Richard Earnshaw.
1.36	13-Oct-2003	scw	Tweak the read/write data abort check to recognise Xscale's strd/ldrd instructions. While the original code matched "strd" just fine, it also matched the "ldrd" instruction ...
1.35	08-Oct-2003	thorpej	* Shuffle some data structures so, and add a flags word to ksiginfo_t. Right now the only flag is used to indicate if a ksiginfo_t is a result of a trap. Add a predicate macro to test for this flag. * Add initialization macros for ksiginfo_t's. * Add accssor macro for ksi_trap. Expands to 0 if the ksiginfo_t was not the result of a trap. This matches the sigcontext trapcode semantics. * In kpsendsig(), use KSI_TRAP_P() to select the lwp that gets the signal. Inspired by Matthias Drochner's fix to kpsendsig(), but correctly handles the case of non-trap-generated signals that have a > 0 si_code. This patch fixes a signal delivery problem with threaded programs noted by Matthias Drochner on tech-kern. As discussed on tech-kern. Reviewed and OK's by Christos.
1.34	05-Oct-2003	matt	Add SA_SIGINFO support for ARM (from Chris Gilbert).
1.33	19-Sep-2003	agc	If we're going to reference SA variables in this file, might as well include the header file to define them. From Steve Woodford.
1.32	18-Sep-2003	cl	add MD part of SA/pthread pagefault handling on arm
1.31	09-Jul-2003	thorpej	Make faulting in DDB continue back in the top-level command loop properly.
1.30	21-May-2003	thorpej	branches: 1.30.2; Remove #ifdefs supporting the old pmap, switching fully to the new.
1.29	28-Apr-2003	scw	Fix the bug reported by Richard Earnshaw in port-arm32/21349. Make sure to check the access permissions before doing ref/mod/domain fixups. This is particularly important on machines with ARM_VECTORS_LOW.
1.28	28-Apr-2003	briggs	Add arm32 machine-specific remote kgdb support. Largely from PR port-arm/15530 by bsh@, but with some updates from me, including a fresh arm32/kgdb_machdep.c--ported from pc532.
1.27	18-Apr-2003	scw	Add the generic arm32 bits of the new pmap, contributed by Wasabi Systems. Some features of the new pmap are: - It allows L1 descriptor tables to be shared efficiently between multiple processes. A typical "maxusers 32" kernel, where NPROC is set to 532, requires 35 L1s. A "maxusers 2" kernel runs quite happily with just 4 L1s. This completely solves the problem of running out of contiguous physical memory for allocating new L1s at runtime on a busy system. - Much improved cache/TLB management "smarts". This change ripples out to encompass the low-level context switch code, which is also much smarter about when to flush the cache/TLB, and when not to. - Faster allocation of L2 page tables and associated metadata thanks, in part, to the pool_cache enhancements recently contributed to NetBSD by Wasabi Systems. - Faster VM space teardown due to accurate referenced tracking of L2 page tables. - Better/faster cache-alias tracking. The new pmap is enabled by adding options ARM32_PMAP_NEW to the kernel config file, and making the necessary changes to the port-specific initarm() function. Several ports have already been converted and will be committed shortly.
1.26	17-Jan-2003	thorpej	Merge the nathanw_sa branch.
1.25	13-Oct-2002	bjh21	branches: 1.25.2; 1.25.4; It appears that MI code requires ci_cpuid to be the CPU number of the CPU in question, whereas the ARM code was using it to hold the model identification. To fix this, rename: ci_cpuid -> ci_arm_cpuid ci_cputype -> ci_arm_cputype (for consistency) ci_cpurev -> ci_arm_cpurev (ditto) ci_cpunum -> ci_cpuid This makes top(1) give correct CPU numbers in its "STATE" column (all 0 for now).
1.24	27-Sep-2002	provos	remove trailing \n in panic(). approved perry.
1.23	21-Sep-2002	nathanw	In the fault handler, record growth of the stack, so that core dumps actually contain the entire stack.
1.22	14-Aug-2002	briggs	G/c cowfault.
1.21	12-Aug-2002	bjh21	__KERNEL_RCSID
1.20	12-Aug-2002	bjh21	When pcb_onfault is set, pass the error code we get from uvm_fault() (or EFAULT if we never called uvm_fault) to the onfault handler in R0, in case it wants to use it.
1.19	25-May-2002	ichiro	make compile when define DEBUG
1.18	12-Apr-2002	thorpej	branches: 1.18.2; 1.18.4; Centralize ARM CPU configuration information by adding a new header file, <arm/cpuconf.h>, which pulls in "opt_cputypes.h" and then defines the following: * CPU_NTYPES -- now many CPU types are configured into the kernel. What you really want to know is "== 1" or "> 1". * Defines ARM_ARCH_2, ARM_ARCH_3, ARM_ARCH_4, ARM_ARCH_5, depending on which ARM architecture versions are configured (based on CPU_* options). Also defines ARM_NARCH to determins how many architecture versions are configured. * Defines ARM_MMU_MEMC, ARM_MMU_GENERIC, ARM_MMU_XSCALE depending on which classes of ARM MMUs are configured into the kernel, and ARM_NMMUS to determine how many MMU classes are configured. Remove the needless inclusion of "opt_cputypes.h" in several places. Convert remaining users to <arm/cpuconf.h>.
1.17	04-Apr-2002	skrll	Fix compile problem when DDB not defined.
1.16	29-Mar-2002	thorpej	Fix a printf format.
1.15	25-Mar-2002	thorpej	Garbage-collect fetchuserword(); nothing uses it any more.
1.14	25-Mar-2002	thorpej	In the Prefetch Abort handler, just do the uvm_fault() dance directly, rather than doing a data access to fetch the page, which meant we had to take another fault (!!).
1.13	24-Mar-2002	thorpej	Only check for SA110 bugs on SA110 CPUs with step <= K.
1.12	24-Mar-2002	thorpej	* Only check for SA110 rev K bug if we're on an SA110 (XXX should also check stepping). * In said check, don't use pmap_pte(). * Garbage-collect some useless debug code.
1.11	15-Mar-2002	reinoud	Serious bug fix: a userland program could panic the kernel when it tried to issue an instruction that caused the late abort handler to be called for wich the kernel had no support build in for. It now only panics when it happends in kernel but otherwise signals the process a SEGV signal.
1.10	22-Feb-2002	thorpej	When reporting there is no VM map for a fault, also report the faulting address.
1.9	14-Feb-2002	bjh21	Undo part of rev 1.8: SWP intructions really do both read and write the referenced address.
1.8	14-Feb-2002	chs	allow writing to write-only mappings. fixes PR 3493.
1.7	05-Jan-2002	chris	Make some of the arm32 files build with LOOSE_PROTOTYPES not set in the makefile. Turned up a few mismatched functions. Note that this isn't all of the arm32 files. Aim will be to get arm32 kernels built with LOOSE_PROTOTYPES not set.
1.6	23-Nov-2001	thorpej	No need to pull in <machine/pte.h> directly.
1.5	22-Nov-2001	thorpej	Kill <machine/katelib.h>. Any place that still uses it should just reference <arm/arm32/katelib.h> until such time as all use of this file has been purged from the face of the earth.
1.4	09-Nov-2001	thorpej	branches: 1.4.2; Print the fault PC for non-USR Prefetch Aborts.
1.3	09-Nov-2001	thorpej	Implement a badaddr_read() routine which performs a load of the specified size for the caller, and returns true or false indicating whether or not a Data Abort occurred (i.e. the address was "bad").
1.2	05-Sep-2001	matt	branches: 1.2.4; Change <machine/irqhandler.h> to <machine/intr.h> since the latter always includes the former and is a standard include file.
1.1	28-Jul-2001	chris	branches: 1.1.2; Move the generic arm32 files into arm/arm32 from arm32/arm32, tested kernel builds on cats and riscpc.
1.1.2.8	10-Oct-2002	jdolecek	sync kqueue with -current; this includes merge of gehenna-devsw branch, merge of i386 MP branch, and part of autoconf rototil work
1.1.2.7	06-Sep-2002	jdolecek	sync kqueue branch with HEAD
1.1.2.6	23-Jun-2002	jdolecek	catch up with -current on kqueue branch
1.1.2.5	16-Mar-2002	jdolecek	Catch up with -current.
1.1.2.4	10-Jan-2002	thorpej	Sync kqueue branch with -current.
1.1.2.3	13-Sep-2001	thorpej	Update the kqueue branch to HEAD.
1.1.2.2	03-Aug-2001	lukem	update to -current
1.1.2.1	28-Jul-2001	lukem	file fault.c was added on branch kqueue on 2001-08-03 04:10:58 +0000
1.2.4.1	12-Nov-2001	thorpej	Sync the thorpej-mips-cache branch with -current.
1.4.2.15	18-Oct-2002	nathanw	Catch up to -current.
1.4.2.14	26-Sep-2002	nathanw	Pull up stack-tracking fix.
1.4.2.13	28-Aug-2002	nathanw	Merge fix - G/C cowfault.
1.4.2.12	19-Aug-2002	thorpej	Partial (ARM only) sync with trunk -- significant performance improvements for XScale-based systems.
1.4.2.11	13-Aug-2002	nathanw	Catch up to -current.
1.4.2.10	24-Jun-2002	nathanw	Curproc->curlwp renaming. Change uses of "curproc->l_proc" back to "curproc", which is more like the original use. Bare uses of "curproc" are now "curlwp". "curproc" is now #defined in proc.h as ((curlwp) ? (curlwp)->l_proc) : NULL) so that it is always safe to reference curproc (dereferencing curproc is another story, but that's always been true).
1.4.2.9	20-Jun-2002	nathanw	Catch up to -current.
1.4.2.8	17-Apr-2002	nathanw	Catch up to -current.
1.4.2.7	11-Apr-2002	thorpej	Make this compile again.
1.4.2.6	01-Apr-2002	nathanw	Catch up to -current. (CVS: It's not just a program. It's an adventure!)
1.4.2.5	28-Feb-2002	nathanw	Catch up to -current.
1.4.2.4	11-Jan-2002	nathanw	More catchup.
1.4.2.3	08-Jan-2002	nathanw	Catch up to -current.
1.4.2.2	15-Nov-2001	thorpej	Machine-dependent kernel mods for scheduler activations on 32-bit ARM processors. Kernel boots multi-user on an XScale, but upcalls not yet tested.
1.4.2.1	09-Nov-2001	thorpej	file fault.c was added on branch nathanw_sa on 2001-11-15 06:39:21 +0000
1.18.4.1	01-Oct-2002	lukem	Pull up revision 1.23 (requested by nathanw in ticket #885): In the fault handler, record growth of the stack, so that core dumps actually contain the entire stack.
1.18.2.2	30-Aug-2002	gehenna	catch up with -current.
1.18.2.1	30-May-2002	gehenna	Catch up with -current.
1.25.4.1	18-Dec-2002	gmcgarry	Merge pcred and ucred, and poolify. TBD: check backward compatibility and factor-out some higher-level functionality.
1.25.2.2	24-Oct-2002	bjh21	Remove DEBUG check for pcb != curpcb. This can legitimately occur if curpcb == NULL and curproc == NULL on entry. At least, I think it's legitimate.
1.25.2.1	19-Oct-2002	bjh21	Lock the kernel when handling page faults and undefined instructions.
1.30.2.7	17-Jan-2005	skrll	Sync with HEAD.
1.30.2.6	02-Nov-2004	skrll	Sync with HEAD.
1.30.2.5	21-Sep-2004	skrll	Fix the sync with head I botched.
1.30.2.4	18-Sep-2004	skrll	Sync with HEAD.
1.30.2.3	25-Aug-2004	skrll	Sync with HEAD.
1.30.2.2	12-Aug-2004	skrll	Sync with HEAD.
1.30.2.1	03-Aug-2004	skrll	Sync with HEAD
1.54.10.4	21-Jan-2008	yamt	sync with head
1.54.10.3	26-Feb-2007	yamt	sync with head.
1.54.10.2	30-Dec-2006	yamt	sync with head.
1.54.10.1	21-Jun-2006	yamt	sync with head.
1.56.10.2	19-Apr-2006	elad	sync with head - hopefully this will work
1.56.10.1	08-Mar-2006	elad	Adapt to kernel authorization KPI. I expect some lossage here...
1.56.8.3	11-Aug-2006	yamt	sync with head
1.56.8.2	24-May-2006	yamt	sync with head.
1.56.8.1	01-Apr-2006	yamt	sync with head.
1.56.6.2	01-Jun-2006	kardel	Sync with head.
1.56.6.1	22-Apr-2006	simonb	Sync with head.
1.56.4.1	09-Sep-2006	rpaulo	sync with head
1.58.2.1	24-May-2006	tron	Merge 2006-05-24 NetBSD-current into the "peter-altq" branch.
1.62.4.1	30-Jan-2007	ad	Remove support for SA. Ok core@.
1.63.2.1	27-Feb-2007	yamt	- sync with head. - move sched_changepri back to kern_synch.c as it doesn't know PPQ anymore.
1.64.36.1	08-Jan-2008	bouyer	Sync with HEAD
1.64.30.1	18-Feb-2008	mjf	Sync with HEAD.
1.64.24.2	09-Jan-2008	matt	sync with HEAD
1.64.24.1	28-Aug-2007	matt	Update to new reality.
1.64.22.1	20-Jan-2008	chris	Sync to HEAD.
1.64.18.1	28-Feb-2008	rjs	Sync with HEAD.
1.65.6.4	17-Jan-2009	mjf	Sync with HEAD.
1.65.6.3	28-Sep-2008	mjf	Sync with HEAD.
1.65.6.2	02-Jun-2008	mjf	Sync with HEAD.
1.65.6.1	03-Apr-2008	mjf	Sync with HEAD.
1.66.4.4	11-Aug-2010	yamt	sync with head.
1.66.4.3	11-Mar-2010	yamt	sync with head
1.66.4.2	04-May-2009	yamt	sync with head.
1.66.4.1	16-May-2008	yamt	sync with head.
1.66.2.2	04-Jun-2008	yamt	sync with head
1.66.2.1	18-May-2008	yamt	sync with head.
1.67.2.4	18-Sep-2008	wrstuden	Sync with wrstuden-revivesa-base-2.
1.67.2.3	30-Jun-2008	wrstuden	Change how we make SA threads not generate upcalls. Instead of clearing LW_SA, use a private flag, LP_SA_NOBLOCK, that we set when we want to not generate upcalls. This means we do NOT need to lock (l) (ourselves) to set it. Adjust tests that look at LW_SA. Now, we are an upcall-generating lwp if ((l->l_flag & LW_SA) && (~l->l_pflag & LP_SA_NOBLOCK)). Introduce code pattern to set & remember this: f = ~l->l_pflag & LP_SA_NOBLOCK; l->l_pflag \|= LP_SA_NOBLOCK; ... /* f is now LP_SA_NOBLOCK if it wasn't set in l_pflag before */ l->l_pflag ^= f; I updated a lot of the trap handlers to do trap handling iff LP_SA_NOBLOCK is not set. I tried to figure out if the trap handler could be triggered for user-based faults as opposed to kernel faults to user addresses, and only look at LP_SA_NOBLOCK for the latter. Above is a result of discussions with rmind at to reduce lock twiddling. Also, per same discussions, add locking to sys_sa_preempt(). p_lock is the lock we want. Also, per same discussions, remove use of LSSUSPENDED as a thread state. We needed to use it when we were emulating the 4.X and previous behavior of hiding cached threads. For the moment, we now have them instead remain visible to all and have them sleeping on the "lwpcache" wait channel. sa_newcachelwp(): sa_putcachelwp() wants savp_mutex held, not p_lock. Tweak some comments.
1.67.2.2	23-Jun-2008	wrstuden	Sync w/ -current. 34 merge conflicts to follow.
1.67.2.1	22-Jun-2008	wrstuden	Re-add cpu_upcall() and page fault code. i386 kernels now compile. They don't boot, but that seems to be a consequence of current from the day this branch was started.
1.68.4.2	13-Dec-2008	haad	Update haad-dm branch to haad-dm-base2.
1.68.4.1	19-Oct-2008	haad	Sync with HEAD.
1.71.8.1	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.71.2.1	19-Jan-2009	skrll	Sync with HEAD.
1.75.4.2	05-Mar-2011	rmind	sync with head
1.75.4.1	30-May-2010	rmind	sync with head
1.75.2.2	17-Aug-2010	uebayasi	Sync with HEAD.
1.75.2.1	30-Apr-2010	uebayasi	Sync with HEAD.
1.78.12.2	24-Feb-2012	mrg	sync to -current.
1.78.12.1	18-Feb-2012	mrg	merge to -current.
1.78.8.4	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.78.8.3	16-Jan-2013	yamt	sync with (a bit old) head
1.78.8.2	30-Oct-2012	yamt	sync with head
1.78.8.1	17-Apr-2012	yamt	sync with head
1.79.4.1	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.85.2.4	03-Dec-2017	jdolecek	update from HEAD
1.85.2.3	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.85.2.2	25-Feb-2013	tls	resync with head
1.85.2.1	20-Nov-2012	tls	Resync to 2012-11-19 00:00:00 UTC
1.88.2.2	18-May-2014	rmind	sync with head
1.88.2.1	28-Aug-2013	rmind	sync with head
1.99.2.1	10-Aug-2014	tls	Rebase.
1.102.2.2	28-Aug-2017	skrll	Sync with HEAD
1.102.2.1	06-Apr-2015	skrll	Sync with HEAD
1.103.10.1	02-Nov-2017	snj	Pull up following revision(s) (requested by pgoyette in ticket #335): share/man/man9/kernhist.9: 1.5-1.8 sys/arch/acorn26/acorn26/pmap.c: 1.39 sys/arch/arm/arm32/fault.c: 1.105 via patch sys/arch/arm/arm32/pmap.c: 1.350, 1.359 sys/arch/arm/broadcom/bcm2835_bsc.c: 1.7 sys/arch/arm/omap/if_cpsw.c: 1.20 sys/arch/arm/omap/tiotg.c: 1.7 sys/arch/evbarm/conf/RPI2_INSTALL: 1.3 sys/dev/ic/sl811hs.c: 1.98 sys/dev/usb/ehci.c: 1.256 sys/dev/usb/if_axe.c: 1.83 sys/dev/usb/motg.c: 1.18 sys/dev/usb/ohci.c: 1.274 sys/dev/usb/ucom.c: 1.119 sys/dev/usb/uhci.c: 1.277 sys/dev/usb/uhub.c: 1.137 sys/dev/usb/umass.c: 1.160-1.162 sys/dev/usb/umass_quirks.c: 1.100 sys/dev/usb/umass_scsipi.c: 1.55 sys/dev/usb/usb.c: 1.168 sys/dev/usb/usb_mem.c: 1.70 sys/dev/usb/usb_subr.c: 1.221 sys/dev/usb/usbdi.c: 1.175 sys/dev/usb/usbdi_util.c: 1.67-1.70 sys/dev/usb/usbroothub.c: 1.3 sys/dev/usb/xhci.c: 1.75 sys/external/bsd/drm2/dist/drm/i915/i915_gem.c: 1.34 sys/kern/kern_history.c: 1.15 sys/kern/kern_xxx.c: 1.74 sys/kern/vfs_bio.c: 1.275-1.276 sys/miscfs/genfs/genfs_io.c: 1.71 sys/sys/kernhist.h: 1.21 sys/ufs/ffs/ffs_balloc.c: 1.63 sys/ufs/lfs/lfs_vfsops.c: 1.361 sys/ufs/lfs/ulfs_inode.c: 1.21 sys/ufs/lfs/ulfs_vnops.c: 1.52 sys/ufs/ufs/ufs_inode.c: 1.102 sys/ufs/ufs/ufs_vnops.c: 1.239 sys/uvm/pmap/pmap.c: 1.37-1.39 sys/uvm/pmap/pmap_tlb.c: 1.22 sys/uvm/uvm_amap.c: 1.108 sys/uvm/uvm_anon.c: 1.64 sys/uvm/uvm_aobj.c: 1.126 sys/uvm/uvm_bio.c: 1.91 sys/uvm/uvm_device.c: 1.66 sys/uvm/uvm_fault.c: 1.201 sys/uvm/uvm_km.c: 1.144 sys/uvm/uvm_loan.c: 1.85 sys/uvm/uvm_map.c: 1.353 sys/uvm/uvm_page.c: 1.194 sys/uvm/uvm_pager.c: 1.111 sys/uvm/uvm_pdaemon.c: 1.109 sys/uvm/uvm_swap.c: 1.175 sys/uvm/uvm_vnode.c: 1.103 usr.bin/vmstat/vmstat.c: 1.219 Reorder to test for null before null deref in debug code -- Reorder to test for null before null deref in debug code -- KNF -- No need for '\n' in UVMHIST_LOG -- normalise a BIOHIST log message -- Update the kernhist(9) kernel history code to address issues identified in PR kern/52639, as well as some general cleaning-up... (As proposed on tech-kern@ with additional changes and enhancements.) Details of changes: * All history arguments are now stored as uintmax_t values[1], both in the kernel and in the structures used for exporting the history data to userland via sysctl(9). This avoids problems on some architectures where passing a 64-bit (or larger) value to printf(3) can cause it to process the value as multiple arguments. (This can be particularly problematic when printf()'s format string is not a literal, since in that case the compiler cannot know how large each argument should be.) * Update the data structures used for exporting kernel history data to include a version number as well as the length of history arguments. * All [2] existing users of kernhist(9) have had their format strings updated. Each format specifier now includes an explicit length modifier 'j' to refer to numeric values of the size of uintmax_t. * All [2] existing users of kernhist(9) have had their format strings updated to replace uses of "%p" with "%#jx", and the pointer arguments are now cast to (uintptr_t) before being subsequently cast to (uintmax_t). This is needed to avoid compiler warnings about casting "pointer to integer of a different size." * All [2] existing users of kernhist(9) have had instances of "%s" or "%c" format strings replaced with numeric formats; several instances of mis-match between format string and argument list have been fixed. * vmstat(1) has been modified to handle the new size of arguments in the history data as exported by sysctl(9). * vmstat(1) now provides a warning message if the history requested with the -u option does not exist (previously, this condition was silently ignored, with only a single blank line being printed). * vmstat(1) now checks the version and argument length included in the data exported via sysctl(9) and exits if they do not match the values with which vmstat was built. * The kernhist(9) man-page has been updated to note the additional requirements imposed on the format strings, along with several other minor changes and enhancements. [1] It would have been possible to use an explicit length (for example, uint64_t) for the history arguments. But that would require another "rototill" of all the users in the future when we add support for an architecture that supports a larger size. Also, the printf(3) format specifiers for explicitly-sized values, such as "%"PRIu64, are much more verbose (and less aesthetically appealing, IMHO) than simply using "%ju". [2] I've tried very hard to find "all [the] existing users of kernhist(9)" but it is possible that I've missed some of them. I would be glad to update any stragglers that anyone identifies. -- For some reason this single kernel seems to have outgrown its declared size as a result of the kernhist(9) changes. Bump the size. XXX The amount of increase may be excessive - anyone with more detailed XXX knowledge please feel free to further adjust the value appropriately. -- Misssed one cast of pointer --> uintptr_t in previous kernhist(9) commit -- And yet another one. :( -- Use correct mark-up for NetBSD version. -- More improvements in grammar and readability. -- Remove a stray '"' (obvious typo) and add a couple of casts that are probably needed. -- And replace an instance of "%p" conversion with "%#jx" -- Whitespace fix. Give Bl tag table a width. Fix Xr.
1.105.4.2	08-Apr-2020	martin	Merge changes from current as of 20200406
1.105.4.1	10-Jun-2019	christos	Sync with HEAD
1.105.2.2	06-Sep-2018	pgoyette	Sync with HEAD Resolve a couple of conflicts (result of the uimin/uimax changes)
1.105.2.1	28-Jul-2018	pgoyette	Sync with HEAD
1.108.4.1	08-Dec-2019	martin	Pull up following revision(s) (requested by ryo in ticket #510): sys/arch/arm/arm32/fault.c: revision 1.109 if Thumb-32 bit instruction located on a page boundariy, also need to consider the pc + 2 address. Fix PR/54720. more detail and PoC are descrived in the PR.
1.109.2.1	29-Feb-2020	ad	Sync with head.
1.113.2.1	03-Apr-2021	thorpej	Sync with HEAD.
1.16	18-Jan-2009	bjh21	Move arch/arm/arm32/fusu.S to arch/arm/arm/fusu.S in preparation for making it usable on acorn26 as well.
1.15	18-Jan-2009	bjh21	Now that GET_CURPCB and GET_CURCPU are generally available, use them unconditionally rather than rolling our own (often badly) all over the place.
1.14	17-Jan-2009	bjh21	Clear out the vestigial support for the Simtec Hydra board. Now that we're getting support for proper SMP ARMs, keeping non-functional support for a seriously crippled not-really-SMP system is likely to cause more problems than it's worth, even if it was fun for a while.
1.13	27-Apr-2008	matt	branches: 1.13.8; 1.13.16; Merge kernel changes in matt-armv6 to HEAD.
1.12	04-Mar-2007	christos	branches: 1.12.22; 1.12.42; 1.12.44; 1.12.46; Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.
1.11	11-Dec-2005	christos	branches: 1.11.26; merge ktrace-lwp.
1.10	01-Dec-2003	rearnsha	branches: 1.10.16; Avoid alignment faults in fusword and fuswintr. Also handle big-endian systems in susword and suswintr.
1.9	13-Oct-2002	bjh21	branches: 1.9.8; Instead of "add rd, pc, #foo - . - 8", use either "adr rd, foo" or (where appropriate) "mov lr, pc". This makes things slightly less confusing and ugly.
1.8	13-Oct-2002	bjh21	Use cpu_number() to find curpcb rather than assuming we're on CPU 0.
1.7	12-Oct-2002	bjh21	Move curpcb into struct cpu_info in MULTIPROCESSOR kernels.
1.6	17-Aug-2002	thorpej	More local label fixups.
1.5	15-Aug-2002	briggs	* Use local label names (.Lfoo vs. (Lfoo or foo)) * When moving from cpsr, use "cpsr" instead of "cpsr_all" (which is provided, but doesn't make sense since mrs doesn't support fields like msr does).
1.4	09-Aug-2002	thorpej	Use ldrt/strt.
1.3	25-Mar-2002	thorpej	branches: 1.3.2; 1.3.4; Garbage-collect fetchuserword(); nothing uses it any more.
1.2	02-Mar-2002	chris	Remove ref to VM_MAXKERN_ADDRESS, it's not used in this file
1.1	28-Jul-2001	chris	branches: 1.1.2; 1.1.8; Move the generic arm32 files into arm/arm32 from arm32/arm32, tested kernel builds on cats and riscpc.
1.1.8.5	18-Oct-2002	nathanw	Catch up to -current.
1.1.8.4	19-Aug-2002	thorpej	Partial (ARM only) sync with trunk -- significant performance improvements for XScale-based systems.
1.1.8.3	13-Aug-2002	nathanw	Catch up to -current.
1.1.8.2	01-Apr-2002	nathanw	Catch up to -current. (CVS: It's not just a program. It's an adventure!)
1.1.8.1	28-Jul-2001	nathanw	file fusu.S was added on branch nathanw_sa on 2002-04-01 07:39:08 +0000
1.1.2.5	06-Sep-2002	jdolecek	sync kqueue branch with HEAD
1.1.2.4	23-Jun-2002	jdolecek	catch up with -current on kqueue branch
1.1.2.3	16-Mar-2002	jdolecek	Catch up with -current.
1.1.2.2	03-Aug-2001	lukem	update to -current
1.1.2.1	28-Jul-2001	lukem	file fusu.S was added on branch kqueue on 2001-08-03 04:10:58 +0000
1.3.4.1	16-Nov-2002	he	Pull up revision 1.4 (requested by thorpej in ticket #657): Use ldrt/strt.
1.3.2.1	30-Aug-2002	gehenna	catch up with -current.
1.9.8.3	21-Sep-2004	skrll	Fix the sync with head I botched.
1.9.8.2	18-Sep-2004	skrll	Sync with HEAD.
1.9.8.1	03-Aug-2004	skrll	Sync with HEAD
1.10.16.1	03-Sep-2007	yamt	sync with head.
1.11.26.1	12-Mar-2007	rmind	Sync with HEAD.
1.12.46.2	04-May-2009	yamt	sync with head.
1.12.46.1	16-May-2008	yamt	sync with head.
1.12.44.1	18-May-2008	yamt	sync with head.
1.12.42.1	02-Jun-2008	mjf	Sync with HEAD.
1.12.22.1	28-Aug-2007	matt	Deal with new world order.
1.13.16.1	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.13.8.1	03-Mar-2009	skrll	Sync with HEAD.
1.97	09-Oct-2025	skrll	Add the beginnings of a GENERIC_V5 kernel that targets armv5 boards and uses FDT. In this first iteration some support is added for OLinuXino boards. Thanks to Yuri Honegger for doing the vast majority of the work.
1.96	04-Oct-2025	skrll	G/C
1.95	28-Aug-2020	skrll	Some KASAN fixes and tweaks - don't access BSS variables when __md_early - centralise the INIT_ARM_STACK_{SHIFT,SIZE} defines and create a new INIT_ARM_TOTAL_STACK - Only create L1PT entries in kasan_md_shadow_map_page if arm32_kernel_vm_init hasn't created the L2PTs (and their L1PT entries) - Add some comments to explain what's going on
1.94	14-Aug-2020	skrll	Mirror the changes to aarch64 and - Switch to TPIDRPRW_IS_CURLWP, because curlwp is accessed much more often by MI code. It also makes curlwp preemption safe, - Make ASTs operate per-LWP rather than per-CPU, otherwise sometimes LWPs can see spurious ASTs (which doesn't cause a problem, it just means some time may be wasted). - Make sure ASTs are always set on the same CPU as the target LWP, and delivered via IPI if posted from a remote CPU so that they are resolved quickly. - Add some cache line padding to struct cpu_info. - Add a memory barrier in a couple of places where ci_curlwp is set. This is needed whenever an LWP that is resuming on the CPU could hold an adaptive mutex. The barrier needs to drain the CPU's store buffer, so that the update to ci_curlwp becomes globally visible before the LWP can resume and call mutex_exit().
1.93	08-Jul-2020	skrll	Use the stack provided by armv6_start.S rather than svcstk. This saves some bss too.
1.92	08-Jul-2020	skrll	Sort the __HAVE_* defines
1.91	08-Jul-2020	skrll	Sort include "opt_..."s
1.90	03-Jul-2020	skrll	KNF (sort includes)
1.89	20-Mar-2020	skrll	Really use armv7 noncache memory attribute for early kernel mapping and not SO
1.88	18-Feb-2020	skrll	G/C
1.87	15-Feb-2020	skrll	Various updates and improvements to cpu start up on arm/aarch64 - start sharing more code around the AP startup messaging. - call arm_cpu_topology_set early so that ci_core_id is available for drivers, e.g. bcm2835_intr.c - both arm and aarch64 now have - a static cpu_info_store array - the same arm_cpu_{hatched,mbox}
1.86	14-Feb-2020	skrll	Sort define CI_*. NFCI.
1.85	29-Jan-2020	skrll	G/C some more
1.84	29-Jan-2020	skrll	G/C
1.83	08-Jan-2020	ad	Hopefully fix some problems seen with MP support on non-x86, in particular where curcpu() is defined as curlwp->l_cpu: - mi_switch(): undo the ~2007ish optimisation to unlock curlwp before calling cpu_switchto(). It's not safe to let other actors mess with the LWP (in particular l->l_cpu) while it's still context switching. This removes l->l_ctxswtch. - Move the LP_RUNNING flag into l->l_flag and rename to LW_RUNNING since it's now covered by the LWP's lock. - Ditch lwp_exit_switchaway() and just call mi_switch() instead. Everything is in cache anyway so it wasn't buying much by trying to avoid saving old state. This means cpu_switchto() will never be called with prevlwp == NULL. - Remove some KERNEL_LOCK handling which hasn't been needed for years.
1.82	24-Nov-2019	skrll	branches: 1.82.2; corect #include order
1.81	23-Nov-2019	ad	cpu_need_resched(): - Remove all code that should be MI, leaving the bare minimum under arch/. - Make the required actions very explicit. - Pass in LWP pointer for convenience. - When a trap is required on another CPU, have the IPI set it locally. - Expunge cpu_did_resched().
1.80	18-Oct-2018	skrll	Provide generic start code that assumes the MMU is off and caches are disabled as per the linux booting protocol for ARMv6 and ARMv7 boards. u-boot image type should be changed to 'linux' for correct behaviour. The new start code builds a minimal "bootstrap" L1PT with cached access disabled and uses the same table for all processors. AP startup is performed in less steps and more code is written in C. The bootstrap tables and stack are placed into an (orphaned) section "_init_memory" which is given to uvm when it is no longer used. Various kernels have been converted to use this code and tested. Some boards were provided by TNF. Thanks! The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS kernels. The GENERIC kernel will also work on RPI2 using u-boot. Thanks to martin@ and aymeric@ for testing on parallella and nanosoc respectively
1.79	15-Oct-2018	skrll	Group/sort struct arm_cache_info members
1.78	27-Jun-2018	ryo	branches: 1.78.2; on evbarm/RPI,RPI2, VERBOSE_INIT_ARM had broken. XPUTC() of evbarm/rpi/rpi_start.S uses bcm283[567]_platform_early_putchar() and it requires stack. fixed to allocate stack when starting from rpi_start.S and a9_mpsubr.S if needed. to work XPUTC(), need to define VERBOSE_INIT_ARM and EARLYCONS option.
1.77	24-Jan-2018	skrll	branches: 1.77.2; Remove port-acorn26 OK core@
1.76	12-Jul-2017	skrll	Alignment whitespace. No functional change.
1.75	12-Jul-2017	skrll	In idcache_wbinv_range if the range size is bigger than the dcache size then call idcache_wbinv_all Avoids a problem with large ranges as seen in port-evbarm/52169: setting dtrace module to load cause Pi to hang on boot
1.74	09-Jun-2015	skrll	branches: 1.74.10; Trailing whitespace.
1.73	09-Jun-2015	skrll	Use TTBR_[UM]PATTR in a9_mpsubr.S as well as cpufunc_asm_armv7 Prompted by matt@
1.72	15-Apr-2015	matt	define __HAVE_PREEMPTION
1.71	07-Apr-2015	matt	__HAVE_UNNESTED_INTRS is never used.
1.70	23-Mar-2015	matt	Add L_FLAG/LW_SYSTEM
1.69	10-Apr-2014	matt	branches: 1.69.2; 1.69.4; emit VERBOSE_INIT_ARM
1.68	28-Mar-2014	matt	branches: 1.68.2; Add ARM_MMU_EXTENDED support.
1.67	26-Feb-2014	matt	Move pmap_recent_user to ci->ci_pmap_lastuser and pmap_previous_active_lwp to ci->ci_lastlwp. Fix some comments.
1.66	09-Nov-2013	jmcneill	wrap opt_* includes with if defined(_KERNEL_OPT)
1.65	18-Aug-2013	matt	include <arm/locore.h>
1.64	18-Aug-2013	matt	Add more TF_* symbols
1.63	02-Jul-2013	matt	Add L2_S_SIZE
1.62	17-Jun-2013	matt	branches: 1.62.2; Add L1_S_V6_S
1.61	29-Apr-2013	kiyohara	Add some defines for epoc32.
1.60	17-Dec-2012	matt	Add CPU_VFP_ID and PCB_VFP_FPEXC
1.59	10-Dec-2012	matt	add __HAVE_MM_MD_DIRECT_MAPPED_PHYS
1.58	10-Dec-2012	matt	Add VFP_FPEXC_EN
1.57	10-Dec-2012	matt	Rename pcb_sp/PCB_SP to pcb_ksp/PCB_KSP so that ipsec.c will compile.
1.56	21-Oct-2012	matt	Change to use symbolic constants from assym.h and fix a typo in a comment.
1.55	21-Oct-2012	matt	Implement a "fast" path for IRQ handling out of the idle loop. Since we are in SVC32 already we only need to save a few registers. Processing is also simplified since we know we can't return to user-mode.
1.54	07-Sep-2012	matt	branches: 1.54.2; Switch cortex_a9 back to need_ptesync = 1 Add code to disable the L2 cache on cortex-a9 (for now). Add evcnt for all the fault types. Move cache info in a structure and have one for the pcache and one for scache. Probe L1/L2 caches properly for ARMv7
1.53	01-Sep-2012	matt	Add __BITS to asm.h (remove from imxuartreg.h) Add L1_S_AP_KR to genassym.h Use L1_S_AP_* in omap_start.S and don't include pmap.h
1.52	31-Aug-2012	matt	Make cpu_reset, most of initarm and the kvm init code common. Add MP hooks for cpu_need_resced Add idlestck which is allocated in arm32_kvminit
1.51	29-Aug-2012	matt	Don't use locations in .data to store exception temporaries, use decidicated space in cpu_info instead. This also moves undefined_handler_address into cpu_info as well. Use the new armreg* inlines for getting TPIDRPRW register. Add MULTIPROCESSOR version of CPU_INFO_FOREACH
1.50	29-Aug-2012	matt	Use ARMV6+ cpsi{d,f} instructions whenever possible. Use r7 to hold previous mode and avoid recomputing it. Add support for obtaining kernel_lock on exception entry and exit.
1.49	16-Aug-2012	matt	small rototill. pcb_flags is dead. PCB_NOALIGNFLT is now in stored l_md.md_flags as MDLWP_NOALIGNFLT. This avoids a few loads of the PCB in exception handling. pcb_tf has been moved to l_md.md_tf. Again this avoids a lot of pcb references just to access or set this. It also means that pcb doesn't need to accessed by MI code. Move pcb_onfault to after the pcb union. Add pcb_sp macro to make code prettier. Add lwp_settrapframe(l, tf) to set the l_md.md_tf field. Use lwp_trapframe to access it (was process_frame but that name was changed in a previous commit). Kill off curpcb in acorn26. Kill the checks for curlwp being NULL. Move TRAP_USERMODE from arm32/fault.c to frame.h and a __PROG26 version. Replace tests for usermode with that macro.
1.48	14-Aug-2012	matt	Kill curpcb/ci_curpcb. Use device_t in cpu_info. Add ci_softc (where ci_curpcb was so cpu_info doesn't change).
1.47	02-Aug-2012	skrll	Remove irqframe and replace with identical trapframe.
1.46	07-Apr-2011	matt	branches: 1.46.4; 1.46.12; Fetch user read-only thread and process id from l->l_private, not the pcb. (need to g/c the pcb field formerly used for this).
1.45	31-Jan-2011	matt	Define the L1* pte values. Now pmap.h and pte.h no longer needed in .S files.
1.44	14-Jan-2011	rmind	branches: 1.44.2; 1.44.4; Retire struct user, remove sys/user.h inclusions. Note sys/user.h header as obsolete. Remove USER_TO_UAREA/UAREA_TO_USER macros. Various #include fixes and review by matt@.
1.43	20-Dec-2010	matt	Move counting of faults, traps, intrs, soft[intr]s, syscalls, and nswtch from uvmexp to per-cpu cpu_data and move them to 64bits. Remove unneeded includes of <uvm/uvm_extern.h> and/or <uvm/uvm.h>.
1.42	10-Dec-2009	rmind	branches: 1.42.4; Rename L_ADDR to L_PCB and amend some comments accordingly.
1.41	20-Sep-2008	tsutsui	branches: 1.41.12; Remove advertising clause for UCB in various genassym.cf files, which were derived from genassym.c in 4.4BSD-Lite2 (or 386BSD). Closes PR misc/39573. Approved by martin@.
1.40	07-Aug-2008	matt	Do fast softint processing in DO_AST_AND_RESTORE_ALIGNMENT_FAULTS. Redo the softint mask so ci_softints >> ci_cpl != 0 becomes an easy test for work to be done.
1.39	27-Apr-2008	matt	branches: 1.39.2; 1.39.6; Merge kernel changes in matt-armv6 to HEAD.
1.38	19-Jan-2008	chris	branches: 1.38.6; 1.38.8; 1.38.10; With the removal of IPKDB on arm, the undefined stack is only used to bounce into SVC32 mode, there is no per-process data stored on it. We can therefore use the undefined stack setup by the platform machdep.c as a system wide undefined stack. This removes the need for a per-process undefined stack, and the processor mode switching overhead it causes in cpu_switchto. The space freed in the USPACE is used to increase the per process kernel stack size.
1.37	08-Jan-2008	matt	As of this commit, all arm32 kernel now build.
1.36	06-Jan-2008	matt	Make sure interrupt handler is updating curcpu()->ci_depth
1.35	17-Oct-2007	garbled	branches: 1.35.2; 1.35.8; Merge the ppcoea-renovation branch to HEAD. This branch was a major cleanup and rototill of many of the various OEA cpu based PPC ports that focused on sharing as much code as possible between the various ports to eliminate near-identical copies of files in every tree. Additionally there is a new PIC system that unifies the interface to interrupt code for all different OEA ppc arches. The work for this branch was done by a variety of people, too long to list here. TODO: bebox still needs work to complete the transition to -renovation. ofppc still needs a bunch of work, which I will be looking at. ev64260 still needs to be renovated amigappc was not attempted. NOTES: pmppc was removed as an arch, and moved to a evbppc target.
1.34	15-Sep-2007	scw	ARM cpu_switchto() has been partially broken since yamt-idlelwp was merged as its cache/tlb management smarts relied too heavily on pre-merge context- switch behaviour. See PR kern/36548 for one manifestation of the breakage. To address this: - Ditch the shadow pmap variables in the PCB (pagedir, l1vec, dacr, cstate) as it was too easy for them to get out of sync with the pmap. - Re-write (and fix) the convoluted cpuswitch.S cache/tlb ASM code in C. It's only slightly less efficient, but is much more readable/maintainable. - Document cpufuncs.cf_context_switch() as being C-callable. - pmap_activate() becomes a no-op if the lwp's vmspace is already active. (Good performance win, since pmap_activate() is now invoked on every context-switch, even though ARM's cpu_switchto() already does all the grunt work) XXX: Some CPU-specific armXX_context_switch() implementations (arm67, arm7tdmi, arm8) always flush the I+D caches. This should not be necessary. Someone with access to hardware (acorn32?) needs to deal with this.
1.33	17-May-2007	yamt	branches: 1.33.6; 1.33.8; 1.33.10; 1.33.12; merge yamt-idlelwp branch. asked by core@. some ports still needs work. from doc/BRANCHES: idle lwp, and some changes depending on it. 1. separate context switching and thread scheduling. (cf. gmcgarry_ctxsw) 2. implement idle lwp. 3. clean up related MD/MI interfaces. 4. make scheduler(s) modular.
1.32	09-Mar-2007	thorpej	branches: 1.32.2; 1.32.4; 1.32.10; Rewrite the ARM mutex implementation to be of the simple-mutex variety. Because pre-v6 ARM lacks support for an atomic compare-and-swap, we implement _lock_cas() as a restartable atomic squence that is checked in the IRQ handler right before AST processing. (This is safe because, for all practical purposes, there are no SMP pre-v6 ARM systems.) This can serve as a model for other non-MP platforms that lack the necessary atomic operations for mutexes (SuperH, for example). Upshots of this change: - kmutex_t is now down to 8 bytes on ARM; about as good as we can get. - ARM2 systems don't have to trap and emulate SWP or SWPB for mutexes. The acorn26 port is not updated by this commit to do the LOCK_CAS_CHECK. That is left as an exercise for the port maintainer. Reviewed and tested by Matt Thomas.
1.31	20-Feb-2007	matt	Add KERNEL_BASE
1.30	19-Feb-2007	briggs	Get DOMAIN_CLIENT directly from arm/arm32/pte.h instead of from genassym to avoid redefinition when both assymh and pte.h are included (as in INTEGRATOR's intmmu.S, which uses more macros from pte.h).
1.29	27-Sep-2006	manu	branches: 1.29.2; 1.29.4; - Document COMPAT_15 as doing nothing - Add COMPAT_15 to all the kernel that had COMPAT_14, for the sake of coherency - Remove the only occurences of #ifdef COMPAT_15 in the tree: for the ARM ports, COMPAT_15 was always used in conjunction with EXEC_AOUT. Only EXEC_AOUT matters here. This address kern/18407
1.28	11-Dec-2005	christos	branches: 1.28.20; 1.28.22; merge ktrace-lwp.
1.27	04-Nov-2003	dsl	branches: 1.27.16; Remove p_nras from struct proc - use LIST_EMPTY(&p->p_raslist) instead. Remove p_raslock and rename p_lwplock p_lock (one lock is enough). Simplify window test when adding a ras and correct test on VM_MAXUSER_ADDRESS. Avoid unpredictable branch in i386 locore.S (pad fields left in struct proc to avoid kernel bump)
1.26	25-Oct-2003	scw	Enable alignment faults on arm32 for both kernel and userland. If COMPAT_15 and EXEC_AOUT are defined, support per-process alignment checking where AFLTs are always enabled when running kernel code and userland ELF binaries, and dynamically disabled/ enabled when switching to/from a.out binaries. This is necessary in order to execute older a.out binaries, where gcc made deliberate use of misaligned loads under certain circumstances.
1.25	11-Sep-2003	scw	Hand-optimised in_cksum/in4_cksum for ARM and XSCALE. Contributed by Wasabi Systems, with input from Chris Gilbert, Richard Earnshaw and David Laight.
1.24	22-May-2003	thorpej	branches: 1.24.2; Remove old pmap support.
1.23	22-Apr-2003	thorpej	Some ARM32_PMAP_NEW-related cleanup: * Define a new "MMU type", ARM_MMU_SA1. While the SA-1's MMU is basically compatible with the generic, the SA-1 cache does not have a write-through mode, and it is useful to know have an indication of this. * Add a new PMAP_NEEDS_PTE_SYNC indicator, and try to evaluate it at compile time. We evaluate it like so: - If SA-1-style MMU is the only type configured -> 1 - If SA-1-style MMU is not configured -> 0 - Otherwise, defer to a run-time variable. If PMAP_NEEDS_PTE_SYNC might evaluate to true (SA-1 only or run-time check), then we also define PMAP_INCLUDE_PTE_SYNC so that e.g. assembly code can include the necessary run-time support. PMAP_INCLUDE_PTE_SYNC largely replaces the ARM32_PMAP_NEEDS_PTE_SYNC manual setting Steve included with the original new pmap. * In the new pmap, make pmap_pte_init_generic() check to see if the CPU has a write-back cache. If so, init the PT cache mode to C=1,B=0 to get write-through mode. Otherwise, init the PT cache mode to C=1,B=1. * Add a new pmap_pte_init_arm8(). Old pmap, same as generic. New pmap, sets page table cacheability to 0 (ARM8 has a write-back cache, but flushing it is quite expensive). * In the new pmap, make pmap_pte_init_arm9() reset the PT cache mode to C=1,B=0, since the write-back check in generic gets it wrong for ARM9, since we use write-through mode all the time on ARM9 right now. (What this really tells me is that the test for write-through cache is less than perfect, but we can fix that later.) * Add a new pmap_pte_init_sa1(). Old pmap, same as generic. New pmap, does generic initialization, then resets page table cache mode to C=1,B=1, since C=1,B=0 does not produce write-through on the SA-1.
1.22	18-Apr-2003	scw	Add the generic arm32 bits of the new pmap, contributed by Wasabi Systems. Some features of the new pmap are: - It allows L1 descriptor tables to be shared efficiently between multiple processes. A typical "maxusers 32" kernel, where NPROC is set to 532, requires 35 L1s. A "maxusers 2" kernel runs quite happily with just 4 L1s. This completely solves the problem of running out of contiguous physical memory for allocating new L1s at runtime on a busy system. - Much improved cache/TLB management "smarts". This change ripples out to encompass the low-level context switch code, which is also much smarter about when to flush the cache/TLB, and when not to. - Faster allocation of L2 page tables and associated metadata thanks, in part, to the pool_cache enhancements recently contributed to NetBSD by Wasabi Systems. - Faster VM space teardown due to accurate referenced tracking of L2 page tables. - Better/faster cache-alias tracking. The new pmap is enabled by adding options ARM32_PMAP_NEW to the kernel config file, and making the necessary changes to the port-specific initarm() function. Several ports have already been converted and will be committed shortly.
1.21	08-Apr-2003	thorpej	Use PAGE_SIZE rather than NBPG.
1.20	17-Jan-2003	thorpej	Merge the nathanw_sa branch.
1.19	19-Oct-2002	bjh21	branches: 1.19.2; Undo recent cpu_switch register usage changes in order to decrease nathanw_sa merge pain.
1.18	18-Oct-2002	bjh21	In cpu_switch(), stack more registers at the start of the function, and hence save fewer into the PCB. This should give me enough free registers in cpu_switch to tidy things up and support MULTIPROCESSOR properly. While we're here, make the stacked registers into an APCS stack frame, so that DDB backtraces through cpu_switch() will work. This also affects cpu_fork(), which has to fabricate a switchframe and PCB for the new process.
1.17	12-Oct-2002	bjh21	Move curpcb into struct cpu_info in MULTIPROCESSOR kernels.
1.16	05-Oct-2002	bjh21	Minimal changes to allow a kernel with "options MULTIPROCESSOR" to compile and boot multi-user on a single-processor machine. Many of these changes are wildly inappropriate for actual multi-processor operation, and correcting this will be my next task.
1.15	31-Aug-2002	thorpej	Add machine-dependent bits of RAS for arm32.
1.14	23-Jun-2002	thorpej	Garbage-collect sigframe references.
1.13	05-Apr-2002	thorpej	branches: 1.13.2; * Rewrite the 32-bit ARM pte.h based on the ARM architecture manual. Significant cleanup, here, including better PTE bit names. * Add XScale PTE extensions (ECC enable, write-allocate cache mode). * Mechanical changes everywhere else to update for new pte.h. While doing this, two bugs (as a result of typos) were fixed in arm/arm32/bus_dma.c evbarm/integrator/int_bus_dma.c
1.12	23-Mar-2002	thorpej	* Rename PROCESS_PAGE_TBLS_BASE -> PTE_BASE * Rename ALT_PAGE_TBLS_BASE -> APTE_BASE * Garbage-collect PAGE_TABLE_SPACE_START
1.11	03-Mar-2002	chris	Implement pmap_growkernel for arm32 based ports. Note that this has been compiled on some systems, cats, IQ80310, IPAQ, netwinder and shark (note that shark's build is currently broken due to other reasons), but only actually run on cats. Shark doesn't make use of the functionality as I believe there has to be a correlation between OFW and the kernel tables so that calls into OFW work.
1.10	05-Feb-2002	thorpej	Allow platforms to use an extra level of indirection for FIQs, enabled by definining __ARM_FIQ_INDIRECT in <machine/types.h>. This is needed for OpenFirmware systems (like the Shark), where the OFW vector page is used, and kernel entries merely patched into it.
1.9	25-Jan-2002	thorpej	Overhaul of the ARM cache code. This is mostly a simplification pass. Rather than providing a whole slew of cache operations that aren't ever used, distill them down to some useful primitives: icache_sync_all Synchronize I-cache icache_sync_range Synchronize I-cache range dcache_wbinv_all Write-back and Invalidate D-cache dcache_wbinv_range Write-back and Invalidate D-cache range dcache_inv_range Invalidate D-cache range dcache_wb_range Write-back D-cache range idcache_wbinv_all Write-back and Invalidate D-cache, Invalidate I-cache idcache_wbinv_range Write-back and Invalidate D-cache, Invalidate I-cache range Note: This does not yet include an overhaul of the actual asm files that implement the primitives. Instead, we've provided a safe default for each CPU type, and the individual CPU types can now be optimized one at a time.
1.8	20-Dec-2001	thorpej	* Share a common vector page between arm26 and arm32. * Use a common set of exception handlers for all arm32 platforms. * New FIQ framework based on discussions with Ben Harris, shared between arm26 and arm32.
1.7	28-Nov-2001	thorpej	Don't define interrupt handler-related offsets here.
1.6	23-Nov-2001	thorpej	Provide __PROG32 to assembly code.
1.5	09-Sep-2001	toshii	branches: 1.5.4; Don't define pcb_* register macros. pcb_sp macro conflicts with sys/netinet6/ipsec.c.
1.4	05-Sep-2001	matt	branches: 1.4.2; Don't compile SPL/INTR stuff if NEWINTR is defined.
1.3	05-Sep-2001	matt	Change <machine/irqhandler.h> to <machine/intr.h>. Change {irq,fiq}handler_t to struct XXXhandler
1.2	27-Aug-2001	chris	Remove unused entries from the pcb. This is with a long term view of merging the arm26 and arm32 pcb's.
1.1	28-Jul-2001	chris	branches: 1.1.2; finish moving common arm32 bits out into arm/arm32.
1.1.2.8	06-Sep-2002	jdolecek	sync kqueue branch with HEAD
1.1.2.7	23-Jun-2002	jdolecek	catch up with -current on kqueue branch
1.1.2.6	16-Mar-2002	jdolecek	Catch up with -current.
1.1.2.5	11-Feb-2002	jdolecek	Sync w/ -current.
1.1.2.4	10-Jan-2002	thorpej	Sync kqueue branch with -current.
1.1.2.3	13-Sep-2001	thorpej	Update the kqueue branch to HEAD.
1.1.2.2	03-Aug-2001	lukem	update to -current
1.1.2.1	28-Jul-2001	lukem	file genassym.cf was added on branch kqueue on 2001-08-03 04:10:58 +0000
1.4.2.1	01-Oct-2001	fvdl	Catch up with -current.
1.5.4.11	18-Oct-2002	nathanw	Catch up to -current.
1.5.4.10	17-Sep-2002	nathanw	This need L_PROC now, for the RAS code.
1.5.4.9	17-Sep-2002	nathanw	Catch up to -current.
1.5.4.8	01-Aug-2002	nathanw	Catch up to -current.
1.5.4.7	05-Jul-2002	thorpej	When delivering an upcall, arrange to have the kernel return to the upcall directly, and use the upcall trampoline only to exit if the upcall returns.
1.5.4.6	17-Apr-2002	nathanw	Catch up to -current.
1.5.4.5	01-Apr-2002	nathanw	Catch up to -current. (CVS: It's not just a program. It's an adventure!)
1.5.4.4	28-Feb-2002	nathanw	Catch up to -current.
1.5.4.3	08-Jan-2002	nathanw	Catch up to -current.
1.5.4.2	15-Nov-2001	thorpej	Machine-dependent kernel mods for scheduler activations on 32-bit ARM processors. Kernel boots multi-user on an XScale, but upcalls not yet tested.
1.5.4.1	09-Sep-2001	thorpej	file genassym.cf was added on branch nathanw_sa on 2001-11-15 06:39:22 +0000
1.13.2.2	31-Aug-2002	gehenna	catch up with -current.
1.13.2.1	16-Jul-2002	gehenna	catch up with -current.
1.19.2.3	24-Oct-2002	bjh21	Add CI_IDLEPCB for cpu_switch().
1.19.2.2	19-Oct-2002	bjh21	Re-do the following revisions, this time on a branch where they won't interfere with the nathanw_sa merge: syssrc/sys/arch/arm/arm32/cpuswitch.S 1.26 syssrc/sys/arch/arm/arm32/genassym.cf 1.18 syssrc/sys/arch/arm/arm32/vm_machdep.c 1.21 syssrc/sys/arch/arm/include/pcb.h 1.5 Original commit message: In cpu_switch(), stack more registers at the start of the function, and hence save fewer into the PCB. This should give me enough free registers in cpu_switch to tidy things up and support MULTIPROCESSOR properly. While we're here, make the stacked registers into an APCS stack frame, so that DDB backtraces through cpu_switch() will work. This also affects cpu_fork(), which has to fabricate a switchframe and PCB for the new process.
1.19.2.1	19-Oct-2002	bjh21	file genassym.cf was added on branch bjh21-hydra on 2002-10-19 11:59:36 +0000
1.24.2.3	21-Sep-2004	skrll	Fix the sync with head I botched.
1.24.2.2	18-Sep-2004	skrll	Sync with HEAD.
1.24.2.1	03-Aug-2004	skrll	Sync with HEAD
1.27.16.5	21-Jan-2008	yamt	sync with head
1.27.16.4	27-Oct-2007	yamt	sync with head.
1.27.16.3	03-Sep-2007	yamt	sync with head.
1.27.16.2	26-Feb-2007	yamt	sync with head.
1.27.16.1	30-Dec-2006	yamt	sync with head.
1.28.22.1	22-Oct-2006	yamt	sync with head
1.28.20.1	18-Nov-2006	ad	Sync with head.
1.29.4.4	27-Apr-2007	skrll	Remove process/LWP status constants.
1.29.4.3	29-Mar-2007	skrll	Adapt arm32. Thanks to scw for helping out. Tested on my cats (SA1) XXX hydra should die. i've made some changes, but no guarantees.
1.29.4.2	12-Mar-2007	rmind	Sync with HEAD.
1.29.4.1	27-Feb-2007	yamt	- sync with head. - move sched_changepri back to kern_synch.c as it doesn't know PPQ anymore.
1.29.2.2	04-Mar-2007	bouyer	Pull up following revision(s) (requested by matt in ticket #470): sys/arch/evbarm/iq80310/iq80310_timer.c: revision 1.20 sys/arch/evbarm/ifpga/pl030_rtc.c: revision 1.8 sys/arch/evbarm/include/types.h: revision 1.7 sys/arch/arm/arm32/genassym.cf: revision 1.30 sys/arch/arm/arm32/cpuswitch.S: revision 1.46 Get DOMAIN_CLIENT directly from arm/arm32/pte.h instead of from genassym to avoid redefinition when both assymh and pte.h are included (as in INTEGRATOR's intmmu.S, which uses more macros from pte.h). Convert evbarm to __HAVE_GENERIC_TODR.
1.29.2.1	24-Feb-2007	snj	Pull up following revision(s) (requested by matt in ticket #457): sys/arch/arm/arm32/genassym.cf: revision 1.31 Add KERNEL_BASE
1.32.10.2	03-Oct-2007	garbled	Sync with HEAD
1.32.10.1	22-May-2007	matt	Update to HEAD.
1.32.4.1	11-Jul-2007	mjf	Sync with head.
1.32.2.2	09-Oct-2007	ad	Sync with head.
1.32.2.1	27-May-2007	ad	Sync with head.
1.33.12.5	23-Mar-2008	matt	sync with HEAD
1.33.12.4	28-Jan-2008	matt	Add assym symbols needed for fast softint switching
1.33.12.3	09-Jan-2008	matt	sync with HEAD
1.33.12.2	06-Nov-2007	matt	sync with HEAD
1.33.12.1	29-Aug-2007	matt	Update to new world order.
1.33.10.2	20-Jan-2008	chris	Sync to HEAD.
1.33.10.1	01-Jan-2008	chris	Sync with HEAD.
1.33.8.1	02-Oct-2007	joerg	Sync with HEAD.
1.33.6.2	28-Feb-2008	rjs	Sync with HEAD.
1.33.6.1	01-Nov-2007	rjs	Sync with HEAD.
1.35.8.2	20-Jan-2008	bouyer	Sync with HEAD
1.35.8.1	08-Jan-2008	bouyer	Sync with HEAD
1.35.2.1	18-Feb-2008	mjf	Sync with HEAD.
1.38.10.3	11-Mar-2010	yamt	sync with head
1.38.10.2	04-May-2009	yamt	sync with head.
1.38.10.1	16-May-2008	yamt	sync with head.
1.38.8.1	18-May-2008	yamt	sync with head.
1.38.6.2	28-Sep-2008	mjf	Sync with HEAD.
1.38.6.1	02-Jun-2008	mjf	Sync with HEAD.
1.39.6.1	19-Oct-2008	haad	Sync with HEAD.
1.39.2.2	10-Oct-2008	skrll	Sync with HEAD.
1.39.2.1	18-Sep-2008	wrstuden	Sync with wrstuden-revivesa-base-2.
1.41.12.1	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.42.4.2	21-Apr-2011	rmind	sync with head
1.42.4.1	05-Mar-2011	rmind	sync with head
1.44.4.1	08-Feb-2011	bouyer	Sync with HEAD
1.44.2.1	06-Jun-2011	jruoho	Sync with HEAD.
1.46.12.1	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.46.4.4	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.46.4.3	23-Jan-2013	yamt	sync with head
1.46.4.2	16-Jan-2013	yamt	sync with (a bit old) head
1.46.4.1	30-Oct-2012	yamt	sync with head
1.54.2.5	03-Dec-2017	jdolecek	update from HEAD
1.54.2.4	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.54.2.3	23-Jun-2013	tls	resync from head
1.54.2.2	25-Feb-2013	tls	resync with head
1.54.2.1	20-Nov-2012	tls	Resync to 2012-11-19 00:00:00 UTC
1.62.2.2	18-May-2014	rmind	sync with head
1.62.2.1	28-Aug-2013	rmind	sync with head
1.68.2.1	10-Aug-2014	tls	Rebase.
1.69.4.4	28-Aug-2017	skrll	Sync with HEAD
1.69.4.3	22-Sep-2015	skrll	Sync with HEAD
1.69.4.2	06-Jun-2015	skrll	Sync with HEAD
1.69.4.1	06-Apr-2015	skrll	Sync with HEAD
1.69.2.2	23-Jul-2017	snj	Pull up following revision(s) (requested by skrll in ticket #1452): sys/arch/arm/arm32/genassym.cf: revision 1.75 sys/arch/arm/arm/cpufunc_asm_arm11x6.S: revision 1.8 In idcache_wbinv_range if the range size is bigger than the dcache size then call idcache_wbinv_all Avoids a problem with large ranges as seen in port-evbarm/52169: setting dtrace module to load cause Pi to hang on boot
1.69.2.1	27-Mar-2015	martin	Pull up following revision(s) (requested by skrll in ticket #646): sys/arch/arm/arm32/genassym.cf: revision 1.70 sys/arch/arm/arm32/cpuswitch.S: revision 1.86-1.89 Only set vfp & tpid registers and do ras lookups if new lwp is not LW_SYSTEM.
1.74.10.1	12-Jul-2017	martin	Pull up following revision(s) (requested by skrll in ticket #122): sys/arch/arm/arm32/genassym.cf: revision 1.75 sys/arch/arm/arm/cpufunc_asm_arm11x6.S: revision 1.8 In idcache_wbinv_range if the range size is bigger than the dcache size then call idcache_wbinv_all Avoids a problem with large ranges as seen in port-evbarm/52169: setting dtrace module to load cause Pi to hang on boot
1.77.2.2	20-Oct-2018	pgoyette	Sync with head
1.77.2.1	28-Jul-2018	pgoyette	Sync with HEAD
1.78.2.2	08-Apr-2020	martin	Merge changes from current as of 20200406
1.78.2.1	10-Jun-2019	christos	Sync with HEAD
1.82.2.2	29-Feb-2020	ad	Sync with head.
1.82.2.1	17-Jan-2020	ad	Sync with head.
1.36	20-Jun-2020	skrll	KNF #includes Remove some unnecessary ones while I'm here.
1.35	20-Jun-2020	skrll	Trailing whitespace
1.34	01-Sep-2012	matt	Rework includes and include <uvm/uvm_extern.h> for pmap.h
1.33	27-Jul-2012	matt	Remove safepri and use IPL_SAFEPRI instead. This may be defined in a MD header file (if not, a value of 0 is assmued).
1.32	20-Dec-2010	matt	branches: 1.32.8; 1.32.16; Move counting of faults, traps, intrs, soft[intr]s, syscalls, and nswtch from uvmexp to per-cpu cpu_data and move them to 64bits. Remove unneeded includes of <uvm/uvm_extern.h> and/or <uvm/uvm.h>.
1.31	13-Jun-2010	tsutsui	Apply fixes for PR port-arm/43339: Set proper IPL_SOFTfoo values even in !FAST_SOFTINTS case. Some assertions in MI code expect they have unique values, per comments from rmind@. Also cleanup various "interrupt hierarchy" code since IPL_NONE and IPL_SOFTfoo should not be set by any hardware interrupt establish functions. Ok'ed by mrg@, tested on shark and hpcarm.
1.30	19-Nov-2008	matt	branches: 1.30.6; 1.30.8; No need to include <machine/atomic.h>
1.29	11-Jun-2008	rafal	branches: 1.29.2; 1.29.4; 1.29.10; Let the shark boot again. Fixes port-shark/38929. While I'm here fix the splsoft... macros to always raise the IPL (oops!).
1.28	27-Apr-2008	matt	branches: 1.28.2; 1.28.4; Merge kernel changes in matt-armv6 to HEAD.
1.27	24-Feb-2008	matt	branches: 1.27.2; 1.27.4; no need to include opt_irqstats.h
1.26	06-Jan-2008	matt	branches: 1.26.2; 1.26.6; Cleanup softint lossage.
1.25	03-Dec-2007	ad	branches: 1.25.6; Interrupt handling changes, in discussion since February: - Reduce available SPL levels for hardware devices to none, vm, sched, high. - Acquire kernel_lock only for interrupts at IPL_VM. - Implement threaded soft interrupts.
1.24	17-Oct-2007	garbled	branches: 1.24.2; Merge the ppcoea-renovation branch to HEAD. This branch was a major cleanup and rototill of many of the various OEA cpu based PPC ports that focused on sharing as much code as possible between the various ports to eliminate near-identical copies of files in every tree. Additionally there is a new PIC system that unifies the interface to interrupt code for all different OEA ppc arches. The work for this branch was done by a variety of people, too long to list here. TODO: bebox still needs work to complete the transition to -renovation. ofppc still needs a bunch of work, which I will be looking at. ev64260 still needs to be renovated amigappc was not attempted. NOTES: pmppc was removed as an arch, and moved to a evbppc target.
1.23	13-Aug-2007	tsutsui	branches: 1.23.2; Remove all references to spl_mask. Now it isn't used by any sources. Discussed on port-arm.
1.22	04-Aug-2007	tsutsui	branches: 1.22.2; Fix a typo in a debug printf message.
1.21	09-Mar-2007	thorpej	branches: 1.21.2; 1.21.8; 1.21.10; 1.21.12; 1.21.14; 1.21.16; 1.21.18; Make ipl_t and ipl_cookie_t 8-bit values. kmutex is now down to 12 bytes (from 20) on ARM. Approved by Matt Thomas.
1.20	20-Feb-2007	matt	Don't double count uvmexp.softs
1.19	20-Feb-2007	matt	_setsoftintr takes a si, not a ipl, so don't map it. Shark now boots to multiuser!
1.18	18-Feb-2007	matt	Move declaration of spl_smasks. make spl_smasks and soft_interrupts static.
1.17	18-Feb-2007	matt	Don't export spl_smasks or soft_interrupts. They are local to intr.c Make sure that softintr_init() is called when needed. Assume __HAVE_GENERIC_SOFT_INTERRUPTS is defined (since newlock2 requires it).
1.16	18-Feb-2007	matt	Map IPL_SOFTxxx to SI_SOFTxxx.
1.15	18-Feb-2007	matt	Add __HAVE_GENERIC_SOFT_INTERRUPTS support for shark. This was done by extenting the current arm generic intrs to support softintrs. Add IPL_SOFTCLOCK, IPL_SOFTNET, IPL_SOFTSERIAL.
1.14	21-Dec-2006	yamt	branches: 1.14.2; merge yamt-splraiseipl branch. - finish implementing splraiseipl (and makeiplcookie). http://mail-index.NetBSD.org/tech-kern/2006/07/01/0000.html - complete workqueue(9) and fix its ipl problem, which is reported to cause audio skipping. - fix netbt (at least compilation problems) for some ports. - fix PR/33218.
1.13	11-Dec-2005	christos	branches: 1.13.20; 1.13.22; merge ktrace-lwp.
1.12	15-Jul-2003	lukem	branches: 1.12.16; __KERNEL_RCSID()
1.11	16-Jun-2003	thorpej	branches: 1.11.2; Rename IPL_IMP -> IPL_VM.
1.10	19-Oct-2002	bsh	make atomic_{set,clear}_bit() inline for arm32 ports, and add <machine/atomic.h> for them.
1.9	06-Sep-2002	gehenna	branches: 1.9.2; Merge the gehenna-devsw branch into the trunk. This merge changes the device switch tables from static array to dynamically generated by config(8). - All device switches is defined as a constant structure in device drivers. - The new grammer ``device-major'' is introduced to ``files''. device-major <prefix> char <num> [block <num>] [<rules>] - All device major numbers must be listed up in port dependent majors.<arch> by using this grammer. - Added the new naming convention. The name of the device switch must be <prefix>_[bc]devsw for auto-generation of device switch tables. - The backward compatibility of loading block/character device switch by LKM framework is broken. This is necessary to convert from block/character device major to device name in runtime and vice versa. - The restriction to assign device major by LKM is completely removed. We don't need to reserve LKM entries for dynamic loading of device switch. - In compile time, device major numbers list is packed into the kernel and the LKM framework will refer it to assign device major number dynamically.
1.8	31-Jan-2002	chris	branches: 1.8.4; 1.8.8; Fix the type of irqmasks (any reason it's even been added as an extern when it's in irqhandler.h with the correct type and array size?)
1.7	30-Jan-2002	thorpej	New interrupt framework for NetBSD/evbarm, and accompanying new interrupt code for the IQ80310 board support package. XXX The Integrator board support package still uses the old-style arm32 interrupt code, so some compatibility hacks have been added for it. When the Integrator uses new-style interrupts, those hacks can go away.
1.6	07-Jan-2002	chris	Finish up the changes to get LOOSE_PROTOTYPES working for cats. Note that this leaves a few inconsistencies (no more than we already had though) eg initarm is now prototyped in arm32/machdep.h, however only cats currently makes use of that header.
1.5	21-Dec-2001	bjh21	Merge ast() and userret() between arm32 and arm26. The implementation used is the arm32 one.
1.4	26-Nov-2001	thorpej	Move interrupt-related stuff out of stubs.c into intr.c.
1.3	27-Oct-2001	rearnsha	branches: 1.3.2; Pull in machine/conf.h to find out if we have the plcom serial driver. If so, then call plcomsoft when appropriate.
1.2	05-Sep-2001	matt	branches: 1.2.4; Change <machine/irqhandler.h> to <machine/intr.h> since the latter always includes the former and is a standard include file.
1.1	28-Jul-2001	chris	branches: 1.1.2; Move the generic arm32 files into arm/arm32 from arm32/arm32, tested kernel builds on cats and riscpc.
1.1.2.6	10-Oct-2002	jdolecek	sync kqueue with -current; this includes merge of gehenna-devsw branch, merge of i386 MP branch, and part of autoconf rototil work
1.1.2.5	11-Feb-2002	jdolecek	Sync w/ -current.
1.1.2.4	10-Jan-2002	thorpej	Sync kqueue branch with -current.
1.1.2.3	13-Sep-2001	thorpej	Update the kqueue branch to HEAD.
1.1.2.2	03-Aug-2001	lukem	update to -current
1.1.2.1	28-Jul-2001	lukem	file intr.c was added on branch kqueue on 2001-08-03 04:10:58 +0000
1.2.4.1	12-Nov-2001	thorpej	Sync the thorpej-mips-cache branch with -current.
1.3.2.6	11-Nov-2002	nathanw	Catch up to -current
1.3.2.5	17-Sep-2002	nathanw	Catch up to -current.
1.3.2.4	28-Feb-2002	nathanw	Catch up to -current.
1.3.2.3	11-Jan-2002	nathanw	More catchup.
1.3.2.2	08-Jan-2002	nathanw	Catch up to -current.
1.3.2.1	27-Oct-2001	nathanw	file intr.c was added on branch nathanw_sa on 2002-01-08 00:23:08 +0000
1.8.8.1	19-May-2002	gehenna	Remove unnecessary #include
1.8.4.1	17-Mar-2002	thorpej	IPL_IMP -> IPL_VM
1.9.2.1	24-Oct-2002	bjh21	Sync with trunk.
1.11.2.3	21-Sep-2004	skrll	Fix the sync with head I botched.
1.11.2.2	18-Sep-2004	skrll	Sync with HEAD.
1.11.2.1	03-Aug-2004	skrll	Sync with HEAD
1.12.16.6	27-Feb-2008	yamt	sync with head.
1.12.16.5	21-Jan-2008	yamt	sync with head
1.12.16.4	07-Dec-2007	yamt	sync with head
1.12.16.3	03-Sep-2007	yamt	sync with head.
1.12.16.2	26-Feb-2007	yamt	sync with head.
1.12.16.1	30-Dec-2006	yamt	sync with head.
1.13.22.6	18-Dec-2006	yamt	ipl_to_spl: include ipl number in panic messages.
1.13.22.5	23-Oct-2006	yamt	ipl_to_spl: add IPL_STATCLOCK.
1.13.22.4	09-Oct-2006	yamt	add missing IPL_NONE case.
1.13.22.3	21-Sep-2006	yamt	implement splraiseipl for hpcarm, shark, and acorn32.
1.13.22.2	21-Sep-2006	yamt	revert the previous which was committed unintentionally.
1.13.22.1	21-Sep-2006	yamt	* empty log message *
1.13.20.1	12-Jan-2007	ad	Sync with head.
1.14.2.2	12-Mar-2007	rmind	Sync with HEAD.
1.14.2.1	27-Feb-2007	yamt	- sync with head. - move sched_changepri back to kern_synch.c as it doesn't know PPQ anymore.
1.21.18.3	09-Dec-2007	jmcneill	Sync with HEAD.
1.21.18.2	16-Aug-2007	jmcneill	Sync with HEAD.
1.21.18.1	09-Aug-2007	jmcneill	Sync with HEAD.
1.21.16.3	28-Feb-2008	rjs	Sync with HEAD.
1.21.16.2	26-Dec-2007	rjs	Sync with HEAD.
1.21.16.1	01-Nov-2007	rjs	Sync with HEAD.
1.21.14.1	15-Aug-2007	skrll	Sync with HEAD.
1.21.12.1	07-Aug-2007	matt	Sync with HEAD.
1.21.10.1	03-Oct-2007	garbled	Sync with HEAD
1.21.8.1	19-Apr-2007	thorpej	Convert to the new atomic ops API.
1.21.2.2	03-Dec-2007	ad	Sync with HEAD.
1.21.2.1	20-Aug-2007	ad	Sync with HEAD.
1.22.2.5	21-Mar-2008	chris	Sync with head.
1.22.2.4	26-Jan-2008	chris	Fix merge botch.
1.22.2.3	20-Jan-2008	chris	Sync to HEAD.
1.22.2.2	01-Jan-2008	chris	Sync with HEAD.
1.22.2.1	18-Aug-2007	chris	Sync with HEAD
1.23.2.4	23-Mar-2008	matt	sync with HEAD
1.23.2.3	28-Jan-2008	matt	Given the that there are only 4 IPLs (ignoring soft IPLs), a number of cleanups can be done: Remove _SPL_* aliases. Don't store irqmasks in ci_cpl, just make it an ipl level. Add fast softint switching support.
1.23.2.2	09-Jan-2008	matt	sync with HEAD
1.23.2.1	11-Sep-2007	matt	s/current_spl_level/curcpu()->ci_cpl/
1.24.2.2	18-Feb-2008	mjf	Sync with HEAD.
1.24.2.1	08-Dec-2007	mjf	Sync with HEAD.
1.25.6.1	08-Jan-2008	bouyer	Sync with HEAD
1.26.6.4	17-Jan-2009	mjf	Sync with HEAD.
1.26.6.3	29-Jun-2008	mjf	Sync with HEAD.
1.26.6.2	02-Jun-2008	mjf	Sync with HEAD.
1.26.6.1	03-Apr-2008	mjf	Sync with HEAD.
1.26.2.1	24-Mar-2008	keiichi	sync with head.
1.27.4.3	11-Aug-2010	yamt	sync with head.
1.27.4.2	04-May-2009	yamt	sync with head.
1.27.4.1	16-May-2008	yamt	sync with head.
1.27.2.2	17-Jun-2008	yamt	sync with head.
1.27.2.1	18-May-2008	yamt	sync with head.
1.28.4.1	18-Jun-2008	simonb	Sync with head.
1.28.2.1	23-Jun-2008	wrstuden	Sync w/ -current. 34 merge conflicts to follow.
1.29.10.1	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.29.4.1	19-Jan-2009	skrll	Sync with HEAD.
1.29.2.1	13-Dec-2008	haad	Update haad-dm branch to haad-dm-base2.
1.30.8.2	05-Mar-2011	rmind	sync with head
1.30.8.1	03-Jul-2010	rmind	sync with head
1.30.6.1	17-Aug-2010	uebayasi	Sync with HEAD.
1.32.16.1	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.32.8.1	30-Oct-2012	yamt	sync with head
1.17	21-Nov-2020	skrll	Sprinkle some comments about ENABLE_ALIGNMENT_FAULTS leaving curcpu in r4 and curlwp in r5
1.16	02-Jun-2015	matt	branches: 1.16.30; Add a clrex/dmb to irq path as recommended by ARM.
1.15	18-Aug-2013	matt	branches: 1.15.6; Move parts of cpu.h that are not needed by MI code in <arm/locore.h> Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h> Use <arm/asm.h> instead of <machine/arm.h>
1.14	21-Oct-2012	matt	branches: 1.14.2; Add softint processing for irq_idle_entry
1.13	21-Oct-2012	matt	Implement a "fast" path for IRQ handling out of the idle loop. Since we are in SVC32 already we only need to save a few registers. Processing is also simplified since we know we can't return to user-mode.
1.12	29-Aug-2012	matt	branches: 1.12.2; Avoid using r7 (which is being reserved for a different purpose).
1.11	28-May-2011	jakllsch	branches: 1.11.4; 1.11.12; Remove unused local variable. Spelling fix in comment.
1.10	27-Apr-2008	matt	branches: 1.10.18; 1.10.22; 1.10.28; Merge kernel changes in matt-armv6 to HEAD.
1.9	06-Jan-2008	matt	branches: 1.9.6; 1.9.8; 1.9.10; Truly kill current_intr_depth once and for all.
1.8	09-Mar-2007	thorpej	branches: 1.8.8; 1.8.16; 1.8.20; 1.8.22; 1.8.28; 1.8.34; Rewrite the ARM mutex implementation to be of the simple-mutex variety. Because pre-v6 ARM lacks support for an atomic compare-and-swap, we implement _lock_cas() as a restartable atomic squence that is checked in the IRQ handler right before AST processing. (This is safe because, for all practical purposes, there are no SMP pre-v6 ARM systems.) This can serve as a model for other non-MP platforms that lack the necessary atomic operations for mutexes (SuperH, for example). Upshots of this change: - kmutex_t is now down to 8 bytes on ARM; about as good as we can get. - ARM2 systems don't have to trap and emulate SWP or SWPB for mutexes. The acorn26 port is not updated by this commit to do the LOCK_CAS_CHECK. That is left as an exercise for the port maintainer. Reviewed and tested by Matt Thomas.
1.7	11-Dec-2005	christos	branches: 1.7.26; merge ktrace-lwp.
1.6	31-May-2005	chs	branches: 1.6.2; remove vestigal {,e}intr{names,cnt} symbols now that vmstat doesn't need them.
1.5	30-Oct-2003	scw	Move the alignment fault enable/disable code into macroes to avoid needless duplication. Additionally, merge AST handling into the same code. exception.S and the generic irq_dispatch.S routines have been updated to use the macroes. XXX: I have patches for the non-generic IRQ dispatch routines, but they need testing by someone with hardware.
1.4	26-Oct-2003	scw	Assume that if curpcb is NULL, we're already running with alignment faults enabled.
1.3	25-Oct-2003	scw	Oops, forgot to commit this along with the others... Enable alignment faults on arm32 for both kernel and userland. If COMPAT_15 and EXEC_AOUT are defined, support per-process alignment checking where AFLTs are always enabled when running kernel code and userland ELF binaries, and dynamically disabled/ enabled when switching to/from a.out binaries. This is necessary in order to execute older a.out binaries, where gcc made deliberate use of misaligned loads under certain circumstances.
1.2	03-Jan-2003	thorpej	branches: 1.2.2; 1.2.4; Fiddle with current_intr_depth in assembly code again. Because we have just pushed a frame, we can make some assumptions that the compiler cannot as easily make, and can thus do it slightly more efficiently.
1.1	02-Jan-2003	thorpej	Clean up evbarm interrupt support a little: * Define an ARM_INTR_IMPL option, which specifies a header file describing the interrupt implementation for the platform. Use this instead of the list of EVBARM_BOARDTYPE checks. * Make the s3c2xx0 interrupt dispatch code a bit more generic, and move it to a generic location so that other platforms can use it. This eliminates all uses of the EVBARM_BOARDTYPE stuff, so delete it.
1.2.4.4	10-Nov-2005	skrll	Sync with HEAD. Here we go again...
1.2.4.3	21-Sep-2004	skrll	Fix the sync with head I botched.
1.2.4.2	18-Sep-2004	skrll	Sync with HEAD.
1.2.4.1	03-Aug-2004	skrll	Sync with HEAD
1.2.2.2	03-Jan-2003	thorpej	Sync with HEAD.
1.2.2.1	03-Jan-2003	thorpej	file irq_dispatch.S was added on branch nathanw_sa on 2003-01-03 16:41:07 +0000
1.6.2.2	21-Jan-2008	yamt	sync with head
1.6.2.1	03-Sep-2007	yamt	sync with head.
1.7.26.1	12-Mar-2007	rmind	Sync with HEAD.
1.8.34.1	08-Jan-2008	bouyer	Sync with HEAD
1.8.28.1	18-Feb-2008	mjf	Sync with HEAD.
1.8.22.2	09-Jan-2008	matt	sync with HEAD
1.8.22.1	28-Aug-2007	matt	Teach this about the new world order (cpu_info = r4, intr_depth in cpu_info)
1.8.20.1	20-Jan-2008	chris	Sync to HEAD.
1.8.16.1	28-Feb-2008	rjs	Sync with HEAD.
1.8.8.1	18-Apr-2007	thorpej	Remove _lock_cas() in favor of atomic_cas_32().
1.9.10.1	16-May-2008	yamt	sync with head.
1.9.8.1	18-May-2008	yamt	sync with head.
1.9.6.1	02-Jun-2008	mjf	Sync with HEAD.
1.10.28.1	06-Jun-2011	jruoho	Sync with HEAD.
1.10.22.1	31-May-2011	rmind	sync with head
1.10.18.1	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.11.12.1	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.11.4.2	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.11.4.1	30-Oct-2012	yamt	sync with head
1.12.2.3	03-Dec-2017	jdolecek	update from HEAD
1.12.2.2	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.12.2.1	20-Nov-2012	tls	Resync to 2012-11-19 00:00:00 UTC
1.14.2.1	28-Aug-2013	rmind	sync with head
1.15.6.1	06-Jun-2015	skrll	Sync with HEAD
1.16.30.1	14-Dec-2020	thorpej	Sync w/ HEAD.
1.10	20-Jun-2020	skrll	KNF
1.9	20-Jun-2020	skrll	KNF #includes Remove some unnecessary ones while I'm here.
1.8	20-Jun-2020	skrll	Trailing whitespace
1.7	18-Oct-2009	snj	Move Matthias Pfaller's files to 2-clause license. OK matthias@.
1.6	14-Mar-2009	dsl	Change about 4500 of the K&R function definitions to ANSI ones. There are still about 1600 left, but they have ',' or /* ... */ in the actual variable definitions - which my awk script doesn't handle. There are also many that need () -> (void). (The script does handle misordered arguments.)
1.5	11-Jan-2009	cegger	branches: 1.5.2; adaption for making kgdb_dev a dev_t
1.4	24-Dec-2005	perry	branches: 1.4.76; 1.4.80; 1.4.88; 1.4.96; bare asm -> __asm
1.3	11-Dec-2005	christos	merge ktrace-lwp.
1.2	15-Jul-2003	lukem	branches: 1.2.16; __KERNEL_RCSID()
1.1	28-Apr-2003	briggs	branches: 1.1.2; Add arm32 machine-specific remote kgdb support. Largely from PR port-arm/15530 by bsh@, but with some updates from me, including a fresh arm32/kgdb_machdep.c--ported from pc532.
1.1.2.3	21-Sep-2004	skrll	Fix the sync with head I botched.
1.1.2.2	18-Sep-2004	skrll	Sync with HEAD.
1.1.2.1	03-Aug-2004	skrll	Sync with HEAD
1.2.16.1	21-Jun-2006	yamt	sync with head.
1.4.96.1	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.4.88.2	28-Apr-2009	skrll	Sync with HEAD.
1.4.88.1	19-Jan-2009	skrll	Sync with HEAD.
1.4.80.2	11-Mar-2010	yamt	sync with head
1.4.80.1	04-May-2009	yamt	sync with head.
1.4.76.1	17-Jan-2009	mjf	Sync with HEAD.
1.5.2.1	13-May-2009	jym	Sync with HEAD. Commit is split, to avoid a "too many arguments" protocol error.
1.16	28-Apr-2023	skrll	Pass local symbols relocations in both passes and provide the kobj_reloc implementation visibility of these relocations. Currently all implementations resolve local symbol relocations in the first pass and simply skip them in the second. The RISC-V implementation will make use of this visiblity.
1.15	01-Dec-2020	rin	Switch earmv6{,hf}eb to BE8 in kernel side. My strategy here is to define _ARM_ARCH_BE8 macro in arm/cdefs.h, if __ARMEB__ && _ARM_ARCH_6. Use this macro to determine whether system is compiled for and running on BE8 mode or not. Note that, for __ARMEB__, some conditions become compile-time constants determined by _ARM_ARCH_BE8 macro, e.g., whether BE8 or BE32 are accepted as a userland binary, or unaligned memory access is possible or not.
1.14	20-Jun-2020	skrll	branches: 1.14.2; KNF #includes Remove some unnecessary ones while I'm here.
1.13	20-Jun-2020	skrll	Trailing whitespace
1.12	03-Nov-2017	maxv	Handle absolute relocations coming from the kernel: preserve SHN_ABS in the kernel and module symbols, and when relocating a symbol that has SHN_ABS, take its value as-is and don't return an error if it equals zero. Sent on tech-kern@.
1.11	11-Jul-2016	martin	kobj_machdep() is now called multiple times for the same module. Only do arm-BE8 symbol fixup when called for the text segment.
1.10	07-Nov-2014	martin	branches: 1.10.2; PR port-arm/49299: add support for BE8 byte swapped instructions.
1.9	27-Aug-2013	skrll	branches: 1.9.4; Minor tidyup
1.8	27-Aug-2013	skrll	Support R_ARM_REL32 and R_ARM_PREL31. ok matt.
1.7	09-Aug-2013	matt	Use cpu_idcache_wbinv_range so we don't nuke the entire idcache. Add a test to make sure we are only modifying movw/movt
1.6	09-Aug-2013	matt	Fix addend manipulation
1.5	08-Aug-2013	matt	Don't sync idcache/tlb when _RUMPKERNEL is defined.
1.4	07-Aug-2013	matt	Add R_ARM_V4BX, R_ARM_MOVW_ABS_NC, R_ARM_MOVT_ABS Fix R_ARM_PC24 and match R_ARM_CALL and R_ARM_JUMP24
1.3	17-Aug-2009	dsl	branches: 1.3.12; 1.3.22; 1.3.26; Add support for R_ARM_PC24 relocations and fix R_ARM_ABS32. Changes from PR/40309, but structure changed so there is a common error printf. Compiles ok, but my quick kernel build failed to find module_init_md().
1.2	28-Apr-2008	martin	branches: 1.2.18; Remove clause 3 and 4 from TNF licenses
1.1	04-Jan-2008	ad	branches: 1.1.2; 1.1.4; 1.1.6; 1.1.8; 1.1.10; 1.1.16; 1.1.18; 1.1.20; 1.1.22; Linker bits for arm.
1.1.22.2	19-Aug-2009	yamt	sync with head.
1.1.22.1	16-May-2008	yamt	sync with head.
1.1.20.1	18-May-2008	yamt	sync with head.
1.1.18.2	28-Feb-2008	rjs	Sync with HEAD.
1.1.18.1	04-Jan-2008	rjs	file kobj_machdep.c was added on branch hpcarm-cleanup on 2008-02-28 21:58:52 +0000
1.1.16.1	02-Jun-2008	mjf	Sync with HEAD.
1.1.10.2	18-Feb-2008	mjf	Sync with HEAD.
1.1.10.1	04-Jan-2008	mjf	file kobj_machdep.c was added on branch mjf-devfs on 2008-02-18 21:04:22 +0000
1.1.8.2	21-Jan-2008	yamt	sync with head
1.1.8.1	04-Jan-2008	yamt	file kobj_machdep.c was added on branch yamt-lazymbuf on 2008-01-21 09:35:36 +0000
1.1.6.2	20-Jan-2008	chris	Sync to HEAD.
1.1.6.1	04-Jan-2008	chris	file kobj_machdep.c was added on branch chris-arm-intr-rework on 2008-01-20 16:03:57 +0000
1.1.4.2	09-Jan-2008	matt	sync with HEAD
1.1.4.1	04-Jan-2008	matt	file kobj_machdep.c was added on branch matt-armv6 on 2008-01-09 01:45:12 +0000
1.1.2.2	08-Jan-2008	bouyer	Sync with HEAD
1.1.2.1	04-Jan-2008	bouyer	file kobj_machdep.c was added on branch bouyer-xeni386 on 2008-01-08 22:09:25 +0000
1.2.18.1	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.3.26.1	28-Aug-2013	rmind	sync with head
1.3.22.2	03-Dec-2017	jdolecek	update from HEAD
1.3.22.1	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.3.12.1	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.9.4.1	14-Nov-2014	snj	Pull up following revision(s) (requested by martin in ticket #228): sys/arch/arm/arm32/kobj_machdep.c: revision 1.10 PR port-arm/49299: add support for BE8 byte swapped instructions.
1.10.2.1	05-Oct-2016	skrll	Sync with HEAD
1.14.2.1	14-Dec-2020	thorpej	Sync w/ HEAD.
1.44	02-Apr-2022	skrll	Update to support EFI runtime outside the kernel virtual address space by creating an EFI RT pmap that can be activated / deactivated when required. Adds support for EFI RT to ARM_MMU_EXTENDED (ASID) 32-bit Arm machines. On Arm64 the usage of pmapboot_enter is reduced and the mappings are created much later in the boot process -- now in cpu_startup_hook. Backward compatiblity for KVA mapped RT from old bootaa64.efi is maintained. Adding support to other platforms should be easier as a result.
1.43	28-Aug-2020	skrll	Some KASAN fixes and tweaks - don't access BSS variables when __md_early - centralise the INIT_ARM_STACK_{SHIFT,SIZE} defines and create a new INIT_ARM_TOTAL_STACK - Only create L1PT entries in kasan_md_shadow_map_page if arm32_kernel_vm_init hasn't created the L2PTs (and their L1PT entries) - Add some comments to explain what's going on
1.42	28-Aug-2020	skrll	Fix typo
1.41	08-Jul-2020	skrll	Use the stack provided by armv6_start.S rather than svcstk. This saves some bss too.
1.40	14-Jul-2019	skrll	Spell initarm correctly in comments
1.39	18-Oct-2018	skrll	Provide generic start code that assumes the MMU is off and caches are disabled as per the linux booting protocol for ARMv6 and ARMv7 boards. u-boot image type should be changed to 'linux' for correct behaviour. The new start code builds a minimal "bootstrap" L1PT with cached access disabled and uses the same table for all processors. AP startup is performed in less steps and more code is written in C. The bootstrap tables and stack are placed into an (orphaned) section "_init_memory" which is given to uvm when it is no longer used. Various kernels have been converted to use this code and tested. Some boards were provided by TNF. Thanks! The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS kernels. The GENERIC kernel will also work on RPI2 using u-boot. Thanks to martin@ and aymeric@ for testing on parallella and nanosoc respectively
1.38	14-Oct-2017	skrll	branches: 1.38.2; 1.38.4; Fix a comment
1.37	27-Aug-2014	matt	Make the initial svcstack is doubleword aligned if EABI.
1.36	11-Apr-2014	matt	branches: 1.36.2; whitespace cleanup
1.35	17-Dec-2013	joerg	branches: 1.35.2; Write out register pairs for strd.
1.34	01-Dec-2013	joerg	For load/store double, name the second register explicitly.
1.33	18-Aug-2013	matt	Move parts of cpu.h that are not needed by MI code in <arm/locore.h> Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h> Use <arm/asm.h> instead of <machine/arm.h>
1.32	17-Jun-2013	matt	branches: 1.32.2; If possible, use strd to clear .bss
1.31	27-Feb-2013	matt	Don't include <machine/param.h> since we should be getting that stuff from "assym.h"
1.30	21-Nov-2012	matt	Fix missing registers (don't make then implicit).
1.29	27-Sep-2012	matt	Make sure SPSR[23:8] is set to a known valid value (taken from CPSR).
1.28	03-Sep-2012	matt	branches: 1.28.2; Always cpu_info_store as the 3rd work unless TPIDRPRW_IS_CURLWP and then it needs to be lwp0. Fix IGEPV2 boot problem.
1.27	29-Aug-2012	matt	Rename ARM options PROCESS_ID_IS_CUR{CPU,LWP} to TPIDRPRW_IS_CUR{CPU,LWP} since TPIDRPRW is the cp15 register name. Initialize it early in start along with CI_ARM_CPUID. Remove other initializations. We alays have ci_curlwp. Enable TIPRPRW_IS_CURCPU in std.beagle. [tested on a beaglboard (cortex-a8)]
1.26	16-Aug-2012	matt	Move the standard definitions of the {UND,IRQ,FIQ,ABT}_STACK_SIZE to <arm32/machdep.h> Move the extern for cpu_reset_address to the same file. Add cpu_reset_address_paddr. Kill cpu_reset_v4_MMU_disable. if cpu_reset_address is NULL, then the MMU will be disabled.
1.25	19-Jun-2010	matt	branches: 1.25.8; 1.25.16; Cleanup the armv7 changes. Add ARM_ARCH_7. Use CPU_CORTEX instead of CPU_CORTEXA8 everywhere since there more types of Cortex than just the A8. CPU_CORTEXA8 still exists but causes CPU_CORTEX to be defined. Add CPU_CORTEXA9 as well. Use .arch armv7a to get us the isb/dsb instructions. Test booted to root device prompt on a Beagleboard. All ARM kernels successfully test built.
1.24	07-Aug-2008	matt	branches: 1.24.12; 1.24.14; 1.24.16; Use IF32_bits instead of I32_bit \| F32_bit
1.23	27-Apr-2008	matt	branches: 1.23.2; 1.23.6; Merge kernel changes in matt-armv6 to HEAD.
1.22	19-Jan-2008	chris	branches: 1.22.6; 1.22.8; 1.22.10; Remove arm support for IPKDB. It hasn't worked since arm was broken out from arm32 in Jan 2001, and no-one has noticed or cared to fix it.
1.21	13-Jan-2008	skrll	Update a comment.
1.20	12-Jan-2008	skrll	Push a switchframe in dumpsys and cpu_switchto, but as dumpsys calls other funcs a switchframe needs to be a multiple of 8 bytes. Stash sp as well in the switchframe to bump it to 24bytes. Setup the switchframe appropriately in cpu_lwp_fork. Remove savectx - nothing uses it. All of this make gdb's life much easier when dealing with crash dumps and live kernels. Reviewd by chris.
1.19	01-Jan-2008	chris	Add support for kcore headers to arm32 kernel core dumps. The kcore code is based on i386's kcore header handling. Having an asm stub for dumpsys, to dump the registers onto the stack, and then call the C code to do the memory dump is based on amd64's core dump code. This allows a successful core dump on cats. Part of fixing PR cats/18026.
1.18	11-Dec-2005	christos	branches: 1.18.46; 1.18.50; 1.18.52; 1.18.58; 1.18.60; 1.18.66; merge ktrace-lwp.
1.17	10-Oct-2005	pooka	foreach NOTEACHED make the comment say NOTREACHED
1.16	19-Nov-2004	skrll	branches: 1.16.12; Fix syntax error from 1.9. I guess IPKDB isn't used very much...
1.15	13-Feb-2004	wiz	Uppercase CPU, plural is CPUs.
1.14	20-Apr-2003	thorpej	branches: 1.14.2; Reinstate one change from rev. 1.12, but differently. Preload r2 with 0 before frobbing the control register, and use r2 in the ARMv4 TLB flush.
1.13	20-Apr-2003	thorpej	Back out previous. There were several problems with the patch that was checked in: * It was not actually disabling the MMU, and so jumping to the reset vector would happily cause a panic(), since it would be the kernel's reset vector, not the ROM's. * In the event the system was using high vectors, VECRELOC was not getting cleared, which has the potential to wreak havoc when re-entering the ROM. * It was totally broken for CPUs < ARMv4; you still need to disable the MMU on those, just need to skip the ARMv4 TLB flush. * The code that was checked in would only work if the kernel is mapped VA==PA. For systems where the kernel is NOT mapped VA==PA, you only get the prefetch depth # of insns (2) after the MMU is turned off before you have fix the PC. Backing out the change fixes rebooting on several evbarm platforms.
1.12	26-Mar-2003	mycroft	Fix multiple bugs in the way we do the v4 MMU disable -- it was blasting way too many bits (including some reserved ones) and was writing the wrong value for the TLB flush. Also, if the flag is off, don't write the control register!
1.11	19-Oct-2002	bsh	make atomic_{set,clear}_bit() inline for arm32 ports, and add <machine/atomic.h> for them.
1.10	15-Oct-2002	bsh	branches: 1.10.2; fix a bug sneaked into cpu_reset() in "- . - 8 purge" (s/mov pc,lr/mov lr,pc/)
1.9	13-Oct-2002	bjh21	Instead of "add rd, pc, #foo - . - 8", use either "adr rd, foo" or (where appropriate) "mov lr, pc". This makes things slightly less confusing and ugly.
1.8	17-Aug-2002	thorpej	More local label fixups.
1.7	15-Aug-2002	briggs	* Use local label names (.Lfoo vs. (Lfoo or foo)) * When moving from cpsr, use "cpsr" instead of "cpsr_all" (which is provided, but doesn't make sense since mrs doesn't support fields like msr does).
1.6	25-Apr-2002	thorpej	branches: 1.6.2; Make a comment describe what the code actually does.
1.5	03-Apr-2002	thorpej	Always provide kernel_text.
1.4	25-Mar-2002	thorpej	* Clean up some comments/whitespace. * Don't construct a fake trap frame and pass it to main(); that hasn't been needed for some time. * panic if main() returns.
1.3	25-Jan-2002	thorpej	Overhaul of the ARM cache code. This is mostly a simplification pass. Rather than providing a whole slew of cache operations that aren't ever used, distill them down to some useful primitives: icache_sync_all Synchronize I-cache icache_sync_range Synchronize I-cache range dcache_wbinv_all Write-back and Invalidate D-cache dcache_wbinv_range Write-back and Invalidate D-cache range dcache_inv_range Invalidate D-cache range dcache_wb_range Write-back D-cache range idcache_wbinv_all Write-back and Invalidate D-cache, Invalidate I-cache idcache_wbinv_range Write-back and Invalidate D-cache, Invalidate I-cache range Note: This does not yet include an overhaul of the actual asm files that implement the primitives. Instead, we've provided a safe default for each CPU type, and the individual CPU types can now be optimized one at a time.
1.2	20-Dec-2001	thorpej	* Share a common vector page between arm26 and arm32. * Use a common set of exception handlers for all arm32 platforms. * New FIQ framework based on discussions with Ben Harris, shared between arm26 and arm32.
1.1	28-Jul-2001	chris	branches: 1.1.2; 1.1.8; finish moving common arm32 bits out into arm/arm32.
1.1.8.9	11-Nov-2002	nathanw	Catch up to -current
1.1.8.8	18-Oct-2002	nathanw	Catch up to -current.
1.1.8.7	19-Aug-2002	thorpej	Partial (ARM only) sync with trunk -- significant performance improvements for XScale-based systems.
1.1.8.6	20-Jun-2002	nathanw	Catch up to -current.
1.1.8.5	17-Apr-2002	nathanw	Catch up to -current.
1.1.8.4	01-Apr-2002	nathanw	Catch up to -current. (CVS: It's not just a program. It's an adventure!)
1.1.8.3	28-Feb-2002	nathanw	Catch up to -current.
1.1.8.2	08-Jan-2002	nathanw	Catch up to -current.
1.1.8.1	28-Jul-2001	nathanw	file locore.S was added on branch nathanw_sa on 2002-01-08 00:23:09 +0000
1.1.2.6	06-Sep-2002	jdolecek	sync kqueue branch with HEAD
1.1.2.5	23-Jun-2002	jdolecek	catch up with -current on kqueue branch
1.1.2.4	11-Feb-2002	jdolecek	Sync w/ -current.
1.1.2.3	10-Jan-2002	thorpej	Sync kqueue branch with -current.
1.1.2.2	03-Aug-2001	lukem	update to -current
1.1.2.1	28-Jul-2001	lukem	file locore.S was added on branch kqueue on 2001-08-03 04:10:58 +0000
1.6.2.1	30-Aug-2002	gehenna	catch up with -current.
1.10.2.1	24-Oct-2002	bjh21	Sync with trunk.
1.14.2.5	10-Nov-2005	skrll	Sync with HEAD. Here we go again...
1.14.2.4	29-Nov-2004	skrll	Sync with HEAD.
1.14.2.3	21-Sep-2004	skrll	Fix the sync with head I botched.
1.14.2.2	18-Sep-2004	skrll	Sync with HEAD.
1.14.2.1	03-Aug-2004	skrll	Sync with HEAD
1.16.12.2	21-Jan-2008	yamt	sync with head
1.16.12.1	21-Jun-2006	yamt	sync with head.
1.18.66.3	20-Jan-2008	bouyer	Sync with HEAD
1.18.66.2	19-Jan-2008	bouyer	Sync with HEAD
1.18.66.1	02-Jan-2008	bouyer	Sync with HEAD
1.18.60.1	10-Nov-2007	matt	Add AT91 support from Sami Kantoluoto Add TI OMAP2430 support from Marty Fouts @ Danger Inc
1.18.58.1	18-Feb-2008	mjf	Sync with HEAD.
1.18.52.2	23-Mar-2008	matt	sync with HEAD
1.18.52.1	09-Jan-2008	matt	sync with HEAD
1.18.50.2	20-Jan-2008	chris	Sync to HEAD.
1.18.50.1	01-Jan-2008	chris	Sync with HEAD.
1.18.46.1	28-Feb-2008	rjs	Sync with HEAD.
1.22.10.3	11-Aug-2010	yamt	sync with head.
1.22.10.2	04-May-2009	yamt	sync with head.
1.22.10.1	16-May-2008	yamt	sync with head.
1.22.8.1	18-May-2008	yamt	sync with head.
1.22.6.2	28-Sep-2008	mjf	Sync with HEAD.
1.22.6.1	02-Jun-2008	mjf	Sync with HEAD.
1.23.6.1	19-Oct-2008	haad	Sync with HEAD.
1.23.2.1	18-Sep-2008	wrstuden	Sync with wrstuden-revivesa-base-2.
1.24.16.1	03-Jul-2010	rmind	sync with head
1.24.14.1	17-Aug-2010	uebayasi	Sync with HEAD.
1.24.12.1	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.25.16.1	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.25.8.3	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.25.8.2	16-Jan-2013	yamt	sync with (a bit old) head
1.25.8.1	30-Oct-2012	yamt	sync with head
1.28.2.5	03-Dec-2017	jdolecek	update from HEAD
1.28.2.4	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.28.2.3	23-Jun-2013	tls	resync from head
1.28.2.2	25-Feb-2013	tls	resync with head
1.28.2.1	20-Nov-2012	tls	Resync to 2012-11-19 00:00:00 UTC
1.32.2.2	18-May-2014	rmind	sync with head
1.32.2.1	28-Aug-2013	rmind	sync with head
1.35.2.1	10-Aug-2014	tls	Rebase.
1.36.2.1	14-Nov-2014	martin	Pull up the following revisions, requested by skrll in ticket #222: src/sys/arch/arm/arm32/locore.S 1.37 src/sys/arch/arm/arm32/bus_dma.c 1.87 Make the initial svcstack is doubleword aligned if EABI. With PMAP_NEED_ALLOC_POOLPAGE, before using pmap_map_poolpage make sure the page comes from the same freelist that pmap_map_poolpage uses.
1.38.4.2	13-Apr-2020	martin	Mostly merge changes from HEAD upto 20200411
1.38.4.1	10-Jun-2019	christos	Sync with HEAD
1.38.2.1	20-Oct-2018	pgoyette	Sync with head
1.32	12-Jun-2011	rmind	Welcome to 5.99.53! Merge rmind-uvmplock branch: - Reorganize locking in UVM and provide extra serialisation for pmap(9). New lock order: [vmpage-owner-lock] -> pmap-lock. - Simplify locking in some pmap(9) modules by removing P->V locking. - Use lock object on vmobjlock (and thus vnode_t::v_interlock) to share the locks amongst UVM objects where necessary (tmpfs, layerfs, unionfs). - Rewrite and optimise x86 TLB shootdown code, make it simpler and cleaner. Add TLBSTATS option for x86 to collect statistics about TLB shootdowns. - Unify /dev/mem et al in MI code and provide required locking (removes kernel-lock on some ports). Also, avoid cache-aliasing issues. Thanks to Andrew Doran and Joerg Sonnenberger, as their initial patches formed the core changes of this branch.
1.31	08-Feb-2011	rmind	branches: 1.31.2; Remove clause 3 (UCB advertising clause) from the University of Utah copyright. Confirmed by Mike Hibler, mike at cs.utah.edu - thanks! Also, merge UCB and Utah copyright texts back into one, as they originally were. Extra verification by snj@.
1.30	12-Nov-2010	uebayasi	branches: 1.30.2; 1.30.4; Put VM_PAGE_TO_MD() definition in one place. No functional changes.
1.29	06-Nov-2010	uebayasi	Machine dependent code is considered as part of UVM. Include internal API header.
1.28	02-Nov-2010	uebayasi	Fix build of evbarm.
1.27	30-Oct-2010	uebayasi	Use VM_PAGE_TO_MD() to locate struct vm_page_md. No functional changes.
1.26	19-Nov-2008	matt	branches: 1.26.6; 1.26.8; Allocate /dev/mem's page in pmap_init. Mark /dev/mem as MPSAFE. Ansify.
1.25	18-Nov-2008	nonaka	enable _DEV_ZERO_oARM case, when only COMPAT_16 defined.
1.24	15-Nov-2008	ad	Remove compat ifdef.
1.23	04-Nov-2008	matt	Just move the mutex ops into the DEV_MEM case.
1.22	04-Nov-2008	matt	Use a mutex to control access DEV_MEM.
1.21	07-Aug-2008	matt	branches: 1.21.2; 1.21.8; Now that pmap allocates ncolors for memhook, use them to properly memory.
1.20	01-Jan-2008	chris	branches: 1.20.6; 1.20.10; 1.20.12; 1.20.16; Add support for kcore headers to arm32 kernel core dumps. The kcore code is based on i386's kcore header handling. Having an asm stub for dumpsys, to dump the registers onto the stack, and then call the C code to do the memory dump is based on amd64's core dump code. This allows a successful core dump on cats. Part of fixing PR cats/18026.
1.19	04-Mar-2007	christos	branches: 1.19.16; 1.19.20; 1.19.22; 1.19.28; 1.19.34; fix caddr_t fallout.
1.18	04-Mar-2007	christos	Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.
1.17	26-Dec-2006	elad	branches: 1.17.2; Make machdep scope architecture-agnostic by removing all arch-specific requests and centralizing them all. The result is that some of these are not used on some architectures, but the documentation was updated to reflect that.
1.16	22-Dec-2006	elad	Add requests indicating access to unmanaged memory for arm, pc532, powerpc, sh3, sh5, and vax, and use them instead of KAUTH_GENERIC_ISSUSER. Update documentation and example secmodel code.
1.15	25-Jul-2006	elad	branches: 1.15.4; 1.15.8; typo; from Arnaud Lacombe, thanks!
1.14	23-Jul-2006	ad	Use the LWP cached credentials where sane.
1.13	14-May-2006	elad	integrate kauth.
1.12	11-Dec-2005	christos	branches: 1.12.4; 1.12.6; 1.12.8; 1.12.10; 1.12.12; merge ktrace-lwp.
1.11	16-Oct-2003	jdolecek	branches: 1.11.16; switch ARM to use same minor for /dev/zero as other archs as discussed on tech-arm@
1.10	07-Aug-2003	agc	Move UCB-licensed code from 4-clause to 3-clause licence. Patches provided by Joel Baker in PR 22364, verified by myself.
1.9	01-Apr-2003	thorpej	branches: 1.9.2; Use PAGE_SIZE rather than NBPG.
1.8	23-Oct-2002	jdolecek	merge kqueue branch into -current kqueue provides a stateful and efficient event notification framework currently supported events include socket, file, directory, fifo, pipe, tty and device changes, and monitoring of processes and signals kqueue is supported by all writable filesystems in NetBSD tree (with exception of Coda) and all device drivers supporting poll(2) based on work done by Jonathan Lemon for FreeBSD initial NetBSD port done by Luke Mewburn and Jason Thorpe
1.7	06-Sep-2002	gehenna	branches: 1.7.2; Merge the gehenna-devsw branch into the trunk. This merge changes the device switch tables from static array to dynamically generated by config(8). - All device switches is defined as a constant structure in device drivers. - The new grammer ``device-major'' is introduced to ``files''. device-major <prefix> char <num> [block <num>] [<rules>] - All device major numbers must be listed up in port dependent majors.<arch> by using this grammer. - Added the new naming convention. The name of the device switch must be <prefix>_[bc]devsw for auto-generation of device switch tables. - The backward compatibility of loading block/character device switch by LKM framework is broken. This is necessary to convert from block/character device major to device name in runtime and vice versa. - The restriction to assign device major by LKM is completely removed. We don't need to reserve LKM entries for dynamic loading of device switch. - In compile time, device major numbers list is packed into the kernel and the LKM framework will refer it to assign device major number dynamically.
1.6	24-Mar-2002	thorpej	branches: 1.6.2; * arm_byte_to_page() -> arm_btop() * arm_page_to_byte() -> arm_ptob()
1.5	27-Feb-2002	christos	- Use DEV_ constants, instead of documenting the numbers! - Delete cdev_decl(mm); where appropriate, and other hand-crufting [hi powerpc!]
1.4	05-Jan-2002	chris	include <arm/conf.h> for prototypes. Correct args to mmopen and mmclose. Add RCSID line.
1.3	05-Jan-2002	chris	Update mem device to bring it into line with a change in version 1.32 of i386/mem.c. Appears that we may move uio twice. Original i386 log message: Optimize the case of writing to /dev/zero, and clean up the surrounding code a bit. Partly suggested by gwr. I think this needs to be applied to arm26 as well.
1.2	10-Sep-2001	chris	branches: 1.2.4; Update pmap_update to now take the updated pmap as an argument. This will allow improvements to the pmaps so that they can more easily defer expensive operations, eg tlb/cache flush, til the last possible moment. Currently this is a no-op on most platforms, so they should see no difference. Reviewed by Jason.
1.1	28-Jul-2001	chris	branches: 1.1.2; 1.1.4; Move the generic arm32 files into arm/arm32 from arm32/arm32, tested kernel builds on cats and riscpc.
1.1.4.2	10-Oct-2001	fvdl	Convert all remaining devices.
1.1.4.1	01-Oct-2001	fvdl	Catch up with -current.
1.1.2.7	10-Oct-2002	jdolecek	sync kqueue with -current; this includes merge of gehenna-devsw branch, merge of i386 MP branch, and part of autoconf rototil work
1.1.2.6	23-Jun-2002	jdolecek	catch up with -current on kqueue branch
1.1.2.5	16-Mar-2002	jdolecek	Catch up with -current.
1.1.2.4	10-Jan-2002	thorpej	Sync kqueue branch with -current.
1.1.2.3	13-Sep-2001	thorpej	Update the kqueue branch to HEAD.
1.1.2.2	03-Aug-2001	lukem	update to -current
1.1.2.1	28-Jul-2001	lukem	file mem.c was added on branch kqueue on 2001-08-03 04:10:58 +0000
1.2.4.8	11-Nov-2002	nathanw	Catch up to -current
1.2.4.7	17-Sep-2002	nathanw	Catch up to -current.
1.2.4.6	24-Jun-2002	nathanw	Curproc->curlwp renaming. Change uses of "curproc->l_proc" back to "curproc", which is more like the original use. Bare uses of "curproc" are now "curlwp". "curproc" is now #defined in proc.h as ((curlwp) ? (curlwp)->l_proc) : NULL) so that it is always safe to reference curproc (dereferencing curproc is another story, but that's always been true).
1.2.4.5	01-Apr-2002	nathanw	Catch up to -current. (CVS: It's not just a program. It's an adventure!)
1.2.4.4	28-Feb-2002	nathanw	Catch up to -current.
1.2.4.3	11-Jan-2002	nathanw	More catchup.
1.2.4.2	15-Nov-2001	thorpej	Machine-dependent kernel mods for scheduler activations on 32-bit ARM processors. Kernel boots multi-user on an XScale, but upcalls not yet tested.
1.2.4.1	10-Sep-2001	thorpej	file mem.c was added on branch nathanw_sa on 2001-11-15 06:39:22 +0000
1.6.2.1	17-May-2002	gehenna	Add the character device switch.
1.7.2.1	24-Oct-2002	bjh21	Sync with trunk.
1.9.2.3	21-Sep-2004	skrll	Fix the sync with head I botched.
1.9.2.2	18-Sep-2004	skrll	Sync with HEAD.
1.9.2.1	03-Aug-2004	skrll	Sync with HEAD
1.11.16.4	21-Jan-2008	yamt	sync with head
1.11.16.3	03-Sep-2007	yamt	sync with head.
1.11.16.2	30-Dec-2006	yamt	sync with head.
1.11.16.1	21-Jun-2006	yamt	sync with head.
1.12.12.1	24-May-2006	tron	Merge 2006-05-24 NetBSD-current into the "peter-altq" branch.
1.12.10.3	13-May-2006	elad	sprinkle some #include <sys/kauth.h> in files that use kauth kpi but don't include it yet. hopefully this will prevent some fallout.
1.12.10.2	10-Mar-2006	elad	generic_authorize() -> kauth_authorize_generic().
1.12.10.1	08-Mar-2006	elad	Adapt to kernel authorization KPI. I expect some lossage here...
1.12.8.2	11-Aug-2006	yamt	sync with head
1.12.8.1	24-May-2006	yamt	sync with head.
1.12.6.1	01-Jun-2006	kardel	Sync with head.
1.12.4.1	09-Sep-2006	rpaulo	sync with head
1.15.8.1	06-Jan-2007	bouyer	Pull up following revision(s) (requested by elad in ticket #316): share/examples/secmodel/secmodel_example.c: revision 1.10 via patch sys/arch/i386/i386/sys_machdep.c: revision 1.79 sys/arch/amd64/amd64/netbsd32_machdep.c: revision 1.31 share/man/man9/secmodel_bsd44.9: revision 1.9 sys/arch/vax/vax/mem.c: revision 1.34 via patch sys/arch/sh3/sh3/mem.c: revision 1.23 via patch sys/arch/sh5/sh5/mem.c: revision 1.14 via patch sys/secmodel/bsd44/secmodel_bsd44_suser.c: revision 1.22 via patch sys/arch/powerpc/powerpc/mem.c: revision 1.27 via patch sys/arch/x86/x86/x86_machdep.c: revision 1.5 sys/arch/alpha/alpha/machdep.c: revision 1.291 sys/arch/arm/arm32/mem.c: revision 1.17 via patch sys/secmodel/bsd44/secmodel_bsd44_securelevel.c: revision 1.20 sys/sys/kauth.h: revision 1.29 via patch sys/arch/amd64/amd64/sys_machdep.c: revision 1.10 share/man/man9/kauth.9: revision 1.43 via patch sys/arch/xen/i386/sys_machdep.c: revision 1.10 sys/kern/kern_auth.c: revision 1.35 sys/arch/pc532/pc532/mem.c: revision 1.43 via patch Make machdep scope architecture-agnostic by removing all arch-specific requests and centralizing them all. The result is that some of these are not used on some architectures, but the documentation was updated to reflect that.
1.15.4.1	12-Jan-2007	ad	Sync with head.
1.17.2.1	12-Mar-2007	rmind	Sync with HEAD.
1.19.34.1	02-Jan-2008	bouyer	Sync with HEAD
1.19.28.1	18-Feb-2008	mjf	Sync with HEAD.
1.19.22.1	09-Jan-2008	matt	sync with HEAD
1.19.20.1	01-Jan-2008	chris	Sync with HEAD.
1.19.16.1	28-Feb-2008	rjs	Sync with HEAD.
1.20.16.2	13-Dec-2008	haad	Update haad-dm branch to haad-dm-base2.
1.20.16.1	19-Oct-2008	haad	Sync with HEAD.
1.20.12.1	18-Sep-2008	wrstuden	Sync with wrstuden-revivesa-base-2.
1.20.10.1	04-May-2009	yamt	sync with head.
1.20.6.3	17-Jan-2009	mjf	Sync with HEAD.
1.20.6.2	28-Sep-2008	mjf	Sync with HEAD.
1.20.6.1	29-Mar-2008	mjf	- etc/devfsd.conf: Add some rules to give nodes like /dev/tty and /dev/null better default modes, i.e. 0666. - sbin/init: Run devfsd -s before going to multiuser. - sys/arch: Provide arm32, i386, sparc with a mem_init() function to request device nodes for /dev/null, /dev/zero, etc. - sys/dev: Convert rnd, wd, agp, raid, cd, sd, wsdisplay, wskbd, wsmouse, wsmux, tty, bpf, swap to devfs New World Order. - sys/fs/devfs: Make the visibility attribute of device nodes configurable. Also provide a function to mount a devfs on boot. - sys/kern: Add a new boot flag, -n. This disables devfs support. Unless the -n flag is specified the kernel will mount a devfs file system on boot.
1.21.8.1	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.21.2.1	19-Jan-2009	skrll	Sync with HEAD.
1.26.8.1	18-Mar-2010	rmind	Unify /dev/{mem,kmem,zero,null} implementations in MI code. Based on patch from Joerg Sonnenberger, proposed on tech-kern@, in February 2008. Work and depression still in progress.
1.26.6.8	15-Nov-2010	uebayasi	Revert xmd(4).
1.26.6.7	06-Nov-2010	uebayasi	Sync with HEAD.
1.26.6.6	30-Oct-2010	uebayasi	Implement pmap_physload_device(9) to replace xmd(4) MD backend. Implement pmap_mmap(9) and use it from mem(4) and xmd(4).
1.26.6.5	07-Jul-2010	uebayasi	Clean up; merge options DIRECT_PAGE into options XIP.
1.26.6.4	31-May-2010	uebayasi	Re-define the definition of "device page"; device pages are pages of device memory. Pages which don't have vm_page (== can't be used for generic use), but whose PV are tracked, are called "direct pages" from now.
1.26.6.3	25-Feb-2010	uebayasi	A few more VM_PAGE_TO_MD().
1.26.6.2	25-Feb-2010	uebayasi	pg->mdpage -> VM_PAGE_TO_MD(pg)
1.26.6.1	10-Feb-2010	uebayasi	Missing bits of pmap_is_page_colored_p() conversion.
1.30.4.1	17-Feb-2011	bouyer	Sync with HEAD
1.30.2.1	06-Jun-2011	jruoho	Sync with HEAD.
1.31.2.1	23-Jun-2011	cherry	Catchup with rmind-uvmplock merge.
1.11	20-Jun-2020	skrll	KNF #includes Remove some unnecessary ones while I'm here.
1.10	20-Jun-2020	skrll	Trailing whitespace
1.9	13-Nov-2019	pgoyette	Clean-up unnecessary inclusions of opt_coredump.h
1.8	27-Jan-2019	pgoyette	Merge the [pgoyette-compat] branch
1.7	26-Nov-2015	martin	branches: 1.7.16; 1.7.18; We never exec(2) with a kernel vmspace, so do not test for that, but instead KASSERT() that we don't. When calculating the load address for the interpreter (e.g. ld.elf_so), we need to take into account wether the exec'd process will run with topdown memory or bottom up. We can not use the current vmspace's flags to test for that, as this happens too early. Luckily the execpack already knows what the new state will be later, so instead of testing the current vmspace, pass the info as additional argument to struct emul e_vm_default_addr. Fix all such functions and adopt all callers.
1.6	05-May-2014	skrll	branches: 1.6.4; Fill in netbsd32_vm_default_addr, and provide - compat_13_netbsd32_sigreturn, and - compat_16_netbsd32___sigreturn14
1.5	28-Jan-2014	martin	branches: 1.5.2; 1.5.4; Simplify netbsd32_vm_default_addr (for now) to make it compilable.
1.4	26-Jan-2014	christos	whitespace
1.3	25-Jan-2014	christos	use the topdown hint.
1.2	01-Jan-2014	dsl	Change the type of the 'cookie' that holds the state of the core dump file from 'void ' to the actual type 'struct coredump_iostate '. In most of the code the contents of the structure are still unknown. This just stops the wrong type of pointer being passed to the 'void *' parameter. I hope I've found everything, amd64 GENERIC and i386 GENERIC & ALL compile.
1.1	03-Aug-2012	matt	branches: 1.1.2; 1.1.4; 1.1.6; 1.1.8; COMPAT_NETBSD32 support for ARM. Which is strange since ARM is already 32-bits. But the newer ARM ABI AAPCS changes the alignment of 64-bit fields so structures need to copied in and out to deal with the alignment change. This is a kludge but makes debugging of AAPCS support much easier.
1.1.8.1	18-May-2014	rmind	sync with head
1.1.6.2	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.1.6.1	03-Aug-2012	matt	file netbsd32_machdep.c was added on branch matt-nb6-plus on 2012-11-28 22:40:19 +0000
1.1.4.3	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.1.4.2	30-Oct-2012	yamt	sync with head
1.1.4.1	03-Aug-2012	yamt	file netbsd32_machdep.c was added on branch yamt-pagecache on 2012-10-30 17:18:57 +0000
1.1.2.2	03-Dec-2017	jdolecek	update from HEAD
1.1.2.1	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.5.4.1	10-Aug-2014	tls	Rebase.
1.5.2.2	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.5.2.1	28-Jan-2014	matt	file netbsd32_machdep.c was added on branch matt-nb5-mips64 on 2014-02-15 16:18:36 +0000
1.6.4.1	27-Dec-2015	skrll	Sync with HEAD (as of 26th Dec)
1.7.18.2	13-Apr-2020	martin	Mostly merge changes from HEAD upto 20200411
1.7.18.1	10-Jun-2019	christos	Sync with HEAD
1.7.16.2	27-Sep-2018	pgoyette	oopppsss - it's opt_coredump.h not opt_compat_coredump.h
1.7.16.1	27-Sep-2018	pgoyette	(Try to) move the arm-specific compat_netbsd32_machdep stuff to the arm directory, not in acorn32! XXX We still need to come back and hook up the _13 and _16 code!
1.5	20-Jun-2020	skrll	KNF #includes Remove some unnecessary ones while I'm here.
1.4	20-Jun-2020	skrll	Trailing whitespace
1.3	13-Nov-2019	pgoyette	Clean-up unnecessary inclusions of opt_coredump.h
1.2	27-Jan-2019	pgoyette	branches: 1.2.4; Merge the [pgoyette-compat] branch
1.1	27-Sep-2018	pgoyette	branches: 1.1.2; file netbsd32_machdep_13.c was initially added on branch pgoyette-compat.
1.1.2.3	27-Sep-2018	pgoyette	Hook up the arm compat_netbsd32_13 & _16 code
1.1.2.2	27-Sep-2018	pgoyette	oopppsss - it's opt_coredump.h not opt_compat_coredump.h
1.1.2.1	27-Sep-2018	pgoyette	(Try to) move the arm-specific compat_netbsd32_machdep stuff to the arm directory, not in acorn32! XXX We still need to come back and hook up the _13 and _16 code!
1.2.4.3	13-Apr-2020	martin	Mostly merge changes from HEAD upto 20200411
1.2.4.2	10-Jun-2019	christos	Sync with HEAD
1.2.4.1	27-Jan-2019	christos	file netbsd32_machdep_13.c was added on branch phil-wifi on 2019-06-10 22:05:51 +0000
1.5	20-Jun-2020	skrll	KNF #includes Remove some unnecessary ones while I'm here.
1.4	20-Jun-2020	skrll	Trailing whitespace
1.3	13-Nov-2019	pgoyette	Clean-up unnecessary inclusions of opt_coredump.h
1.2	27-Jan-2019	pgoyette	branches: 1.2.4; Merge the [pgoyette-compat] branch
1.1	27-Sep-2018	pgoyette	branches: 1.1.2; file netbsd32_machdep_16.c was initially added on branch pgoyette-compat.
1.1.2.3	27-Sep-2018	pgoyette	Hook up the arm compat_netbsd32_13 & _16 code
1.1.2.2	27-Sep-2018	pgoyette	oopppsss - it's opt_coredump.h not opt_compat_coredump.h
1.1.2.1	27-Sep-2018	pgoyette	(Try to) move the arm-specific compat_netbsd32_machdep stuff to the arm directory, not in acorn32! XXX We still need to come back and hook up the _13 and _16 code!
1.2.4.3	13-Apr-2020	martin	Mostly merge changes from HEAD upto 20200411
1.2.4.2	10-Jun-2019	christos	Sync with HEAD
1.2.4.1	27-Jan-2019	christos	file netbsd32_machdep_16.c was added on branch phil-wifi on 2019-06-10 22:05:51 +0000
1.443	13-Apr-2024	skrll	port-arm/58135: reproducible pmap KASSERT failure for armv7 with NFS root Don't unconditionally set XN in pmap_clearbit - only set it if a mapping exists VM_PROT_EXEC is being cleared. I've simplified the #ifdefs in the patch from the PR.
1.442	13-Apr-2024	skrll	Restore a space I accidentally removed from a copyright with $NetBSD: pmap.c,v 1.396 2020/03/13 16:14:18 skrll Exp $
1.441	13-Dec-2023	rin	arm: pmap: Fix clang build without DIAGNOSTIC
1.440	12-Oct-2023	skrll	Fix non-DIAGNOSTIC builds
1.439	20-Apr-2023	skrll	Provide a shared pmap_devmap implementation and convert all pmap_devmap arrays to use DEVMAP_ENTRY{,_END}
1.438	18-Dec-2022	skrll	Appease KDASSERT / LOCKDEBUG. Tested by mlelstv.
1.437	03-May-2022	skrll	branches: 1.437.4; Catch up with aarch64 TTBR0 handling in pmap_{,de}activate_efirt and kpreempt_{en,dis}able.
1.436	09-Apr-2022	riastradh	sys: Use membar_release/acquire around reference drop. This just goes through my recent reference count membar audit and changes membar_exit to membar_release and membar_enter to membar_acquire -- this should make everything cheaper on most CPUs without hurting correctness, because membar_acquire is generally cheaper than membar_enter.
1.435	02-Apr-2022	skrll	Update to support EFI runtime outside the kernel virtual address space by creating an EFI RT pmap that can be activated / deactivated when required. Adds support for EFI RT to ARM_MMU_EXTENDED (ASID) 32-bit Arm machines. On Arm64 the usage of pmapboot_enter is reduced and the mappings are created much later in the boot process -- now in cpu_startup_hook. Backward compatiblity for KVA mapped RT from old bootaa64.efi is maintained. Adding support to other platforms should be easier as a result.
1.434	19-Mar-2022	skrll	Alight code re-organisation so it better matches the VPRINTF headings it is under. NFCI.
1.433	12-Mar-2022	riastradh	sys: Membar audit around reference count releases. If two threads are using an object that is freed when the reference count goes to zero, we need to ensure that all memory operations related to the object happen before freeing the object. Using an atomic_dec_uint_nv(&refcnt) == 0 ensures that only one thread takes responsibility for freeing, but it's not enough to ensure that the other thread's memory operations happen before the freeing. Consider: Thread A Thread B obj->foo = 42; obj->baz = 73; mumble(&obj->bar); grumble(&obj->quux); /* membar_exit(); / / membar_exit(); / atomic_dec -- not last atomic_dec -- last / membar_enter(); / KASSERT(invariant(obj->foo, obj->bar)); free_stuff(obj); The memory barriers ensure that obj->foo = 42; mumble(&obj->bar); in thread A happens before KASSERT(invariant(obj->foo, obj->bar)); free_stuff(obj); in thread B. Without them, this ordering is not guaranteed. So in general it is necessary to do membar_exit(); if (atomic_dec_uint_nv(&obj->refcnt) != 0) return; membar_enter(); to release a reference, for the `last one out hit the lights' style of reference counting. (This is in contrast to the style where one thread blocks new references and then waits under a lock for existing ones to drain with a condvar -- no membar needed thanks to mutex(9).) I searched for atomic_dec to find all these. Obviously we ought to have a better abstraction for this because there's so much copypasta. This is a stop-gap measure to fix actual bugs until we have that. It would be nice if an abstraction could gracefully handle the different styles of reference counting in use -- some years ago I drafted an API for this, but making it cover everything got a little out of hand (particularly with struct vnode::v_usecount) and I ended up setting it aside to work on psref/localcount instead for better scalability. I got bored of adding #ifdef __HAVE_ATOMIC_AS_MEMBAR everywhere, so I only put it on things that look performance-critical on 5sec review. We should really adopt membar_enter_preatomic/membar_exit_postatomic or something (except they are applicable only to atomic r/m/w, not to atomic_load/store_, making the naming annoying) and get rid of all the ifdefs.
1.432	02-Jan-2022	riastradh	arm: Remove #ifdef DIAGNOSTIC now wrong after KASSERT change. Objects in question aren't volatile here so access is flushable.
1.431	01-Jan-2022	christos	KASSERT now always uses the expression, so don't protect with DIAGNOSTIC
1.430	26-Aug-2021	skrll	Improve a comment
1.429	24-Aug-2021	skrll	Remove '\n' from UVMHIST format
1.428	23-Mar-2021	skrll	Another missing kpreempt_enable
1.427	23-Mar-2021	skrll	Re-enable kpreemption in an error path. Spotted by nat@
1.426	14-Mar-2021	skrll	branches: 1.426.2; Sprinkle kpreempt_{dis,en}able ready for when preemption gets turned on.
1.425	01-Feb-2021	skrll	"as appropos" -> "as appropriate" in comments
1.424	29-Jan-2021	skrll	More debug
1.423	24-Jan-2021	skrll	More debug
1.422	30-Oct-2020	skrll	branches: 1.422.2; Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.
1.421	12-Aug-2020	skrll	Whack-a-mole
1.420	11-Aug-2020	skrll	s/pmaphist/maphist/
1.419	10-Aug-2020	skrll	More UVMHIST_LOG and a new KASSERT
1.418	10-Aug-2020	skrll	In pmag_page_remove initilise pvp after taking the page lock
1.417	10-Jul-2020	skrll	Add support for KASAN on ARMv[67] Thanks to maxv for many pointers and reviews.
1.416	03-Jul-2020	skrll	1 page is enough for memhook now since the merge of the rmind-uvmplock branch and the removal of sys/arch/arm/arm32/mem.c The last users of memhook don't care about number of CPUs or page colours.
1.415	21-Jun-2020	skrll	Use howmany(). NFCI.
1.414	27-May-2020	skrll	KNF
1.413	27-May-2020	skrll	Remove duplicate #include
1.412	21-Apr-2020	skrll	There is no fast spoon^Wfast path in pmap_clearbit. PR port-arm/55186: tests crash arm pmap Tested by martin@
1.411	19-Apr-2020	ad	PR port-arm/55186: tests crash arm pmap pmap_clearbit(): take execbits into account in the fastpath.
1.410	19-Apr-2020	kre	Give UVMHIST_LOG() the 6 args it requires. Unbreak builds.
1.409	19-Apr-2020	skrll	Fix typo in UVMHIST_LOG
1.408	18-Apr-2020	skrll	Remove PMAP_DEBUG by converting to UVMHIST
1.407	17-Apr-2020	skrll	Fix build after PV locking change
1.406	17-Apr-2020	skrll	Use UVMHIST_CALLARGS
1.405	16-Apr-2020	ad	With the right timing, V->P operations could change stuff behind the back of callers working in the opposite direction - fix it. Tested by skrll@.
1.404	14-Apr-2020	skrll	Fix a comment. From ad@
1.403	13-Apr-2020	chs	slightly change and fix the semantics of pool_setwat(), pool_sethardlimit() and pool_prime() (and their pool_cache_ counterparts): - the pool_set*wat() APIs are supposed to specify thresholds for the count of free items in the pool before pool pages are automatically allocated or freed during pool_get() / pool_put(), whereas pool_sethardlimit() and pool_prime() are supposed to specify minimum and maximum numbers of total items in the pool (both free and allocated). these were somewhat conflated in the existing code, so separate them as they were intended. - change pool_prime() to take an absolute number of items to preallocate rather than an increment over whatever was done before, and wait for any memory allocations to succeed. since pool_prime() can no longer fail after this, change its return value to void and adjust all callers. - pool_setlowat() is documented as not immediately attempting to allocate any memory, but it was changed some time ago to immediately try to allocate up to the lowat level, so just fix the manpage to describe the current behaviour. - add a pool_cache_prime() to complete the API set.
1.402	29-Mar-2020	skrll	branches: 1.402.2; PTE_SYNC before TLB flush and no need to PTE_SYNC after an unmap.
1.401	29-Mar-2020	skrll	Support PMAP_FAULTINFO on arm
1.400	23-Mar-2020	skrll	Reduce #ifdefs
1.399	14-Mar-2020	ad	pmap_remove_all(): Return a boolean value to indicate the behaviour. If true, all mappings have been removed, the pmap is totally cleared out, and UVM can then avoid doing the work to call pmap_remove() for each map entry. If false, either nothing has been done, or some helpful arch-specific voodoo has taken place.
1.398	13-Mar-2020	skrll	Enhance the DIAGNOSTICs around pmap_grow_map
1.397	13-Mar-2020	skrll	Re-indent a function call. NFCI.
1.396	13-Mar-2020	skrll	Oops... remove a stray <space>
1.395	13-Mar-2020	skrll	Fixup some comments
1.394	24-Feb-2020	ad	Adjust for UVM locking changes
1.393	23-Feb-2020	skrll	type in comment
1.392	12-Feb-2020	skrll	Convert the DEBUG code in pmap_grow_map to DIAGNOSTIC
1.391	12-Feb-2020	skrll	Add a CTASSERT to pmap_grow_l2_bucket that PAGE_SIZE is a multiple of L2_TABLE_SIZE_REAL.
1.390	12-Feb-2020	skrll	Add a KASERT that we're not overwriting anything in pmap_growkernel
1.389	12-Feb-2020	skrll	Minor changes to make pmap_grow_l2_bucket look more like pmap_alloc_l2_bucket. NFCI.
1.388	05-Feb-2020	skrll	Fix the armv[67] memory attributes for uncached memory. Previously it was mapped as strongly-ordered which meant that unaligned accesses would fault. armv7_generic_bs_map now maps pages with PMAP_DEV which is treated as SO bus_dma continues to use PMAP_NOCACHE as appropriate, but this now get mapped to the correct memory attribute bits for armv[67] DEVMAP_ENTRY usees a new flag PTE_DEV. The workaround for the unaligned access faults is now removed. XXX Other armv[67] boards bus_space implementations should be checked. XXX There is scope to reduce the difference to aarch64
1.387	02-Feb-2020	skrll	More KNF
1.386	02-Feb-2020	skrll	Always call pmap_grow_map with a page aligned new VA. KASSERT that this happenes.
1.385	02-Feb-2020	skrll	Always pmap_kenter_pa the page in pmap_grow_map regardless of how we got it.
1.384	02-Feb-2020	skrll	KNF
1.383	02-Feb-2020	skrll	Fix comment
1.382	25-Jan-2020	skrll	A fix and an optimisation to pmap_l1tt_free - in the !__HAVE_MM_MD_DIRECT_MAPPED_PHYS case pass UVM_KMF_WIRED so that the mappings are removed and the KVA is released. Fixes the KASSERT seen in the automated test runs. - in the __HAVE_MM_MD_DIRECT_MAPPED_PHYS case we can work out pa much easier than caling pmap_extract.
1.381	19-Jan-2020	skrll	Fix non-ARM_MMU_EXTENDED buildx
1.380	18-Jan-2020	skrll	Use 4K pages on ARM_MMU_EXTENDED platforms (all armv[67] except RPI) by creating a new pool l1ttpl for the userland L1 translation table which needs to be 8KB and 8KB aligned. Limit the pool to maxproc and add hooks to allow the sysctl changing of maxproc to adjust the pool. This comes at a 5% performance penalty for build.sh -j8 kernel on a Tegra TK1.
1.379	18-Jan-2020	skrll	Trailing whitespace
1.378	17-Jan-2020	skrll	Fix a bug introduced in 1.271 where pmap_grow_map would no longer map the allocated page for the uvm.page_init_done == false case when PMAP_STEAL_MEMORY is not defined.
1.377	17-Jan-2020	skrll	Typo in comment
1.376	17-Jan-2020	skrll	Update PMAP_STEAL_MEMORY code to uvm_hotplug
1.375	31-Dec-2019	skrll	branches: 1.375.2; Improve a comment
1.374	25-Sep-2019	skrll	Convert a __CTASSERT into a KASSERT as L1_S_CACHE_MASK may not be a compile time constant if ARM_NMMUS > 1
1.373	23-Apr-2019	bouyer	branches: 1.373.2; Fix a deadlock between the pool and pmap codes: - cpu0 grabs the kernel lock (e.g. from a non-MPSAFE interrupt) and calls pool_get(). - cpu1 does a pool_get() on the same pool from MPSAFE code, which needs a pool_page_alloc(), which ends up in pmap_extract_coherency(). So cpu0 holds the kernel_lock and wants the pool lock. cpu1 holds the pool lock and wants the kernel_lock in pmap_extract_coherency(). The pmap code should not rely on kernel_lock. Intead make the pmap_kernel()->pm_obj_lock a IPL_VM lock and use it as pmap lock (thus dropping the pmap test pmap_{acquire,release}_pmap_lock()). This needs to be a IPL_VM because unlike user pmaps, this can be locked from interrupt context. Add a IPL_NONE lock for pmap_growkernel(). We can't use pmap_kernel()->pm_obj_lock here because pmap_grow_map() may sleep. Make pmap_lock (which may be locked with pm_obj_lock held) a IPL_VM lock in all case. reorder a few things to not call pool_get()/pool_put() (which may sleep) with pm_obj_lock held. Patch initially posted to port-arm@ on April 19, improved patch (per suggestions from Nick Hudson and Jason Thorpe) on April 21.
1.372	23-Apr-2019	bouyer	Don't try to aquire/release the pmap lock when in ddb. Avoids a deadlock when entering ddb, or on "mach cpu n" ddb command (the pmap lock may already be held by another CPU, which is halted when entering ddb). Posted to port-arm@ on April 19.
1.371	28-Oct-2018	skrll	Fix the comment near pmap_bootstrap itself as well
1.370	18-Oct-2018	skrll	Provide generic start code that assumes the MMU is off and caches are disabled as per the linux booting protocol for ARMv6 and ARMv7 boards. u-boot image type should be changed to 'linux' for correct behaviour. The new start code builds a minimal "bootstrap" L1PT with cached access disabled and uses the same table for all processors. AP startup is performed in less steps and more code is written in C. The bootstrap tables and stack are placed into an (orphaned) section "_init_memory" which is given to uvm when it is no longer used. Various kernels have been converted to use this code and tested. Some boards were provided by TNF. Thanks! The GENERIC kernel now boots on boards using the TEGRA, SUNXI and EXYNOS kernels. The GENERIC kernel will also work on RPI2 using u-boot. Thanks to martin@ and aymeric@ for testing on parallella and nanosoc respectively
1.369	14-Oct-2018	skrll	Use __nothing
1.368	03-Sep-2018	riastradh	Rename min/max -> uimin/uimax for better honesty. These functions are defined on unsigned int. The generic name min/max should not silently truncate to 32 bits on 64-bit systems. This is purely a name change -- no functional change intended. HOWEVER! Some subsystems have #define min(a, b) ((a) < (b) ? (a) : (b)) #define max(a, b) ((a) > (b) ? (a) : (b)) even though our standard name for that is MIN/MAX. Although these may invite multiple evaluation bugs, these do _not_ cause integer truncation. To avoid `fixing' these cases, I first changed the name in libkern, and then compile-tested every file where min/max occurred in order to confirm that it failed -- and thus confirm that nothing shadowed min/max -- before changing it. I have left a handful of bootloaders that are too annoying to compile-test, and some dead code: cobalt ews4800mips hp300 hppa ia64 luna68k vax acorn32/if_ie.c (not included in any kernels) macppc/if_gm.c (superseded by gem(4)) It should be easy to fix the fallout once identified -- this way of doing things fails safe, and the goal here, after all, is to _avoid_ silent integer truncations, not introduce them. Maybe one day we can reintroduce min/max as type-generic things that never silently truncate. But we should avoid doing that for a while, so that existing code has a chance to be detected by the compiler for conversion to uimin/uimax without changing the semantics until we can properly audit it all. (Who knows, maybe in some cases integer truncation is actually intended!)
1.367	28-Aug-2018	skrll	Fix arguments to align and align_offset for pmap_l2ptp_cache, i.e.align is now L2_TABLE_SIZE_REAL and align_offset is now 0. (There were reversed previously)
1.366	31-Jul-2018	skrll	Define and use VPRINTF
1.365	01-Apr-2018	ryo	branches: 1.365.2; Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@) - sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@) - add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)
1.364	22-Jan-2018	skrll	branches: 1.364.2; Add PMAP_WRITE_COMBINE: to the list of flags supported by pmap_kenter_pa
1.363	22-Jan-2018	skrll	Trailing whitespace
1.362	17-Jan-2018	skrll	G/C ARM32_NEW_VM_LAYOUT
1.361	01-Nov-2017	skrll	Unwrap two lines. NFC.
1.360	01-Nov-2017	skrll	Fix a comment
1.359	28-Oct-2017	pgoyette	Update the kernhist(9) kernel history code to address issues identified in PR kern/52639, as well as some general cleaning-up... (As proposed on tech-kern@ with additional changes and enhancements.) Details of changes: * All history arguments are now stored as uintmax_t values[1], both in the kernel and in the structures used for exporting the history data to userland via sysctl(9). This avoids problems on some architectures where passing a 64-bit (or larger) value to printf(3) can cause it to process the value as multiple arguments. (This can be particularly problematic when printf()'s format string is not a literal, since in that case the compiler cannot know how large each argument should be.) * Update the data structures used for exporting kernel history data to include a version number as well as the length of history arguments. * All [2] existing users of kernhist(9) have had their format strings updated. Each format specifier now includes an explicit length modifier 'j' to refer to numeric values of the size of uintmax_t. * All [2] existing users of kernhist(9) have had their format strings updated to replace uses of "%p" with "%#jx", and the pointer arguments are now cast to (uintptr_t) before being subsequently cast to (uintmax_t). This is needed to avoid compiler warnings about casting "pointer to integer of a different size." * All [2] existing users of kernhist(9) have had instances of "%s" or "%c" format strings replaced with numeric formats; several instances of mis-match between format string and argument list have been fixed. * vmstat(1) has been modified to handle the new size of arguments in the history data as exported by sysctl(9). * vmstat(1) now provides a warning message if the history requested with the -u option does not exist (previously, this condition was silently ignored, with only a single blank line being printed). * vmstat(1) now checks the version and argument length included in the data exported via sysctl(9) and exits if they do not match the values with which vmstat was built. * The kernhist(9) man-page has been updated to note the additional requirements imposed on the format strings, along with several other minor changes and enhancements. [1] It would have been possible to use an explicit length (for example, uint64_t) for the history arguments. But that would require another "rototill" of all the users in the future when we add support for an architecture that supports a larger size. Also, the printf(3) format specifiers for explicitly-sized values, such as "%"PRIu64, are much more verbose (and less aesthetically appealing, IMHO) than simply using "%ju". [2] I've tried very hard to find "all [the] existing users of kernhist(9)" but it is possible that I've missed some of them. I would be glad to update any stragglers that anyone identifies.
1.358	08-Oct-2017	flxd	Revert attempt at tracking unmanaged mappings for VIVT as it was incomplete and buggy. PR port-shark/52102 From skrll@. Tested by martin@ and me.
1.357	06-Sep-2017	skrll	Remove useless KASSERT - we can't assert !mutex_owned()
1.356	02-Sep-2017	skrll	Perform tracking of unmanaged mappings for VIVT and call vac_me_harder as appropriate. PR/52102 shark: ffs_newvnode panic when unpacking sets installing -current Thanks to Felix Deichmann for bisecting the problem and testing the fix.
1.355	02-Sep-2017	skrll	KNF
1.354	02-Sep-2017	skrll	Remove an #ifdef PMAP_CACHE_VIVT that's inside #ifdef PMAP_CACHE_VIVT already
1.353	24-Aug-2017	jmcneill	Do runtime detection of MP extensions to allow using a MULTIPROCESSOR kernel on CPUs without the MP extensions feature (like Cortex-A8).
1.352	27-Jul-2017	skrll	Macro confusion - fortunately this has no functional change.
1.351	27-Jul-2017	skrll	Remove redundant test - the compiler realised anyway as we get same binary output
1.350	10-Jul-2017	skrll	No need for '\n' in UVMHIST_LOG
1.349	24-May-2017	skrll	branches: 1.349.2; Check the "Havard TLB" maintenance operations if the "Unified TLB" maintenance opeations don't include invalidate by ASID. Some CPUs, e.g. Cortex-A8, have Havard TLBs and report ASID operations this way.
1.348	24-May-2017	skrll	Move closer to the common pmap by using the same pmap_remove_all optimisation where TLB flushes are avoided by clever ASID assignment. pmap_remove_all_complete can now be removed.
1.347	22-May-2017	skrll	Indent comment to match code it's describing
1.346	21-May-2017	skrll	KNF
1.345	17-Apr-2017	skrll	Perform icache syncs for ARM_MMU_EXTENDED as well. This helps the PT_STEP code in pr/52119 and probably other things.
1.344	25-Feb-2017	christos	fix unused.
1.343	23-Feb-2017	skrll	Fixup the compile time decisions around PMAP_{INCLUDE,NEEDS}_PTE_SYNC and fix the options for xscale boards which require the code in pmap_l2ptp_ctor marked as #ifndef PMAP_INCLUDE_PTE_SYNC. Fix the typo (pte -> opte) in this code block and consistently use opte elsewhere. PR/51990: Regression data_abort_handler: data_aborts fsr=0x406 far=0xbfffeff5 on copyout in init
1.342	23-Dec-2016	cherry	branches: 1.342.2; "Make NetBSD great again!" Introduce uvm_hotplug(9) to the kernel. Many thanks, in no particular order to: TNF, for funding the project. Chuck Silvers - for multiple API reviews and feedback. Nick Hudson - for testing on multiple architectures and bugfix patches. Everyone who helped with boot testing. KeK (http://www.kek.org.in) for hosting the primary developers.
1.341	17-Dec-2016	flxd	Fix typo "one the" and architecture where appropriate.
1.340	04-Aug-2016	skrll	provide and use 'ci' in pmap_remove_all_complete.
1.339	03-Aug-2016	skrll	Don't touch pm_onproc at all in pmap_{update,destroy} and adjust KASSERT to suit. Update to cover the PMAP_TLB_MAX > 1 case as well while I'm here.
1.338	01-Aug-2016	skrll	pm_remove_all needs handling in pmap_destroy as well as pmap_update
1.337	29-Jul-2016	skrll	more debug
1.336	29-Jul-2016	skrll	Simplify ARM_MMU_EXTENDED #ifdefs No functional change
1.335	14-Jul-2016	skrll	branches: 1.335.2; Adapt this to the recent sys/uvm/pmap/pmap_tlb.c changes. MP kernels now don't trigger KASSERTs
1.334	14-Jul-2016	skrll	Spell PMAP_TLB_NEED_SHOOTDOWN correctly
1.333	12-Jul-2016	skrll	Fix harmless (?) typo
1.332	14-Dec-2015	skrll	Delete pmap_pmaps and its only user pmap_dump_all. The list wasn't being updated in an MP-safe manner.
1.331	25-Nov-2015	skrll	In the ARM_MMU_EXTENDED case make sure the kernel mappings are marked with XN (eXecute Never) appropriately. The XN logic is inconsistent and could do with changing to XN always set and cleared for VM_PROT_EXECUTE (or the inverse) everywhere.
1.330	13-Nov-2015	skrll	Tweak the KASSERTs in pmap_update in the ARM_MMU_EXTENDED case - Lazy updating is not done on the kernel pmap. PR port-arm/50420: curcpu()->ci_pmap_cur != pm \|\| pm->pm_pai[0].pai_asid == curcpu()->ci_pmap_asid_cur" failed
1.329	13-Nov-2015	skrll	Wrap long lines.
1.328	11-Nov-2015	skrll	Support pmap_pv_track and friends
1.327	06-Nov-2015	skrll	Trailing whitespace
1.326	26-Jul-2015	matt	KASSERT->KASSERTMSG
1.325	09-Jun-2015	skrll	Use armreg_auxctl_{read,write} instead of inline asm. No functional change.
1.324	01-Jun-2015	matt	pmap_directbase is a failed experiment, nuke it.
1.323	30-May-2015	matt	Support directmapped systems with >1GB that start memory at 0x80000000.
1.322	13-May-2015	skrll	Use PDE_SYNC when syncing pdeps
1.321	11-May-2015	matt	Make sure nptes is a multiple of PAGE_SIZE / L2_S_SIZE.
1.320	13-Apr-2015	matt	Add pmap locking to pmap_kenter_pa/kremove
1.319	11-Apr-2015	skrll	#include "opt_arm_debug.h" for VERBOSE_INIT_ARM
1.318	07-Apr-2015	matt	Fix two bugs. pmap_is_cached fix for MULTIPROCESSOR (not just ASID on local cpu -> any valid ASID on any cpu). pmap_deactivate: update curcpu()->ci_pmap_cur_asid to KERNEL_PID too.
1.317	25-Feb-2015	joerg	Improve inline asm around dsb/dmb/isb: - always use volatile and mark them as memory barrier - use the common version from locore.h in all places not included from userland
1.316	10-Nov-2014	skrll	branches: 1.316.2; Update PTE_SYNC_CURRENT to add a dsb for armv7 - part of the break-before-make fix.
1.315	10-Nov-2014	skrll	Remove an XXXNH comment.
1.314	10-Nov-2014	skrll	Remove an unnecessary flush that sneaked in as part of break-before-make change.
1.313	10-Nov-2014	skrll	In pmap_fault_fixup re-instate the TLB flush for the shared L1 case that occurs for non-ARM_MMU_EXTENDED kernels. This fixes rump/rumpkern/t_sp:stress_killer on rpi which is currently non-ARM_MMU_EXTENDED
1.312	08-Nov-2014	matt	When allocing a l1page, if a page isn't available, use uvm_wait to wait for one to become available. Should fix PR/49364.
1.311	07-Nov-2014	skrll	The fixup debug message can report false positives on MULTIPROCESSOR, so disable them there.
1.310	07-Nov-2014	skrll	In pmap_enter only flush the TLB if really necessary
1.309	05-Nov-2014	skrll	Fix typo in comment
1.308	04-Nov-2014	matt	pmap_tlb_flushD is for !ARM_MMU_EXTENDED only now
1.307	29-Oct-2014	skrll	Apply a bunch of break-before-make, i.e. set PTEs to zero, flush the TLB (across all CPUs) and set new PTE value. Mostly from matt@ with some updates from me. Flush the branch predictor in pmap_update.
1.306	29-Oct-2014	skrll	In pmap_deactivate don't set TTBR with the ASID of the deactivated LWP - use KERNEL_PID instead. This is probably a no-op as TTBCR_S_PD0 should (still) be set at the time of the call to cpu_setttb.
1.305	25-Oct-2014	skrll	Remove katelib.h and references to it. {Read,Write}{Word,Byte} macros are provided in the files that still use them. Someone(tm) should convert them to bus_space(9)
1.304	20-Oct-2014	skrll	Reduce code a little. Reviewed by gimpy.
1.303	14-Oct-2014	skrll	Typo in comment
1.302	23-Sep-2014	matt	Use right conditional for checking nG.
1.301	23-Sep-2014	nonaka	nG bit exists only in ARMv6 and above.
1.300	21-Sep-2014	christos	remove dead code
1.299	05-Sep-2014	matt	Don't nest structure definitions.
1.298	30-Aug-2014	kiyohara	It expects return value 'va != NULL' from uvm_km_alloc().
1.297	13-Aug-2014	matt	Fix for PR/49061 only kassert in pmap_kenter_pa if PMAP_CACHE_PIVT && !ARM_MMU_EXTENDED
1.296	13-Aug-2014	matt	Fix for PR/49107. Make sure pmap_copy_page_xscale clears the ptes afters its done with them.
1.295	25-Jul-2014	matt	branches: 1.295.2; PTE_SYNC_RANGE a newly allocated L1 page for ARM_MMU_EXTENDED
1.294	15-Jun-2014	ozaki-r	Add missing semicolon
1.293	05-Jun-2014	matt	Fix occupancy bug.
1.292	30-Apr-2014	joerg	pmap_is_current might be unused, tag it as such.
1.291	22-Apr-2014	skrll	Remove stray comment.
1.290	22-Apr-2014	skrll	Call pmap_free_l2_bucket for the kernel pmap so that l2b_occupancy is updated. pmap_free_l2_bucket already deals with the kernel pmap properly. ok matt@ Should fix the panic: kernel debugging assertion "mappings <= l2b->l2b_occupancy" failed: file "/usr/src/sys/arch/arm/arm32/pmap.c", line 3838 problem reported on port-arm by Joachim Thiemann
1.289	22-Apr-2014	skrll	Fix a format string to actually print the prot
1.288	20-Apr-2014	matt	Reduce resident_count by number of pages, not number of ptes.
1.287	12-Apr-2014	matt	KDASSERT -> KDASSERTMSG
1.286	12-Apr-2014	skrll	Trailing whitespace
1.285	12-Apr-2014	skrll	Fix typo and unbreak the build for various arm kernel builds.
1.284	11-Apr-2014	matt	Add a kernel for the CUBIETRUCK (CUBIEBOARD3). Allow direct mapping of all memory (but for now allow the memory mapped above KERNEL_BASE to used for poolpages).
1.283	10-Apr-2014	matt	Fix pasto.
1.282	10-Apr-2014	matt	Fix pmap_extract to deal with non-4KB pages.
1.281	05-Apr-2014	skrll	Add a missing pmap_release_page_lock
1.280	02-Apr-2014	matt	branches: 1.280.2; Mark omd as diagused for the ARM_MMU_EXTENDED case.
1.279	02-Apr-2014	skrll	Fix non-DIAGNOSTIC build
1.278	02-Apr-2014	matt	Init the page_lock to IPL_VM iff VIPT && arm_cache_prefer_mask != 0 otherwise use IPL_NONE. Don't bother with page_lock for KMPAGEs.
1.277	02-Apr-2014	matt	braces are your friends. use them.
1.276	02-Apr-2014	matt	Really fix locking this time.
1.275	02-Apr-2014	matt	Because vector_page might be 0, we have to process the entry L1pt. Make sure to map the new l2 area after we've grown the kernel. If msgbufaddr is set, don't alloc space for msgbuf.
1.274	01-Apr-2014	matt	For ARM_MMU_EXTENDED, if the page being mapped asked for EXEC but is not EXEC, sync it.
1.273	31-Mar-2014	matt	tag a variable with __diagused
1.272	30-Mar-2014	matt	Fix debug code in fault_fixup
1.271	30-Mar-2014	matt	Make the ARM pmap use ASIDs, split TTBRs, and MP safe. This only happens for ARMv6 or later CPUs. This means that on context switch that the TLBs and caches no longer to cleaned/flushed. Also, eXecute Never (XN) protection has been added so non-exec pages can not be run. Change the page size for ARMv6+ to be 8KB while allows a L1PT to be a normal page. This means that the L1PT is not special. Use the XN support to only sync pages that are executed from.
1.270	27-Feb-2014	joerg	Member will never be null, so remove check.
1.269	26-Feb-2014	matt	Only track kenter_pa'ed pages if arm_cache_prefer_mask is non-zero.
1.268	26-Feb-2014	matt	Don't do ref/mod emulation for KENTRY pages. l2pte_minidata -> l2pte_minidata_p
1.267	26-Feb-2014	matt	Move pmap_recent_user to ci->ci_pmap_lastuser and pmap_previous_active_lwp to ci->ci_lastlwp. Fix some comments.
1.266	26-Feb-2014	matt	l2pte_valid -> l2pte_valid_p
1.265	26-Feb-2014	matt	Add support for PMAP_PTE to pmap_kenter_pa
1.264	12-Sep-2013	kiyohara	Fix VIVT cache operation. Tested on Kirkwood machines.
1.263	18-Aug-2013	matt	Include <arm/locore.h>
1.262	03-Jul-2013	matt	Add l2pte_set and l2pte_reset inlines to set/reset a pte. These will be used to support > 4KB pages sizes. Don't use >> L1_S_SHIFT, use L1_IDX() instead.
1.261	03-Jul-2013	matt	restore deleted conditional
1.260	03-Jul-2013	matt	Fix c&p error
1.259	03-Jul-2013	matt	Collapse multiple inlines and move repeated tests into them. No functional change.
1.258	03-Jul-2013	matt	Add pmap_domain and pmap_l1_kva inlines.
1.257	12-Jun-2013	matt	branches: 1.257.2; Add a ARM_HAS_VBAR option which forces the use of the VBAR register. This allows much code to deal with vector_page mappings to be eliminated. On a BEAGLEBONE kernel, this saves 8KB of text and instructions that never have to be executed. (The PJ4B has VBAR but doesn't implement the security extensions it is part of so a method was needed to allow it use VBAR with relying on the default test for the security extensions.)
1.256	12-Jun-2013	matt	If the vector_page is not ARM_VECTORS_{LOW,HIGH}, assume it's in kernel text and don't do anything special to map it.
1.255	11-May-2013	skrll	Fix !DDB build.
1.254	29-Mar-2013	matt	Fix pmap_flush_page to also flush the secondary cache, if there is one. This solves a bus_dma problem with DMA from uncached pages.
1.253	13-Feb-2013	matt	Some armv7 fixes for speculative tlb loads.
1.252	04-Feb-2013	macallan	support ARM32_MMAP_WRITECOMBINE for managed pages as well
1.251	01-Feb-2013	matt	cleanup PVF_WRITE & pvh_attrs interaction.
1.250	31-Jan-2013	skrll	Another typo in a comment.
1.249	31-Jan-2013	skrll	Typo in comment.
1.248	19-Jan-2013	matt	Switch from only UVM_PGA_STRAT_ONLY to UVM_PGA_STRAT_FALLBACK in arm_pmap_alloc_poolpage.
1.247	11-Jan-2013	matt	Fix a bug in pmap_modify_pv where we didn't set PVF_WRITE on a page after changing its mapping to writeable. Add more KASSERTS Don't go into DDB by default in pmap_fixup.
1.246	11-Dec-2012	matt	Fix C&P bug.
1.245	11-Dec-2012	matt	Fix c&p error.
1.244	11-Dec-2012	matt	Optimize pmap_{copy,zerp}_page_generic to understand that when all of memory is always mapped that you don't have create mappings dynamically.
1.243	10-Dec-2012	matt	Change a KASSERT to a KASSERTMSG
1.242	12-Nov-2012	skrll	C99 types
1.241	17-Oct-2012	matt	Add a PMAP_NEEDS_ALLOC_POOLPAGE / PMAP_ALLOC_POOLPAGE hook so systems can allocate pool pages from a specific VM freelist.
1.240	17-Oct-2012	matt	Need to set pmap_needs_pte_sync before calling PTE_SYNC
1.239	17-Oct-2012	matt	When setting pmap_needs_pte_sync to 1 be sure to sync pte that caused the issue.
1.238	26-Sep-2012	matt	If we get a fault we shouldn't have, set pmap_needs_pte_sync and retry.
1.237	22-Sep-2012	matt	Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead but add a second argument to it to indicate whether the TLB/caches need to be flushed. Default cortex to pmap_needs_fixup = 1. But check the MMFR3 field to see if the fixed can be skipped. Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1) or enabeld (bit = 0). With these changes, the A9 MMU can use traverse caches to do MMU tablewalks Also, make sure all memory has the shareable bit for the A9.
1.236	02-Sep-2012	matt	branches: 1.236.2; Supersections are on armv6 too.
1.235	30-Aug-2012	matt	Teach pmap_extract about supersections.
1.234	29-Aug-2012	matt	Make all cortex and arm11 cpus uses writeback cached memories for pagetables
1.233	29-Aug-2012	matt	Support PMAP_NOCACHE in pmap_kenter_pa
1.232	29-Aug-2012	matt	Use the correct prot mask in vector_page_setprot
1.231	27-Aug-2012	matt	Use the correct (L1_S_PROT, not L2_S_PROT) macro for setting the protection of the vector page. This fixes a nasty little bug that shows up on armv7 systems when the vector page physical address changes (bit 12 of the address is cleared) and then any exception causes the system to hang.
1.230	20-Aug-2012	matt	Add support for mapping SuperSection on armv6 and armv7. These always a domain of 0 so move the kernel from domain 15 to domain 0.
1.229	13-Jul-2012	skrll	Fix a KASSERT. From/OK'ed by matt@
1.228	29-Jan-2012	he	branches: 1.228.2; Only declare helper variable which is only used in KASSERT() if DIAGNOSTIC is defined, to avoid "variable defined but never used" warning if DIAGNOSTIC isn't defined, and KASSERT() expands to nothing.
1.227	28-Jan-2012	matt	Since we don't do MULTIPROCESSOR, and hence preemption, locking the pvlists doesn't really matter.
1.226	28-Jan-2012	matt	Don't use simple locks.
1.225	27-Jan-2012	para	extending vmem(9) to be able to allocated resources for it's own needs. simplifying uvm_map handling (no special kernel entries anymore no relocking) make malloc(9) a thin wrapper around kmem(9) (with private interface for interrupt safety reasons) releng@ acknowledged
1.224	01-Jul-2011	dyoung	branches: 1.224.2; 1.224.6; #include <sys/bus.h> instead of <machine/bus.h>.
1.223	30-Jun-2011	wiz	dependant -> dependent
1.222	12-Jun-2011	rmind	Welcome to 5.99.53! Merge rmind-uvmplock branch: - Reorganize locking in UVM and provide extra serialisation for pmap(9). New lock order: [vmpage-owner-lock] -> pmap-lock. - Simplify locking in some pmap(9) modules by removing P->V locking. - Use lock object on vmobjlock (and thus vnode_t::v_interlock) to share the locks amongst UVM objects where necessary (tmpfs, layerfs, unionfs). - Rewrite and optimise x86 TLB shootdown code, make it simpler and cleaner. Add TLBSTATS option for x86 to collect statistics about TLB shootdowns. - Unify /dev/mem et al in MI code and provide required locking (removes kernel-lock on some ports). Also, avoid cache-aliasing issues. Thanks to Andrew Doran and Joerg Sonnenberger, as their initial patches formed the core changes of this branch.
1.221	10-Mar-2011	bsh	branches: 1.221.2; Preliminary ARM11 MPCore support. I have confirmed this commit doesn't affect existing evbarm kernels by comparing binaries.
1.220	28-Feb-2011	macallan	implement arm32_pmap_flags() to allow mappings with write buffering enabled, mostly for video memory Tested on shark
1.219	12-Nov-2010	uebayasi	branches: 1.219.2; 1.219.4; Put VM_PAGE_TO_MD() definition in one place. No functional changes.
1.218	10-Nov-2010	uebayasi	Use more VM_PHYSMEM_*() accessors. No functional changes.
1.217	03-Nov-2010	uebayasi	Fix build of IXM1200 too. Pointed out by cegger, thanks.
1.216	02-Nov-2010	uebayasi	Fix build of XScale.
1.215	30-Oct-2010	uebayasi	Pass struct vm_page_md * where possible. This causes 1% code increase, mainly because additional argument (paddr_t) affects register usage. This will be fixed when per-page data structure (struct vm_page) is redone, and physical address can be retrieved from struct vm_page_md *. Tested on (uncommitted) i.MX35 (ARM1136).
1.214	16-Jun-2010	jmcneill	PR port-arm/43299: Support added for igepv2/cortexa8/omap3530 Apply patch from PR, with build fixes. ok skrll, matt
1.213	14-May-2010	cegger	Move PMAP_KMPAGE to be used in pmap_kenter_pa flags argument. 'Looks good to me' gimpy@
1.212	15-Feb-2010	skrll	branches: 1.212.2; Typo in comment.
1.211	02-Jan-2010	he	branches: 1.211.2; Remove a shadowed and unused local declaration so that this builds again.
1.210	01-Jan-2010	uebayasi	Sprinkle assertions after calling pmap_get_l2_bucket().
1.209	31-Dec-2009	uebayasi	Use pmap_is_current() where appropriate. No functional changes.
1.208	31-Dec-2009	uebayasi	pmap_page_remove(): remove an unused local variable; no functional changes.
1.207	31-Dec-2009	uebayasi	Correct assertions for PMAP_CACHE_VIPT code; if page coloring is disabled (arm_cache_prefer_mask == 0), pvh_attrs has never PVF_COLORED, so don't assert it. No functional changes.
1.206	28-Dec-2009	uebayasi	Indent.
1.205	28-Dec-2009	uebayasi	Always name struct pv_entry * as pv, not pve. No binary change.
1.204	27-Dec-2009	uebayasi	Add write-through cache work-around for ARM11 as well as ARM9/ARM10. Analyzed & tested on i.MX35 with help from Tsubai Masanari.
1.203	28-Nov-2009	scw	Apply some band-aid to pmap_activate() for PR kern/41058: There's a corner case here which can leave turds in the cache as reported in kern/41058. They're probably left over during tear-down and switching away from an exiting process. Until the root cause is identified and fixed, zap the cache when switching pmaps. This will result in a few unnecessary cache flushes, but that's better than silently corrupting data. Also remove an extraneous return statement in pmap_page_protect() which crept in during the matt-armv6 merge.
1.202	21-Nov-2009	rmind	Use lwp_getpcb() on ARM (and acorn26/32), clean from struct user usage.
1.201	07-Nov-2009	cegger	Add a flags argument to pmap_kenter_pa(9). Patch showed on tech-kern@ http://mail-index.netbsd.org/tech-kern/2009/11/04/msg006434.html No objections.
1.200	22-Oct-2009	rmind	Simplify pmap_remove() a little by avoiding pmap_do_remove() layer, since possibility to skip wired mappings is not needed anymore. Apart from that, no functional differences are intended.
1.199	21-Oct-2009	rmind	Remove uarea swap-out functionality: - Addresses the issue described in PR/38828. - Some simplification in threading and sleepq subsystems. - Eliminates pmap_collect() and, as a side note, allows pmap optimisations. - Eliminates XS_CTL_DATA_ONSTACK in scsipi code. - Avoids few scans on LWP list and thus potentially long holds of proc_lock. - Cuts ~1.5k lines of code. Reduces amd64 kernel size by ~4k. - Removes __SWAP_BROKEN cases. Tested on x86, mips, acorn32 (thanks <mpumford>) and partly tested on acorn26 (thanks to <bjh21>). Discussed on <tech-kern>, reviewed by <ad>.
1.198	21-Apr-2009	cegger	change pmap flags argument from int to u_int. discussed with christos@ on source-changes-d@
1.197	15-Mar-2009	cegger	ansify function definitions
1.196	09-Mar-2009	nonaka	avail_start and avail_end is paddr_t.
1.195	08-Jan-2009	matt	branches: 1.195.2; When allocating a KMPAGE and it has multiple colors, make sure to flush them. Add some more KASSERTs for multiple colors (or lack thereof).
1.194	30-Dec-2008	matt	Reclaim PVF_KNC in VIPT to be PVF_MULTCLR (page has multiple colors). Track when a page is mapping in multiple colors and deal with the ramifications. When a page's MOD attribute is cleared, clean it from the cache. Fix a logic inversion. With these changes, the TI SDP2420 H4 board can successfully natively build a TISDP2420 kernel.
1.193	10-Dec-2008	pooka	Make kernel_pmap_ptr a const. Requested by steve_martin.
1.192	09-Dec-2008	pooka	Make pmap_kernel() a MI macro for struct pmap *kernel_pmap_ptr, which is now the "API" provided by the pmap module. pmap_kernel() remains as the syntactic sugar. Bonus cosmetics round: move all the pmap_t pointer typedefs into uvm_pmap.h. Thanks to Greg Oster for providing cpu muscle for doing test builds.
1.191	19-Nov-2008	matt	Allocate /dev/mem's page in pmap_init. Mark /dev/mem as MPSAFE. Ansify.
1.190	12-Nov-2008	ad	Remove LKMs and switch to the module framework, pass 1. Proposed on tech-kern@.
1.189	04-Nov-2008	matt	Use a mutex to control access DEV_MEM.
1.188	04-Nov-2008	matt	Protect some code with if (pg) { .. }
1.187	28-Sep-2008	skrll	branches: 1.187.2; 1.187.4; 1.187.8; Typo in comment.
1.186	14-Aug-2008	matt	Now that we track pages used by any of the kernel memory allocators, keep a count of them and export it as a sysctl node machdep.kmpages
1.185	13-Aug-2008	matt	Fix a few more corner cases. Always KMPAGE or pages with unmanaged writeable kernel mappings as modified. Only ever set DIRTY bit is DMOD is true and NC is false. Don't modify unmanaged mappings in pmap_clearbit.
1.184	08-Aug-2008	dogcow	fix "warning: 'npv' may be used uninitialized in this function"
1.183	06-Aug-2008	matt	Change pv_entries to use SLIST. For VIPT caches, keep track of when pages are dirty so that their content can be flushed back to main memory. This is done when the page is read-only mapped by more than 1 color. Pages become when either their modified bit gets set or an unmanaged writeable page is mapped. When a page in unmapped or changed to read-only, run pmap_vac_me_harder in case the page can be mapped read-only. Thanks are given to Imre Deak for giving me the idea to assert for PVF_DIRTY.
1.182	16-Jul-2008	matt	Revamp bookkeeping for pages entered by pmap_kenter_pa. Keep track of them on pvlists so that the cacheability can be properly tracked.
1.181	09-Jul-2008	scw	When dealing with 'cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE' in pmap_do_remove(), make sure to use PTE_SYNC() for each rolled-back PTE on the list. Fixes potential MMU inconsistencies on some ARM platforms where page-tables are mapped write-back.
1.180	03-Jul-2008	matt	branches: 1.180.2; Use the same login in pmap_kenter_pa when removing an unmamanged mapping as in pmap_kremove (otherwise kro_mappings will become incorrect).
1.179	03-Jul-2008	matt	For armv6(VIPT), change the rules for mapping via kenter_pa. Allow readonly pages to be mapped by different cache color indexes.
1.178	24-Jun-2008	scw	In pmap_deactivate(), if the process is exiting make sure the next call to pmap_activate() performs a full MMU context-switch and cache flush, which might otherwise be skipped. Fixes ARM_LOW_VECTORS problem reported in PR port-arm/38950.
1.177	17-Jun-2008	chris	Fix two KASSERT(value \| (C1\|C2)) to KASSERT(value & (C1\|C2)) so that it tests for something, rather than always being true. Pointed out by Andy Shevchenko in: http://mail-index.netbsd.org/port-arm/2008/06/17/msg000255.html
1.176	04-Jun-2008	ad	branches: 1.176.2; vm_page: put TAILQ_ENTRY into a union with LIST_ENTRY, so we can use both.
1.175	28-Apr-2008	martin	branches: 1.175.2; Remove clause 3 and 4 from TNF licenses
1.174	27-Apr-2008	matt	Merge kernel changes in matt-armv6 to HEAD.
1.173	20-Apr-2008	scw	branches: 1.173.2; There's really no need to switch VM contexts within cpu_switchto() as MI code always calls pmap_deactivate/pmap_activate on context switch. Instead, just record the last active lwp (or NULL if it exited) and defer switching VM context to pmap_activate(). This saves an additional function call overhead in cpu_switchto(). While here, g/c unused cpuswitch.S local .Lblock_userspace_access.
1.172	29-Mar-2008	chris	branches: 1.172.2; Fix LOCKDEBUG build on arm by: * converting simple_{un}lock to mutex_enter/exit * Using UVM_OBJ_INIT & DESTROY for the uvm_object in the pmap structure
1.171	06-Jan-2008	matt	branches: 1.171.6; current_intr_depth is dead. Make sure we don't use it anymore.
1.170	01-Jan-2008	chris	Add support for kcore headers to arm32 kernel core dumps. The kcore code is based on i386's kcore header handling. Having an asm stub for dumpsys, to dump the registers onto the stack, and then call the C code to do the memory dump is based on amd64's core dump code. This allows a successful core dump on cats. Part of fixing PR cats/18026.
1.169	08-Nov-2007	matt	branches: 1.169.6; Make this compile again.
1.168	07-Nov-2007	ad	Merge from vmlocking: - pool_cache changes. - Debugger/procfs locking fixes. - Other minor changes.
1.167	17-Oct-2007	garbled	branches: 1.167.2; Merge the ppcoea-renovation branch to HEAD. This branch was a major cleanup and rototill of many of the various OEA cpu based PPC ports that focused on sharing as much code as possible between the various ports to eliminate near-identical copies of files in every tree. Additionally there is a new PIC system that unifies the interface to interrupt code for all different OEA ppc arches. The work for this branch was done by a variety of people, too long to list here. TODO: bebox still needs work to complete the transition to -renovation. ofppc still needs a bunch of work, which I will be looking at. ev64260 still needs to be renovated amigappc was not attempted. NOTES: pmppc was removed as an arch, and moved to a evbppc target.
1.166	10-Oct-2007	ad	branches: 1.166.2; Comment out references to spinlockmgr().
1.165	15-Sep-2007	scw	branches: 1.165.2; ARM cpu_switchto() has been partially broken since yamt-idlelwp was merged as its cache/tlb management smarts relied too heavily on pre-merge context- switch behaviour. See PR kern/36548 for one manifestation of the breakage. To address this: - Ditch the shadow pmap variables in the PCB (pagedir, l1vec, dacr, cstate) as it was too easy for them to get out of sync with the pmap. - Re-write (and fix) the convoluted cpuswitch.S cache/tlb ASM code in C. It's only slightly less efficient, but is much more readable/maintainable. - Document cpufuncs.cf_context_switch() as being C-callable. - pmap_activate() becomes a no-op if the lwp's vmspace is already active. (Good performance win, since pmap_activate() is now invoked on every context-switch, even though ARM's cpu_switchto() already does all the grunt work) XXX: Some CPU-specific armXX_context_switch() implementations (arm67, arm7tdmi, arm8) always flush the I+D caches. This should not be necessary. Someone with access to hardware (acorn32?) needs to deal with this.
1.164	17-May-2007	yamt	branches: 1.164.6; 1.164.8; 1.164.10; 1.164.12; merge yamt-idlelwp branch. asked by core@. some ports still needs work. from doc/BRANCHES: idle lwp, and some changes depending on it. 1. separate context switching and thread scheduling. (cf. gmcgarry_ctxsw) 2. implement idle lwp. 3. clean up related MD/MI interfaces. 4. make scheduler(s) modular.
1.163	09-Apr-2007	chris	branches: 1.163.4; In pmap_activate restore interrupts to their previous state rather than always enabling them. It's not clear if this actually caused any problems, but it seems safer to restore to the previous state in case pmap_activate is ever called with interrupts disabled.
1.162	12-Mar-2007	ad	branches: 1.162.2; Pass an ipl argument to pool_init/POOL_INIT to be used when initializing the pool's lock.
1.161	04-Mar-2007	christos	branches: 1.161.2; Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.
1.160	22-Feb-2007	thorpej	TRUE -> true, FALSE -> false
1.159	21-Feb-2007	thorpej	Replace the Mach-derived boolean_t type with the C99 bool type. A future commit will replace use of TRUE and FALSE with true and false.
1.158	06-Jan-2007	christos	branches: 1.158.2; From Scott Allen in http://mail-index.netbsd.org/port-arm/2006/07/26/0000.html I ran into a problem when I tried to set up a mapping that started at virtual address 0xFFF00000 and was 0x00100000 long. In other words, the mapping should have gone to the end of the 32 bit address space. The mapping was made with no problem, but pmap_devmap_find_va() wouldn't find an address within the mapping. For example, if I told it to find a mapping for 0x1000 bytes at 0xFFF01000, it would try to make sure that 0xFFF01000 was greater than 0xFFF00000 and that (0xFFF01000+0x1000) was less than (0xFFF00000+0x00100000). However, that last expression (0xFFF00000+0x00100000) wrapped around to be simply 0x00000000 so it wasn't found. This patch fixes this problem in pmap_devmap_find_va() and pmap_devmap_find_pa() by subtracting one off of the sizes to be compared, so in my example, (0xFFF01000+0x1000-1) will be less than (0xFFF00000+0x00100000-1).
1.157	24-Dec-2005	perry	branches: 1.157.20; 1.157.24; Remove leading __ from __(const\|inline\|signed\|volatile) -- it is obsolete.
1.156	10-Dec-2005	scw	Implement pmap_collect() for arm32.
1.155	08-Dec-2005	yamt	use VM_PAGE_TO_PHYS macro.
1.154	04-Jul-2005	bsh	branches: 1.154.2; The first step to support Intel PXA270. kernel config option CPU_XSCALE_PXA2X0 is now obsoleted by CPU_XSCALE_PXA250 and CPU_XSCALE_PXA270. If both of them are defined, CPU is determined run-time.
1.153	24-Jun-2005	scw	In pmap_devmap_find_pa(), use 64-bit arithmetic to handle the case where 'pa + size' == 0x0. As in, if we're passed details of a region right at the top of physical address space. Otherwise we'll likely hit a false-positive due to 32-bit wrap-around.
1.152	26-Apr-2005	scw	Since pmap_page_remove() is called from pmap_page_protect(), don't modify the current pmap's pm_cstate if we have to flush the TLB, as callers of pmap_page_protect() are not required to invoke pmap_update() afterwards. Otherwise we can end up with a pm_cstate which is inconsistent with reality in the TLB, which can lead to future TLB flushes being erroneously skipped.
1.151	01-Apr-2005	yamt	merge yamt-km branch. - don't use managed mappings/backing objects for wired memory allocations. save some resources like pv_entry. also fix (most of) PR/27030. - simplify kernel memory management API. - simplify pmap bootstrap of some ports. - some related cleanups.
1.150	14-Jan-2005	joff	branches: 1.150.2; 1.150.4; Dont try freeing bootstrap pages with pool_page_free. Fixes kern/28869
1.149	02-Jan-2005	chris	Remove direct references to TAILQ internal structures. No functional change, just tidying up code.
1.148	03-Apr-2004	bsh	pmap_pte_init_arm9() is necessary only when defined(CPU_ARM9) and defined(ARM9_CACHE_WRITE_THROUGH)
1.147	18-Jan-2004	scw	Fix ARM_VECTORS_LOW fallout caused by the recent reaper removal. Just before removing the vector page mapping, switch to the kernel pmap's L1/vector page mapping so as not to pull the rug out from under ourselves. To prevent the stale L1/vector page mapping from being restored by cpu_switch, replace the relevant fields of the dying process' pcb with those of lwp0's pcb.
1.146	01-Nov-2003	jdolecek	avoid stong words in comments
1.145	29-Oct-2003	mycroft	Whitespace.
1.144	29-Oct-2003	mycroft	The previous patch was wrong -- mcr does not output anything. Instead give a junk input (it's not used when the last argument is 0).
1.143	28-Oct-2003	scw	Fix an uninitialised variable warning, reported by Shoichi Miyake in port-arm/23293.
1.142	26-Oct-2003	chris	Fix up some unitialised variables.
1.141	13-Oct-2003	scw	On Xscale, define PMAP_UAREA() and use it to tweak uarea mappings so they use the mini D$. This results in a small performance boost on xscale platforms, since flushing the main cache on a context switch won't affect the kernel stack/pcb.
1.140	05-Oct-2003	matt	Add SA_SIGINFO support for ARM (from Chris Gilbert).
1.139	21-Sep-2003	matt	Change some type-punning detected by gcc 3.3.1 to (void *).
1.138	06-Sep-2003	rearnsha	Support for initializing ARM10 processors in write-through mode.
1.137	23-Jun-2003	martin	branches: 1.137.2; Make sure to include opt_foo.h if a defflag option FOO is used.
1.136	15-Jun-2003	thorpej	Add another devmap routine that allows bootstrap code to register a devmap reflecting mappings that are created by really early bootstrap code before pmap_devmap_bootstrap() is called.
1.135	15-Jun-2003	thorpej	Replace the ad-hoc "section mapping table" for static device mappings with a more generic "devmap" structure that can also handle mappings made with large and small pages. Add new pmap routines to enter these mappings during bootstrap (and "remember" the devmap), and routines to look up the static mappings once the kernel is running.
1.134	21-May-2003	thorpej	Move the new pmap from arm32/pmap_new.c to arm32/pmap.c, fully replacing the old.
1.133	10-May-2003	thorpej	Back out the following chagne: http://mail-index.netbsd.org/source-changes/2003/05/08/0068.html There were some side-effects that I didn't anticipate, and fixing them is proving to be more difficult than I thought, do just eject for now. Maybe one day we can look at this again. Fixes PR kern/21517.
1.132	08-May-2003	thorpej	Simplify the way the bounds of the managed kernel virtual address space is advertised to UVM by making virtual_avail and virtual_end first-class exported variables by UVM. Machine-dependent code is responsible for initializing them before main() is called. Anything that steals KVA must adjust these variables accordingly. This reduces the number of instances of this info from 3 to 1, and simplifies the pmap(9) interface by removing the pmap_virtual_space() function call, and removing two arguments from pmap_steal_memory(). This also eliminates some kludges such as having to burn kernel_map entries on space used by the kernel and stolen KVA. This also eliminates use of VM_{MIN,MAX}_KERNEL_ADDRESS from MI code, this giving MD code greater flexibility over the bounds of the managed kernel virtual address space if a given port's specific platforms can vary in this regard (this is especially true of the evb* ports).
1.131	22-Apr-2003	thorpej	Some ARM32_PMAP_NEW-related cleanup: * Define a new "MMU type", ARM_MMU_SA1. While the SA-1's MMU is basically compatible with the generic, the SA-1 cache does not have a write-through mode, and it is useful to know have an indication of this. * Add a new PMAP_NEEDS_PTE_SYNC indicator, and try to evaluate it at compile time. We evaluate it like so: - If SA-1-style MMU is the only type configured -> 1 - If SA-1-style MMU is not configured -> 0 - Otherwise, defer to a run-time variable. If PMAP_NEEDS_PTE_SYNC might evaluate to true (SA-1 only or run-time check), then we also define PMAP_INCLUDE_PTE_SYNC so that e.g. assembly code can include the necessary run-time support. PMAP_INCLUDE_PTE_SYNC largely replaces the ARM32_PMAP_NEEDS_PTE_SYNC manual setting Steve included with the original new pmap. * In the new pmap, make pmap_pte_init_generic() check to see if the CPU has a write-back cache. If so, init the PT cache mode to C=1,B=0 to get write-through mode. Otherwise, init the PT cache mode to C=1,B=1. * Add a new pmap_pte_init_arm8(). Old pmap, same as generic. New pmap, sets page table cacheability to 0 (ARM8 has a write-back cache, but flushing it is quite expensive). * In the new pmap, make pmap_pte_init_arm9() reset the PT cache mode to C=1,B=0, since the write-back check in generic gets it wrong for ARM9, since we use write-through mode all the time on ARM9 right now. (What this really tells me is that the test for write-through cache is less than perfect, but we can fix that later.) * Add a new pmap_pte_init_sa1(). Old pmap, same as generic. New pmap, does generic initialization, then resets page table cache mode to C=1,B=1, since C=1,B=0 does not produce write-through on the SA-1.
1.130	01-Apr-2003	thorpej	Use PAGE_SIZE rather than NBPG.
1.129	29-Mar-2003	bsh	for Intel PXA2[15][05] processors, select write-back/write-through cache based on CPU id. write-through on PXA2[15]0 B2 stepping and earlier. write-back on C0 and C1 stepping (a.k.a PXA2[15]5 A0) options XSCALE_CACHE_WRITE_{THROUGH,BACK} can override it. for other XScale CPUs than PXA2xx, XSCALE_CACHE_WRITE_THROUGH works same as before.
1.128	27-Mar-2003	mycroft	Remove references to variables that aren't used here.
1.127	23-Mar-2003	chris	Garbage collect pmap_map, the last (and only?) use has been removed.
1.126	23-Feb-2003	thorpej	Change pcb32_pagedir to a paddr_t (after all, it's used as a paddr_t everywhere in the code).
1.125	21-Feb-2003	chris	Convert a few types into things that are more accurate, mostly: int's to unsigned int/u_int where they shouldn't go negative. int's to boolean_t's where they're being used as bools. No real functional change (in the produced asm a few condition codes changed)
1.124	17-Jan-2003	thorpej	Merge the nathanw_sa branch.
1.123	24-Nov-2002	chris	Add a debug assert that wired pages provide protection flags in the flags argument as well. Also update a couple of debug messages to NPDEBUG.
1.122	12-Nov-2002	chris	Tweak a few minor things: when looking to reenable caching, only do so if all the pages aren't already cached. Convert some ints to unsigned int. (scarily this actually shows the biggest decrease in timing for my benchmark, I guess the compiler can optimise better)
1.121	11-Nov-2002	chris	gratuitous whitespace and de-__P'ing. No functional change.
1.120	11-Nov-2002	chris	A few minor tweaks. Use pmap_free_pvs in pmap_remove, should save on the overhead of freeing each pv on it's own. Correctly set ptp when calling pmap_enter_pv, this adds more overhead, but the effect is minimal. Timings show that it increases gmake's make configure step from 2:07.90 to 2:08.90. I've more optimisations planned that should negate this increase.
1.119	11-Nov-2002	chris	Remove unused pa variable (it's assigned but not used any more)
1.118	27-Sep-2002	provos	remove trailing \n in panic(). approved perry.
1.117	22-Sep-2002	chs	rename the existing pmap_remove_all() here to pmap_page_remove() (ala the x86 pmap) to avoid conflicting with the new pmap interface function of the same name.
1.116	05-Sep-2002	jdolecek	whitespace fix past __KERNEL_RCSID()
1.115	24-Aug-2002	thorpej	In pmap_map_in_l1() and pmap_unmap_in_l1(), make sure that the VA that is passed in is already aligned to a 4M super-section.
1.114	24-Aug-2002	thorpej	When we allocate a PTP, make sure the offset we specify is for the 4M super-section that the PTP will map, not some random 1M chunk of it. This gives the PTP hint code a much better chance to working properly, and allows us to tidy up the code that flushes a PTP from the cache in pmap_destroy().
1.113	24-Aug-2002	thorpej	Enable caching on kernel and user page tables. This saves having to do uncached memory access during VM operations (which can be quite expensive on some CPUs). We currently write-back PTEs as soon as they're modified; there is some room for optimization (to write them back in larger chunks). For PTEs in the APTE space (i.e. PTEs for pmaps that describe another process's address space), PTEs must also be evicted from the cache complete (PTEs in PTE space will be evicted durint a context switch).
1.112	22-Aug-2002	thorpej	* Add PTE_SYNC() and PTE_SYNC_RANGE() macros. These don't actually do anything yet. * Use PTE_SYNC() and PTE_SYNC_RANGE() in some obvious places, i.e. where vtopte() is used.
1.111	21-Aug-2002	thorpej	Use a pool cache for PT-PTs.
1.110	21-Aug-2002	thorpej	Do cached memory access to L1 tables, making sure to write-back the cache after any L1 table modifications.
1.109	13-Aug-2002	thorpej	Add the brutal hack that allows us to limp along using the read/write cache line allocation policy on XScale CPUs: in pmap_enter(), if the pmap is the kernel pmap, clear the X-bit in the PTE, thus disabling read/write-allocate for managed kernel mappings. Yes, this is ugly. But it makes userland code run with r/w-allocate, which is a huge improvement on systems with low core memory performance.
1.108	10-Aug-2002	thorpej	Tidy up pmap_clean_page() a little, and reenable some code that was disabled previously: Skip cleaning mappings which are read-only, because the pmap (now) does clean pages on a r/w -> r/o transition.
1.107	10-Aug-2002	thorpej	Clean up some warts in pmap_protect().
1.106	09-Aug-2002	thorpej	Add an XSCALE_CACHE_READ_WRITE_ALLOCATE option for people who want to play fast-and-loose.
1.105	09-Aug-2002	thorpej	Add some code, conditional on PMAP_ALIAS_DEBUG, that can be used to hunt for virtual aliases between managed (pmap_enter) and non-managed (pmap_kenter_pa) mappings.
1.104	06-Aug-2002	thorpej	- pmap_remove(): unmap the PTEs after we have finished with the page tables. - pmap_enter(): if making a mapping for the same PA rw->ro, write-back the cache before doing so. - pmap_clearbit(): if revoking REF on a page, make sure to wbinv the cache if the page has write permission, else inv the cache if the page's PTE is valid (XXX we actually wbinv in this case, as well, due to lack of idcache_inv_range()). Only flush the TLB if the PTE changed.
1.103	31-Jul-2002	thorpej	Overhaul how DMA ranges work in the ARM bus_dma implementation. A new "arm32_dma_range" structure now describes a DMA window, with a system address base, bus address base, and length. In addition to providing info about which memory regions are legal for DMA, the new structure provides address translation support, as well. As before, if a tag does not list any ranges, then all addresses are considered valid, and no DMA address translation is performed. This allows us to remove a large chunk of code which was duplicated and tweaked slightly (to do the address translation) from the stock ARM bus_dma in the XScale IOP and ARM Integrator ports. Test compiled on all ARM platforms, test booted on Intel IQ80321 and Shark.
1.102	31-Jul-2002	thorpej	Move the calls to uvm_page_physload() out of pmap_bootstrap() and into platform-specific initialization code, giving platform-specific code control over which free list a given chunk of memory gets put onto. Changes are essentially mechanical. Test compiled for all ARM platforms, test booted on Intel IQ80321 and Shark. Discussed some time ago on port-arm.
1.101	30-Jul-2002	thorpej	Move the uvm_setpagesize() call to platform-dependent code in preparation for other changes to pmap_bootstrap().
1.100	30-Jul-2002	thorpej	Don't use pmap_kenter_pa() in pmap_map(); doing so causes an assertion failure in pmap_kenter_pa().
1.99	02-Jun-2002	drochner	move initialization of the "struct pglist" returned by uvm_pglistalloc() from the calling code into uvm_pglistalloc() itself for consistency and easier error handling
1.98	01-Jun-2002	lukem	SIMPLEQ rototill: - implement SIMPLEQ_REMOVE(head, elm, type, field). whilst it's O(n), this mirrors the functionality of SLIST_REMOVE() (the other singly-linked list type) and FreeBSD's STAILQ_REMOVE() - remove the unnecessary elm arg from SIMPLEQ_REMOVE_HEAD(). this mirrors the functionality of SLIST_REMOVE_HEAD() (the other singly-linked list type) and FreeBSD's STAILQ_REMOVE_HEAD() - remove notes about SIMPLEQ not supporting arbitrary element removal - use SIMPLEQ_FOREACH() instead of home-grown for loops - use SIMPLEQ_EMPTY() appropriately - use SIMPLEQ_*() instead of accessing sqh_first,sqh_last,sqe_next directly - reorder manual page; be consistent about how the types are listed - other minor cleanups
1.97	14-May-2002	chris	branches: 1.97.2; 1.97.4; Implement scheduler lock protocol, this fixes PR arm/10863. Also add correct locking when freeing pages in pmap_destroy (fix from potr) This now means that arm32 kernels can be built with LOCKDEBUG enabled. (only tested on cats though)
1.96	24-Apr-2002	thorpej	* pmap_clean_page(): Clean up a comment. * pmap_protect(): write back the range when doing a r/w -> r/o transition. (Still leave the block concerned with this in pmap_clean_page() disabled, for now.) * pmap_pte_init_xscale(): Disable read/write-allocate for now, until we figure out why sometimes cache lines of NULs get deposited into file data. Also, make sure ECC protection of page table access is disabled for now. * xscale_setup_minidata(): Make sure the mini-data cache is configured write-back with read/write-allocate.
1.95	12-Apr-2002	thorpej	Default all XScale core processors to the read/write-allocate write-back cache mode. Add a new XSCALE_CACHE_WRITE_THROUGH option for people who are paranoid about the cache-related errata (you do have to line up the planets correctly to trip them, but having the option is useful).
1.94	10-Apr-2002	thorpej	On XScale processors where we use write-back caching, use are read/write-allocate line allocation policy. On the i80321, this improves nearly every lmbench benchmark, dramatically so the ones that are sensitive to memory bandwidth (100-300% improvement for these).
1.93	10-Apr-2002	thorpej	Add a new function, pmap_alloc_ptpt(), that allocates the PTPT and maps it the way we want, rather than using uvm_km_zalloc() and playing the "revoke cacheability" song-and-dance.
1.92	10-Apr-2002	thorpej	pmap_alloc_l1pt(): Just enter the mappings for the L1 table by hand, rather than calling pmap_kenter_pa() and then revoking cacheability in the PTE.
1.91	10-Apr-2002	thorpej	Use L2_S_CACHE_MASK in places where we revoke cacheability.
1.90	10-Apr-2002	thorpej	pmap_kenter_pa(): Obey the "prot" argument, rather than simply making all mappings r/w (!!).
1.89	10-Apr-2002	thorpej	In pmap_copy_page_xscale(), put the source page in the mini-data cache, as well. The mini-data cache is 2-way, so src and dst won't clobber each other, and the smallness of the cache doesn't matter, since we access each page once sequentially. While we still have to do the initial clean of the source page, this saves another 4K of main D$ pollution, and also means we don't have to do 2 cache passes after the copy is complete (i.e. we can skip the invalidation of the source page in the main cache, since it's no longer there).
1.88	10-Apr-2002	thorpej	Add separate pmap_{zero,copy}_page() functions for generic ARM vs. XScale. Use the mini-data cache for the destination on XScale, thus saving tossing out 4K of possible-useful data from the main data cache each time. This significantly improves every test in lmbench.
1.87	09-Apr-2002	thorpej	* Move the code that cleans the XScale mini-data cache into its own function. * Add a new function which sets up the mini-data cache clean area properly.
1.86	09-Apr-2002	thorpej	* Split pte_cache_mode into pte_l1_s_cache_mode, pte_l2_l_cache_mode, and pte_l2_s_cache_mode. The cache-meaningful bits are different for these descriptor types on some processor models. * Add pte_*_cache_mask, corresponding to each above, which has a mask of the cache-meangful bits, and define those for generic and XScale MMU classes. Note, the L2_S_CACHE_MASK_xscale definition requires use of the Extended Small Page L2 descriptor (the "X" bit overlaps with AP bits otherwise).
1.85	09-Apr-2002	thorpej	Define 2 classes of ARM MMUs: 1. Generic (compatible with ARM6) 1. XScale (can be used as generic, but also has certainly nifty extensions). Define abstract PTE bit defintions for each MMU class. If only one MMU class is configured into the kernel (based on CPU_* options), then we get the constants for that MMU class. Otherwise we indirect through varaibles set up via set_cpufuncs(). XXX The XScale bits are currently the same as the generic bits. Baby steps.
1.84	09-Apr-2002	thorpej	L2_TYPE_S -> L2_S_PROTO
1.83	09-Apr-2002	thorpej	Use abstract names for the protection and PTE type bits in L1 and L2 descriptors. This will allow us to support different PTE layouts that enable the use of extensions on different processor models.
1.82	05-Apr-2002	thorpej	Back-out rev 1.75 (pmap_extract() rewrite), and fix the (minor) bug that revision intended to fix properly.
1.81	05-Apr-2002	thorpej	* Rewrite the 32-bit ARM pte.h based on the ARM architecture manual. Significant cleanup, here, including better PTE bit names. * Add XScale PTE extensions (ECC enable, write-allocate cache mode). * Mechanical changes everywhere else to update for new pte.h. While doing this, two bugs (as a result of typos) were fixed in arm/arm32/bus_dma.c evbarm/integrator/int_bus_dma.c
1.80	04-Apr-2002	thorpej	Eliminate a mask against PD_MASK.
1.79	04-Apr-2002	thorpej	There is no need to mask VAs and PAs w/ PG_FRAME to clear the lower bits; UVM provides us page-aligned addresses for everything. For the paranoid, we'll leave KDASSERT()'s in that check for this if the kernel is built with DEBUG. Low-hanging fruit that shaves some cycles.
1.78	04-Apr-2002	thorpej	Rename flags that are really part of the pv_entry/mdpage into pmap.h and give them more descriptive names and better comments: * PT_M -> PVF_MOD (page is modified) * PT_H -> PVF_REF (page is referenced) * PT_W -> PVF_WIRED (mapping is wired) * PT_Wr -> PVF_WRITE (mapping is writable) * PT_NC -> PVF_NC (mapping is non-cacheable; multiple mappings)
1.77	04-Apr-2002	thorpej	Catch a couple more vector page mapping manipulations.
1.76	03-Apr-2002	thorpej	Clean up handling of the vector page on 32-bit ARM systems: * Don't refer to VA 0, instead refer to a new variable: vector_page * Delete the old zero_page_() functions, replacing them with a new one: vector_page_setprot(). When manipulating vector page mappings in user pmaps, only do so if the vector page is below KERNEL_BASE (if it's above KERNEL_BASE, the vector page is mapped by the kernel pmap). * Add a new function, arm32_vector_init(), which takes the virtual address of the vector page (which MUST be valid when the function is called) and a bitmask of vectors the kernel is going to take over, and performs all vector page initialization, including setting the V bit in the CPU Control register ("relocate vectors to high address"), if necessary.
1.75	03-Apr-2002	reinoud	Rototil and fix the pmap_extract function. It wouldn't even return data when the part being quiried was mapped with a section (!) giving weird results and had become a mess of goto's. Complete rewrite and cleaned up the `goto'-jungle entirely ... ripped all goto's. The resulting code is much better to read and might even have a small performance gain.
1.74	25-Mar-2002	thorpej	Fix reporting of the kernel virtual address space range to UVM.
1.73	25-Mar-2002	thorpej	* Some cleanup. * Delete the call to pmap_copy() in pmap.h
1.72	25-Mar-2002	thorpej	Clean up pmap_map_ptes() and pmap_unmap_ptes() a little, and add a debug assertion that curproc is never NULL if mapping a non-current pmap.
1.71	25-Mar-2002	thorpej	The target page of pmap_zero_page(), pmap_pageidlezero(), and pmap_copy_page() will never have any mappings. Therefore, it is unnecessary to do a cache clean for that page. Add assertions in #ifdef DEBUG that assert this invariant. This shaves some cycles off the frequently-called pmap_zero_page() and pmap_copy_page() (no need to look up the dst page's vm_page structure, and one less function call to clean the page).
1.70	25-Mar-2002	thorpej	* Fix use of pmap_curmaxkvaddr. * Use the PTP hint in the pmap.
1.69	25-Mar-2002	thorpej	Move some private pmap data structures into pmap.c
1.68	24-Mar-2002	thorpej	Garbage-collect pmap_pte() (and good riddance!)
1.67	24-Mar-2002	chris	remove pointless pg = NULL in else part of if (pg != NULL)
1.66	24-Mar-2002	thorpej	pmap_enter(): Use pmap_map_ptes() correctly.
1.65	24-Mar-2002	chris	Update pmap_copy_page to only map in the src readonly and only invalidate it after the copy, no need for it to flush the wb.
1.64	24-Mar-2002	thorpej	pmap_allocpagedir(): Don't use pmap_pte(), and simplify a little.
1.63	24-Mar-2002	thorpej	pmap_handled_emulation(): Fix locking protocol botch. XXX Should we traverse the PV list and enable all PTEs?
1.62	24-Mar-2002	thorpej	pmap_handled_emulation(): Use pmap_map_ptes() correctly.
1.61	24-Mar-2002	thorpej	pmap_modified_emulation(): Use pmap_map_ptes() correctly.
1.60	24-Mar-2002	thorpej	pmap_unwire(): Use pmap_map_ptes() correctly.
1.59	24-Mar-2002	thorpej	pmap_clearbit(): Use pmap_map_ptes() correctly.
1.58	24-Mar-2002	thorpej	Use pmap_is_curpmap() consistently.
1.57	24-Mar-2002	thorpej	Clean up the PTP allocation functions a bit.
1.56	24-Mar-2002	thorpej	* arm_byte_to_page() -> arm_btop() * arm_page_to_byte() -> arm_ptob()
1.55	24-Mar-2002	thorpej	Remove some redundant tests in pmap_enter().
1.54	23-Mar-2002	thorpej	Garbage-collect the "pagehook" stuff.
1.53	23-Mar-2002	thorpej	* Rename PROCESS_PAGE_TBLS_BASE -> PTE_BASE * Rename ALT_PAGE_TBLS_BASE -> APTE_BASE * Garbage-collect PAGE_TABLE_SPACE_START
1.52	08-Mar-2002	thorpej	Pool deals fairly well with physical memory shortage, but it doesn't deal with shortages of the VM maps where the backing pages are mapped (usually kmem_map). Try to deal with this: * Group all information about the backend allocator for a pool in a separate structure. The pool references this structure, rather than the individual fields. * Change the pool_init() API accordingly, and adjust all callers. * Link all pools using the same backend allocator on a list. * The backend allocator is responsible for waiting for physical memory to become available, but will still fail if it cannot callocate KVA space for the pages. If this happens, carefully drain all pools using the same backend allocator, so that some KVA space can be freed. * Change pool_reclaim() to indicate if it actually succeeded in freeing some pages, and use that information to make draining easier and more efficient. * Get rid of PR_URGENT. There was only one use of it, and it could be dealt with by the caller. From art@openbsd.org.
1.51	06-Mar-2002	chris	Mostly style changes to stop us directly referencing tqh_first, and use TAILQ_FIRST instead. Based on rev 1.130 of the i386 pmap.c.
1.50	05-Mar-2002	thorpej	* Make pmap_is_{modified,referenced}() macros in pmap.h that just test the attributes in the vm_page_md directly. * Clean up pmap_clear_{modified,referenced}(). * Delete now-unused pmap_testbit().
1.49	05-Mar-2002	thorpej	Switch back to using vm_page_md (thanks chuq for finding the bug in the code that made it unstable before!)
1.48	03-Mar-2002	chris	Implement pmap_growkernel for arm32 based ports. Note that this has been compiled on some systems, cats, IQ80310, IPAQ, netwinder and shark (note that shark's build is currently broken due to other reasons), but only actually run on cats. Shark doesn't make use of the functionality as I believe there has to be a correlation between OFW and the kernel tables so that calls into OFW work.
1.47	22-Feb-2002	thorpej	Change pmap_map_entry() to work like pmap_map_chunk(): take a pointer to the L1 table and a virtual address, and no pointer to the L2 table. The L2 table will be looked up by pmap_map_entry(), which will panic if the there is no L2 table for the requested VA. NOTE: IT IS EXTREMELY IMPORTANT THAT THE CORRECT VIRTUAL ADDRESS BE PROVIDED TO pmap_map_entry()! Notably, the code that mapped the kernel L2 tables into the kernel PT mapping L2 table were not passing actual virtual addresses, but rather offsets into the range mapped by the L2 table. I have fixed up all of these call sites, and tested the resulting kernel on both an IQ80310 and a Shark. Other portmasters should examine their pmap_map_entry() calls if their new kernels fail.
1.46	21-Feb-2002	thorpej	Keep track of which kernel PTs are available during bootstrap, and let pmap_map_chunk() lookup the correct one to use for the current VA. Eliminate the "l2table" argument to pmap_map_chunk(). Add a second L2 table for mapping kernel text/data/bss on the IQ80310 (fixes booting kernels with ramdisks).
1.45	21-Feb-2002	thorpej	In pmap_map_chunk(), if we can't use a section mapping, then make sure that the L1 slot for the current VA points to an L2 table, and panic if it doesn't.
1.44	21-Feb-2002	thorpej	Always pass the L1 table to pmap_map_chunk(). This allows pmap_map_chunk() to perform some error checking.
1.43	21-Feb-2002	thorpej	map_chunk() -> pmap_map_chunk(), and move it to pmap.c
1.42	20-Feb-2002	thorpej	map_pagetable() -> pmap_link_l2pt(), and move it to pmap.c
1.41	20-Feb-2002	thorpej	Collapse map_entry{,ro,nc}() into a single pmap_map_entry() that takes a prot and a "cacheable" indicator.
1.40	20-Feb-2002	thorpej	Rename map_section() to pmap_map_section(), move it to pmap.c, and give it an extra argument (prot - specifies protection of the mapping).
1.39	06-Feb-2002	thorpej	Back out all the vm_page_md changes. They are causing some mysterious problems (a similar change to the i386 pmap causes mysterious problems there, as well), and the issue needs to be investigated more.
1.38	06-Feb-2002	thorpej	Efficiency tweaks, some made possible by vm_page_md.
1.37	05-Feb-2002	thorpej	Use vm_page_md rather than pmap_physseg. Saves lots of cycles in common operations.
1.36	25-Jan-2002	thorpej	Overhaul of the ARM cache code. This is mostly a simplification pass. Rather than providing a whole slew of cache operations that aren't ever used, distill them down to some useful primitives: icache_sync_all Synchronize I-cache icache_sync_range Synchronize I-cache range dcache_wbinv_all Write-back and Invalidate D-cache dcache_wbinv_range Write-back and Invalidate D-cache range dcache_inv_range Invalidate D-cache range dcache_wb_range Write-back D-cache range idcache_wbinv_all Write-back and Invalidate D-cache, Invalidate I-cache idcache_wbinv_range Write-back and Invalidate D-cache, Invalidate I-cache range Note: This does not yet include an overhaul of the actual asm files that implement the primitives. Instead, we've provided a safe default for each CPU type, and the individual CPU types can now be optimized one at a time.
1.35	20-Jan-2002	thorpej	Some prototype cleanup.
1.34	17-Jan-2002	thorpej	Teach pmap_extract() about section mappings.
1.33	05-Jan-2002	chris	Make some of the arm32 files build with LOOSE_PROTOTYPES not set in the makefile. Turned up a few mismatched functions. Note that this isn't all of the arm32 files. Aim will be to get arm32 kernels built with LOOSE_PROTOTYPES not set.
1.32	22-Nov-2001	thorpej	Add cpu_cpwait() calls after TLB updates that are not expected to be followed up by a pmap_update().
1.31	19-Nov-2001	thorpej	Implement pmap_update(). Currently it just calls cpu_cpwait(), which ensures that TLB/cache operations have completed.
1.30	03-Nov-2001	rearnsha	branches: 1.30.2; Replace most uses of pmap_pde_p with pmap_pde_page, since that is what we need later in the code. This fixes a fatal kernel fault in pmap_modified_emulation if a user application tries to access a kernel address that is section-mapped. Add a diagnostic that detects attempts to call pmap_kenter_pa with a va that is section-mapped.
1.29	01-Nov-2001	rearnsha	When clearing the modified bit for modified emulation, don't turn caching on for a page just because we are clearing the writable bit in the PTE: this is incompatible with the way pmap_vac_me_harder works, and the code in the modified emulation handler doesn't know about recalculating the cachable attributes (nor should it, IMO). Also, if we are invalidating a page, flush its TLB entry; for some reason we were only doing this when clearing the Write or modified bits. These patches together seem to solve the random seg-faults that were still occuring occasionally under heavy paging.
1.28	18-Oct-2001	rearnsha	branches: 1.28.2; Add a comment describing the logic implemented by pmap_vac_me_harder.
1.27	18-Oct-2001	rearnsha	On processors that support both write-through and write-back cacheing (eg ARM920), the mode in which the processor operates is governed by the use of both the PT_C and PT_B bits: PT_C=1,PT_B=1 -> Write-back PT_C=1,PT_B=0 -> Write-through To support this define pte_cache_mode (initialized to PT_C\|PT_B) and use that when enabling cacheing for a page.
1.26	18-Oct-2001	rearnsha	With a diagnostic kernel, printing out a message each time we fail to allocate a L1 pt is often enough to bring the system to its knees: so make the messages PDEBUG(0,...). However, even with this step having more than a small number of processes searching for a L1 pt can still be enough to bring the system down, since they all run at high priority and sleep for very little time, thus blocking out user code from completing. So implement an exponential backoff when waiting for a page table, so that we don't hog the CPU when memory is scarce. Tested by running a make of the C compiler with "gnumake -j30" (and plenty of swap space).
1.25	18-Oct-2001	rearnsha	Fix pmap_vac_me_harder to take into account pages that are mapped into both kernel and user space. Fixes port-arm32/13998.
1.24	29-Sep-2001	chris	Add a couple of simplelocks to make sure we call pagealloc with the uvm_object locked. Found while running a LOCKDEBUG kernel on cats.
1.23	15-Sep-2001	chs	a whole bunch of changes to improve performance and robustness under load: - remove special treatment of pager_map mappings in pmaps. this is required now, since I've removed the globals that expose the address range. pager_map now uses pmap_kenter_pa() instead of pmap_enter(), so there's no longer any need to special-case it. - eliminate struct uvm_vnode by moving its fields into struct vnode. - rewrite the pageout path. the pager is now responsible for handling the high-level requests instead of only getting control after a bunch of work has already been done on its behalf. this will allow us to UBCify LFS, which needs tighter control over its pages than other filesystems do. writing a page to disk no longer requires making it read-only, which allows us to write wired pages without causing all kinds of havoc. - use a new PG_PAGEOUT flag to indicate that a page should be freed on behalf of the pagedaemon when it's unlocked. this flag is very similar to PG_RELEASED, but unlike PG_RELEASED, PG_PAGEOUT can be cleared if the pageout fails due to eg. an indirect-block buffer being locked. this allows us to remove the "version" field from struct vm_page, and together with shrinking "loan_count" from 32 bits to 16, struct vm_page is now 4 bytes smaller. - no longer use PG_RELEASED for swap-backed pages. if the page is busy because it's being paged out, we can't release the swap slot to be reallocated until that write is complete, but unlike with vnodes we don't keep a count of in-progress writes so there's no good way to know when the write is done. instead, when we need to free a busy swap-backed page, just sleep until we can get it busy ourselves. - implement a fast-path for extending writes which allows us to avoid zeroing new pages. this substantially reduces cpu usage. - encapsulate the data used by the genfs code in a struct genfs_node, which must be the first element of the filesystem-specific vnode data for filesystems which use genfs_{get,put}pages(). - eliminate many of the UVM pagerops, since they aren't needed anymore now that the pager "put" operation is a higher-level operation. - enhance the genfs code to allow NFS to use the genfs_{get,put}pages instead of a modified copy. - clean up struct vnode by removing all the fields that used to be used by the vfs_cluster.c code (which we don't use anymore with UBC). - remove kmem_object and mb_object since they were useless. instead of allocating pages to these objects, we now just allocate pages with no object. such pages are mapped in the kernel until they are freed, so we can use the mapping to find the page to free it. this allows us to remove splvm() protection in several places. The sum of all these changes improves write throughput on my decstation 5000/200 to within 1% of the rate of NetBSD 1.5 and reduces the elapsed time for "make release" of a NetBSD 1.5 source tree on my 128MB pc to 10% less than a 1.5 kernel took.
1.22	13-Sep-2001	chris	Sprinkle some static and inline into a couple of functions. Remove dead entries from pmap.h.
1.21	13-Sep-2001	chris	Update pmap_clearbit to flush the cache if the area is being made readonly. Also only do this and the tlb flush if the pmap is the current pmap.
1.20	10-Sep-2001	chris	Update the pmap following some comments from Chuck Silvers: Remove some overzealous locking of HEAD_TO_MAP Remove a potential deadlock in pmap_copy_page Change alloc and free l1pt to use kenter/kremove. Update pmap_map to use kenter (only actually used by dumpsys, so no matching kremove)
1.19	10-Sep-2001	chris	Update pmap_update to now take the updated pmap as an argument. This will allow improvements to the pmaps so that they can more easily defer expensive operations, eg tlb/cache flush, til the last possible moment. Currently this is a no-op on most platforms, so they should see no difference. Reviewed by Jason.
1.18	11-Aug-2001	chris	branches: 1.18.2; Fix compile without DIAGNOSTICs enabled
1.17	11-Aug-2001	chris	Checking a whole host of pmap changes: Improved locking (not that we actually use it on a uniprocessor, but one day :) Removed unneeded splvm's tweaked pmap_clean_page code to only flush the cache if the page is mapped in the current pmap (based on diff from richard E) Adopted pv entry allocation mechanism from i386. Laid framework for returning ptp's when we've finished with them rather than holding onto them till the process exits. ptp's are now allocated with a uvm object for the pmap, means that we can walk a list to free them off in pmap_release, until they get freed off by pmap_remove. Also implemented a page zeroing function when the processor is idling. Note that hpcarm may wish to disable this. I believe this code to be stable, if anyone has any problems please shout up.
1.16	29-Jul-2001	chris	Rework the pmap_release code to not have to walk the ptpt, it now uses a uvm_object to track the allocated vm_pages, this means it can free off the entries in the uvm_object. Testing shows that it's about 5% faster on the make configure step for gmake.
1.15	28-Jul-2001	chris	A couple of tidy ups to pmap: pmap_t -> struct pmap * in pmap.c and pmap.h kernel_pmap -> pmap_kernel() everywhere. Compiled and booted on riscpc and cats.
1.14	08-Jul-2001	chs	branches: 1.14.2; clean up pmap_k{enter_pa,remove}(): a page is allowed to be mapped normally when k-mapped. use UVM_PGA_ZERO to get zeroed pages rather than zeroing here.
1.13	06-Jul-2001	chris	Implement proper versions of kenter_pa and kremove, I've based them on versions provided by Richard E.
1.12	25-Jun-2001	chris	Improve the vac_me_harder function, it is now slightly faster, however pmap_enter_pv is also now slightly slower, so they appear to balance out. Note that I've some ideas in the works on how to improve the pv handling, so the slow down is short term only. Also added non-advertising licence and copyright to myself and richard.
1.11	24-Jun-2001	chris	Add a pmap_map_ptes function to map another process page table entries into the current pmap (similair to pmap_pte) but this allows multiple use of it, rather than repeated calls of pmap_pte for pte, map_ptes returns a pointer to the va where the entries were mapped so it can be reused ptes can be found by indexing into it. Update some of the functions that use pmap_pte to pmap_map_ptes. Note that there's a dummy macro for pmap_unmap_ptes, this is because at some point locking will be needed, so we need to be able to unlock them. Performance gain seems to be minimal, however long term it should help improve things. This is similair to the i386 pmap_map_ptes, however it's based on a version from Richard Earnshaw.
1.10	22-Jun-2001	chris	Use a pool to store pmap structs.
1.9	26-May-2001	chs	replace vm_page_t with struct vm_page *.
1.8	25-Apr-2001	thorpej	Garbage-collect pmap_page_index().
1.7	24-Apr-2001	thorpej	Sprinkle pmap_update() calls after calls to: - pmap_enter() - pmap_remove() - pmap_protect() - pmap_kenter_pa() - pmap_kremove() as described in pmap(9). These calls are relatively conservative. It may be possible to optimize these a little more.
1.6	22-Apr-2001	thorpej	Remove pmap_kenter_pgs(). It was never really adopted by anything, and the interface itself wasn't as flexible as callers would have probably liked.
1.5	20-Apr-2001	toshii	In pmap_allocpagedir(), check if uvm_km_zalloc of ptpt is successful, and handle alloc failure case.
1.4	15-Mar-2001	chs	eliminate the KERN_* error codes in favor of the traditional E* codes. the mapping is: KERN_SUCCESS 0 KERN_INVALID_ADDRESS EFAULT KERN_PROTECTION_FAILURE EACCES KERN_NO_SPACE ENOMEM KERN_INVALID_ARGUMENT EINVAL KERN_FAILURE various, mostly turn into KASSERTs KERN_RESOURCE_SHORTAGE ENOMEM KERN_NOT_RECEIVER <unused> KERN_NO_ACCESS <unused> KERN_PAGES_LOCKED <unused>
1.3	04-Mar-2001	matt	branches: 1.3.2; 1.3.4; more vm_offset_t/vm_size_t -> {p,v}{addr,size}_t changes move pmap_* declarations to pmap.h. fix conflicts this exposed (e.g different definitions for pmap_bootstrap).
1.2	04-Mar-2001	matt	Convert some vm_size_t to vsize_t/psize_t. Change vaddr_t to paddr_t where appropriate.
1.1	04-Mar-2001	matt	Move from arm32/arm32. s/vm_offset_t/vaddr_t/g
1.3.4.4	23-Apr-2001	bouyer	Sync with HEAD.
1.3.4.3	27-Mar-2001	bouyer	Sync with HEAD.
1.3.4.2	12-Mar-2001	bouyer	Sync with HEAD.
1.3.4.1	04-Mar-2001	bouyer	file pmap.c was added on branch thorpej_scsipi on 2001-03-12 13:27:20 +0000
1.3.2.2	21-Jun-2001	nathanw	Catch up to -current.
1.3.2.1	09-Apr-2001	nathanw	Catch up with -current.
1.14.2.9	10-Oct-2002	jdolecek	sync kqueue with -current; this includes merge of gehenna-devsw branch, merge of i386 MP branch, and part of autoconf rototil work
1.14.2.8	06-Sep-2002	jdolecek	sync kqueue branch with HEAD
1.14.2.7	23-Jun-2002	jdolecek	catch up with -current on kqueue branch
1.14.2.6	16-Mar-2002	jdolecek	Catch up with -current.
1.14.2.5	11-Feb-2002	jdolecek	Sync w/ -current.
1.14.2.4	10-Jan-2002	thorpej	Sync kqueue branch with -current.
1.14.2.3	13-Sep-2001	thorpej	Update the kqueue branch to HEAD.
1.14.2.2	25-Aug-2001	thorpej	Merge Aug 24 -current into the kqueue branch.
1.14.2.1	03-Aug-2001	lukem	update to -current
1.18.2.1	01-Oct-2001	fvdl	Catch up with -current.
1.28.2.1	12-Nov-2001	thorpej	Sync the thorpej-mips-cache branch with -current.
1.30.2.19	11-Dec-2002	thorpej	Sync with HEAD.
1.30.2.18	11-Nov-2002	nathanw	Catch up to -current
1.30.2.17	18-Oct-2002	nathanw	Catch up to -current.
1.30.2.16	17-Sep-2002	nathanw	Catch up to -current.
1.30.2.15	28-Aug-2002	wrstuden	There is no 'p', there is only 'l'.
1.30.2.14	27-Aug-2002	thorpej	Sync with -current.
1.30.2.13	13-Aug-2002	thorpej	From trunk: Add the brutal hack that allows us to limp along using the read/write cache line allocation policy on XScale CPUs: in pmap_enter(), if the pmap is the kernel pmap, clear the X-bit in the PTE, thus disabling read/write-allocate for managed kernel mappings. Yes, this is ugly. But it makes userland code run with r/w-allocate, which is a huge improvement on systems with low core memory performance.
1.30.2.12	13-Aug-2002	nathanw	Catch up to -current.
1.30.2.11	01-Aug-2002	nathanw	Catch up to -current.
1.30.2.10	02-Jul-2002	nathanw	Several curlwp references here can revert to curproc.
1.30.2.9	24-Jun-2002	nathanw	Curproc->curlwp renaming. Change uses of "curproc->l_proc" back to "curproc", which is more like the original use. Bare uses of "curproc" are now "curlwp". "curproc" is now #defined in proc.h as ((curlwp) ? (curlwp)->l_proc) : NULL) so that it is always safe to reference curproc (dereferencing curproc is another story, but that's always been true).
1.30.2.8	20-Jun-2002	nathanw	Catch up to -current.
1.30.2.7	17-Apr-2002	nathanw	Catch up to -current.
1.30.2.6	01-Apr-2002	nathanw	Catch up to -current. (CVS: It's not just a program. It's an adventure!)
1.30.2.5	28-Feb-2002	nathanw	Catch up to -current.
1.30.2.4	11-Jan-2002	nathanw	More catchup.
1.30.2.3	08-Jan-2002	nathanw	Catch up to -current.
1.30.2.2	15-Nov-2001	thorpej	Machine-dependent kernel mods for scheduler activations on 32-bit ARM processors. Kernel boots multi-user on an XScale, but upcalls not yet tested.
1.30.2.1	03-Nov-2001	thorpej	file pmap.c was added on branch nathanw_sa on 2001-11-15 06:39:22 +0000
1.97.4.6	14-Feb-2003	he	Revert pull-up of revision 1.110 (requested by rearnsha in ticket #1170): Revert cached memory access to L1 tables, this causes instability on the release branch.
1.97.4.5	07-Dec-2002	he	Pull up revision 1.111 (requested by thorpej in ticket #714): Use a pool cache for PT-PTs.
1.97.4.4	07-Dec-2002	he	Pull up revision 1.105 (requested by thorpej in ticket #714): Add code, conditional on PMAP_ALIAS_DEBUG, which can be used to hunt for virtual aliases between managed (pmap_enter) and unmanaged (pmap_kenter_pa) mappings.
1.97.4.3	21-Nov-2002	he	Pull up revision 1.110 (requested by thorpej in ticket #712): Do cached memory access to L1 tables, making sure to write-back the cache after any L1 table modifications.
1.97.4.2	16-Nov-2002	he	Pull up revision 1.107 (requested by thorpej in ticket #662): Clean up some warts in pmap_protect().
1.97.4.1	31-Jul-2002	lukem	Pull up revision 1.100 (requested by thorpej in ticket #587): Don't use pmap_kenter_pa() in pmap_map(); doing so causes an assertion failure in pmap_kenter_pa().
1.97.2.2	30-Aug-2002	gehenna	catch up with -current.
1.97.2.1	14-Jul-2002	gehenna	catch up with -current.
1.137.2.7	11-Dec-2005	christos	Sync with head.
1.137.2.6	10-Nov-2005	skrll	Sync with HEAD. Here we go again...
1.137.2.5	01-Apr-2005	skrll	Sync with HEAD.
1.137.2.4	17-Jan-2005	skrll	Sync with HEAD.
1.137.2.3	21-Sep-2004	skrll	Fix the sync with head I botched.
1.137.2.2	18-Sep-2004	skrll	Sync with HEAD.
1.137.2.1	03-Aug-2004	skrll	Sync with HEAD
1.150.4.1	28-Jan-2005	yamt	convert arch/arm to new apis.
1.150.2.1	29-Apr-2005	kent	sync with -current
1.154.2.6	21-Jan-2008	yamt	sync with head
1.154.2.5	15-Nov-2007	yamt	sync with head.
1.154.2.4	27-Oct-2007	yamt	sync with head.
1.154.2.3	03-Sep-2007	yamt	sync with head.
1.154.2.2	26-Feb-2007	yamt	sync with head.
1.154.2.1	21-Jun-2006	yamt	sync with head.
1.157.24.1	21-Feb-2007	snj	branches: 1.157.24.1.4; Pull up following revision(s) (requested by matt in ticket #457): sys/arch/arm/arm32/pmap.c: revision 1.158 From Scott Allan in http://mail-index.netbsd.org/port-arm/2006/07/26/0000.html I ran into a problem when I tried to set up a mapping that started at virtual address 0xFFF00000 and was 0x00100000 long. In other words, the mapping should have gone to the end of the 32 bit address space. The mapping was made with no problem, but pmap_devmap_find_va() wouldn't find an address within the mapping. For example, if I told it to find a mapping for 0x1000 bytes at 0xFFF01000, it would try to make sure that 0xFFF01000 was greater than 0xFFF00000 and that (0xFFF01000+0x1000) was less than (0xFFF00000 +0x00100000). However, that last expression (0xFFF00000+0x00100000) wrapped around to be simply 0x00000000 so it wasn't found. This patch fixes this problem in pmap_devmap_find_va() and pmap_devmap_find_pa() by subtracting one off of the
1.157.24.1.4.3	10-Nov-2007	matt	Refix thinko. (deal with non-page-aligned starts/lengths)
1.157.24.1.4.2	10-Nov-2007	matt	Fix thinko.
1.157.24.1.4.1	10-Nov-2007	matt	Add AT91 support from Sami Kantoluoto Add TI OMAP2430 support from Marty Fouts @ Danger Inc
1.157.20.1	12-Jan-2007	ad	Sync with head.
1.158.2.5	15-Apr-2007	yamt	sync with head.
1.158.2.4	29-Mar-2007	skrll	Adapt arm32. Thanks to scw for helping out. Tested on my cats (SA1) XXX hydra should die. i've made some changes, but no guarantees.
1.158.2.3	24-Mar-2007	yamt	sync with head.
1.158.2.2	12-Mar-2007	rmind	Sync with HEAD.
1.158.2.1	27-Feb-2007	yamt	- sync with head. - move sched_changepri back to kern_synch.c as it doesn't know PPQ anymore.
1.161.2.6	03-Dec-2007	ad	Sync with HEAD.
1.161.2.5	19-Oct-2007	ad	Sync with head.
1.161.2.4	09-Oct-2007	ad	Sync with head.
1.161.2.3	27-May-2007	ad	Sync with head.
1.161.2.2	10-Apr-2007	ad	Sync with head.
1.161.2.1	13-Mar-2007	ad	Sync with head.
1.162.2.1	11-Jul-2007	mjf	Sync with head.
1.163.4.3	16-Oct-2007	garbled	Sync with HEAD
1.163.4.2	03-Oct-2007	garbled	Sync with HEAD
1.163.4.1	22-May-2007	matt	Update to HEAD.
1.164.12.10	04-Mar-2008	matt	Fix a bug in pmap_flush_page which could nuke a PTE being used by pmap_zero_page or pmap_copy_page.
1.164.12.9	09-Jan-2008	matt	sync with HEAD
1.164.12.8	10-Nov-2007	matt	Fix thinko. (need to deal non-page-aligned size/lengths)
1.164.12.7	09-Nov-2007	matt	Add pmap_icache_sync_range and change arm32_sync_icache to use it. This will only invalidate va that have valid PTEs. This avoids cleaning unneeded cache lines.
1.164.12.6	09-Nov-2007	matt	Make all the evbarm kernels build again. Fix lossage from rebase.
1.164.12.5	08-Nov-2007	matt	sync with -HEAD
1.164.12.4	07-Nov-2007	matt	Fix botched color assertion
1.164.12.3	06-Nov-2007	matt	sync with HEAD
1.164.12.2	12-Oct-2007	matt	Import TI OMAP 2430 and ARM11/ARMv6 support. Now on ARMv6, the cache is no longer purged on context switches.
1.164.12.1	29-Aug-2007	matt	Use ci_intr_depth
1.164.10.2	20-Jan-2008	chris	Sync to HEAD.
1.164.10.1	01-Jan-2008	chris	Sync with HEAD.
1.164.8.3	11-Nov-2007	joerg	Sync with HEAD.
1.164.8.2	26-Oct-2007	joerg	Sync with HEAD. Follow the merge of pmap.c on i386 and amd64 and move pmap_init_tmp_pgtbl into arch/x86/x86/pmap.c. Modify the ACPI wakeup code to restore CR4 before jumping back into kernel space as the large page option might cover that.
1.164.8.1	02-Oct-2007	joerg	Sync with HEAD.
1.164.6.3	28-Feb-2008	rjs	Sync with HEAD.
1.164.6.2	26-Dec-2007	rjs	Sync with HEAD.
1.164.6.1	01-Nov-2007	rjs	Sync with HEAD.
1.165.2.1	14-Oct-2007	yamt	sync with head.
1.166.2.1	13-Nov-2007	bouyer	Sync with HEAD
1.167.2.2	18-Feb-2008	mjf	Sync with HEAD.
1.167.2.1	19-Nov-2007	mjf	Sync with HEAD.
1.169.6.2	08-Jan-2008	bouyer	Sync with HEAD
1.169.6.1	02-Jan-2008	bouyer	Sync with HEAD
1.171.6.7	17-Jan-2009	mjf	Sync with HEAD.
1.171.6.6	05-Oct-2008	mjf	Sync with HEAD.
1.171.6.5	28-Sep-2008	mjf	Sync with HEAD.
1.171.6.4	29-Jun-2008	mjf	Sync with HEAD.
1.171.6.3	05-Jun-2008	mjf	Sync with HEAD. Also fix build.
1.171.6.2	02-Jun-2008	mjf	Sync with HEAD.
1.171.6.1	03-Apr-2008	mjf	Sync with HEAD.
1.172.2.2	17-Jun-2008	yamt	sync with head.
1.172.2.1	18-May-2008	yamt	sync with head.
1.173.2.4	11-Aug-2010	yamt	sync with head.
1.173.2.3	11-Mar-2010	yamt	sync with head
1.173.2.2	04-May-2009	yamt	sync with head.
1.173.2.1	16-May-2008	yamt	sync with head.
1.175.2.3	10-Oct-2008	skrll	Sync with HEAD.
1.175.2.2	18-Sep-2008	wrstuden	Sync with wrstuden-revivesa-base-2.
1.175.2.1	23-Jun-2008	wrstuden	Sync w/ -current. 34 merge conflicts to follow.
1.176.2.4	18-Jul-2008	simonb	Sync with head.
1.176.2.3	03-Jul-2008	simonb	Sync with head.
1.176.2.2	27-Jun-2008	simonb	Sync with head.
1.176.2.1	18-Jun-2008	simonb	Sync with head.
1.180.2.2	13-Dec-2008	haad	Update haad-dm branch to haad-dm-base2.
1.180.2.1	19-Oct-2008	haad	Sync with HEAD.
1.187.8.2	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.187.8.1	21-Apr-2010	matt	sync to netbsd-5
1.187.4.1	03-Dec-2009	sborrill	Pull up the following revisions(s) (requested by scw in ticket #1168): sys/arch/arm/arm32/pmap.c: revision 1.203 Work-around a possible process exit corner case which can leave stale data in the cache after a context-switch. Addresses kern/41058.
1.187.2.2	28-Apr-2009	skrll	Sync with HEAD.
1.187.2.1	19-Jan-2009	skrll	Sync with HEAD.
1.195.2.1	13-May-2009	jym	Sync with HEAD. Commit is split, to avoid a "too many arguments" protocol error.
1.211.2.23	15-Nov-2010	uebayasi	Revert xmd(4).
1.211.2.22	10-Nov-2010	uebayasi	Fix thinko; make vm_physseg ptr swap really work.
1.211.2.21	10-Nov-2010	uebayasi	opt_xip.h isn't needed any more here.
1.211.2.20	10-Nov-2010	uebayasi	Always use VM_PHYSMEM_PTR().
1.211.2.19	06-Nov-2010	uebayasi	Sync with HEAD.
1.211.2.18	31-Oct-2010	uebayasi	We already have a flag PMAP_NOCACHE. s/PMAP_UNMANAGED/PMAN_NOCACHE/. Pointed out by Chuck Silvers, thanks.
1.211.2.17	31-Oct-2010	uebayasi	More struct vm_page * -> struct vm_page_md * adjustments.
1.211.2.16	30-Oct-2010	uebayasi	Implement pmap_physload_device(9) to replace xmd(4) MD backend. Implement pmap_mmap(9) and use it from mem(4) and xmd(4).
1.211.2.15	17-Aug-2010	uebayasi	Sync with HEAD.
1.211.2.14	07-Jul-2010	uebayasi	Clean up; merge options DIRECT_PAGE into options XIP.
1.211.2.13	31-May-2010	uebayasi	Re-define the definition of "device page"; device pages are pages of device memory. Pages which don't have vm_page (== can't be used for generic use), but whose PV are tracked, are called "direct pages" from now.
1.211.2.12	30-Apr-2010	uebayasi	Sync with HEAD.
1.211.2.11	28-Apr-2010	uebayasi	Always use struct vm_physseg *vm_physmem_ptrs[] in MD code.
1.211.2.10	27-Apr-2010	uebayasi	Support PMAP_UNMANAGED in some pmaps. (Others should be converted eventually, but no problem while managed device page is not used.)
1.211.2.9	25-Feb-2010	uebayasi	A few more VM_PAGE_TO_MD().
1.211.2.8	20-Feb-2010	uebayasi	Fix \!DIAGNOSTIC build.
1.211.2.7	10-Feb-2010	uebayasi	Adjust previous.
1.211.2.6	10-Feb-2010	uebayasi	Replace all remaining pg->mdpage references with VM_PAGE_TO_MD(). Now struct vm_page * is fully opaque.
1.211.2.5	10-Feb-2010	uebayasi	Fix previous again & use VM_PAGE_TO_MD() where appropriate.
1.211.2.4	10-Feb-2010	uebayasi	Convert pmap_enter() and pmap_vac_me_harder().
1.211.2.3	10-Feb-2010	uebayasi	Convert pmap_enter_pv().
1.211.2.2	10-Feb-2010	uebayasi	Convert pmap_remove_pv() / pmap_modify_pv() to take struct vm_page_md *.
1.211.2.1	10-Feb-2010	uebayasi	Start changing this to be ready for device page (XIP). The basic rule is device pages don't have struct vm_page * objects. Instead per-page data (mainly PV mappings) is rooted from the global struct vm_page_md array. Convert 2 functions to take struct vm_page_md * instead of struct vm_page *.
1.212.2.6	19-May-2011	rmind	Implement sharing of vnode_t::v_interlock amongst vnodes: - Lock is shared amongst UVM objects using uvm_obj_setlock() or getnewvnode(). - Adjust vnode cache to handle unsharing, add VI_LOCKSHARE flag for that. - Use sharing in tmpfs and layerfs for underlying object. - Simplify locking in ubc_fault(). - Sprinkle some asserts. Discussed with ad@.
1.212.2.5	21-Apr-2011	rmind	sync with head
1.212.2.4	05-Mar-2011	rmind	sync with head
1.212.2.3	03-Jul-2010	rmind	sync with head
1.212.2.2	30-May-2010	rmind	sync with head
1.212.2.1	16-Mar-2010	rmind	Change struct uvm_object::vmobjlock to be dynamically allocated with mutex_obj_alloc(). It allows us to share the locks among UVM objects.
1.219.4.1	05-Mar-2011	bouyer	Sync with HEAD
1.219.2.1	06-Jun-2011	jruoho	Sync with HEAD.
1.221.2.1	23-Jun-2011	cherry	Catchup with rmind-uvmplock merge.
1.224.6.1	18-Feb-2012	mrg	merge to -current.
1.224.2.5	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.224.2.4	23-Jan-2013	yamt	sync with head
1.224.2.3	16-Jan-2013	yamt	sync with (a bit old) head
1.224.2.2	30-Oct-2012	yamt	sync with head
1.224.2.1	17-Apr-2012	yamt	sync with head
1.228.2.2	09-Feb-2013	riz	Pull up following revision(s) (requested by msaitoh in ticket #803):
1.251	01-Feb-2013	matt	cleanup PVF_WRITE & pvh_attrs interaction.
1.250	31-Jan-2013	skrll	Another typo in a comment.
1.249	31-Jan-2013	skrll	Typo in comment.
1.247	11-Jan-2013	matt	Fix a bug in pmap_modify_pv where we didnt set PVF_WRITE on a page after changing its mapping to writeable. Add more KASSERTS Dont go into DDB by default in pmap_fixup.
1.243	10-Dec-2012	matt	Change a KASSERT to a KASSERTMSG
1.233	29-Aug-2012	matt	Support PMAP_NOCACHE in pmap_kenter_pa
1.232	29-Aug-2012	matt	Use the correct prot mask in vector_page_setprot
1.228.2.1	09-Aug-2012	jdc	branches: 1.228.2.1.2; Pull up revisions: src/sys/arch/evbarm/dev/plcomreg.h revisions 1.2,1.3,1.4 src/sys/arch/evbarm/conf/INTEGRATOR revision 1.65 src/sys/arch/evbarm/dev/plcom.c revisions 1.34,1.35,1.36,1.37,1.38,1.39,1.40 src/sys/arch/evbarm/ifpga/plcom_ifpga.c revisions 1.12,1.13,1.14 src/sys/arch/evbarm/dev/plcomvar.h revisions 1.9,1.10,1.11 src/sys/arch/evbarm/ifpga/plcom_ifpgavar.h revision 1.2 src/sys/arch/arm/arm/cpufunc.c revisions 1.105,1.108 src/sys/arch/arm/arm32/cpu.c revision 1.79 src/sys/arch/arm/include/armreg.h revisions 1.49,1.54 src/sys/arch/arm/arm32/pmap.c revision 1.229 src/sys/arch/arm/arm32/arm32_machdep.c revision 1.77 src/sys/arch/arm/include/cpu.h revision 1.64 src/sys/arch/arm/arm/cpufunc_asm_arm1136.S revision 1.3 src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S revision 1.1 src/sys/arch/arm/conf/files.arm revision 1.106 src/sys/arch/arm/include/cpufunc.h revision 1.57 src/sys/dev/sdmmc/sdhc.c revisions 1.14,1.24 src/sys/dev/sdmmc/sdhcvar.h revisions 1.7,1.8 src/sys/arch/evbarm/ifpga/ifpgareg.h revision 1.4 src/sys/arch/evbarm/integrator/integrator_machdep.c revision 1.69 src/sys/arch/arm/broadcom/bcm2835_dma.c revision 1.1 src/sys/arch/arm/broadcom/bcm2835_emmc.c revision 1.1 src/sys/arch/arm/broadcom/bcm2835_intr.c revision 1.1 src/sys/arch/arm/broadcom/bcm2835_intr.h revision 1.1 src/sys/arch/arm/broadcom/bcm2835_obio.c revision 1.1 src/sys/arch/arm/broadcom/bcm2835_plcom.c revision 1.1 src/sys/arch/arm/broadcom/bcm2835_pm.c revision 1.1 src/sys/arch/arm/broadcom/bcm2835_pmvar.h revision 1.1 src/sys/arch/arm/broadcom/bcm2835_space.c revision 1.1 src/sys/arch/arm/broadcom/bcm2835_tmr.c revision 1.1 src/sys/arch/arm/broadcom/bcm2835reg.h revision 1.1 src/sys/arch/arm/broadcom/bcm2835var.h revision 1.1 src/sys/arch/arm/broadcom/bcm_amba.h revision 1.1 src/sys/arch/arm/broadcom/files.bcm2835 revision 1.1 src/sys/arch/evbarm/Makefile revision 1.9 src/sys/arch/evbarm/conf/RPI revision 1.1 src/sys/arch/evbarm/conf/files.rpi revision 1.1 src/sys/arch/evbarm/conf/mk.rpi revision 1.1 src/sys/arch/evbarm/conf/std.rpi revision 1.1 src/sys/arch/evbarm/rpi/genassym.cf revision 1.1 src/sys/arch/evbarm/rpi/rpi.h revision 1.1 src/sys/arch/evbarm/rpi/rpi_machdep.c revision 1.1 src/sys/arch/evbarm/rpi/rpi_start.S revision 1.1,1.2 src/etc/etc.evbarm/Makefile.inc revision 1.28 (requested by skrll in ticket #454). don't mix #define<TAB> and #define<SPACE> in a file. avoid warning with options PLCOM_DEBUG for INTEGRATOR. Rename register values. No functional change - same code before and after. Existing names are prefixed with PL01X_ where they're common between the PL010 and the PL011. The PL010_/PL011_ prefixes are added where they're found only on the respective chips. Replace the simple_lock with a kmutex_t. Update the locking to match com(4) in the few places it didn't already. DOH. Replace a line that got accidently deleted in the last commit. device_t/softc split struct device * -> device_t struct cfdata * -> cfdata_t Add the 'Z' to the 1176 cpu product name. ok matt@ Fix locking botch introduced in 1.36. Fix a KASSERT. From/OK'ed by matt@ Fix racy softint dispatch that lead to KASSERT(si->si_active) in softint_execute Discussed with matt@. "Looks good to me" Add the documented ARM11[37]6 Auxiliary control register defines. Add support for the ARM1176JZS Add a flag for the lack of LED_ON in HOST_CTL (ti omap3 doesn't do that). Provide a method for attachments to specify capabilites. Add support for the PL011 to plcom. Pull across a bunch of fixes from com(4) while I'm here and do some other tidyup. Tested on a RaspberryPi. PL010 not tested. Initial commit of support for the RaspberryPI (www.raspberrypi.org) This is enough for serial console via the gpio header pins and to get to multiuser. A huge thank you to Matt Thomas for all his help. Add RPI to KERNEL_SETS Remove #if 0 code.
1.228.2.1.2.3	13-Feb-2013	matt	Sync with HEAD
1.228.2.1.2.2	07-Feb-2013	matt	pullup pmap changes from HEAD
1.228.2.1.2.1	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.236.2.5	03-Dec-2017	jdolecek	update from HEAD
1.236.2.4	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.236.2.3	23-Jun-2013	tls	resync from head
1.236.2.2	25-Feb-2013	tls	resync with head
1.236.2.1	20-Nov-2012	tls	Resync to 2012-11-19 00:00:00 UTC
1.257.2.2	18-May-2014	rmind	sync with head
1.257.2.1	28-Aug-2013	rmind	sync with head
1.280.2.1	10-Aug-2014	tls	Rebase.
1.295.2.11	03-Jun-2017	snj	Pull up following revision(s) (requested by skrll in ticket #1424): sys/arch/arm/arm32/pmap.c: revision 1.345 Perform icache syncs for ARM_MMU_EXTENDED as well. This helps the PT_STEP code in pr/52119 and probably other things.
1.295.2.10	11-Mar-2017	snj	fix fallout from ticket #1366: __nothing is nothing on netbsd-7
1.295.2.9	11-Mar-2017	snj	Pull up following revision(s) (requested by skrll in ticket #1366): sys/arch/arm/include/arm32/pmap.h: 1.145 sys/arch/arm/arm32/pmap.c: 1.343, 1.344 sys/arch/evbarm/gumstix/gumstix_machdep.c: 1.58 via patch Fixup the compile time decisions around PMAP_{INCLUDE,NEEDS}_PTE_SYNC and fix the options for xscale boards which require the code in pmap_l2ptp_ctor marked as #ifndef PMAP_INCLUDE_PTE_SYNC. Fix the typo (pte -> opte) in this code block and consistently use opte elsewhere. PR/51990: Regression data_abort_handler: data_aborts fsr=0x406 far=0xbfffeff5 on copyout in init -- fix unused. -- Set xscale_cache_clean_addr appropriately and re-arrange default KVA layout to allow direct map for all boards. OVERO/DUOVERO/PEPPER aren't tested. PR/52010: Regression: Gumstix Verdex is hanging in enabling cache + KASSERT ram_size
1.295.2.8	26-Feb-2016	snj	branches: 1.295.2.8.2; Pull up following revision(s) (requested by skrll in ticket #1106): sys/arch/arm/arm32/pmap.c: revision 1.332 Delete pmap_pmaps and its only user pmap_dump_all. The list wasn't being updated in an MP-safe manner.
1.295.2.7	27-May-2015	msaitoh	Pull up following revision(s) (requested by skrll in ticket #805): sys/arch/arm/include/arm32/pmap.h: revision 1.138 sys/arch/arm/arm/cpufunc.c: revision 1.151 sys/arch/arm/arm32/bus_dma.c: revision 1.90 sys/arch/arm/broadcom/bcm53xx_pax.c: revision 1.14 sys/arch/arm/arm32/bus_dma.c: revision 1.91 sys/arch/arm/samsung/exynos_space.c: revision 1.2 sys/arch/arm/arm32/db_machdep.c: revision 1.23 sys/arch/arm/allwinner/awin_space.c: revision 1.4 sys/arch/arm/include/rwlock.h: revision 1.9 sys/arch/arm/amlogic/amlogic_space.c: revision 1.2 sys/arch/arm/zynq/zynq_space.c: revision 1.2 sys/arch/arm/broadcom/bcm2835_space.c: revision 1.7 sys/arch/arm/arm32/pmap.c: revision 1.317 sys/arch/arm/include/locore.h: revision 1.19 sys/arch/arm/include/mutex.h: revision 1.20 sys/arch/arm/include/lock.h: revision 1.31 sys/arch/arm/include/lock.h: revision 1.32 sys/arch/arm/broadcom/bcmgen_space.c: revision 1.5 - Kill redundant semicolons. - Indentation. - Improve inline asm around dsb/dmb/isb: - always use volatile and mark them as memory barrier - use the common version from locore.h in all places not included from userland
1.295.2.6	26-May-2015	msaitoh	Pull up following revision(s) (requested by skrll in ticket #800): sys/arch/arm/arm32/pmap.c: revision 1.320 sys/arch/arm/arm32/pmap.c: revision 1.321 sys/arch/arm/arm32/pmap.c: revision 1.322 sys/arch/arm/arm32/pmap.c: revision 1.319 - include "opt_arm_debug.h" for VERBOSE_INIT_ARM - Add pmap locking to pmap_kenter_pa/kremove - Make sure nptes is a multiple of PAGE_SIZE / L2_S_SIZE. - Use PDE_SYNC when syncing pdeps
1.295.2.5	19-May-2015	snj	Pull up following revision(s) (requested by joerg in ticket #777): sys/arch/arm/arm32/pmap.c: revision 1.308 pmap_tlb_flushD is for !ARM_MMU_EXTENDED only now
1.295.2.4	10-Apr-2015	snj	Pull up following revision(s) (requested by skrll in ticket #669): sys/arch/arm/arm32/pmap.c: revision 1.318 Fix two bugs. pmap_is_cached fix for MULTIPROCESSOR (not just ASID on local cpu -> any valid ASID on any cpu). pmap_deactivate: update curcpu()->ci_pmap_cur_asid to KERNEL_PID too.
1.295.2.3	10-Nov-2014	martin	Pull up following revision(s) (requested by skrll in ticket #209): sys/arch/arm/pic/pic.c: revision 1.25 sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.21 sys/arch/arm/arm32/pmap.c: revision 1.312 sys/arch/arm/arm32/bus_dma.c: revision 1.89 sys/arch/arm/arm32/pmap.c: revision 1.313 sys/arch/arm/arm32/pmap.c: revision 1.314 sys/arch/arm/arm32/pmap.c: revision 1.315 sys/arch/arm/arm32/pmap.c: revision 1.316 Include opt_multiprocessor.h When allocing a l1page, if a page isn't available, use uvm_wait to wait for one to become available. Should fix PR/49364. Post a dmb before invalidating the cache in the post-{read,write} operations to ensure that any/all cachelines brought in via speculation are really flushed. Ensure all memory operations are complete by before wfi. For example, the cpu could have just been in uvm_pageidlezero. In pmap_fault_fixup re-instate the TLB flush for the shared L1 case that occurs for non-ARM_MMU_EXTENDED kernels. This fixes rump/rumpkern/t_sp:stress_killer on rpi which is currently non-ARM_MMU_EXTENDED Remove an unnecessary flush that sneaked in as part of break-before-make change. Remove an XXXNH comment. Update PTE_SYNC_CURRENT to add a dsb for armv7 - part of the break-before-make fix.
1.295.2.2	09-Nov-2014	martin	Pull up following revision(s) (requested by skrll in ticket #188): sys/arch/arm/include/arm32/pmap.h: revision 1.136 sys/arch/arm/include/armreg.h: revision 1.100 sys/arch/arm/cortex/gic.c: revision 1.11 sys/arch/arm/arm32/db_interface.c: revision 1.54 sys/arch/arm/include/armreg.h: revision 1.101 sys/arch/arm/cortex/gic.c: revision 1.12 sys/arch/arm/arm32/arm32_machdep.c: revision 1.107 sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.19 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.20 sys/arch/evbarm/conf/BPI: revision 1.5 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.21 sys/arch/arm/arm32/pmap.c: revision 1.306 sys/arch/arm/arm32/db_machdep.c: revision 1.22 sys/arch/arm/arm32/arm32_tlb.c: revision 1.3 sys/arch/arm/arm/undefined.c: revision 1.55 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.22 sys/arch/arm/arm32/pmap.c: revision 1.307 sys/arch/arm/arm32/arm32_tlb.c: revision 1.4 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.23 sys/arch/arm/arm32/arm32_tlb.c: revision 1.5 sys/arch/evbarm/conf/BPI: revision 1.8 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.24 sys/arch/arm/arm32/arm32_tlb.c: revision 1.6 sys/arch/arm/arm32/arm32_tlb.c: revision 1.7 sys/arch/evbarm/conf/CUBIETRUCK: revision 1.5 sys/arch/arm/pic/pic.c: revision 1.23 sys/arch/arm/pic/pic.c: revision 1.24 sys/arch/arm/pic/picvar.h: revision 1.11 sys/arch/arm/arm/cpufunc_asm_armv7.S: revision 1.20 sys/arch/arm/mainbus/cpu_mainbus.c: revision 1.16 sys/arch/arm/arm32/pmap.c: revision 1.298 sys/arch/arm/arm/cpufunc_asm_arm11.S: revision 1.17 sys/arch/arm/arm/cpufunc_asm_pj4b.S: revision 1.5 sys/arch/arm/arm32/pmap.c: revision 1.310 sys/arch/arm/arm32/pmap.c: revision 1.311 sys/arch/arm/arm32/arm32_kvminit.c: revision 1.32 sys/arch/arm/cortex/a9_mpsubr.S: revision 1.19 sys/arch/arm/arm32/arm32_boot.c: revision 1.10 sys/arch/arm/arm/ast.c: revision 1.25 sys/arch/arm/include/armreg.h: revision 1.98 sys/uvm/pmap/pmap_tlb.c: revision 1.10 sys/arch/arm/arm32/arm32_boot.c: revision 1.8 sys/arch/arm/arm32/arm32_boot.c: revision 1.9 sys/arch/arm/arm/arm_machdep.c: revision 1.43 Various ARM MP fixes.
1.295.2.1	30-Oct-2014	martin	Pull up following revision(s) (requested by maxv in ticket #165): sys/arch/newsmips/stand/boot/netif_news.c: revision 1.9 sys/arch/mvme68k/stand/installboot/installboot.c: revision 1.19 sys/arch/arm/arm32/pmap.c: revision 1.300 sys/arch/amiga/dev/siop2.c: revision 1.43 sys/arch/amiga/amiga/disksubr.c: revision 1.62 sys/arch/news68k/news68k/bus_space.c: revision 1.13 sys/arch/amiga/dev/siop.c: revision 1.69 sys/arch/x86/x86/x86_autoconf.c: revision 1.72 Remove dead code in various places under arch/.
1.295.2.8.2.1	13-Mar-2017	skrll	Sync with netbsd-7-1-RELEASE
1.316.2.7	28-Aug-2017	skrll	Sync with HEAD
1.316.2.6	05-Feb-2017	skrll	Sync with HEAD
1.316.2.5	05-Oct-2016	skrll	Sync with HEAD
1.316.2.4	27-Dec-2015	skrll	Sync with HEAD (as of 26th Dec)
1.316.2.3	22-Sep-2015	skrll	Sync with HEAD
1.316.2.2	06-Jun-2015	skrll	Sync with HEAD
1.316.2.1	06-Apr-2015	skrll	Sync with HEAD
1.335.2.4	26-Apr-2017	pgoyette	Sync with HEAD
1.335.2.3	20-Mar-2017	pgoyette	Sync with HEAD
1.335.2.2	07-Jan-2017	pgoyette	Sync with HEAD. (Note that most of these changes are simply $NetBSD$ tag issues.)
1.335.2.1	06-Aug-2016	pgoyette	Sync with HEAD
1.342.2.1	21-Apr-2017	bouyer	Sync with HEAD
1.349.2.3	23-Apr-2019	martin	Pull up following revision(s) (requested by bouyer in ticket #1246): sys/arch/arm/arm32/pmap.c: revision 1.373 (via patch) Fix a deadlock between the pool and pmap codes: - cpu0 grabs the kernel lock (e.g. from a non-MPSAFE interrupt) and calls pool_get(). - cpu1 does a pool_get() on the same pool from MPSAFE code, which needs a pool_page_alloc(), which ends up in pmap_extract_coherency(). So cpu0 holds the kernel_lock and wants the pool lock. cpu1 holds the pool lock and wants the kernel_lock in pmap_extract_coherency(). The pmap code should not rely on kernel_lock. Intead make the pmap_kernel()->pm_obj_lock a IPL_VM lock and use it as pmap lock (thus dropping the pmap test pmap_{acquire,release}_pmap_lock()). This needs to be a IPL_VM because unlike user pmaps, this can be locked from interrupt context. Add a IPL_NONE lock for pmap_growkernel(). We can't use pmap_kernel()->pm_obj_lock here because pmap_grow_map() may sleep. Make pmap_lock (which may be locked with pm_obj_lock held) a IPL_VM lock in all case. reorder a few things to not call pool_get()/pool_put() (which may sleep) with pm_obj_lock held. Patch initially posted to port-arm@ on April 19, improved patch (per suggestions from Nick Hudson and Jason Thorpe) on April 21.
1.349.2.2	23-Apr-2019	martin	Pull up following revision(s) (requested by bouyer in ticket #1245): sys/arch/arm/arm32/pmap.c: revision 1.372 Don't try to aquire/release the pmap lock when in ddb. Avoids a deadlock when entering ddb, or on "mach cpu n" ddb command (the pmap lock may already be held by another CPU, which is halted when entering ddb). Posted to port-arm@ on April 19.
1.349.2.1	02-Nov-2017	snj	Pull up following revision(s) (requested by pgoyette in ticket #335): share/man/man9/kernhist.9: 1.5-1.8 sys/arch/acorn26/acorn26/pmap.c: 1.39 sys/arch/arm/arm32/fault.c: 1.105 via patch sys/arch/arm/arm32/pmap.c: 1.350, 1.359 sys/arch/arm/broadcom/bcm2835_bsc.c: 1.7 sys/arch/arm/omap/if_cpsw.c: 1.20 sys/arch/arm/omap/tiotg.c: 1.7 sys/arch/evbarm/conf/RPI2_INSTALL: 1.3 sys/dev/ic/sl811hs.c: 1.98 sys/dev/usb/ehci.c: 1.256 sys/dev/usb/if_axe.c: 1.83 sys/dev/usb/motg.c: 1.18 sys/dev/usb/ohci.c: 1.274 sys/dev/usb/ucom.c: 1.119 sys/dev/usb/uhci.c: 1.277 sys/dev/usb/uhub.c: 1.137 sys/dev/usb/umass.c: 1.160-1.162 sys/dev/usb/umass_quirks.c: 1.100 sys/dev/usb/umass_scsipi.c: 1.55 sys/dev/usb/usb.c: 1.168 sys/dev/usb/usb_mem.c: 1.70 sys/dev/usb/usb_subr.c: 1.221 sys/dev/usb/usbdi.c: 1.175 sys/dev/usb/usbdi_util.c: 1.67-1.70 sys/dev/usb/usbroothub.c: 1.3 sys/dev/usb/xhci.c: 1.75 sys/external/bsd/drm2/dist/drm/i915/i915_gem.c: 1.34 sys/kern/kern_history.c: 1.15 sys/kern/kern_xxx.c: 1.74 sys/kern/vfs_bio.c: 1.275-1.276 sys/miscfs/genfs/genfs_io.c: 1.71 sys/sys/kernhist.h: 1.21 sys/ufs/ffs/ffs_balloc.c: 1.63 sys/ufs/lfs/lfs_vfsops.c: 1.361 sys/ufs/lfs/ulfs_inode.c: 1.21 sys/ufs/lfs/ulfs_vnops.c: 1.52 sys/ufs/ufs/ufs_inode.c: 1.102 sys/ufs/ufs/ufs_vnops.c: 1.239 sys/uvm/pmap/pmap.c: 1.37-1.39 sys/uvm/pmap/pmap_tlb.c: 1.22 sys/uvm/uvm_amap.c: 1.108 sys/uvm/uvm_anon.c: 1.64 sys/uvm/uvm_aobj.c: 1.126 sys/uvm/uvm_bio.c: 1.91 sys/uvm/uvm_device.c: 1.66 sys/uvm/uvm_fault.c: 1.201 sys/uvm/uvm_km.c: 1.144 sys/uvm/uvm_loan.c: 1.85 sys/uvm/uvm_map.c: 1.353 sys/uvm/uvm_page.c: 1.194 sys/uvm/uvm_pager.c: 1.111 sys/uvm/uvm_pdaemon.c: 1.109 sys/uvm/uvm_swap.c: 1.175 sys/uvm/uvm_vnode.c: 1.103 usr.bin/vmstat/vmstat.c: 1.219 Reorder to test for null before null deref in debug code -- Reorder to test for null before null deref in debug code -- KNF -- No need for '\n' in UVMHIST_LOG -- normalise a BIOHIST log message -- Update the kernhist(9) kernel history code to address issues identified in PR kern/52639, as well as some general cleaning-up... (As proposed on tech-kern@ with additional changes and enhancements.) Details of changes: * All history arguments are now stored as uintmax_t values[1], both in the kernel and in the structures used for exporting the history data to userland via sysctl(9). This avoids problems on some architectures where passing a 64-bit (or larger) value to printf(3) can cause it to process the value as multiple arguments. (This can be particularly problematic when printf()'s format string is not a literal, since in that case the compiler cannot know how large each argument should be.) * Update the data structures used for exporting kernel history data to include a version number as well as the length of history arguments. * All [2] existing users of kernhist(9) have had their format strings updated. Each format specifier now includes an explicit length modifier 'j' to refer to numeric values of the size of uintmax_t. * All [2] existing users of kernhist(9) have had their format strings updated to replace uses of "%p" with "%#jx", and the pointer arguments are now cast to (uintptr_t) before being subsequently cast to (uintmax_t). This is needed to avoid compiler warnings about casting "pointer to integer of a different size." * All [2] existing users of kernhist(9) have had instances of "%s" or "%c" format strings replaced with numeric formats; several instances of mis-match between format string and argument list have been fixed. * vmstat(1) has been modified to handle the new size of arguments in the history data as exported by sysctl(9). * vmstat(1) now provides a warning message if the history requested with the -u option does not exist (previously, this condition was silently ignored, with only a single blank line being printed). * vmstat(1) now checks the version and argument length included in the data exported via sysctl(9) and exits if they do not match the values with which vmstat was built. * The kernhist(9) man-page has been updated to note the additional requirements imposed on the format strings, along with several other minor changes and enhancements. [1] It would have been possible to use an explicit length (for example, uint64_t) for the history arguments. But that would require another "rototill" of all the users in the future when we add support for an architecture that supports a larger size. Also, the printf(3) format specifiers for explicitly-sized values, such as "%"PRIu64, are much more verbose (and less aesthetically appealing, IMHO) than simply using "%ju". [2] I've tried very hard to find "all [the] existing users of kernhist(9)" but it is possible that I've missed some of them. I would be glad to update any stragglers that anyone identifies. -- For some reason this single kernel seems to have outgrown its declared size as a result of the kernhist(9) changes. Bump the size. XXX The amount of increase may be excessive - anyone with more detailed XXX knowledge please feel free to further adjust the value appropriately. -- Misssed one cast of pointer --> uintptr_t in previous kernhist(9) commit -- And yet another one. :( -- Use correct mark-up for NetBSD version. -- More improvements in grammar and readability. -- Remove a stray '"' (obvious typo) and add a couple of casts that are probably needed. -- And replace an instance of "%p" conversion with "%#jx" -- Whitespace fix. Give Bl tag table a width. Fix Xr.
1.364.2.4	26-Nov-2018	pgoyette	Sync with HEAD, resolve a couple of conflicts
1.364.2.3	20-Oct-2018	pgoyette	Sync with head
1.364.2.2	06-Sep-2018	pgoyette	Sync with HEAD Resolve a couple of conflicts (result of the uimin/uimax changes)
1.364.2.1	07-Apr-2018	pgoyette	Sync with HEAD. 77 conflicts resolved - all of them $NetBSD$
1.365.2.4	21-Apr-2020	martin	Sync with HEAD
1.365.2.3	13-Apr-2020	martin	Mostly merge changes from HEAD upto 20200411
1.365.2.2	08-Apr-2020	martin	Merge changes from current as of 20200406
1.365.2.1	10-Jun-2019	christos	Sync with HEAD
1.373.2.2	27-Feb-2020	martin	Pull up following revision(s) (requested by skrll in ticket #742): sys/arch/arm/arm32/pmap.c: revision 1.388 sys/arch/arm/arm32/armv7_generic_space.c: revision 1.11 sys/arch/arm/arm/cpufunc.c: revision 1.176 sys/arch/arm/conf/Makefile.arm: revision 1.54 (via patch) sys/arch/arm/include/arm32/pmap.h: revision 1.161 Fix the armv[67] memory attributes for uncached memory. Previously it was mapped as strongly-ordered which meant that unaligned accesses would fault. armv7_generic_bs_map now maps pages with PMAP_DEV which is treated as SO bus_dma continues to use PMAP_NOCACHE as appropriate, but this now get mapped to the correct memory attribute bits for armv[67] DEVMAP_ENTRY usees a new flag PTE_DEV. The workaround for the unaligned access faults is now removed. XXX Other armv[67] boards bus_space implementations should be checked. XXX There is scope to reduce the difference to aarch64
1.373.2.1	10-Feb-2020	martin	Pull up following revision(s) (requested by skrll in ticket #691): sys/arch/arm/arm32/pmap.c: revision 1.383 sys/arch/arm/arm32/pmap.c: revision 1.385 sys/arch/arm/arm32/pmap.c: revision 1.386 sys/arch/arm/arm32/pmap.c: revision 1.387 sys/arch/arm/arm32/pmap.c: revision 1.374 sys/arch/arm/arm32/pmap.c: revision 1.375 sys/arch/arm/arm32/pmap.c: revision 1.376 sys/arch/arm/arm32/pmap.c: revision 1.377 sys/arch/arm/arm32/pmap.c: revision 1.378 sys/arch/arm/arm32/pmap.c: revision 1.379 Convert a __CTASSERT into a KASSERT as L1_S_CACHE_MASK may not be a compile time constant if ARM_NMMUS > 1 Improve a comment Update PMAP_STEAL_MEMORY code to uvm_hotplug Typo in comment Fix a bug introduced in 1.271 where pmap_grow_map would no longer map the allocated page for the uvm.page_init_done == false case when PMAP_STEAL_MEMORY is not defined. Trailing whitespace Fix comment Always pmap_kenter_pa the page in pmap_grow_map regardless of how we got it. Always call pmap_grow_map with a page aligned new VA. KASSERT that this happenes. More KNF
1.375.2.4	29-Feb-2020	ad	Sync with head.
1.375.2.3	29-Feb-2020	ad	Sync with head.
1.375.2.2	25-Jan-2020	ad	Sync with head.
1.375.2.1	17-Jan-2020	ad	Sync with head.
1.402.2.2	25-Apr-2020	bouyer	Sync with bouyer-xenpvh-base2 (HEAD)
1.402.2.1	20-Apr-2020	bouyer	Sync with HEAD
1.422.2.1	03-Apr-2021	thorpej	Sync with HEAD.
1.426.2.1	03-Apr-2021	thorpej	Sync with HEAD.
1.437.4.4	18-Apr-2024	martin	Pull up following revision(s) (requested by skrll in ticket #666): sys/arch/arm/arm32/pmap.c: revision 1.443 port-arm/58135: reproducible pmap KASSERT failure for armv7 with NFS root Don't unconditionally set XN in pmap_clearbit - only set it if a mapping exists VM_PROT_EXEC is being cleared. I've simplified the #ifdefs in the patch from the PR.
1.437.4.3	14-Dec-2023	martin	Pull up following revision(s) (requested by rin in ticket #495): sys/arch/arm/arm/smccc.c: revision 1.4 sys/arch/arm/arm32/pmap.c: revision 1.441 smccc: Adjust SMCCC_ARCH_ATTRIBUTE for clang/arm Conditionally use (1) __attribute__ ((target("arch=armv7ve"))) (2) __attribute__ ((target("armv7ve"))) for gcc and clang, respectively. While gcc does not accept (2), clang accepts (1) but silently ignores it :( arm: pmap: Fix clang build without DIAGNOSTIC
1.437.4.2	14-Oct-2023	martin	Pull up following revision(s) (requested by skrll in ticket #411): sys/arch/evbarm/nslu2/nslu2_machdep.c: revision 1.41 sys/arch/evbarm/gumstix/gumstix_machdep.c: revision 1.75 sys/arch/evbarm/iq80321/iq80321_machdep.c: revision 1.66 sys/arch/iyonix/iyonix/iyonix_machdep.c: revision 1.34 sys/arch/zaurus/zaurus/machdep.c: revision 1.52 sys/arch/evbarm/g42xxeb/g42xxeb_machdep.c: revision 1.41 sys/arch/hpcarm/hpcarm/pxa2x0_hpc_machdep.c: revision 1.33 sys/arch/evbarm/iq80310/iq80310_machdep.c: revision 1.96 sys/arch/evbarm/adi_brh/brh_machdep.c: revision 1.53 sys/arch/arm/include/arm32/pmap.h: revision 1.177 sys/arch/evbarm/viper/viper_machdep.c: revision 1.34 sys/arch/evbarm/iyonix/iyonix_machdep.c: revision 1.5 sys/arch/evbarm/npwr_fc/npwr_fc_machdep.c: revision 1.30 sys/arch/evbarm/hdl_g/hdlg_machdep.c: revision 1.35 sys/arch/arm/arm32/pmap.c: revision 1.440 sys/arch/evbarm/lubbock/lubbock_machdep.c: revision 1.45 sys/arch/evbarm/ixdp425/ixdp425_machdep.c: revision 1.47 Fix non-DIAGNOSTIC builds
1.437.4.1	19-Dec-2022	martin	Pull up following revision(s) (requested by skrll in ticket #4): sys/arch/arm/arm32/pmap.c: revision 1.438 sys/arch/arm/arm/efi_machdep.c: revision 1.3 Appease KDASSERT / LOCKDEBUG. Tested by mlelstv.
1.13	21-May-2003	thorpej	Move the new pmap from arm32/pmap_new.c to arm32/pmap.c, fully replacing the old.
1.12	10-May-2003	thorpej	Back out the following chagne: http://mail-index.netbsd.org/source-changes/2003/05/08/0068.html There were some side-effects that I didn't anticipate, and fixing them is proving to be more difficult than I thought, do just eject for now. Maybe one day we can look at this again. Fixes PR kern/21517.
1.11	08-May-2003	thorpej	Simplify the way the bounds of the managed kernel virtual address space is advertised to UVM by making virtual_avail and virtual_end first-class exported variables by UVM. Machine-dependent code is responsible for initializing them before main() is called. Anything that steals KVA must adjust these variables accordingly. This reduces the number of instances of this info from 3 to 1, and simplifies the pmap(9) interface by removing the pmap_virtual_space() function call, and removing two arguments from pmap_steal_memory(). This also eliminates some kludges such as having to burn kernel_map entries on space used by the kernel and stolen KVA. This also eliminates use of VM_{MIN,MAX}_KERNEL_ADDRESS from MI code, this giving MD code greater flexibility over the bounds of the managed kernel virtual address space if a given port's specific platforms can vary in this regard (this is especially true of the evb* ports).
1.10	03-May-2003	thorpej	Fix a couple of comments.
1.9	03-May-2003	thorpej	Reduce differences between ARM32_NEW_VM_LAYOUT and not; always pass the start and end of the kernel managed virtual address space to pmap_bootstrap() in the new pmap.
1.8	02-May-2003	thorpej	Eliminate the last reference to PTE_BASE in the new pmap.
1.7	02-May-2003	scw	Rework pmap_growkernel() to not use the regular pmap_alloc_l2_bucket() for L2 allocation. This avoids potential recursive calls into uvm_km_kmemalloc() via the pool allocator. Bug spotted by Allen Briggs while trying to boot on a machine with 512MB of memory.
1.6	28-Apr-2003	scw	Fix the bug reported by Richard Earnshaw in port-arm32/21349. Make sure to check the access permissions before doing ref/mod/domain fixups. This is particularly important on machines with ARM_VECTORS_LOW.
1.5	22-Apr-2003	thorpej	pmap_link_l2pt(): If not ARM32_NEW_VM_LAYOUT, add an assertion that the VA that the page table maps is aligned to a 4MB boundary.
1.4	22-Apr-2003	thorpej	Some ARM32_PMAP_NEW-related cleanup: * Define a new "MMU type", ARM_MMU_SA1. While the SA-1's MMU is basically compatible with the generic, the SA-1 cache does not have a write-through mode, and it is useful to know have an indication of this. * Add a new PMAP_NEEDS_PTE_SYNC indicator, and try to evaluate it at compile time. We evaluate it like so: - If SA-1-style MMU is the only type configured -> 1 - If SA-1-style MMU is not configured -> 0 - Otherwise, defer to a run-time variable. If PMAP_NEEDS_PTE_SYNC might evaluate to true (SA-1 only or run-time check), then we also define PMAP_INCLUDE_PTE_SYNC so that e.g. assembly code can include the necessary run-time support. PMAP_INCLUDE_PTE_SYNC largely replaces the ARM32_PMAP_NEEDS_PTE_SYNC manual setting Steve included with the original new pmap. * In the new pmap, make pmap_pte_init_generic() check to see if the CPU has a write-back cache. If so, init the PT cache mode to C=1,B=0 to get write-through mode. Otherwise, init the PT cache mode to C=1,B=1. * Add a new pmap_pte_init_arm8(). Old pmap, same as generic. New pmap, sets page table cacheability to 0 (ARM8 has a write-back cache, but flushing it is quite expensive). * In the new pmap, make pmap_pte_init_arm9() reset the PT cache mode to C=1,B=0, since the write-back check in generic gets it wrong for ARM9, since we use write-through mode all the time on ARM9 right now. (What this really tells me is that the test for write-through cache is less than perfect, but we can fix that later.) * Add a new pmap_pte_init_sa1(). Old pmap, same as generic. New pmap, does generic initialization, then resets page table cache mode to C=1,B=1, since C=1,B=0 does not produce write-through on the SA-1.
1.3	18-Apr-2003	thorpej	Use L1_S_MAPPABLE_P() and L2_L_MAPPABLE_P().
1.2	18-Apr-2003	scw	Didn't mean to leave PMAP_DEBUG enabled ...
1.1	18-Apr-2003	scw	Add the generic arm32 bits of the new pmap, contributed by Wasabi Systems. Some features of the new pmap are: - It allows L1 descriptor tables to be shared efficiently between multiple processes. A typical "maxusers 32" kernel, where NPROC is set to 532, requires 35 L1s. A "maxusers 2" kernel runs quite happily with just 4 L1s. This completely solves the problem of running out of contiguous physical memory for allocating new L1s at runtime on a busy system. - Much improved cache/TLB management "smarts". This change ripples out to encompass the low-level context switch code, which is also much smarter about when to flush the cache/TLB, and when not to. - Faster allocation of L2 page tables and associated metadata thanks, in part, to the pool_cache enhancements recently contributed to NetBSD by Wasabi Systems. - Faster VM space teardown due to accurate referenced tracking of L2 page tables. - Better/faster cache-alias tracking. The new pmap is enabled by adding options ARM32_PMAP_NEW to the kernel config file, and making the necessary changes to the port-specific initarm() function. Several ports have already been converted and will be committed shortly.
1.2	05-Aug-2001	chris	branches: 1.2.6; Share procfs_machdep.c across arm.
1.1	28-Jul-2001	chris	branches: 1.1.2; Move the generic arm32 files into arm/arm32 from arm32/arm32, tested kernel builds on cats and riscpc.
1.1.2.3	25-Aug-2001	thorpej	Merge Aug 24 -current into the kqueue branch.
1.1.2.2	03-Aug-2001	lukem	update to -current
1.1.2.1	28-Jul-2001	lukem	file procfs_machdep.c was added on branch kqueue on 2001-08-03 04:10:59 +0000
1.2.6.2	05-Aug-2001	chris	Share procfs_machdep.c across arm.
1.2.6.1	05-Aug-2001	chris	file procfs_machdep.c was added on branch nathanw_sa on 2001-08-05 13:09:48 +0000
1.3	18-Aug-2013	matt	Move parts of cpu.h that are not needed by MI code in <arm/locore.h> Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h> Use <arm/asm.h> instead of <machine/arm.h>
1.2	15-Aug-2002	briggs	branches: 1.2.134; 1.2.150; 1.2.160; 1.2.166; * Use local label names (.Lfoo vs. (Lfoo or foo)) * When moving from cpsr, use "cpsr" instead of "cpsr_all" (which is provided, but doesn't make sense since mrs doesn't support fields like msr does).
1.1	28-Jul-2001	chris	branches: 1.1.2; 1.1.8; 1.1.16; Move the generic arm32 files into arm/arm32 from arm32/arm32, tested kernel builds on cats and riscpc.
1.1.16.1	30-Aug-2002	gehenna	catch up with -current.
1.1.8.2	19-Aug-2002	thorpej	Partial (ARM only) sync with trunk -- significant performance improvements for XScale-based systems.
1.1.8.1	28-Jul-2001	thorpej	file setcpsr.S was added on branch nathanw_sa on 2002-08-19 21:39:05 +0000
1.1.2.3	06-Sep-2002	jdolecek	sync kqueue branch with HEAD
1.1.2.2	03-Aug-2001	lukem	update to -current
1.1.2.1	28-Jul-2001	lukem	file setcpsr.S was added on branch kqueue on 2001-08-03 04:10:59 +0000
1.2.166.1	28-Aug-2013	rmind	sync with head
1.2.160.1	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.2.150.1	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.2.134.1	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.6	18-Aug-2013	matt	Move parts of cpu.h that are not needed by MI code in <arm/locore.h> Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h> Use <arm/asm.h> instead of <machine/arm.h>
1.5	16-Feb-2012	christos	branches: 1.5.2; 1.5.4; don't need arm/cpu.h, we just need the cpureg.h...
1.4	27-Apr-2008	matt	branches: 1.4.18; 1.4.34; 1.4.38; 1.4.42; Merge kernel changes in matt-armv6 to HEAD.
1.3	19-Jan-2008	chris	branches: 1.3.6; 1.3.8; 1.3.10; When chaning processor mode on ARM use cpsr_c, rather than cpsr_all.
1.2	15-Aug-2002	briggs	branches: 1.2.24; 1.2.82; 1.2.86; 1.2.88; 1.2.94; 1.2.102; * Use local label names (.Lfoo vs. (Lfoo or foo)) * When moving from cpsr, use "cpsr" instead of "cpsr_all" (which is provided, but doesn't make sense since mrs doesn't support fields like msr does).
1.1	28-Jul-2001	chris	branches: 1.1.2; 1.1.8; 1.1.16; Move the generic arm32 files into arm/arm32 from arm32/arm32, tested kernel builds on cats and riscpc.
1.1.16.1	30-Aug-2002	gehenna	catch up with -current.
1.1.8.2	19-Aug-2002	thorpej	Partial (ARM only) sync with trunk -- significant performance improvements for XScale-based systems.
1.1.8.1	28-Jul-2001	thorpej	file setstack.S was added on branch nathanw_sa on 2002-08-19 21:39:06 +0000
1.1.2.3	06-Sep-2002	jdolecek	sync kqueue branch with HEAD
1.1.2.2	03-Aug-2001	lukem	update to -current
1.1.2.1	28-Jul-2001	lukem	file setstack.S was added on branch kqueue on 2001-08-03 04:10:59 +0000
1.2.102.1	20-Jan-2008	bouyer	Sync with HEAD
1.2.94.1	18-Feb-2008	mjf	Sync with HEAD.
1.2.88.1	23-Mar-2008	matt	sync with HEAD
1.2.86.1	20-Jan-2008	chris	Sync to HEAD.
1.2.82.1	28-Feb-2008	rjs	Sync with HEAD.
1.2.24.1	21-Jan-2008	yamt	sync with head
1.3.10.1	16-May-2008	yamt	sync with head.
1.3.8.1	18-May-2008	yamt	sync with head.
1.3.6.1	02-Jun-2008	mjf	Sync with HEAD.
1.4.42.1	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.4.38.1	18-Feb-2012	mrg	merge to -current.
1.4.34.2	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.4.34.1	17-Apr-2012	yamt	sync with head
1.4.18.1	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.5.4.1	28-Aug-2013	rmind	sync with head
1.5.2.1	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.11	11-Oct-2021	rin	splx: Restore interrupts before dosoftints() for __HAVE_FAST_SOFTINTS. No functional changes; All the users of arm32/spl.S, i.e., acorn32, hpcarm/sa11x0, and shark have not switched to __HAVE_FAST_SOFTINTS yet.
1.10	02-Dec-2013	joerg	Don't use cpsr_all/spsr_all with mrs, it doesn't take a mask.
1.9	18-Aug-2013	matt	Move parts of cpu.h that are not needed by MI code in <arm/locore.h> Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h> Use <arm/asm.h> instead of <machine/arm.h>
1.8	27-Apr-2008	matt	branches: 1.8.18; 1.8.34; 1.8.44; 1.8.50; Merge kernel changes in matt-armv6 to HEAD.
1.7	03-Dec-2007	ad	branches: 1.7.14; 1.7.16; 1.7.18; Interrupt handling changes, in discussion since February: - Reduce available SPL levels for hardware devices to none, vm, sched, high. - Acquire kernel_lock only for interrupts at IPL_VM. - Implement threaded soft interrupts.
1.6	17-Oct-2007	garbled	branches: 1.6.2; Merge the ppcoea-renovation branch to HEAD. This branch was a major cleanup and rototill of many of the various OEA cpu based PPC ports that focused on sharing as much code as possible between the various ports to eliminate near-identical copies of files in every tree. Additionally there is a new PIC system that unifies the interface to interrupt code for all different OEA ppc arches. The work for this branch was done by a variety of people, too long to list here. TODO: bebox still needs work to complete the transition to -renovation. ofppc still needs a bunch of work, which I will be looking at. ev64260 still needs to be renovated amigappc was not attempted. NOTES: pmppc was removed as an arch, and moved to a evbppc target.
1.5	13-Aug-2007	tsutsui	branches: 1.5.2; Remove all references to spl_mask. Now it isn't used by any sources. Discussed on port-arm.
1.4	17-Aug-2002	thorpej	branches: 1.4.24; 1.4.66; 1.4.74; 1.4.80; 1.4.82; 1.4.84; 1.4.86; More local label fixups.
1.3	26-Nov-2001	thorpej	branches: 1.3.8; Use <arm/arm32/psl.h>, not <machine/psl.h>.
1.2	28-Sep-2001	chris	branches: 1.2.4; Tweak spl functions a little, try to do something between an ldr and it's use. Not the greatest of gains but spl is called a lot it might add up. Also add comments stating alignment of stack.
1.1	28-Jul-2001	chris	branches: 1.1.2; 1.1.4; Move the generic arm32 files into arm/arm32 from arm32/arm32, tested kernel builds on cats and riscpc.
1.1.4.1	01-Oct-2001	fvdl	Catch up with -current.
1.1.2.4	06-Sep-2002	jdolecek	sync kqueue branch with HEAD
1.1.2.3	10-Jan-2002	thorpej	Sync kqueue branch with -current.
1.1.2.2	03-Aug-2001	lukem	update to -current
1.1.2.1	28-Jul-2001	lukem	file spl.S was added on branch kqueue on 2001-08-03 04:10:59 +0000
1.2.4.3	19-Aug-2002	thorpej	Partial (ARM only) sync with trunk -- significant performance improvements for XScale-based systems.
1.2.4.2	08-Jan-2002	nathanw	Catch up to -current.
1.2.4.1	28-Sep-2001	nathanw	file spl.S was added on branch nathanw_sa on 2002-01-08 00:23:09 +0000
1.3.8.1	30-Aug-2002	gehenna	catch up with -current.
1.4.86.2	01-Jan-2008	chris	Sync with HEAD.
1.4.86.1	18-Aug-2007	chris	Sync with HEAD
1.4.84.2	09-Dec-2007	jmcneill	Sync with HEAD.
1.4.84.1	16-Aug-2007	jmcneill	Sync with HEAD.
1.4.82.2	26-Dec-2007	rjs	Sync with HEAD.
1.4.82.1	01-Nov-2007	rjs	Sync with HEAD.
1.4.80.1	15-Aug-2007	skrll	Sync with HEAD.
1.4.74.1	03-Oct-2007	garbled	Sync with HEAD
1.4.66.3	03-Dec-2007	ad	Sync with HEAD.
1.4.66.2	03-Dec-2007	ad	Sync with HEAD.
1.4.66.1	20-Aug-2007	ad	Sync with HEAD.
1.4.24.2	07-Dec-2007	yamt	sync with head
1.4.24.1	03-Sep-2007	yamt	sync with head.
1.5.2.3	28-Jan-2008	matt	Given the that there are only 4 IPLs (ignoring soft IPLs), a number of cleanups can be done: Remove _SPL_* aliases. Don't store irqmasks in ci_cpl, just make it an ipl level. Add fast softint switching support.
1.5.2.2	09-Jan-2008	matt	sync with HEAD
1.5.2.1	11-Sep-2007	matt	Adapt to move of current_spl_level to curcpu()->ci_cpl
1.6.2.1	08-Dec-2007	mjf	Sync with HEAD.
1.7.18.1	16-May-2008	yamt	sync with head.
1.7.16.1	18-May-2008	yamt	sync with head.
1.7.14.1	02-Jun-2008	mjf	Sync with HEAD.
1.8.50.2	18-May-2014	rmind	sync with head
1.8.50.1	28-Aug-2013	rmind	sync with head
1.8.44.1	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.8.34.1	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.8.18.1	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.2	13-May-2001	bjh21	branches: 1.2.8; strstr() is no longer used in the kernel. G/C it.
1.1	04-Mar-2001	matt	branches: 1.1.4; Move compat_13_machdep.c, strstr.c, copystr.S, bcopyinout.S, and bcopy_page.S to arm/arm32 and remove port-local copies.
1.1.4.2	12-Mar-2001	bouyer	Sync with HEAD.
1.1.4.1	04-Mar-2001	bouyer	file strstr.c was added on branch thorpej_scsipi on 2001-03-12 13:27:20 +0000
1.2.8.2	13-May-2001	bjh21	strstr() is no longer used in the kernel. G/C it.
1.2.8.1	13-May-2001	bjh21	file strstr.c was added on branch nathanw_sa on 2001-05-13 14:17:37 +0000
1.27	03-Jul-2020	skrll	KNF
1.26	20-Jun-2020	skrll	KNF
1.25	20-Jun-2020	skrll	KNF #includes Remove some unnecessary ones while I'm here.
1.24	12-Nov-2012	skrll	branches: 1.24.18; 1.24.28; C99 types
1.23	12-Dec-2011	mrg	branches: 1.23.4; 1.23.6; implement bdev_size(9) wrapper around d_psize() routine, so we can take the device lock in relevant places. avoid doing so while actually dumping. tested i386 crash dumps still work, and that all touched files compile. fixes PR#45705.
1.22	07-Nov-2009	cegger	branches: 1.22.12; 1.22.16; Add a flags argument to pmap_kenter_pa(9). Patch showed on tech-kern@ http://mail-index.netbsd.org/tech-kern/2009/11/04/msg006434.html No objections.
1.21	15-Mar-2009	cegger	ansify function definitions
1.20	21-Jan-2009	he	branches: 1.20.2; Re-adapt to the changed return types for major() and minor().
1.19	11-Jan-2009	cegger	use PRI format macros to printf major and minor values
1.18	01-Jan-2008	chris	branches: 1.18.6; 1.18.10; 1.18.18; 1.18.26; Add support for kcore headers to arm32 kernel core dumps. The kcore code is based on i386's kcore header handling. Having an asm stub for dumpsys, to dump the registers onto the stack, and then call the C code to do the memory dump is based on amd64's core dump code. This allows a successful core dump on cats. Part of fixing PR cats/18026.
1.17	04-Mar-2007	christos	branches: 1.17.16; 1.17.20; 1.17.22; 1.17.28; 1.17.34; Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.
1.16	21-Oct-2006	mrg	branches: 1.16.4; in cpu_dumpconf(), don't panic() if we can't bdevsw_lookup() the dumpdev. this occurs when we try to set the dumpdev to a device with no driver loaded. this fixes PR#34872. in sys_swapctl, if bdevsw_lookup() fails, set dumpdev = NODEV before calling cpu_dumpconf(). (this also fixes PR#34872.) XXX: cpu_dumpconf() should probably be changed to take a dumpdev XXX: and return an error in such cases, but that is a much more XXX: intrusive change. XXX2: this is only run-tested on sparc64 and compile tested on a XXX2: couple of platforms.
1.15	11-Dec-2005	christos	branches: 1.15.20; 1.15.22; merge ktrace-lwp.
1.14	15-Jul-2003	lukem	branches: 1.14.16; __KERNEL_RCSID()
1.13	01-Apr-2003	thorpej	branches: 1.13.2; Use PAGE_SIZE rather than NBPG.
1.12	23-Mar-2003	chris	When doing a kernel dump use the pmap_k* funcs. Also make sure that all data is written to ram. This avoids issues with tlb's not being flushed etc. As discussed a long time ago on port-arm
1.11	28-Dec-2002	reinoud	Remove spurious declaration of bootconfig structure since that is already done in bootconfig.h
1.10	06-Sep-2002	gehenna	Merge the gehenna-devsw branch into the trunk. This merge changes the device switch tables from static array to dynamically generated by config(8). - All device switches is defined as a constant structure in device drivers. - The new grammer ``device-major'' is introduced to ``files''. device-major <prefix> char <num> [block <num>] [<rules>] - All device major numbers must be listed up in port dependent majors.<arch> by using this grammer. - Added the new naming convention. The name of the device switch must be <prefix>_[bc]devsw for auto-generation of device switch tables. - The backward compatibility of loading block/character device switch by LKM framework is broken. This is necessary to convert from block/character device major to device name in runtime and vice versa. - The restriction to assign device major by LKM is completely removed. We don't need to reserve LKM entries for dynamic loading of device switch. - In compile time, device major numbers list is packed into the kernel and the LKM framework will refer it to assign device major number dynamically.
1.9	23-Mar-2002	thorpej	branches: 1.9.2; Garbage-collect the "pagehook" stuff.
1.8	06-Mar-2002	tsutsui	Change type of dumpmag to u_int32_t since it is actually a 32bit unsigned magic number. As per discussion on tech-kern, and fixes port-sparc64/11949.
1.7	05-Jan-2002	chris	Make some of the arm32 files build with LOOSE_PROTOTYPES not set in the makefile. Turned up a few mismatched functions. Note that this isn't all of the arm32 files. Aim will be to get arm32 kernels built with LOOSE_PROTOTYPES not set.
1.6	26-Nov-2001	thorpej	Move interrupt-related stuff out of stubs.c into intr.c.
1.5	27-Oct-2001	rearnsha	branches: 1.5.2; Set initial spl level to SPL_SERIAL, which for some strange reason is higher than SPL_HIGH (maybe we should be fixing SPL_HIGH). If IPL_STATCLOCK is defined, initialize spl_masks[_SPL_STATCLOCK] from it; otherwise initialize use IPL_CLOCK.
1.4	05-Sep-2001	matt	branches: 1.4.4; Don't compile SPL/INTR stuff if NEWINTR is defined.
1.3	05-Sep-2001	matt	Change <machine/irqhandler.h> to <machine/intr.h> since the latter always includes the former and is a standard include file.
1.2	12-Aug-2001	jdolecek	Move _insque()/_remque() to libkern. Once remaining uses would be converted to <sys/queue.h> macros, _insque()/_remque() would be eliminated altogether.
1.1	28-Jul-2001	chris	branches: 1.1.2; Move the generic arm32 files into arm/arm32 from arm32/arm32, tested kernel builds on cats and riscpc.
1.1.2.8	10-Oct-2002	jdolecek	sync kqueue with -current; this includes merge of gehenna-devsw branch, merge of i386 MP branch, and part of autoconf rototil work
1.1.2.7	23-Jun-2002	jdolecek	catch up with -current on kqueue branch
1.1.2.6	16-Mar-2002	jdolecek	Catch up with -current.
1.1.2.5	10-Jan-2002	thorpej	Sync kqueue branch with -current.
1.1.2.4	13-Sep-2001	thorpej	Update the kqueue branch to HEAD.
1.1.2.3	25-Aug-2001	thorpej	Merge Aug 24 -current into the kqueue branch.
1.1.2.2	03-Aug-2001	lukem	update to -current
1.1.2.1	28-Jul-2001	lukem	file stubs.c was added on branch kqueue on 2001-08-03 04:10:59 +0000
1.4.4.1	12-Nov-2001	thorpej	Sync the thorpej-mips-cache branch with -current.
1.5.2.7	29-Dec-2002	thorpej	Sync with HEAD.
1.5.2.6	17-Sep-2002	nathanw	Catch up to -current.
1.5.2.5	01-Apr-2002	nathanw	Catch up to -current. (CVS: It's not just a program. It's an adventure!)
1.5.2.4	28-Feb-2002	nathanw	Catch up to -current.
1.5.2.3	11-Jan-2002	nathanw	More catchup.
1.5.2.2	08-Jan-2002	nathanw	Catch up to -current.
1.5.2.1	27-Oct-2001	nathanw	file stubs.c was added on branch nathanw_sa on 2002-01-08 00:23:09 +0000
1.9.2.1	19-May-2002	gehenna	Replace the access to devsw table and the hard-coded majors with devsw API.
1.13.2.3	21-Sep-2004	skrll	Fix the sync with head I botched.
1.13.2.2	18-Sep-2004	skrll	Sync with HEAD.
1.13.2.1	03-Aug-2004	skrll	Sync with HEAD
1.14.16.3	21-Jan-2008	yamt	sync with head
1.14.16.2	03-Sep-2007	yamt	sync with head.
1.14.16.1	30-Dec-2006	yamt	sync with head.
1.15.22.1	22-Oct-2006	yamt	sync with head
1.15.20.1	18-Nov-2006	ad	Sync with head.
1.16.4.1	12-Mar-2007	rmind	Sync with HEAD.
1.17.34.1	02-Jan-2008	bouyer	Sync with HEAD
1.17.28.1	18-Feb-2008	mjf	Sync with HEAD.
1.17.22.1	09-Jan-2008	matt	sync with HEAD
1.17.20.1	01-Jan-2008	chris	Sync with HEAD.
1.17.16.1	28-Feb-2008	rjs	Sync with HEAD.
1.18.26.1	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.18.18.3	28-Apr-2009	skrll	Sync with HEAD.
1.18.18.2	03-Mar-2009	skrll	Sync with HEAD.
1.18.18.1	19-Jan-2009	skrll	Sync with HEAD.
1.18.10.2	11-Mar-2010	yamt	sync with head
1.18.10.1	04-May-2009	yamt	sync with head.
1.18.6.1	17-Jan-2009	mjf	Sync with HEAD.
1.20.2.1	13-May-2009	jym	Sync with HEAD. Commit is split, to avoid a "too many arguments" protocol error.
1.22.16.1	18-Feb-2012	mrg	merge to -current.
1.22.12.2	16-Jan-2013	yamt	sync with (a bit old) head
1.22.12.1	17-Apr-2012	yamt	sync with head
1.23.6.1	20-Nov-2012	tls	Resync to 2012-11-19 00:00:00 UTC
1.23.4.1	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.24.28.1	27-Apr-2017	pgoyette	Restore all work from the former pgoyette-localcount branch (which is now abandoned doe to cvs merge botch). The branch now builds, and installs via anita. There are still some problems (cgd is non-functional and all atf tests time-out) but they will get resolved soon.
1.24.18.1	20-Jul-2016	pgoyette	Adapt the machine/arch dependent code to the new {b,c}devsw reference counting. XXX Most of these will require testing by someone other than myself, as I have a limited selection of hardware!
1.26	20-Jun-2020	skrll	KNF
1.25	20-Jun-2020	skrll	KNF #includes Remove some unnecessary ones while I'm here.
1.24	20-Jun-2020	skrll	Trailing whitespace
1.23	16-Mar-2017	chs	allow pcu_save() and pcu_discard() to be called on other threads, ptrace needs to use it that way.
1.22	02-Jul-2015	skrll	branches: 1.22.2; 1.22.4; Use armreg_*_{read,write} instead of handcrafted asm No functional change.
1.21	22-Mar-2015	joerg	Mark as volatile, just to be sure.
1.20	03-Mar-2014	matt	branches: 1.20.6; Query the media and vfp feature registers to determine what our default mode should be and what bits in the fpscr can be changed. Print what features are supported: vfp0 at cpu0: NEON MPE (VFP 3.0+), rounding, NaN propogation, denormals
1.19	23-Aug-2013	matt	Make use of vfp_used_p condition on FPU_VFP
1.18	23-Aug-2013	matt	Reap LWP_VFPUSED and use PCU internal tracking. Add bool vfp_used_p(void);
1.17	18-Aug-2013	matt	Move parts of cpu.h that are not needed by MI code in <arm/locore.h> Don't include <machine/cpu.h> or <machine/frame.h>, use <arm/locore.h> Use <arm/asm.h> instead of <machine/arm.h>
1.16	31-Jan-2013	matt	branches: 1.16.2; add a fpu_used sysarch
1.15	12-Aug-2012	matt	branches: 1.15.2; Rework VFP support to use PCU. Add emulation of instruction which save/restore the VFP FPSCR. Add a sysarch hook to VFP FPSCR manipulation. [The emulation will be used by libc to store/fetch exception modes and rounding mode on a per-thread basis.]
1.14	17-Nov-2011	joerg	branches: 1.14.8; Don't return ENOSYS if nothing needs to be done for the CPU. XXX Shouldn't this be a runtime test on the CPU?
1.13	30-Jun-2011	wiz	branches: 1.13.2; dependant -> dependent
1.12	07-Apr-2011	matt	Don't use the pcb anymore since the user read-only thread and process id value is now grabbed from l_private.
1.11	07-Jul-2010	chs	branches: 1.11.2; implement cpu_lwp_setprivate() on several platforms.
1.10	27-Apr-2008	matt	branches: 1.10.2; 1.10.18; 1.10.20; 1.10.22; Merge kernel changes in matt-armv6 to HEAD.
1.9	20-Dec-2007	dsl	branches: 1.9.6; 1.9.8; 1.9.10; Convert all the system call entry points from: int foo(struct lwp l, void v, register_t retval) to: int foo(struct lwp l, const struct foo_args uap, register_t retval) Fixup compat code to not write into 'uap' and (in some cases) to actually pass a correctly formatted 'uap' structure with the right name to the next routine. A few 'compat' routines that just call standard ones have been deleted. All the 'compat' code compiles (along with the kernels required to test build it). 98% done by automated scripts.
1.8	09-Feb-2007	ad	branches: 1.8.20; 1.8.24; 1.8.26; 1.8.34; 1.8.38; Merge newlock2 to head.
1.7	11-Dec-2005	christos	branches: 1.7.20; 1.7.28; merge ktrace-lwp.
1.6	15-Jul-2003	lukem	branches: 1.6.16; __KERNEL_RCSID()
1.5	17-Jan-2003	thorpej	branches: 1.5.2; Merge the nathanw_sa branch.
1.4	30-Mar-2002	thorpej	Rename the ARM sysarch calls from arm32* -> arm*
1.3	25-Jan-2002	thorpej	Overhaul of the ARM cache code. This is mostly a simplification pass. Rather than providing a whole slew of cache operations that aren't ever used, distill them down to some useful primitives: icache_sync_all Synchronize I-cache icache_sync_range Synchronize I-cache range dcache_wbinv_all Write-back and Invalidate D-cache dcache_wbinv_range Write-back and Invalidate D-cache range dcache_inv_range Invalidate D-cache range dcache_wb_range Write-back D-cache range idcache_wbinv_all Write-back and Invalidate D-cache, Invalidate I-cache idcache_wbinv_range Write-back and Invalidate D-cache, Invalidate I-cache range Note: This does not yet include an overhaul of the actual asm files that implement the primitives. Instead, we've provided a safe default for each CPU type, and the individual CPU types can now be optimized one at a time.
1.2	05-Jan-2002	chris	Make some of the arm32 files build with LOOSE_PROTOTYPES not set in the makefile. Turned up a few mismatched functions. Note that this isn't all of the arm32 files. Aim will be to get arm32 kernels built with LOOSE_PROTOTYPES not set.
1.1	04-Mar-2001	matt	branches: 1.1.4; 1.1.6; 1.1.10; Move these from arm32/arm32
1.1.10.5	29-May-2002	nathanw	#include <sys/sa.h> before <sys/syscallargs.h>, to provide sa_upcall_t now that <sys/param.h> doesn't include <sys/sa.h>. (Behold the Power of Ed)
1.1.10.4	17-Apr-2002	nathanw	Catch up to -current.
1.1.10.3	28-Feb-2002	nathanw	Catch up to -current.
1.1.10.2	11-Jan-2002	nathanw	More catchup.
1.1.10.1	15-Nov-2001	thorpej	Machine-dependent kernel mods for scheduler activations on 32-bit ARM processors. Kernel boots multi-user on an XScale, but upcalls not yet tested.
1.1.6.3	23-Jun-2002	jdolecek	catch up with -current on kqueue branch
1.1.6.2	11-Feb-2002	jdolecek	Sync w/ -current.
1.1.6.1	10-Jan-2002	thorpej	Sync kqueue branch with -current.
1.1.4.2	12-Mar-2001	bouyer	Sync with HEAD.
1.1.4.1	04-Mar-2001	bouyer	file sys_machdep.c was added on branch thorpej_scsipi on 2001-03-12 13:27:20 +0000
1.5.2.3	21-Sep-2004	skrll	Fix the sync with head I botched.
1.5.2.2	18-Sep-2004	skrll	Sync with HEAD.
1.5.2.1	03-Aug-2004	skrll	Sync with HEAD
1.6.16.2	21-Jan-2008	yamt	sync with head
1.6.16.1	26-Feb-2007	yamt	sync with head.
1.7.28.1	10-Nov-2007	matt	Add AT91 support from Sami Kantoluoto Add TI OMAP2430 support from Marty Fouts @ Danger Inc
1.7.20.1	30-Jan-2007	ad	Remove support for SA. Ok core@.
1.8.38.1	02-Jan-2008	bouyer	Sync with HEAD
1.8.34.1	26-Dec-2007	ad	Sync with head.
1.8.26.3	09-Jan-2008	matt	sync with HEAD
1.8.26.2	09-Nov-2007	matt	Add pmap_icache_sync_range and change arm32_sync_icache to use it. This will only invalidate va that have valid PTEs. This avoids cleaning unneeded cache lines.
1.8.26.1	06-Nov-2007	matt	Cleanup (de-__P, ansify) Use lwp instead of proc (since neither is used). Use void * instead of char *
1.8.24.1	01-Jan-2008	chris	Sync with HEAD.
1.8.20.1	26-Dec-2007	rjs	Sync with HEAD.
1.9.10.2	11-Aug-2010	yamt	sync with head.
1.9.10.1	16-May-2008	yamt	sync with head.
1.9.8.1	18-May-2008	yamt	sync with head.
1.9.6.1	02-Jun-2008	mjf	Sync with HEAD.
1.10.22.2	21-Apr-2011	rmind	sync with head
1.10.22.1	05-Mar-2011	rmind	sync with head
1.10.20.1	17-Aug-2010	uebayasi	Sync with HEAD.
1.10.18.1	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.10.2.2	14-May-2008	wrstuden	Per discussion with ad, remove most of the #include <sys/sa.h> lines as they were including sa.h just for the type(s) needed for syscallargs.h. Instead, create a new file, sys/satypes.h, which contains just the types needed for syscallargs.h. Yes, there's only one now, but that may change and it's probably more likely to change if it'd be difficult to handle. :-) Per discussion with matt at n dot o, add an include of satypes.h to sigtypes.h. Upcall handlers are kinda signal handlers, and signalling is the header file that's already included for syscallargs.h that closest matches SA. This shaves about 3000 lines off of the diff of the branch relative to the base. That also represents about 18% of the total before this checkin. I think this reduction is very good thing.
1.10.2.1	10-May-2008	wrstuden	Initial checkin of re-adding SA. Everything except kern_sa.c compiles in GENERIC for i386. This is still a work-in-progress, but this checkin covers most of the mechanical work (changing signalling to be able to accomidate SA's process-wide signalling and re-adding includes of sys/sa.h and savar.h). Subsequent changes will be much more interesting. Also, kern_sa.c has received partial cleanup. There's still more to do, though.
1.11.2.1	06-Jun-2011	jruoho	Sync with HEAD.
1.13.2.3	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.13.2.2	30-Oct-2012	yamt	sync with head
1.13.2.1	17-Apr-2012	yamt	sync with head
1.14.8.1	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.15.2.3	03-Dec-2017	jdolecek	update from HEAD
1.15.2.2	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.15.2.1	25-Feb-2013	tls	resync with head
1.16.2.2	18-May-2014	rmind	sync with head
1.16.2.1	28-Aug-2013	rmind	sync with head
1.20.6.3	28-Aug-2017	skrll	Sync with HEAD
1.20.6.2	22-Sep-2015	skrll	Sync with HEAD
1.20.6.1	06-Apr-2015	skrll	Sync with HEAD
1.22.4.1	21-Apr-2017	bouyer	Sync with HEAD
1.22.2.1	20-Mar-2017	pgoyette	Sync with HEAD
1.4	12-Jan-2002	bjh21	Combined syscall handler for all ARM ports. This is basically the arm32 version, made readable and compatible with arm26. In addition, this adds support for NetBSD/arm's newly allocated SWI range.
1.3	05-Jan-2002	chris	Make some of the arm32 files build with LOOSE_PROTOTYPES not set in the makefile. Turned up a few mismatched functions. Note that this isn't all of the arm32 files. Aim will be to get arm32 kernels built with LOOSE_PROTOTYPES not set.
1.2	22-Nov-2001	thorpej	Kill <machine/katelib.h>. Any place that still uses it should just reference <arm/arm32/katelib.h> until such time as all use of this file has been purged from the face of the earth.
1.1	04-Mar-2001	matt	branches: 1.1.4; 1.1.6; 1.1.10; Move these from arm32/arm32
1.1.10.4	28-Feb-2002	nathanw	Catch up to -current.
1.1.10.3	11-Jan-2002	nathanw	More catchup.
1.1.10.2	08-Jan-2002	nathanw	Catch up to -current.
1.1.10.1	15-Nov-2001	thorpej	Machine-dependent kernel mods for scheduler activations on 32-bit ARM processors. Kernel boots multi-user on an XScale, but upcalls not yet tested.
1.1.6.2	11-Feb-2002	jdolecek	Sync w/ -current.
1.1.6.1	10-Jan-2002	thorpej	Sync kqueue branch with -current.
1.1.4.2	12-Mar-2001	bouyer	Sync with HEAD.
1.1.4.1	04-Mar-2001	bouyer	file syscall.c was added on branch thorpej_scsipi on 2001-03-12 13:27:20 +0000
1.79	15-Jan-2024	andvar	Include <sys/syslog.h> with "#ifdef STACKCHECKS" guard. The include was lost on rev 1.77 during includes cleanup and KNF, however it is still needed with STACKCHECKS build option.
1.78	28-Mar-2021	skrll	fix a comment that has been c&p'ed around and not updated
1.77	20-Jun-2020	skrll	branches: 1.77.2; 1.77.4; KNF #includes Remove some unnecessary ones while I'm here.
1.76	18-Apr-2020	skrll	PMAP_DEBUG has been deleted on arm
1.75	12-Jul-2018	jakllsch	branches: 1.75.10; <sys/pmc.h> is gone; don't #include it
1.74	12-Jul-2018	maxv	Remove the kernel PMC code. Sent yesterday on tech-kern@. This change: * Removes "options PERFCTRS", the associated includes, and the associated ifdefs. In doing so, it removes several XXXSMPs in the MI code, which is good. * Removes the PMC code of ARM XSCALE. * Removes all the pmc.h files. They were all empty, except for ARM XSCALE. * Reorders the x86 PMC code not to rely on the legacy pmc.h file. The definitions are put in sysarch.h. * Removes the kern/sys_pmc.c file, and along with it, the sys_pmc_control and sys_pmc_get_info syscalls. They are marked as OBSOL in kern, netbsd32 and rump. * Removes the pmc_evid_t and pmc_ctr_t types. * Removes all the associated man pages. The sets are marked as obsolete.
1.73	28-May-2018	chs	branches: 1.73.2; merge a new version of the CDDL dtrace and ZFS code. this changes the upstream vendor from OpenSolaris to FreeBSD, and this version is based on FreeBSD svn r315983. in addition to the 10 years of improvements from upstream, this version also has these NetBSD-specific enhancements: - dtrace FBT probes can now be placed in kernel modules. - ZFS now supports mmap().
1.72	17-Oct-2017	skrll	branches: 1.72.2; Fix eva argument to pmap_remove and passed prot bits in flags for pmap_enter, i.e. fix previous.
1.71	08-Oct-2017	flxd	In vmapbuf use pmap_enter(pmap_kernel(), ...) and not pmap_kenter_pa as the former handles multiple mappings for VIPT AND VIVT correctly whereas the latter doesn't work for VIVT. PR port-shark/52102 From skrll@. Tested by martin@ and me.
1.70	29-Mar-2015	matt	branches: 1.70.10; cache pmap in vmapbuf.
1.69	10-Mar-2014	matt	branches: 1.69.6; Use pmap_kenter_pa/pmap_kremove for vmapbuf/vunmapbuf
1.68	10-Sep-2013	matt	Support an optional MARCH ELF tag. Store the MACHINE_ARCH of the executable in mdproc and override sysctl so that value returned.
1.67	23-Aug-2013	matt	Reap LWP_VFPUSED and use PCU internal tracking. Add bool vfp_used_p(void);
1.66	11-May-2013	skrll	branches: 1.66.2; Whitespace
1.65	25-Jan-2013	skrll	Shut up noisy debug unless pmap_debug_level > 0
1.64	18-Dec-2012	matt	Remove unneeded definitions. When forking a LWP, disable the VFP in the new LWP since it isn't the LWP that owns the VFP.
1.63	10-Dec-2012	matt	Rename pcb_sp/PCB_SP to pcb_ksp/PCB_KSP so that ipsec.c will compile.
1.62	05-Dec-2012	matt	ARMFPE hasn't compiled since NetBSD 4. Remove it. Complete support for FPU_VFP. fpregs now contains vfpreg. XXX vfpreg only has space for 16 64-bit FP registers though VFPv3 and later have 32 64-bit FP registers.
1.61	23-Oct-2012	matt	When allocating the kernel virtual addresses, make sure to match the color of the user addresses.
1.60	29-Aug-2012	matt	branches: 1.60.2; Use ARMV6+ cpsi{d,f} instructions whenever possible. Use r7 to hold previous mode and avoid recomputing it. Add support for obtaining kernel_lock on exception entry and exit.
1.59	16-Aug-2012	matt	small rototill. pcb_flags is dead. PCB_NOALIGNFLT is now in stored l_md.md_flags as MDLWP_NOALIGNFLT. This avoids a few loads of the PCB in exception handling. pcb_tf has been moved to l_md.md_tf. Again this avoids a lot of pcb references just to access or set this. It also means that pcb doesn't need to accessed by MI code. Move pcb_onfault to after the pcb union. Add pcb_sp macro to make code prettier. Add lwp_settrapframe(l, tf) to set the l_md.md_tf field. Use lwp_trapframe to access it (was process_frame but that name was changed in a previous commit). Kill off curpcb in acorn26. Kill the checks for curlwp being NULL. Move TRAP_USERMODE from arm32/fault.c to frame.h and a __PROG26 version. Replace tests for usermode with that macro.
1.58	12-Aug-2012	matt	Rework VFP support to use PCU. Add emulation of instruction which save/restore the VFP FPSCR. Add a sysarch hook to VFP FPSCR manipulation. [The emulation will be used by libc to store/fetch exception modes and rounding mode on a per-thread basis.]
1.57	03-Aug-2012	matt	COMPAT_NETBSD32 support for ARM. Which is strange since ARM is already 32-bits. But the newer ARM ABI AAPCS changes the alignment of 64-bit fields so structures need to copied in and out to deal with the alignment change. This is a kludge but makes debugging of AAPCS support much easier.
1.56	19-Feb-2012	rmind	Remove COMPAT_SA / KERN_SA. Welcome to 6.99.3! Approved by core@.
1.55	10-Feb-2011	pooka	branches: 1.55.4; 1.55.8; 1.55.12; Make vmapbuf() return success/error and make physio deal with a failure.
1.54	14-Jan-2011	rmind	branches: 1.54.2; 1.54.4; Retire struct user, remove sys/user.h inclusions. Note sys/user.h header as obsolete. Remove USER_TO_UAREA/UAREA_TO_USER macros. Various #include fixes and review by matt@.
1.53	29-Nov-2009	rmind	branches: 1.53.4; Replace l_addr with uvm_lwp_getuarea() in various MD code, mostly cpu_lwp_fork().
1.52	26-Nov-2009	matt	Kill proc0paddr. Use lwp0.l_addr instead.
1.51	21-Nov-2009	rmind	Use lwp_getpcb() on ARM (and acorn26/32), clean from struct user usage.
1.50	21-Oct-2009	rmind	Remove uarea swap-out functionality: - Addresses the issue described in PR/38828. - Some simplification in threading and sleepq subsystems. - Eliminates pmap_collect() and, as a side note, allows pmap optimisations. - Eliminates XS_CTL_DATA_ONSTACK in scsipi code. - Avoids few scans on LWP list and thus potentially long holds of proc_lock. - Cuts ~1.5k lines of code. Reduces amd64 kernel size by ~4k. - Removes __SWAP_BROKEN cases. Tested on x86, mips, acorn32 (thanks <mpumford>) and partly tested on acorn26 (thanks to <bjh21>). Discussed on <tech-kern>, reviewed by <ad>.
1.49	14-Mar-2009	dsl	ANSIfy another 1261 function definitions. The only ones left in sys are beyond by sed script! (or in sys/dist or sys/external) Mostly they have function pointer parameters.
1.48	14-Mar-2009	dsl	Change about 4500 of the K&R function definitions to ANSI ones. There are still about 1600 left, but they have ',' or /* ... */ in the actual variable definitions - which my awk script doesn't handle. There are also many that need () -> (void). (The script does handle misordered arguments.)
1.47	14-Mar-2009	dsl	Remove all the __P() from sys (excluding sys/dist) Diff checked with grep and MK1 eyeball. i386 and amd64 GENERIC and sys still build.
1.46	21-Oct-2008	matt	branches: 1.46.2; 1.46.8; 1.46.12; Adapt to SA (conditional KERN_SA) and add cpu_setfunc
1.45	07-Aug-2008	matt	Remove unneeded cast.
1.44	07-Jul-2008	skrll	branches: 1.44.2; Update a comment.
1.43	15-Mar-2008	rearnsha	branches: 1.43.4; 1.43.6; 1.43.8; VFP support.
1.42	19-Jan-2008	chris	branches: 1.42.2; 1.42.6; With the removal of IPKDB on arm, the undefined stack is only used to bounce into SVC32 mode, there is no per-process data stored on it. We can therefore use the undefined stack setup by the platform machdep.c as a system wide undefined stack. This removes the need for a per-process undefined stack, and the processor mode switching overhead it causes in cpu_switchto. The space freed in the USPACE is used to increase the per process kernel stack size.
1.41	12-Jan-2008	skrll	Push a switchframe in dumpsys and cpu_switchto, but as dumpsys calls other funcs a switchframe needs to be a multiple of 8 bytes. Stash sp as well in the switchframe to bump it to 24bytes. Setup the switchframe appropriately in cpu_lwp_fork. Remove savectx - nothing uses it. All of this make gdb's life much easier when dealing with crash dumps and live kernels. Reviewd by chris.
1.40	17-Oct-2007	garbled	branches: 1.40.2; 1.40.8; Merge the ppcoea-renovation branch to HEAD. This branch was a major cleanup and rototill of many of the various OEA cpu based PPC ports that focused on sharing as much code as possible between the various ports to eliminate near-identical copies of files in every tree. Additionally there is a new PIC system that unifies the interface to interrupt code for all different OEA ppc arches. The work for this branch was done by a variety of people, too long to list here. TODO: bebox still needs work to complete the transition to -renovation. ofppc still needs a bunch of work, which I will be looking at. ev64260 still needs to be renovated amigappc was not attempted. NOTES: pmppc was removed as an arch, and moved to a evbppc target.
1.39	15-Sep-2007	scw	ARM cpu_switchto() has been partially broken since yamt-idlelwp was merged as its cache/tlb management smarts relied too heavily on pre-merge context- switch behaviour. See PR kern/36548 for one manifestation of the breakage. To address this: - Ditch the shadow pmap variables in the PCB (pagedir, l1vec, dacr, cstate) as it was too easy for them to get out of sync with the pmap. - Re-write (and fix) the convoluted cpuswitch.S cache/tlb ASM code in C. It's only slightly less efficient, but is much more readable/maintainable. - Document cpufuncs.cf_context_switch() as being C-callable. - pmap_activate() becomes a no-op if the lwp's vmspace is already active. (Good performance win, since pmap_activate() is now invoked on every context-switch, even though ARM's cpu_switchto() already does all the grunt work) XXX: Some CPU-specific armXX_context_switch() implementations (arm67, arm7tdmi, arm8) always flush the I+D caches. This should not be necessary. Someone with access to hardware (acorn32?) needs to deal with this.
1.38	17-May-2007	yamt	branches: 1.38.6; 1.38.8; 1.38.10; 1.38.12; merge yamt-idlelwp branch. asked by core@. some ports still needs work. from doc/BRANCHES: idle lwp, and some changes depending on it. 1. separate context switching and thread scheduling. (cf. gmcgarry_ctxsw) 2. implement idle lwp. 3. clean up related MD/MI interfaces. 4. make scheduler(s) modular.
1.37	04-Mar-2007	christos	branches: 1.37.2; 1.37.4; 1.37.10; Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.
1.36	18-Feb-2007	matt	Changes for newlock2.
1.35	10-May-2006	skrll	branches: 1.35.14; Fix a bunch of cast lvalues.
1.34	11-Dec-2005	christos	branches: 1.34.4; 1.34.6; 1.34.8; 1.34.10; 1.34.12; merge ktrace-lwp.
1.33	01-Apr-2005	yamt	branches: 1.33.2; merge yamt-km branch. - don't use managed mappings/backing objects for wired memory allocations. save some resources like pv_entry. also fix (most of) PR/27030. - simplify kernel memory management API. - simplify pmap bootstrap of some ports. - some related cleanups.
1.32	28-Aug-2004	thorpej	branches: 1.32.4; 1.32.6; Garbage-collect pagemove(); nothing use it anymore (YAY!!!)
1.31	04-Jan-2004	jdolecek	Rearrange process exit path to avoid need to free resources from different process context ('reaper'). From within the exiting process context: * deactivate pmap and free vmspace while we can still block * introduce MD cpu_lwp_free() - this cleans all MD-specific context (such as FPU state), and is the last potentially blocking operation; all of cpu_wait(), and most of cpu_exit(), is now folded into cpu_lwp_free() * process is now immediatelly marked as zombie and made available for pickup by parent; the remaining last lwp continues the exit as fully detached * MI (rather than MD) code bumps uvmexp.swtch, cpu_exit() is now same for both 'process' and 'lwp' exit uvm_lwp_exit() is modified to never block; the u-area memory is now always just linked to the list of available u-areas. Introduce (blocking) uvm_uarea_drain(), which is called to release the excessive u-area memory; this is called by parent within wait4(), or by pagedaemon on memory shortage. uvm_uarea_free() is now private function within uvm_glue.c. MD process/lwp exit code now always calls lwp_exit2() immediatelly after switching away from the exiting lwp. g/c now unneeded routines and variables, including the reaper kernel thread
1.30	23-Oct-2003	scw	Don't drop to spl0 in cpu_switch/cpu_switchto. Do it in the idle loop instead. With this change, we no longer need to save the current interrupt level in the switchframe. This is no great loss since both cpu_switch and cpu_switchto are always called at splsched, so the process' spl is effectively saved somewhere in the callstack. This fixes an evbarm problem reported by Allen Briggs: lwp gets into sa_switch -> mi_switch with newl != NULL when it's the last element on the runqueue, so it hits the second bit of: if (newl == NULL) { retval = cpu_switch(l, NULL); } else { remrunqueue(newl); cpu_switchto(l, newl); retval = 0; } mi_switch calls remrunqueue() and cpu_switchto() cpu_switchto unlocks the sched lock cpu_switchto drops CPU priority softclock is received schedcpu is called from softclock schedcpu hits the first if () {} block here: if (l->l_priority >= PUSER) { if (l->l_stat == LSRUN && (l->l_flag & L_INMEM) && (l->l_priority / PPQ) != (l->l_usrpri / PPQ)) { remrunqueue(l); l->l_priority = l->l_usrpri; setrunqueue(l); } else l->l_priority = l->l_usrpri; } Since mi_switch has already run remrunqueue, the LWP has been removed, but it's not been put back on any queue, so the remrunqueue panics.
1.29	15-Jul-2003	lukem	__KERNEL_RCSID()
1.28	17-May-2003	thorpej	branches: 1.28.2; Rewrite pagemove() to use pmap functions, rather than frobbing PTEs directly. The old code was totally bogus for the new pmap. New code lifted from SH5 port. Fixes panics in ffs_balloc_ufs2() seen while stress-testing a file system on an XScale-based server platform.
1.27	22-Apr-2003	thorpej	Some ARM32_PMAP_NEW-related cleanup: * Define a new "MMU type", ARM_MMU_SA1. While the SA-1's MMU is basically compatible with the generic, the SA-1 cache does not have a write-through mode, and it is useful to know have an indication of this. * Add a new PMAP_NEEDS_PTE_SYNC indicator, and try to evaluate it at compile time. We evaluate it like so: - If SA-1-style MMU is the only type configured -> 1 - If SA-1-style MMU is not configured -> 0 - Otherwise, defer to a run-time variable. If PMAP_NEEDS_PTE_SYNC might evaluate to true (SA-1 only or run-time check), then we also define PMAP_INCLUDE_PTE_SYNC so that e.g. assembly code can include the necessary run-time support. PMAP_INCLUDE_PTE_SYNC largely replaces the ARM32_PMAP_NEEDS_PTE_SYNC manual setting Steve included with the original new pmap. * In the new pmap, make pmap_pte_init_generic() check to see if the CPU has a write-back cache. If so, init the PT cache mode to C=1,B=0 to get write-through mode. Otherwise, init the PT cache mode to C=1,B=1. * Add a new pmap_pte_init_arm8(). Old pmap, same as generic. New pmap, sets page table cacheability to 0 (ARM8 has a write-back cache, but flushing it is quite expensive). * In the new pmap, make pmap_pte_init_arm9() reset the PT cache mode to C=1,B=0, since the write-back check in generic gets it wrong for ARM9, since we use write-through mode all the time on ARM9 right now. (What this really tells me is that the test for write-through cache is less than perfect, but we can fix that later.) * Add a new pmap_pte_init_sa1(). Old pmap, same as generic. New pmap, does generic initialization, then resets page table cache mode to C=1,B=1, since C=1,B=0 does not produce write-through on the SA-1.
1.26	18-Apr-2003	scw	Add the generic arm32 bits of the new pmap, contributed by Wasabi Systems. Some features of the new pmap are: - It allows L1 descriptor tables to be shared efficiently between multiple processes. A typical "maxusers 32" kernel, where NPROC is set to 532, requires 35 L1s. A "maxusers 2" kernel runs quite happily with just 4 L1s. This completely solves the problem of running out of contiguous physical memory for allocating new L1s at runtime on a busy system. - Much improved cache/TLB management "smarts". This change ripples out to encompass the low-level context switch code, which is also much smarter about when to flush the cache/TLB, and when not to. - Faster allocation of L2 page tables and associated metadata thanks, in part, to the pool_cache enhancements recently contributed to NetBSD by Wasabi Systems. - Faster VM space teardown due to accurate referenced tracking of L2 page tables. - Better/faster cache-alias tracking. The new pmap is enabled by adding options ARM32_PMAP_NEW to the kernel config file, and making the necessary changes to the port-specific initarm() function. Several ports have already been converted and will be committed shortly.
1.25	01-Apr-2003	thorpej	Use PAGE_SIZE rather than NBPG.
1.24	17-Jan-2003	thorpej	Merge the nathanw_sa branch.
1.23	24-Nov-2002	chris	Fix's DEBUG kernel's not making it into multiuser on cats. (as spotted by nick) When wiring a page with pmap_enter you must supply the protection in the flags as well as in the prot.
1.22	19-Oct-2002	bjh21	branches: 1.22.2; Undo recent cpu_switch register usage changes in order to decrease nathanw_sa merge pain.
1.21	18-Oct-2002	bjh21	In cpu_switch(), stack more registers at the start of the function, and hence save fewer into the PCB. This should give me enough free registers in cpu_switch to tidy things up and support MULTIPROCESSOR properly. While we're here, make the stacked registers into an APCS stack frame, so that DDB backtraces through cpu_switch() will work. This also affects cpu_fork(), which has to fabricate a switchframe and PCB for the new process.
1.20	22-Aug-2002	thorpej	* Add PTE_SYNC() and PTE_SYNC_RANGE() macros. These don't actually do anything yet. * Use PTE_SYNC() and PTE_SYNC_RANGE() in some obvious places, i.e. where vtopte() is used.
1.19	09-Aug-2002	thorpej	cpu_fork(): If PMCs are not enabled in the parent, clear the machine- dependent PMC state in the child.
1.18	07-Aug-2002	briggs	Implement pmc(9) -- An interface to hardware performance monitoring counters. These counters do not exist on all CPUs, but where they do exist, can be used for counting events such as dcache misses that would otherwise be difficult or impossible to instrument by code inspection or hardware simulation. pmc(9) is meant to be a general interface. Initially, the Intel XScale counters are the only ones supported.
1.17	06-Aug-2002	thorpej	* Pass proc0 to switch_exit(), to make this a little more like the nathanw_sa branch. * In switch_exit(), set the outgoing-proc register to NULL (rather than proc0) so that we actually use the "exiting process" optimization in cpu_switch().
1.16	03-Apr-2002	thorpej	branches: 1.16.2; Clean up handling of the vector page on 32-bit ARM systems: * Don't refer to VA 0, instead refer to a new variable: vector_page * Delete the old zero_page_() functions, replacing them with a new one: vector_page_setprot(). When manipulating vector page mappings in user pmaps, only do so if the vector page is below KERNEL_BASE (if it's above KERNEL_BASE, the vector page is mapped by the kernel pmap). * Add a new function, arm32_vector_init(), which takes the virtual address of the vector page (which MUST be valid when the function is called) and a bitmask of vectors the kernel is going to take over, and performs all vector page initialization, including setting the V bit in the CPU Control register ("relocate vectors to high address"), if necessary.
1.15	04-Mar-2002	simonb	Don't need to declare phys_map - it is declared in <uvm/uvm_extern.h>.
1.14	26-Feb-2002	simonb	Purge CLSIZE, CLSIZELOG2 and MCLOFSET. Be consistant in the way that MSIZE, MCLSHIFT, MCLBYTES and NMBCLUSTERS are defined. Remove old VM constants from cesfic port. Bump MSIZE to 256 on mipsco (the only one that wasn't already 256).
1.13	29-Jan-2002	thorpej	When initializing sf->sf_spl, simply always assume that 0 is equivalent to spl0().
1.12	25-Jan-2002	thorpej	Overhaul of the ARM cache code. This is mostly a simplification pass. Rather than providing a whole slew of cache operations that aren't ever used, distill them down to some useful primitives: icache_sync_all Synchronize I-cache icache_sync_range Synchronize I-cache range dcache_wbinv_all Write-back and Invalidate D-cache dcache_wbinv_range Write-back and Invalidate D-cache range dcache_inv_range Invalidate D-cache range dcache_wb_range Write-back D-cache range idcache_wbinv_all Write-back and Invalidate D-cache, Invalidate I-cache idcache_wbinv_range Write-back and Invalidate D-cache, Invalidate I-cache range Note: This does not yet include an overhaul of the actual asm files that implement the primitives. Instead, we've provided a safe default for each CPU type, and the individual CPU types can now be optimized one at a time.
1.11	29-Nov-2001	thorpej	Provide a hook for platform-specific interrupt code to specify the "spl" cookie in the switch frame.
1.10	24-Nov-2001	thorpej	Move the ARM, Ltd. floating point emulator to arch/arm.
1.9	19-Nov-2001	chris	Give the idle loop a non-profiled entry, means it appears in profile info correctly (rather than all it's time being under remrunqueue) switch_exit only needs to take 1 parameter, it loads the value of proc0 into R1 itself Fixup some comments to reflect the real state of things. Tweak a couple of bits of asm to avoid a load delay. remove excess code for setting curpcb and curproc.
1.8	18-Oct-2001	rearnsha	branches: 1.8.4; Don't unmap page 0 when preparing to swap out a process. If the pmap is shared with another process (as can happen if vfork is being used), then that other process will end up not having a page 0, which is bad news indeed, since then there is no way back into the kernel. Found this using a multi-ice box, so they are useful after all! This seems to fix pr port-arm32/11921 and (possibly) kern/9859.
1.7	20-Sep-2001	chris	Fix bug in vmapbuf, was using len before it had been adjusted. Found by Frank while Luke was tracking down a bug.
1.6	10-Sep-2001	chris	Update pmap_update to now take the updated pmap as an argument. This will allow improvements to the pmaps so that they can more easily defer expensive operations, eg tlb/cache flush, til the last possible moment. Currently this is a no-op on most platforms, so they should see no difference. Reviewed by Jason.
1.5	09-Sep-2001	toshii	Don't define pcb_* register macros. pcb_sp macro conflicts with sys/netinet6/ipsec.c.
1.4	20-Aug-2001	chris	branches: 1.4.2; Arm has a vac, so we must use pmap_enter/remove for vmapbuf rather than k* versions, otherwise we may not be doing the right caching thing.
1.3	11-Aug-2001	chris	Update to make use of a proper kenter implementation for vmapbuf and vunmapbuf.
1.2	05-Aug-2001	matt	Force size_t formats/arge to be (u_long). I'd use 'z' for this but gcc 2.95.3
1.1	28-Jul-2001	chris	branches: 1.1.2; Move the generic arm32 files into arm/arm32 from arm32/arm32, tested kernel builds on cats and riscpc.
1.1.2.9	06-Sep-2002	jdolecek	sync kqueue branch with HEAD
1.1.2.8	23-Jun-2002	jdolecek	catch up with -current on kqueue branch
1.1.2.7	16-Mar-2002	jdolecek	Catch up with -current.
1.1.2.6	11-Feb-2002	jdolecek	Sync w/ -current.
1.1.2.5	10-Jan-2002	thorpej	Sync kqueue branch with -current.
1.1.2.4	13-Sep-2001	thorpej	Update the kqueue branch to HEAD.
1.1.2.3	25-Aug-2001	thorpej	Merge Aug 24 -current into the kqueue branch.
1.1.2.2	03-Aug-2001	lukem	update to -current
1.1.2.1	28-Jul-2001	lukem	file vm_machdep.c was added on branch kqueue on 2001-08-03 04:10:59 +0000
1.4.2.1	01-Oct-2001	fvdl	Catch up with -current.
1.8.4.14	03-Jan-2003	thorpej	Merge switch_exit() and switch_lwp_exit(), and hand-schedule the resulting function to avoid stalls on StrongARM and XScale.
1.8.4.13	31-Dec-2002	thorpej	Copy/initialize PMC state in cpu_proc_fork().
1.8.4.12	11-Dec-2002	thorpej	Sync with HEAD.
1.8.4.11	07-Oct-2002	thorpej	LWP'ify some debug printfs.
1.8.4.10	27-Aug-2002	thorpej	Sync with -current.
1.8.4.9	13-Aug-2002	nathanw	Catch up to -current.
1.8.4.8	24-Jun-2002	nathanw	Curproc->curlwp renaming. Change uses of "curproc->l_proc" back to "curproc", which is more like the original use. Bare uses of "curproc" are now "curlwp". "curproc" is now #defined in proc.h as ((curlwp) ? (curlwp)->l_proc) : NULL) so that it is always safe to reference curproc (dereferencing curproc is another story, but that's always been true).
1.8.4.7	17-Apr-2002	nathanw	Catch up to -current.
1.8.4.6	01-Apr-2002	nathanw	Catch up to -current. (CVS: It's not just a program. It's an adventure!)
1.8.4.5	28-Feb-2002	nathanw	Catch up to -current.
1.8.4.4	08-Jan-2002	nathanw	Catch up to -current.
1.8.4.3	08-Dec-2001	thorpej	cpu_fork() -> cpu_lwp_fork(). This logically forks an LWP, not a complete process. As noted by Gregory McGarry on tech-kern.
1.8.4.2	15-Nov-2001	thorpej	Machine-dependent kernel mods for scheduler activations on 32-bit ARM processors. Kernel boots multi-user on an XScale, but upcalls not yet tested.
1.8.4.1	18-Oct-2001	thorpej	file vm_machdep.c was added on branch nathanw_sa on 2001-11-15 06:39:22 +0000
1.16.2.1	30-Aug-2002	gehenna	catch up with -current.
1.22.2.2	19-Oct-2002	bjh21	Re-do the following revisions, this time on a branch where they won't interfere with the nathanw_sa merge: syssrc/sys/arch/arm/arm32/cpuswitch.S 1.26 syssrc/sys/arch/arm/arm32/genassym.cf 1.18 syssrc/sys/arch/arm/arm32/vm_machdep.c 1.21 syssrc/sys/arch/arm/include/pcb.h 1.5 Original commit message: In cpu_switch(), stack more registers at the start of the function, and hence save fewer into the PCB. This should give me enough free registers in cpu_switch to tidy things up and support MULTIPROCESSOR properly. While we're here, make the stacked registers into an APCS stack frame, so that DDB backtraces through cpu_switch() will work. This also affects cpu_fork(), which has to fabricate a switchframe and PCB for the new process.
1.22.2.1	19-Oct-2002	bjh21	file vm_machdep.c was added on branch bjh21-hydra on 2002-10-19 11:59:37 +0000
1.28.2.5	01-Apr-2005	skrll	Sync with HEAD.
1.28.2.4	21-Sep-2004	skrll	Fix the sync with head I botched.
1.28.2.3	18-Sep-2004	skrll	Sync with HEAD.
1.28.2.2	03-Sep-2004	skrll	Sync with HEAD
1.28.2.1	03-Aug-2004	skrll	Sync with HEAD
1.32.6.1	28-Jan-2005	yamt	convert arch/arm to new apis.
1.32.4.1	29-Apr-2005	kent	sync with -current
1.33.2.6	17-Mar-2008	yamt	sync with head.
1.33.2.5	21-Jan-2008	yamt	sync with head
1.33.2.4	27-Oct-2007	yamt	sync with head.
1.33.2.3	03-Sep-2007	yamt	sync with head.
1.33.2.2	26-Feb-2007	yamt	sync with head.
1.33.2.1	21-Jun-2006	yamt	sync with head.
1.34.12.1	24-May-2006	tron	Merge 2006-05-24 NetBSD-current into the "peter-altq" branch.
1.34.10.1	11-May-2006	elad	sync with head
1.34.8.1	24-May-2006	yamt	sync with head.
1.34.6.1	01-Jun-2006	kardel	Sync with head.
1.34.4.1	09-Sep-2006	rpaulo	sync with head
1.35.14.4	23-Apr-2007	skrll	Nuke cpu_setfunc
1.35.14.3	29-Mar-2007	skrll	Adapt arm32. Thanks to scw for helping out. Tested on my cats (SA1) XXX hydra should die. i've made some changes, but no guarantees.
1.35.14.2	12-Mar-2007	rmind	Sync with HEAD.
1.35.14.1	27-Feb-2007	yamt	- sync with head. - move sched_changepri back to kern_synch.c as it doesn't know PPQ anymore.
1.37.10.2	03-Oct-2007	garbled	Sync with HEAD
1.37.10.1	22-May-2007	matt	Update to HEAD.
1.37.4.1	11-Jul-2007	mjf	Sync with head.
1.37.2.2	09-Oct-2007	ad	Sync with head.
1.37.2.1	27-May-2007	ad	Sync with head.
1.38.12.2	23-Mar-2008	matt	sync with HEAD
1.38.12.1	06-Nov-2007	matt	sync with HEAD
1.38.10.3	21-Mar-2008	chris	Sync with head.
1.38.10.2	20-Jan-2008	chris	Sync to HEAD.
1.38.10.1	01-Jan-2008	chris	Sync with HEAD.
1.38.8.1	02-Oct-2007	joerg	Sync with HEAD.
1.38.6.2	28-Feb-2008	rjs	Sync with HEAD.
1.38.6.1	01-Nov-2007	rjs	Sync with HEAD.
1.40.8.2	20-Jan-2008	bouyer	Sync with HEAD
1.40.8.1	19-Jan-2008	bouyer	Sync with HEAD
1.40.2.1	18-Feb-2008	mjf	Sync with HEAD.
1.42.6.3	17-Jan-2009	mjf	Sync with HEAD.
1.42.6.2	28-Sep-2008	mjf	Sync with HEAD.
1.42.6.1	03-Apr-2008	mjf	Sync with HEAD.
1.42.2.1	24-Mar-2008	keiichi	sync with head.
1.43.8.1	18-Jul-2008	simonb	Sync with head.
1.43.6.1	18-Sep-2008	wrstuden	Sync with wrstuden-revivesa-base-2.
1.43.4.2	11-Mar-2010	yamt	sync with head
1.43.4.1	04-May-2009	yamt	sync with head.
1.44.2.3	13-Dec-2008	haad	Update haad-dm branch to haad-dm-base2.
1.44.2.2	19-Oct-2008	haad	Sync with HEAD.
1.44.2.1	07-Jul-2008	haad	file vm_machdep.c was added on branch haad-dm on 2008-10-19 22:15:41 +0000
1.46.12.1	15-Feb-2014	matt	Merge armv7 support from HEAD, specifically support for the BCM5301X and BCM56340 evbarm kernels.
1.46.8.1	13-May-2009	jym	Sync with HEAD. Commit is split, to avoid a "too many arguments" protocol error.
1.46.2.1	28-Apr-2009	skrll	Sync with HEAD.
1.53.4.1	05-Mar-2011	rmind	sync with head
1.54.4.1	17-Feb-2011	bouyer	Sync with HEAD
1.54.2.1	06-Jun-2011	jruoho	Sync with HEAD.
1.55.12.1	28-Nov-2012	matt	Merge improved arm support (especially Cortex) from HEAD including OMAP and BCM53xx support.
1.55.8.1	24-Feb-2012	mrg	sync to -current.
1.55.4.5	22-May-2014	yamt	sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments")
1.55.4.4	23-Jan-2013	yamt	sync with head
1.55.4.3	16-Jan-2013	yamt	sync with (a bit old) head
1.55.4.2	30-Oct-2012	yamt	sync with head
1.55.4.1	17-Apr-2012	yamt	sync with head
1.60.2.5	03-Dec-2017	jdolecek	update from HEAD
1.60.2.4	20-Aug-2014	tls	Rebase to HEAD as of a few days ago.
1.60.2.3	23-Jun-2013	tls	resync from head
1.60.2.2	25-Feb-2013	tls	resync with head
1.60.2.1	20-Nov-2012	tls	Resync to 2012-11-19 00:00:00 UTC
1.66.2.2	18-May-2014	rmind	sync with head
1.66.2.1	28-Aug-2013	rmind	sync with head
1.69.6.1	06-Apr-2015	skrll	Sync with HEAD
1.70.10.1	24-Oct-2017	snj	Pull up following revision(s) (requested by skrll in ticket #315): sys/arch/arm/arm32/vm_machdep.c: 1.71-1.72 In vmapbuf use pmap_enter(pmap_kernel(), ...) and not pmap_kenter_pa as the former handles multiple mappings for VIPT AND VIVT correctly whereas the latter doesn't work for VIVT. PR port-shark/52102 From skrll@. Tested by martin@ and me. -- Fix eva argument to pmap_remove and passed prot bits in flags for pmap_enter, i.e. fix previous.
1.72.2.2	28-Jul-2018	pgoyette	Sync with HEAD
1.72.2.1	25-Jun-2018	pgoyette	Sync with HEAD
1.73.2.2	21-Apr-2020	martin	Sync with HEAD
1.73.2.1	10-Jun-2019	christos	Sync with HEAD
1.75.10.1	20-Apr-2020	bouyer	Sync with HEAD
1.77.4.1	03-Apr-2021	thorpej	Sync with HEAD.
1.77.2.1	03-Apr-2021	thorpej	Sync with HEAD.

OpenGrok